diff options
Diffstat (limited to 'gcc/config/mips/mips.md')
| -rw-r--r-- | gcc/config/mips/mips.md | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index e2c99733fe3..923fcbf7f60 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -5565,7 +5565,7 @@ move\\t%0,%z4\\n\\ (define_insn "movcc" [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*d,*R,*m,*d,*f,*f,*f,*f,*R,*m") (match_operand:CC 1 "general_operand" "z,*d,*R,*m,*d,*d,*f,*d,*f,*R,*m,*f,*f"))] - "ISA_HAS_FP4 && TARGET_HARD_FLOAT" + "ISA_HAS_8CC && TARGET_HARD_FLOAT" "* return mips_move_1word (operands, insn, FALSE);" [(set_attr "type" "move,move,load,load,store,store,xfer,xfer,move,load,load,store,store") (set_attr "mode" "SI") @@ -5577,7 +5577,7 @@ move\\t%0,%z4\\n\\ [(set (match_operand:CC 0 "register_operand" "=z") (match_operand:CC 1 "general_operand" "z")) (clobber (match_operand:TF 2 "register_operand" "=&f"))] - "ISA_HAS_FP4 && TARGET_HARD_FLOAT" + "ISA_HAS_8CC && TARGET_HARD_FLOAT" " { rtx source; @@ -5615,7 +5615,7 @@ move\\t%0,%z4\\n\\ [(set (match_operand:CC 0 "general_operand" "=z") (match_operand:CC 1 "register_operand" "z")) (clobber (match_operand:CC 2 "register_operand" "=&d"))] - "ISA_HAS_FP4 && TARGET_HARD_FLOAT" + "ISA_HAS_8CC && TARGET_HARD_FLOAT" " { /* This is called when we are copying a condition code register out @@ -9955,7 +9955,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (const_int 0)]) (match_operand:SI 1 "reg_or_0_operand" "dJ,0") (match_operand:SI 2 "reg_or_0_operand" "0,dJ")))] - "ISA_HAS_FP4 && TARGET_HARD_FLOAT" + "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT" "@ mov%T3\\t%0,%z1,%4 mov%t3\\t%0,%z2,%4" @@ -10001,7 +10001,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (const_int 0)]) (match_operand:DI 1 "se_reg_or_0_operand" "dJ,0") (match_operand:DI 2 "se_reg_or_0_operand" "0,dJ")))] - "ISA_HAS_FP4 && TARGET_HARD_FLOAT" + "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT" "@ mov%T3\\t%0,%z1,%4 mov%t3\\t%0,%z2,%4" @@ -10016,7 +10016,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (const_int 0)]) (match_operand:SF 2 "register_operand" "f,0") (match_operand:SF 3 "register_operand" "0,f")))] - "ISA_HAS_FP4 && TARGET_HARD_FLOAT" + "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT" "@ mov%B4.s\\t%0,%2,%1 mov%b4.s\\t%0,%3,%1" @@ -10031,7 +10031,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (const_int 0)]) (match_operand:SF 2 "register_operand" "f,0") (match_operand:SF 3 "register_operand" "0,f")))] - "ISA_HAS_FP4 && TARGET_HARD_FLOAT" + "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT" "@ mov%B4.s\\t%0,%2,%1 mov%b4.s\\t%0,%3,%1" @@ -10047,7 +10047,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (const_int 0)]) (match_operand:SF 1 "register_operand" "f,0") (match_operand:SF 2 "register_operand" "0,f")))] - "ISA_HAS_FP4 && TARGET_HARD_FLOAT" + "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT" "@ mov%T3.s\\t%0,%1,%4 mov%t3.s\\t%0,%2,%4" @@ -10062,7 +10062,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (const_int 0)]) (match_operand:DF 2 "register_operand" "f,0") (match_operand:DF 3 "register_operand" "0,f")))] - "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "@ mov%B4.d\\t%0,%2,%1 mov%b4.d\\t%0,%3,%1" @@ -10077,7 +10077,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (const_int 0)]) (match_operand:DF 2 "register_operand" "f,0") (match_operand:DF 3 "register_operand" "0,f")))] - "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "@ mov%B4.d\\t%0,%2,%1 mov%b4.d\\t%0,%3,%1" @@ -10093,7 +10093,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (const_int 0)]) (match_operand:DF 1 "register_operand" "f,0") (match_operand:DF 2 "register_operand" "0,f")))] - "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "@ mov%T3.d\\t%0,%1,%4 mov%t3.d\\t%0,%2,%4" @@ -10108,7 +10108,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (if_then_else:SI (match_dup 5) (match_operand:SI 2 "reg_or_0_operand" "") (match_operand:SI 3 "reg_or_0_operand" "")))] - "ISA_HAS_CONDMOVE || ISA_HAS_FP4" + "ISA_HAS_CONDMOVE" " { gen_conditional_move (operands); @@ -10121,7 +10121,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (if_then_else:DI (match_dup 5) (match_operand:DI 2 "se_reg_or_0_operand" "") (match_operand:DI 3 "se_reg_or_0_operand" "")))] - "ISA_HAS_CONDMOVE || ISA_HAS_FP4" + "ISA_HAS_CONDMOVE" " { gen_conditional_move (operands); @@ -10134,7 +10134,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (if_then_else:SF (match_dup 5) (match_operand:SF 2 "register_operand" "") (match_operand:SF 3 "register_operand" "")))] - "ISA_HAS_FP4 && TARGET_HARD_FLOAT" + "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT" " { gen_conditional_move (operands); @@ -10147,7 +10147,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\;j\\t%2" (if_then_else:DF (match_dup 5) (match_operand:DF 2 "register_operand" "") (match_operand:DF 3 "register_operand" "")))] - "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" + "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" " { gen_conditional_move (operands); |