diff options
Diffstat (limited to 'gcc/config/mn10300/mn10300.md')
| -rw-r--r-- | gcc/config/mn10300/mn10300.md | 1369 |
1 files changed, 862 insertions, 507 deletions
diff --git a/gcc/config/mn10300/mn10300.md b/gcc/config/mn10300/mn10300.md index d90f0f25836..26126a7c034 100644 --- a/gcc/config/mn10300/mn10300.md +++ b/gcc/config/mn10300/mn10300.md @@ -40,6 +40,114 @@ (include "predicates.md") (include "constraints.md") + +;; Processor type. This attribute must exactly match the processor_type +;; enumeration in mn10300.h. +(define_attr "cpu" "mn10300,am33,am33_2,am34" + (const (symbol_ref "mn10300_tune_cpu"))) + + +;; Pipeline description. + +;; The AM33 only has a single pipeline. It has five stages (fetch, +;; decode, execute, memory access, writeback) each of which normally +;; takes a single CPU clock cycle. + +;; The timings attribute consists of two numbers, the first is the +;; throughput, which is the number of cycles the instruction takes +;; to execute and generate a result. The second is the latency +;; which is the effective number of cycles the instruction takes to +;; execute if its result is used by the following instruction. The +;; latency is always greater than or equal to the throughput. +;; These values were taken from the Appendix of the "MN103E Series +;; Instruction Manual" and the timings for the AM34. + +;; Note - it would be nice to use strings rather than integers for +;; the possible values of this attribute, so that we can have the +;; gcc build mechanism check for values that are not supported by +;; the reservations below. But this will not work because the code +;; in mn10300_adjust_sched_cost() needs integers not strings. + +(define_attr "timings" "" (const_int 11)) + +(define_automaton "pipelining") +(define_cpu_unit "throughput" "pipelining") + +(define_insn_reservation "throughput__1_latency__1" 1 + (eq_attr "timings" "11") "throughput") +(define_insn_reservation "throughput__1_latency__2" 2 + (eq_attr "timings" "12") "throughput,nothing") +(define_insn_reservation "throughput__1_latency__3" 3 + (eq_attr "timings" "13") "throughput,nothing*2") +(define_insn_reservation "throughput__1_latency__4" 4 + (eq_attr "timings" "14") "throughput,nothing*3") +(define_insn_reservation "throughput__2_latency__2" 2 + (eq_attr "timings" "22") "throughput*2") +(define_insn_reservation "throughput__2_latency__3" 3 + (eq_attr "timings" "23") "throughput*2,nothing") +(define_insn_reservation "throughput__2_latency__4" 4 + (eq_attr "timings" "24") "throughput*2,nothing*2") +(define_insn_reservation "throughput__2_latency__5" 5 + (eq_attr "timings" "25") "throughput*2,nothing*3") +(define_insn_reservation "throughput__3_latency__3" 3 + (eq_attr "timings" "33") "throughput*3") +(define_insn_reservation "throughput__3_latency__7" 7 + (eq_attr "timings" "37") "throughput*3,nothing*4") +(define_insn_reservation "throughput__4_latency__4" 4 + (eq_attr "timings" "44") "throughput*4") +(define_insn_reservation "throughput__4_latency__7" 7 + (eq_attr "timings" "47") "throughput*4,nothing*3") +(define_insn_reservation "throughput__4_latency__8" 8 + (eq_attr "timings" "48") "throughput*4,nothing*4") +(define_insn_reservation "throughput__5_latency__5" 5 + (eq_attr "timings" "55") "throughput*5") +(define_insn_reservation "throughput__6_latency__6" 6 + (eq_attr "timings" "66") "throughput*6") +(define_insn_reservation "throughput__7_latency__7" 7 + (eq_attr "timings" "77") "throughput*7") +(define_insn_reservation "throughput__7_latency__8" 8 + (eq_attr "timings" "78") "throughput*7,nothing") +(define_insn_reservation "throughput__8_latency__8" 8 + (eq_attr "timings" "88") "throughput*8") +(define_insn_reservation "throughput__9_latency__9" 9 + (eq_attr "timings" "99") "throughput*9") +(define_insn_reservation "throughput__8_latency_14" 14 + (eq_attr "timings" "814") "throughput*8,nothing*6") +(define_insn_reservation "throughput__9_latency_10" 10 + (eq_attr "timings" "910") "throughput*9,nothing") +(define_insn_reservation "throughput_10_latency_10" 10 + (eq_attr "timings" "1010") "throughput*10") +(define_insn_reservation "throughput_12_latency_16" 16 + (eq_attr "timings" "1216") "throughput*12,nothing*4") +(define_insn_reservation "throughput_13_latency_13" 13 + (eq_attr "timings" "1313") "throughput*13") +(define_insn_reservation "throughput_14_latency_14" 14 + (eq_attr "timings" "1414") "throughput*14") +(define_insn_reservation "throughput_13_latency_17" 17 + (eq_attr "timings" "1317") "throughput*13,nothing*4") +(define_insn_reservation "throughput_23_latency_27" 27 + (eq_attr "timings" "2327") "throughput*23,nothing*4") +(define_insn_reservation "throughput_25_latency_31" 31 + (eq_attr "timings" "2531") "throughput*25,nothing*6") +(define_insn_reservation "throughput_38_latency_39" 39 + (eq_attr "timings" "3839") "throughput*38,nothing") +(define_insn_reservation "throughput_39_latency_40" 40 + (eq_attr "timings" "3940") "throughput*39,nothing") +(define_insn_reservation "throughput_40_latency_40" 40 + (eq_attr "timings" "4040") "throughput*40") +(define_insn_reservation "throughput_41_latency_42" 42 + (eq_attr "timings" "4142") "throughput*41,nothing") +(define_insn_reservation "throughput_43_latency_44" 44 + (eq_attr "timings" "4344") "throughput*43,nothing") +(define_insn_reservation "throughput_45_latency_46" 46 + (eq_attr "timings" "4546") "throughput*45,nothing") +(define_insn_reservation "throughput_47_latency_53" 53 + (eq_attr "timings" "4753") "throughput*47,nothing*6") + +;; Note - the conflict between memory load/store instructions +;; and floating point instructions described in section 1-7-4 +;; of Chapter 3 of the MN103E Series Instruction Manual is +;; handled by the mn10300_adjust_sched_cost function. ;; ---------------------------------------------------------------------- ;; MOVE INSTRUCTIONS @@ -48,7 +156,7 @@ ;; movqi (define_expand "movqi" - [(set (match_operand:QI 0 "general_operand") + [(set (match_operand:QI 0 "nonimmediate_operand") (match_operand:QI 1 "general_operand"))] "" " @@ -60,52 +168,62 @@ }") (define_insn "*am33_movqi" - [(set (match_operand:QI 0 "nonimmediate_operand" "=d*x*a*f,d*x*a,d*x*a,m,*f,d*x*a") - (match_operand:QI 1 "general_operand" "0,d*xai,m,d*xa,d*xa*f,*f"))] + [(set (match_operand:QI 0 "nonimmediate_operand" + ;; 0 1 2 3 4 5 + "=d*x*a*f, d*x*a, d*x*a, m, *f, d*x*a") + (match_operand:QI 1 "general_operand" + "0, d*xai, m, d*xa, d*xa*f, *f"))] "TARGET_AM33 && (register_operand (operands[0], QImode) || register_operand (operands[1], QImode))" "* -{ - switch (which_alternative) - { - case 0: - return \"nop\"; - case 1: - if (CONST_DOUBLE_P (operands[1])) - { - rtx xoperands[2]; - xoperands[0] = operands[0]; - xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); - output_asm_insn (\"mov %1,%0\", xoperands); - return \"\"; - } + { + switch (which_alternative) + { + case 0: + return \"nop\"; + case 1: + gcc_assert (! CONST_DOUBLE_P (operands[1])); - if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS - && CONST_INT_P (operands[1])) - { - HOST_WIDE_INT val = INTVAL (operands[1]); + if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS + && CONST_INT_P (operands[1])) + { + HOST_WIDE_INT val = INTVAL (operands[1]); - if (((val & 0x80) && ! (val & 0xffffff00)) - || ((val & 0x800000) && ! (val & 0xff000000))) - return \"movu %1,%0\"; - } - return \"mov %1,%0\"; - case 2: - case 3: - return \"movbu %1,%0\"; - case 4: - case 5: - return \"fmov %1,%0\"; - default: - gcc_unreachable (); - } -}" + if (((val & 0x80) && ! (val & 0xffffff00)) + || ((val & 0x800000) && ! (val & 0xff000000))) + return \"movu %1,%0\"; + } + return \"mov %1,%0\"; + case 2: + case 3: + return \"movbu %1,%0\"; + case 4: + case 5: + return \"fmov %1,%0\"; + default: + gcc_unreachable (); + } + }" + [(set_attr_alternative "timings" + [(const_int 11) + (if_then_else (eq_attr "cpu" "am34") + (const_int 11) (const_int 22)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 13) (const_int 24)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 13) (const_int 24)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 47) (const_int 25)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 47) (const_int 25)) + ]) + ] ) (define_insn "*mn10300_movqi" [(set (match_operand:QI 0 "nonimmediate_operand" "=d*a,d,d,!*a,d*a,d,m") - (match_operand:QI 1 "general_operand" "0,I,i,i,da,m,d"))] + (match_operand:QI 1 "general_operand" "0, I,i,i, da, m,d"))] "register_operand (operands[0], QImode) || register_operand (operands[1], QImode)" "* @@ -118,15 +236,7 @@ case 2: case 3: case 4: - if (CONST_DOUBLE_P (operands[1])) - { - rtx xoperands[2]; - xoperands[0] = operands[0]; - xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); - output_asm_insn (\"mov %1,%0\", xoperands); - return \"\"; - } - + gcc_assert (! CONST_DOUBLE_P (operands[1])); return \"mov %1,%0\"; case 5: case 6: @@ -135,12 +245,27 @@ gcc_unreachable (); } }" + [(set_attr_alternative "timings" + [(const_int 11) + (const_int 11) + (if_then_else (eq_attr "cpu" "am34") + (const_int 11) (const_int 22)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 11) (const_int 22)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 11) (const_int 22)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 13) (const_int 24)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 13) (const_int 24)) + ]) + ] ) ;; movhi (define_expand "movhi" - [(set (match_operand:HI 0 "general_operand") + [(set (match_operand:HI 0 "nonimmediate_operand") (match_operand:HI 1 "general_operand"))] "" " @@ -152,8 +277,11 @@ }") (define_insn "*am33_movhi" - [(set (match_operand:HI 0 "nonimmediate_operand" "=d*x*a*f,d*x*a,d*x*a,m,*f,d*x*a") - (match_operand:HI 1 "general_operand" "0,d*x*ai,m,d*x*a,d*x*a*f,*f"))] + [(set (match_operand:HI 0 "nonimmediate_operand" + ;; 0 1 2 3 4 5 + "=d*x*a*f, d*x*a, d*x*a, m, *f, d*x*a") + (match_operand:HI 1 "general_operand" + "0, d*x*ai, m, d*x*a, d*x*a*f, *f"))] "TARGET_AM33 && (register_operand (operands[0], HImode) || register_operand (operands[1], HImode))" @@ -164,14 +292,7 @@ case 0: return \"nop\"; case 1: - if (CONST_DOUBLE_P (operands[1])) - { - rtx xoperands[2]; - xoperands[0] = operands[0]; - xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); - output_asm_insn (\"mov %1,%0\", xoperands); - return \"\"; - } + gcc_assert (! CONST_DOUBLE_P (operands[1])); if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS && CONST_INT_P (operands[1])) @@ -193,11 +314,25 @@ gcc_unreachable (); } }" + [(set_attr_alternative "timings" + [(const_int 11) + (if_then_else (eq_attr "cpu" "am34") + (const_int 11) (const_int 22)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 13) (const_int 24)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 13) (const_int 24)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 47) (const_int 25)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 47) (const_int 25)) + ]) + ] ) (define_insn "*mn10300_movhi" [(set (match_operand:HI 0 "nonimmediate_operand" "=d*a,d,d,!*a,d*a,d,m") - (match_operand:HI 1 "general_operand" "0,I,i,i,da,m,d"))] + (match_operand:HI 1 "general_operand" "0, I,i,i, da, m,d"))] "register_operand (operands[0], HImode) || register_operand (operands[1], HImode)" "* @@ -210,14 +345,7 @@ case 2: case 3: case 4: - if (CONST_DOUBLE_P (operands[1])) - { - rtx xoperands[2]; - xoperands[0] = operands[0]; - xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); - output_asm_insn (\"mov %1,%0\", xoperands); - return \"\"; - } + gcc_assert (! CONST_DOUBLE_P (operands[1])); return \"mov %1,%0\"; case 5: case 6: @@ -226,6 +354,21 @@ gcc_unreachable (); } }" + [(set_attr_alternative "timings" + [(const_int 11) + (const_int 11) + (if_then_else (eq_attr "cpu" "am34") + (const_int 11) (const_int 22)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 11) (const_int 22)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 11) (const_int 22)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 13) (const_int 24)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 13) (const_int 24)) + ]) + ] ) ;; movsi and helpers @@ -276,10 +419,13 @@ [(set (reg:SI PIC_REG) (mem:SI (post_inc:SI (reg:SI SP_REG))))] "reload_completed" - "movm (sp),[a2]") + "movm (sp),[a2]" + [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") + (const_int 44) (const_int 33)))] +) (define_expand "movsi" - [(set (match_operand:SI 0 "general_operand") + [(set (match_operand:SI 0 "nonimmediate_operand") (match_operand:SI 1 "general_operand"))] "" " @@ -322,62 +468,49 @@ (define_insn "*movsi_internal" [(set (match_operand:SI 0 "nonimmediate_operand" - "=dx,ax,dx,a,dxm,dxm,axm,axm,dx,dx,ax,ax,axR,!*y,*f,*f,dxaQ") + "=dax, dax, m, dax, axR, !*y") (match_operand:SI 1 "general_operand" - "0,0,I,I,dx,ax,dx,ax,dixm,aixm,dixm,aixm,!*y,axR,0,dxaQi*f,*f"))] + "0, Idax, dax, im, !*y, axR")) + ] "register_operand (operands[0], SImode) || register_operand (operands[1], SImode)" "* -{ - switch (which_alternative) - { - case 0: - case 1: + { + if (which_alternative == 0) return \"nop\"; - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: - case 8: - case 9: - case 10: - case 11: - case 12: - case 13: - if (CONST_DOUBLE_P (operands[1])) - { - rtx xoperands[2]; - xoperands[0] = operands[0]; - xoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); - output_asm_insn (\"mov %1,%0\", xoperands); - return \"\"; - } - if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS - && CONST_INT_P (operands[1])) - { - HOST_WIDE_INT val = INTVAL (operands[1]); + gcc_assert (! CONST_DOUBLE_P (operands[1])); - if (((val & 0x80) && ! (val & 0xffffff00)) - || ((val & 0x800000) && ! (val & 0xff000000))) - return \"movu %1,%0\"; - } - return \"mov %1,%0\"; - case 14: - return \"nop\"; - case 15: - case 16: - return \"fmov %1,%0\"; - default: - gcc_unreachable (); - } -}" + if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS + && CONST_INT_P (operands[1])) + { + HOST_WIDE_INT val = INTVAL (operands[1]); + + if (((val & 0x80) && ! (val & 0xffffff00)) + || ((val & 0x800000) && ! (val & 0xff000000))) + return \"movu %1, %0\"; + } + + return \"mov %1, %0\"; + }" + [(set_attr_alternative "timings" + [(const_int 11) + (if_then_else (eq_attr "cpu" "am34") + (const_int 13) (const_int 24)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 13) (const_int 24)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 13) (const_int 24)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 13) (const_int 24)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 13) (const_int 24)) + ]) + ] ) (define_expand "movsf" - [(set (match_operand:SF 0 "general_operand") + [(set (match_operand:SF 0 "nonimmediate_operand") (match_operand:SF 1 "general_operand"))] "" " @@ -389,44 +522,59 @@ }") (define_insn "*movsf_internal" - [(set (match_operand:SF 0 "nonimmediate_operand" "=f,dx,ax,dx,a,f,dxaQ,daxm,dax") - (match_operand:SF 1 "general_operand" "0,0,0,G,G,fdxaQF,f,dax,daxFm"))] + [(set (match_operand:SF 0 "nonimmediate_operand" + ;; 0 1 2 3 4 5 + "=fdxa, dxa, f, dxaQ, daxm, dax") + (match_operand:SF 1 "general_operand" + " 0, G, fdxaQF, f, dax, daxFm")) + ] "register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode)" "* -{ - switch (which_alternative) - { - case 0: - case 1: - case 2: - return \"nop\"; - /* Cases 3 & 4: below. */ - case 5: - case 6: - return \"fmov %1, %0\"; - case 3: - case 4: - case 7: - case 8: - if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS - && CONST_INT_P (operands[1])) - { - HOST_WIDE_INT val = INTVAL (operands[1]); + { + switch (which_alternative) + { + case 0: + return \"nop\"; + /* case 1: below. */ + case 2: + case 3: + return \"fmov %1, %0\"; + case 1: + case 4: + case 5: + if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS + && CONST_INT_P (operands[1])) + { + HOST_WIDE_INT val = INTVAL (operands[1]); - if (((val & 0x80) && ! (val & 0xffffff00)) - || ((val & 0x800000) && ! (val & 0xff000000))) - return \"movu %1,%0\"; - } - return \"mov %1,%0\"; - default: - gcc_unreachable (); - } -}" + if (((val & 0x80) && ! (val & 0xffffff00)) + || ((val & 0x800000) && ! (val & 0xff000000))) + return \"movu %1, %0\"; + } + return \"mov %1, %0\"; + default: + gcc_unreachable (); + } + }" + [(set_attr_alternative "timings" + [(const_int 11) + (if_then_else (eq_attr "cpu" "am34") + (const_int 13) (const_int 24)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 47) (const_int 25)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 47) (const_int 25)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 13) (const_int 24)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 13) (const_int 24)) + ]) + ] ) (define_expand "movdi" - [(set (match_operand:DI 0 "general_operand") + [(set (match_operand:DI 0 "nonimmediate_operand") (match_operand:DI 1 "general_operand"))] "" " @@ -437,11 +585,10 @@ operands[1] = copy_to_mode_reg (DImode, operand1); }") -(define_insn "*movdi_internal" - [(set (match_operand:DI 0 "nonimmediate_operand" - "=dx,ax,dx,a,dxm,dxm,axm,axm,dx,dx,ax,ax,*f,*f,*f,dxa,*f,Q") - (match_operand:DI 1 "general_operand" - "0,0,I,I,dx,ax,dx,ax,dxim,axim,dxim,axim,0,*f,dxai,*f,Q,*f"))] + +(define_insn "*movdi_internal" ;; 0 1 2 3 4 5 6 7 8 9 + [(set (match_operand:DI 0 "nonimmediate_operand" "=dx,ax,dx,a,dxm,dxm,a, a,dx,a") + (match_operand:DI 1 "general_operand" "0,0, I, I,dx, a, dx,a,im,im"))] "register_operand (operands[0], DImode) || register_operand (operands[1], DImode)" "* @@ -469,8 +616,6 @@ case 7: case 8: case 9: - case 10: - case 11: if (CONST_INT_P (operands[1])) { rtx low, high; @@ -568,34 +713,28 @@ output_asm_insn (\"mov %H1,%H0\", operands); return \"\"; } - case 12: - return \"nop\"; - case 13: - case 14: - case 15: - return \"fmov %L1, %L0\;fmov %H1, %H0\"; - case 16: - if (MEM_P (operands[1]) - && CONST_INT_P (XEXP (operands[1], 0)) - && (INTVAL (XEXP (operands[1], 0)) & 7) == 0) - return \"fmov %D1, %D0\"; - else - return \"fmov %L1, %L0\;fmov %H1, %H0\"; - case 17: - if (MEM_P (operands[0]) - && CONST_INT_P (XEXP (operands[0], 0)) - && (INTVAL (XEXP (operands[0], 0)) & 7) == 0) - return \"fmov %D1, %D0\"; - else - return \"fmov %L1, %L0\;fmov %H1, %H0\"; default: gcc_unreachable (); } -}" + }" + ;; The timing of "37" is an approximation of the worst case sceanario. + [(set_attr_alternative "timings" + [(const_int 11) + (const_int 11) + (const_int 22) + (const_int 22) + (const_int 37) + (const_int 37) + (const_int 37) + (const_int 37) + (const_int 37) + (const_int 37) + ]) + ] ) (define_expand "movdf" - [(set (match_operand:DF 0 "general_operand") + [(set (match_operand:DF 0 "nonimmediate_operand") (match_operand:DF 1 "general_operand"))] "" " @@ -608,63 +747,52 @@ (define_insn "*am33_2_movdf" [(set (match_operand:DF 0 "nonimmediate_operand" - ;; 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 - "=f,dx,ax,dx,f,f,dxa,f,Q,a,dxm,dxm,axm,axm,dx,dx,ax,ax") + ;; 0 1 2 3 4 5 6 7 8 9 10 11 + "=fdax,dax,fdxa,f, f,Q,dxm,dxm,a, a,dx,a") (match_operand:DF 1 "general_operand" - ;; 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 - "0,0,0,G,f,dxaF,f,Q,f,G,dx,ax,dx,ax,dxFm,axFm,dxFm,axFm"))] + " 0, G, f, dxaF,Q,f,dx, a, dx,a,Fm,Fm"))] "TARGET_AM33_2 - && (register_operand (operands[0], DFmode) - || register_operand (operands[1], DFmode))" + && (register_operand (operands[0], DFmode) + || register_operand (operands[1], DFmode))" "* -{ - long val[2]; - REAL_VALUE_TYPE rv; + { + long val[2]; + REAL_VALUE_TYPE rv; - switch (which_alternative) - { + switch (which_alternative) + { case 0: - case 1: - case 2: return \"nop\"; + case 1: + return \"mov 0, %L0\; mov 0, %H0\"; + + case 2: case 3: - return \"mov 0, %L0\;mov 0, %H0\"; + return \"fmov %L1, %L0\; fmov %H1, %H0\"; case 4: - case 5: - case 6: - return \"fmov %L1, %L0\;fmov %H1, %H0\"; - - case 7: if (MEM_P (operands[1]) && CONST_INT_P (XEXP (operands[1], 0)) && (INTVAL (XEXP (operands[1], 0)) & 7) == 0) return \"fmov %D1, %D0\"; else - return \"fmov %L1, %L0\;fmov %H1, %H0\"; + return \"fmov %L1, %L0\; fmov %H1, %H0\"; - case 8: + case 5: if (MEM_P (operands[0]) && CONST_INT_P (XEXP (operands[0], 0)) && (INTVAL (XEXP (operands[0], 0)) & 7) == 0) return \"fmov %D1, %D0\"; else - return \"fmov %L1, %L0\;fmov %H1, %H0\"; + return \"fmov %L1, %L0\; fmov %H1, %H0\"; + case 6: + case 7: + case 8: case 9: - if (rtx_equal_p (operands[0], operands[1])) - return \"sub %L1,%L0\;mov %L0,%H0\"; - else - return \"mov %1,%L0\;mov %L0,%H0\"; case 10: case 11: - case 12: - case 13: - case 14: - case 15: - case 16: - case 17: if (CONST_INT_P (operands[1])) { rtx low, high; @@ -699,9 +827,9 @@ if (reg_overlap_mentioned_p (gen_rtx_REG (SImode, REGNO (temp)), XEXP (operands[1], 0))) - return \"mov %H1,%H0\;mov %L1,%L0\"; + return \"mov %H1, %H0\; mov %L1, %L0\"; else - return \"mov %L1,%L0\;mov %H1,%H0\"; + return \"mov %L1, %L0\; mov %H1, %H0\"; } else if (MEM_P (operands[1]) @@ -713,7 +841,7 @@ xoperands[0] = operands[0]; xoperands[1] = XEXP (operands[1], 0); - output_asm_insn (\"mov %1,%L0\;mov (4,%L0),%H0\;mov (%L0),%L0\", + output_asm_insn (\"mov %1, %L0\; mov (4, %L0), %H0\; mov (%L0), %L0\", xoperands); return \"\"; } @@ -734,9 +862,9 @@ == EXTENDED_REGS) && (((val[0] & 0x80) && ! (val[0] & 0xffffff00)) || ((val[0] & 0x800000) && ! (val[0] & 0xff000000)))) - output_asm_insn (\"movu %L1,%L0\", operands); + output_asm_insn (\"movu %L1, %L0\", operands); else - output_asm_insn (\"mov %L1,%L0\", operands); + output_asm_insn (\"mov %L1, %L0\", operands); if ((CONST_INT_P (operands[1]) || CONST_DOUBLE_P (operands[1])) @@ -745,7 +873,7 @@ if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS) output_asm_insn (\"mov 0, %H0\", operands); else - output_asm_insn (\"mov %H1,%H0\", operands); + output_asm_insn (\"mov %H1, %H0\", operands); } else if ((CONST_INT_P (operands[1]) || CONST_DOUBLE_P (operands[1])) @@ -757,52 +885,60 @@ == EXTENDED_REGS) && (((val[1] & 0x80) && ! (val[1] & 0xffffff00)) || ((val[1] & 0x800000) && ! (val[1] & 0xff000000)))) - output_asm_insn (\"movu %H1,%H0\", operands); + output_asm_insn (\"movu %H1, %H0\", operands); else - output_asm_insn (\"mov %H1,%H0\", operands); + output_asm_insn (\"mov %H1, %H0\", operands); return \"\"; } default: gcc_unreachable (); } -}" + }" + ;; The timing of "37" is an approximation of the worst case sceanario. + [(set_attr_alternative "timings" + [(const_int 11) + (const_int 22) + (const_int 22) + (const_int 22) + (const_int 22) + (const_int 37) + (const_int 37) + (const_int 37) + (const_int 37) + (const_int 37) + (const_int 37) + (const_int 37) + ]) + ] ) (define_insn "*mn10300_movdf" [(set (match_operand:DF 0 "nonimmediate_operand" - ;; 0 1 2 3 4 5 6 7 8 9 10 - "=dxa,dx,a,dxm,dxm,axm,axm,dx,dx,ax,ax") + ;;0 1 2 3 4 5 6 7 + "=dxa, dax, dxm, dxm, a, a, dx, a") (match_operand:DF 1 "general_operand" - ;; 0 1 2 3 4 5 6 7 8 9 10 - "0,G,G,dx,ax,dx,ax,dxFm,axFm,dxFm,axFm"))] + " 0, G, dx, a, dx, a, Fm, Fm"))] "register_operand (operands[0], DFmode) || register_operand (operands[1], DFmode)" "* -{ - long val[2]; - REAL_VALUE_TYPE rv; + { + long val[2]; + REAL_VALUE_TYPE rv; - switch (which_alternative) - { + switch (which_alternative) + { case 0: return \"nop\"; case 1: - return \"mov 0, %L0\;mov 0, %H0\"; + return \"mov 0, %L0\; mov 0, %H0\"; case 2: - if (rtx_equal_p (operands[0], operands[1])) - return \"sub %L1,%L0\;mov %L0,%H0\"; - else - return \"mov %1,%L0\;mov %L0,%H0\"; case 3: case 4: case 5: case 6: case 7: - case 8: - case 9: - case 10: if (CONST_INT_P (operands[1])) { rtx low, high; @@ -810,7 +946,7 @@ val[0] = INTVAL (low); val[1] = INTVAL (high); } - if (CONST_DOUBLE_P (operands[1])) + if (CONST_DOUBLE_P (operands[1])) { if (GET_MODE (operands[1]) == DFmode) { @@ -837,10 +973,9 @@ if (reg_overlap_mentioned_p (gen_rtx_REG (SImode, REGNO (temp)), XEXP (operands[1], 0))) - return \"mov %H1,%H0\;mov %L1,%L0\"; + return \"mov %H1, %H0\; mov %L1, %L0\"; else - return \"mov %L1,%L0\;mov %H1,%H0\"; - + return \"mov %L1, %L0\; mov %H1, %H0\"; } else if (MEM_P (operands[1]) && CONSTANT_ADDRESS_P (XEXP (operands[1], 0)) @@ -851,7 +986,7 @@ xoperands[0] = operands[0]; xoperands[1] = XEXP (operands[1], 0); - output_asm_insn (\"mov %1,%L0\;mov (4,%L0),%H0\;mov (%L0),%L0\", + output_asm_insn (\"mov %1, %L0\; mov (4, %L0), %H0\; mov (%L0), %L0\", xoperands); return \"\"; } @@ -864,7 +999,7 @@ if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS) output_asm_insn (\"mov 0, %L0\", operands); else - output_asm_insn (\"mov %L1,%L0\", operands); + output_asm_insn (\"mov %L1, %L0\", operands); } else if ((CONST_INT_P (operands[1]) || CONST_DOUBLE_P (operands[1])) @@ -872,9 +1007,9 @@ == EXTENDED_REGS) && (((val[0] & 0x80) && ! (val[0] & 0xffffff00)) || ((val[0] & 0x800000) && ! (val[0] & 0xff000000)))) - output_asm_insn (\"movu %L1,%L0\", operands); + output_asm_insn (\"movu %L1, %L0\", operands); else - output_asm_insn (\"mov %L1,%L0\", operands); + output_asm_insn (\"mov %L1, %L0\", operands); if ((CONST_INT_P (operands[1]) || CONST_DOUBLE_P (operands[1])) @@ -883,29 +1018,40 @@ if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS) output_asm_insn (\"mov 0, %H0\", operands); else - output_asm_insn (\"mov %H1,%H0\", operands); + output_asm_insn (\"mov %H1, %H0\", operands); } else if ((CONST_INT_P (operands[1]) || CONST_DOUBLE_P (operands[1])) && val[0] == val[1]) - output_asm_insn (\"mov %L0,%H0\", operands); + output_asm_insn (\"mov %L0, %H0\", operands); else if ((CONST_INT_P (operands[1]) || CONST_DOUBLE_P (operands[1])) && (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS) && (((val[1] & 0x80) && ! (val[1] & 0xffffff00)) || ((val[1] & 0x800000) && ! (val[1] & 0xff000000)))) - output_asm_insn (\"movu %H1,%H0\", operands); + output_asm_insn (\"movu %H1, %H0\", operands); else - output_asm_insn (\"mov %H1,%H0\", operands); + output_asm_insn (\"mov %H1, %H0\", operands); return \"\"; } default: gcc_unreachable (); } -}" + }" + ;; Timings of "37" is approximation of the worst case sceanario. + [(set_attr_alternative "timings" + [(const_int 11) + (const_int 22) + (const_int 37) + (const_int 37) + (const_int 37) + (const_int 37) + (const_int 37) + (const_int 37) + ]) + ] ) - ;; ---------------------------------------------------------------------- ;; ADD INSTRUCTIONS @@ -1000,7 +1146,8 @@ default: gcc_unreachable (); } -}" + }" + [(set_attr "timings" "11,11,11,11,11,11,22")] ) (define_insn "*mn10300_addsi3" @@ -1045,6 +1192,7 @@ gcc_unreachable (); } }" + [(set_attr "timings" "11,11,11,11,11,22")] ) ;; ---------------------------------------------------------------------- @@ -1062,33 +1210,36 @@ "") (define_insn "*am33_subsi3" - [(set (match_operand:SI 0 "register_operand" "=dax,!dax") + [(set (match_operand:SI 0 "register_operand" "=dax,!dax") (minus:SI (match_operand:SI 1 "register_operand" "0,dax") - (match_operand:SI 2 "nonmemory_operand" "daxi,dax")))] + (match_operand:SI 2 "nonmemory_operand" "daxi,dax"))) + (clobber (reg:CC CC_REG)) + ] "TARGET_AM33" "* -{ - if (true_regnum (operands[0]) == true_regnum (operands[1])) - return \"sub %2,%0\"; - else - { - enum reg_class src1_class, src2_class, dst_class; - - src1_class = REGNO_REG_CLASS (true_regnum (operands[1])); - src2_class = REGNO_REG_CLASS (true_regnum (operands[2])); - dst_class = REGNO_REG_CLASS (true_regnum (operands[0])); - - /* If no extended registers are used, then the best way to handle - this is to copy the first source operand into the destination - and emit a two address subtraction. */ - if (src1_class != EXTENDED_REGS - && src2_class != EXTENDED_REGS - && dst_class != EXTENDED_REGS - && true_regnum (operands[0]) != true_regnum (operands[2])) - return \"mov %1,%0\;sub %2,%0\"; - return \"sub %2,%1,%0\"; - } -}" + { + if (true_regnum (operands[0]) == true_regnum (operands[1])) + return \"sub %2,%0\"; + else + { + enum reg_class src1_class, src2_class, dst_class; + + src1_class = REGNO_REG_CLASS (true_regnum (operands[1])); + src2_class = REGNO_REG_CLASS (true_regnum (operands[2])); + dst_class = REGNO_REG_CLASS (true_regnum (operands[0])); + + /* If no extended registers are used, then the best way to handle + this is to copy the first source operand into the destination + and emit a two address subtraction. */ + if (src1_class != EXTENDED_REGS + && src2_class != EXTENDED_REGS + && dst_class != EXTENDED_REGS + && true_regnum (operands[0]) != true_regnum (operands[2])) + return \"mov %1,%0\;sub %2,%0\"; + return \"sub %2,%1,%0\"; + } + }" + [(set_attr "timings" "11,22")] ) (define_insn "*mn10300_subsi3" @@ -1099,6 +1250,8 @@ ] "" "sub %2,%0" + [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") + (const_int 11) (const_int 22)))] ) (define_expand "negsi2" @@ -1127,16 +1280,20 @@ ] "TARGET_AM33" "mul %1,%2,%H0,%L0" + [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") + (const_int 24) (const_int 23)))] ) (define_insn "umulsidi3" - [(set (match_operand:DI 0 "register_operand" "=dax") + [(set (match_operand:DI 0 "register_operand" "=dax") (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "dax")) (zero_extend:DI (match_operand:SI 2 "register_operand" "dax")))) (clobber (reg:CC CC_REG)) ] "TARGET_AM33" "mulu %1,%2,%H0,%L0" + [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") + (const_int 24) (const_int 23)))] ) (define_expand "mulsi3" @@ -1163,6 +1320,7 @@ else return \"mul %2,%0\"; }" + [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") (const_int 24) (const_int 23)))] ) (define_insn "*mn10300_mulsi3" @@ -1179,13 +1337,15 @@ else return \"mul %2,%0\"; }" + [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") + (const_int 24) (const_int 23)))] ) (define_expand "udivmodsi4" - [(parallel [(set (match_operand:SI 0 "nonimmediate_operand") + [(parallel [(set (match_operand:SI 0 "register_operand") (udiv:SI (match_operand:SI 1 "general_operand") (match_operand:SI 2 "general_operand"))) - (set (match_operand:SI 3 "nonimmediate_operand") + (set (match_operand:SI 3 "register_operand") (umod:SI (match_dup 1) (match_dup 2))) (clobber (reg:CC CC_REG)) ]) @@ -1199,11 +1359,11 @@ }" ) -(define_insn "*udivmodsi4_insn" - [(set (match_operand:SI 0 "nonimmediate_operand" "=dx") +(define_insn "*udivmodsi4" + [(set (match_operand:SI 0 "register_operand" "=dx") (udiv:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "register_operand" "dx"))) - (set (match_operand:SI 3 "nonimmediate_operand" "=&d") + (set (match_operand:SI 3 "register_operand" "=&d") (umod:SI (match_dup 1) (match_dup 2))) (clobber (reg:CC CC_REG)) ] @@ -1217,13 +1377,22 @@ else return \"divu %2,%0\;mov mdr,%3\"; }" + ;; Timings: AM33 AM34 + ;; SUB 1/1 1/1 + ;; MOV 1/1 1/1 + ;; DIVU 38/39 42/43 + ;; MOV 1/1 1/1 + ;; -------------------- + ;; total 41/42 45/46 (worst case sceanario) + [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") + (const_int 4546) (const_int 4142)))] ) (define_insn "divmodsi4" - [(set (match_operand:SI 0 "nonimmediate_operand" "=dx") - (div:SI (match_operand:SI 1 "general_operand" "0") - (match_operand:SI 2 "general_operand" "dx"))) - (set (match_operand:SI 3 "nonimmediate_operand" "=d") + [(set (match_operand:SI 0 "register_operand" "=dx") + (div:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "register_operand" "dx"))) + (set (match_operand:SI 3 "register_operand" "=d") (mod:SI (match_dup 1) (match_dup 2))) (clobber (reg:CC CC_REG)) ] @@ -1235,6 +1404,13 @@ else return \"ext %0\;div %2,%0\;mov mdr,%3\"; }" + ;; Timings: AM33 AM34 + ;; EXT 1/1 1/1 + ;; DIV 38/39 42/43 + ;; -------------------- + ;; total 39/40 43/44 (worst case sceanario) + [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") + (const_int 4344) (const_int 3940)))] ) @@ -1259,44 +1435,40 @@ (clobber (reg:CC CC_REG)) ] "TARGET_AM33" - "* -{ - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0xff) - return \"extbu %0\"; - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0xffff) - return \"exthu %0\"; - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0x7fffffff) - return \"add %0,%0\;lsr 1,%0\"; - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0x3fffffff) - return \"asl2 %0\;lsr 2,%0\"; - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0x1fffffff) - return \"add %0,%0\;asl2 %0\;lsr 3,%0\"; - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0x0fffffff) - return \"asl2 %0\;asl2 %0\;lsr 4,%0\"; - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0xfffffffe) - return \"lsr 1,%0\;add %0,%0\"; - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0xfffffffc) - return \"lsr 2,%0\;asl2 %0\"; - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0xfffffff8) - return \"lsr 3,%0\;add %0,%0\;asl2 %0\"; - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0xfffffff0) - return \"lsr 4,%0\;asl2 %0\;asl2 %0\"; - if (REG_P (operands[2]) && REG_P (operands[1]) - && true_regnum (operands[0]) != true_regnum (operands[1]) - && true_regnum (operands[0]) != true_regnum (operands[2]) - && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS - && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS - && REGNO_REG_CLASS (true_regnum (operands[2])) == DATA_REGS) - return \"mov %1,%0\;and %2,%0\"; - if (REG_P (operands[2]) && REG_P (operands[1]) - && true_regnum (operands[0]) != true_regnum (operands[1]) - && true_regnum (operands[0]) != true_regnum (operands[2])) - return \"and %1,%2,%0\"; - if (REG_P (operands[2]) && REG_P (operands[0]) - && true_regnum (operands[2]) == true_regnum (operands[0])) - return \"and %1,%0\"; - return \"and %2,%0\"; -}" + { + if (CONST_INT_P (operands[2])) + switch (INTVAL (operands[2])) + { + case 0xff: return "extbu %0"; + case 0xffff: return "exthu %0"; + case 0x7fffffff: return "add %0, %0; lsr 1, %0"; + case 0x3fffffff: return "asl2 %0; lsr 2, %0"; + case 0x1fffffff: return "add %0, %0; asl2 %0; lsr 3, %0"; + case 0x0fffffff: return "asl2 %0; asl2 %0; lsr 4, %0"; + case 0xfffffffe: return "lsr 1, %0; add %0, %0"; + case 0xfffffffc: return "lsr 2, %0; asl2 %0"; + case 0xfffffff8: return "lsr 3, %0; add %0, %0; asl2 %0"; + case 0xfffffff0: return "lsr 4, %0; asl2 %0; asl2 %0"; + } + + if (REG_P (operands[2]) && REG_P (operands[1]) + && true_regnum (operands[0]) != true_regnum (operands[1]) + && true_regnum (operands[0]) != true_regnum (operands[2]) + && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS + && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS + && REGNO_REG_CLASS (true_regnum (operands[2])) == DATA_REGS) + return "mov %1, %0; and %2, %0"; + if (REG_P (operands[2]) && REG_P (operands[1]) + && true_regnum (operands[0]) != true_regnum (operands[1]) + && true_regnum (operands[0]) != true_regnum (operands[2])) + return "and %1, %2, %0"; + if (REG_P (operands[2]) && REG_P (operands[0]) + && true_regnum (operands[2]) == true_regnum (operands[0])) + return "and %1, %0"; + + return "and %2, %0"; + } + [(set_attr "timings" "33")] ) (define_insn "*mn10300_andsi3" @@ -1306,30 +1478,25 @@ (clobber (reg:CC CC_REG)) ] "" - "* -{ - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0xff) - return \"extbu %0\"; - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0xffff) - return \"exthu %0\"; - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0x7fffffff) - return \"add %0,%0\;lsr 1,%0\"; - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0x3fffffff) - return \"asl2 %0\;lsr 2,%0\"; - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0x1fffffff) - return \"add %0,%0\;asl2 %0\;lsr 3,%0\"; - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0x0fffffff) - return \"asl2 %0\;asl2 %0\;lsr 4,%0\"; - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0xfffffffe) - return \"lsr 1,%0\;add %0,%0\"; - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0xfffffffc) - return \"lsr 2,%0\;asl2 %0\"; - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0xfffffff8) - return \"lsr 3,%0\;add %0,%0\;asl2 %0\"; - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0xfffffff0) - return \"lsr 4,%0\;asl2 %0\;asl2 %0\"; - return \"and %2,%0\"; -}" + { + if (CONST_INT_P (operands[2])) + switch (INTVAL (operands[2])) + { + case 0xff: return "extbu %0"; + case 0xffff: return "exthu %0"; + case 0x7fffffff: return "add %0, %0; lsr 1, %0"; + case 0x3fffffff: return "asl2 %0; lsr 2, %0"; + case 0x1fffffff: return "add %0, %0; asl2 %0; lsr 3, %0"; + case 0x0fffffff: return "asl2 %0; asl2 %0; lsr 4, %0"; + case 0xfffffffe: return "lsr 1, %0; add %0, %0"; + case 0xfffffffc: return "lsr 2, %0; asl2 %0"; + case 0xfffffff8: return "lsr 3, %0; add %0, %0; asl2 %0"; + case 0xfffffff0: return "lsr 4, %0; asl2 %0; asl2 %0"; + } + + return "and %2, %0"; + } + [(set_attr "timings" "33")] ) ;; ---------------------------------------------------------------------- @@ -1354,33 +1521,35 @@ ] "TARGET_AM33" "* -{ - if (REG_P (operands[2]) && REG_P (operands[1]) - && true_regnum (operands[0]) != true_regnum (operands[1]) - && true_regnum (operands[0]) != true_regnum (operands[2]) - && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS - && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS - && REGNO_REG_CLASS (true_regnum (operands[2])) == DATA_REGS) - return \"mov %1,%0\;or %2,%0\"; - if (REG_P (operands[2]) && REG_P (operands[1]) - && true_regnum (operands[0]) != true_regnum (operands[1]) - && true_regnum (operands[0]) != true_regnum (operands[2])) - return \"or %1,%2,%0\"; - if (REG_P (operands[2]) && REG_P (operands[0]) - && true_regnum (operands[2]) == true_regnum (operands[0])) - return \"or %1,%0\"; - return \"or %2,%0\"; -}" + { + if (REG_P (operands[2]) && REG_P (operands[1]) + && true_regnum (operands[0]) != true_regnum (operands[1]) + && true_regnum (operands[0]) != true_regnum (operands[2]) + && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS + && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS + && REGNO_REG_CLASS (true_regnum (operands[2])) == DATA_REGS) + return \"mov %1,%0\;or %2,%0\"; + if (REG_P (operands[2]) && REG_P (operands[1]) + && true_regnum (operands[0]) != true_regnum (operands[1]) + && true_regnum (operands[0]) != true_regnum (operands[2])) + return \"or %1,%2,%0\"; + if (REG_P (operands[2]) && REG_P (operands[0]) + && true_regnum (operands[2]) == true_regnum (operands[0])) + return \"or %1,%0\"; + return \"or %2,%0\"; + }" + [(set_attr "timings" "22")] ) (define_insn "*mn10300_iorsi3" - [(set (match_operand:SI 0 "register_operand" "=dx") + [(set (match_operand:SI 0 "register_operand" "=dx") (ior:SI (match_operand:SI 1 "register_operand" "%0") (match_operand:SI 2 "nonmemory_operand" "dxi"))) (clobber (reg:CC CC_REG)) ] "" "or %2,%0" + [(set_attr "timings" "33")] ) ;; ---------------------------------------------------------------------- @@ -1398,40 +1567,42 @@ "") (define_insn "*am33_xorsi3" - [(set (match_operand:SI 0 "register_operand" "=dx,!dax") + [(set (match_operand:SI 0 "register_operand" "=dx,!dax") (xor:SI (match_operand:SI 1 "register_operand" "%0,dax") (match_operand:SI 2 "nonmemory_operand" "dxi,dax"))) (clobber (reg:CC CC_REG)) ] "TARGET_AM33" "* -{ - if (REG_P (operands[2]) && REG_P (operands[1]) - && true_regnum (operands[0]) != true_regnum (operands[1]) - && true_regnum (operands[0]) != true_regnum (operands[2]) - && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS - && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS - && REGNO_REG_CLASS (true_regnum (operands[2])) == DATA_REGS) - return \"mov %1,%0\;xor %2,%0\"; - if (REG_P (operands[2]) && REG_P (operands[1]) - && true_regnum (operands[0]) != true_regnum (operands[1]) - && true_regnum (operands[0]) != true_regnum (operands[2])) - return \"xor %1,%2,%0\"; - if (REG_P (operands[2]) && REG_P (operands[0]) - && true_regnum (operands[2]) == true_regnum (operands[0])) - return \"xor %1,%0\"; - return \"xor %2,%0\"; -}" + { + if (REG_P (operands[2]) && REG_P (operands[1]) + && true_regnum (operands[0]) != true_regnum (operands[1]) + && true_regnum (operands[0]) != true_regnum (operands[2]) + && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS + && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS + && REGNO_REG_CLASS (true_regnum (operands[2])) == DATA_REGS) + return \"mov %1,%0\;xor %2,%0\"; + if (REG_P (operands[2]) && REG_P (operands[1]) + && true_regnum (operands[0]) != true_regnum (operands[1]) + && true_regnum (operands[0]) != true_regnum (operands[2])) + return \"xor %1,%2,%0\"; + if (REG_P (operands[2]) && REG_P (operands[0]) + && true_regnum (operands[2]) == true_regnum (operands[0])) + return \"xor %1,%0\"; + return \"xor %2,%0\"; + }" + [(set_attr "timings" "22")] ) (define_insn "*mn10300_xorsi3" - [(set (match_operand:SI 0 "register_operand" "=dx") + [(set (match_operand:SI 0 "register_operand" "=dx") (xor:SI (match_operand:SI 1 "register_operand" "%0") (match_operand:SI 2 "nonmemory_operand" "dxi"))) (clobber (reg:CC CC_REG)) ] "" "xor %2,%0" + [(set_attr "timings" "11")] ) ;; ---------------------------------------------------------------------- @@ -1484,17 +1655,29 @@ "@ bclr 255,%A0 clr %0" + [(set_attr_alternative "timings" + [(if_then_else (eq_attr "cpu" "am34") + (const_int 66) (const_int 77)) + (const_int 11) + ]) + ] ) (define_insn "*byte_set" [(set (match_operand:QI 0 "nonimmediate_operand" "=R,d") (const_int -1)) (clobber (reg:CC CC_REG)) ] - "( ! MEM_P (operands[0])) || (! MEM_VOLATILE_P (operands[0]) - && GET_CODE (XEXP (operands[0], 0)) != PLUS)" + "(! MEM_P (operands[0])) || (! MEM_VOLATILE_P (operands[0]) + && GET_CODE (XEXP (operands[0], 0)) != PLUS)" "@ bset 255,%A0 mov -1,%0" + [(set_attr_alternative "timings" + [(if_then_else (eq_attr "cpu" "am34") + (const_int 66) (const_int 77)) + (const_int 11) + ]) + ] ) (define_insn "*bit_clear1" @@ -1508,6 +1691,12 @@ "@ bclr %N1,%A0 and %1,%0" + [(set_attr_alternative "timings" + [(if_then_else (eq_attr "cpu" "am34") + (const_int 66) (const_int 77)) + (const_int 11) + ]) + ] ) (define_insn "*bit_clear2" @@ -1521,6 +1710,12 @@ "@ bclr %U1,%A0 bclr %1,%0" + [(set_attr_alternative "timings" + [(if_then_else (eq_attr "cpu" "am34") + (const_int 66) (const_int 77)) + (const_int 66) + ]) + ] ) (define_insn "*bit_set" @@ -1534,6 +1729,12 @@ "@ bset %U1,%A0 or %1,%0" + [(set_attr_alternative "timings" + [(if_then_else (eq_attr "cpu" "am34") + (const_int 66) (const_int 77)) + (const_int 11) + ]) + ] ) (define_expand "iorqi3" @@ -1547,12 +1748,12 @@ "") (define_insn "*am33_iorqi3" - [(set (match_operand:QI 0 "nonimmediate_operand" "=R,T,r") + [(set (match_operand:QI 0 "nonimmediate_operand" "=R,T,r") (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") ;; This constraint should really be nonmemory_operand, ;; but making it general_operand, along with the - ;; condition that not both input operands are MEMs, it - ;; here helps combine do a better job. + ;; condition that not both input operands are MEMs, + ;; helps combine do a better job. (match_operand:QI 2 "general_operand" "i,d,ir"))) (clobber (reg:CC CC_REG)) ] @@ -1562,15 +1763,22 @@ bset %U2,%A0 bset %2,%0 or %2,%0" + [(set_attr_alternative "timings" + [(if_then_else (eq_attr "cpu" "am34") + (const_int 66) (const_int 77)) + (const_int 66) + (const_int 11) + ]) + ] ) (define_insn "*mn10300_iorqi3" - [(set (match_operand:QI 0 "nonimmediate_operand" "=R,T,d") + [(set (match_operand:QI 0 "nonimmediate_operand" "=R,T,d") (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") ;; This constraint should really be nonmemory_operand, ;; but making it general_operand, along with the - ;; condition that not both input operands are MEMs, it - ;; here helps combine do a better job. + ;; condition that not both input operands are MEMs, + ;; helps combine do a better job. (match_operand:QI 2 "general_operand" "i,d,id"))) (clobber (reg:CC CC_REG)) ] @@ -1579,6 +1787,13 @@ bset %U2,%A0 bset %2,%0 or %2,%0" + [(set_attr_alternative "timings" + [(if_then_else (eq_attr "cpu" "am34") + (const_int 66) (const_int 77)) + (const_int 66) + (const_int 11) + ]) + ] ) (define_insn "*test_int_bitfield" @@ -1611,7 +1826,7 @@ (define_insn "*test_byte_bitfield" [(set (reg:CC CC_REG) - (compare (zero_extract:SI (match_operand:QI 0 "general_operand" "R,dx") + (compare (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "R,dx") (match_operand 1 "const_int_operand" "") (match_operand 2 "const_int_operand" "")) (const_int 0)))] @@ -1653,6 +1868,13 @@ output_asm_insn (\"btst %U1,%A0\", xoperands); return \"\"; }" + [(set_attr_alternative "timings" + [(if_then_else (eq_attr "cpu" "am34") + (const_int 11) (const_int 22)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 44) (const_int 55)) + ]) + ] ) (define_insn "*bit_test" @@ -1663,18 +1885,27 @@ ] "" "btst %1,%0" + [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") + (const_int 11) (const_int 22)))] ) (define_insn "*subreg_bit_test" [(set (reg:CC CC_REG) (compare (and:SI - (subreg:SI (match_operand:QI 0 "general_operand" "R,dx") 0) + (subreg:SI (match_operand:QI 0 "nonimmediate_operand" "R,dx") 0) (match_operand:SI 1 "const_8bit_operand" "")) (const_int 0)))] "" "@ btst %U1,%A0 btst %1,%0" + [(set_attr_alternative "timings" + [(if_then_else (eq_attr "cpu" "am34") + (const_int 44) (const_int 55)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 11) (const_int 22)) + ]) + ] ) @@ -1750,11 +1981,19 @@ return mn10300_output_cmp (operands[0], insn); return \"cmp %1,%0\"; } + [(set_attr_alternative "timings" + [(const_int 11) + (if_then_else (eq_attr "cpu" "am34") + (const_int 11) (const_int 22)) + (const_int 22) + ]) + ] ) (define_insn "integer_conditional_branch" [(set (pc) - (if_then_else (match_operator 0 "comparison_operator" [(reg:CC CC_REG) (const_int 0)]) + (if_then_else (match_operator 0 "comparison_operator" + [(reg:CC CC_REG) (const_int 0)]) (label_ref (match_operand 1 "" "")) (pc)))] "" @@ -1805,6 +2044,8 @@ (match_operand:SF 1 "nonmemory_operand" "fF")))] "TARGET_AM33_2" "fcmp %1, %0" + [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") + (const_int 17) (const_int 25)))] ) (define_insn "float_conditional_branch" @@ -1815,6 +2056,8 @@ (pc)))] "TARGET_AM33_2" "fb%b0 %1" + [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") + (const_int 44) (const_int 33)))] ) ;; Unconditional and other jump instructions. @@ -1824,12 +2067,16 @@ (label_ref (match_operand 0 "" "")))] "" "jmp %l0" + [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") + (const_int 11) (const_int 44)))] ) (define_insn "indirect_jump" [(set (pc) (match_operand:SI 0 "register_operand" "a"))] "" "jmp (%0)" + [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") + (const_int 11) (const_int 33)))] ) (define_expand "builtin_setjmp_receiver" @@ -1876,6 +2123,8 @@ (use (label_ref (match_operand 1 "" "")))] "" "jmp (%0)" + [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") + (const_int 11) (const_int 33)))] ) ;; Call subroutine with no return value. @@ -1909,16 +2158,19 @@ ;; NB: Mode on match_operand 0 deliberately omitted in ;; order to be able to match UNSPECs in PIC mode. (define_insn "call_internal" - [(call (mem:QI (match_operand 0 "call_address_operand" "aS")) - (match_operand:SI 1 "general_operand" "g"))] + [(call (mem:QI (match_operand 0 "call_address_operand" "a,S")) + (match_operand:SI 1 "general_operand" "g,g"))] "" - "* -{ - if (REG_P (operands[0])) - return \"calls %C0\"; - else - return \"call %C0,[],0\"; -}" + "@ + calls %C0 + call %C0,[],0" + [(set_attr_alternative "timings" + [(if_then_else (eq_attr "cpu" "am34") + (const_int 33) (const_int 44)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 55) (const_int 33)) + ]) + ] ) ;; Call subroutine, returning value in operand 0 @@ -1956,17 +2208,20 @@ ;; NB: Mode on match_operands 0 and 1 deliberately omitted ;; in order to be able to match UNSPECs in PIC mode. (define_insn "call_value_internal" - [(set (match_operand 0 "register_operand" "=dax") - (call (mem:QI (match_operand 1 "call_address_operand" "aS")) - (match_operand:SI 2 "general_operand" "g")))] + [(set (match_operand 0 "register_operand" "=dax,dax") + (call (mem:QI (match_operand 1 "call_address_operand" "a,S")) + (match_operand:SI 2 "general_operand" "g,g")))] "" - "* -{ - if (REG_P (operands[1])) - return \"calls %C1\"; - else - return \"call %C1,[],0\"; -}" + "@ + calls %C1 + call %C1,[],0" + [(set_attr_alternative "timings" + [(if_then_else (eq_attr "cpu" "am34") + (const_int 33) (const_int 44)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 55) (const_int 33)) + ]) + ] ) (define_expand "untyped_call" @@ -2000,16 +2255,16 @@ ;; ---------------------------------------------------------------------- (define_expand "zero_extendqisi2" - [(set (match_operand:SI 0 "general_operand") + [(set (match_operand:SI 0 "register_operand") (zero_extend:SI - (match_operand:QI 1 "general_operand")))] + (match_operand:QI 1 "nonimmediate_operand")))] "" "") -(define_insn "" - [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,dx,!dax,!dax,!dax") +(define_insn "*zero_extendqisi2_am33" + [(set (match_operand:SI 0 "register_operand" "=dx,dx,dx,!dax,!dax,!dax") (zero_extend:SI - (match_operand:QI 1 "general_operand" "0,dax,m,0,dax,m")))] + (match_operand:QI 1 "nonimmediate_operand" "0,dax,m,0,dax,m")))] "TARGET_AM33" "@ extbu %0 @@ -2018,30 +2273,48 @@ extbu %0 mov %1,%0\;extbu %0 movbu %1,%0" + [(set_attr_alternative "timings" + [(const_int 11) + (const_int 22) + (if_then_else (eq_attr "cpu" "am34") + (const_int 13) (const_int 24)) + (const_int 11) + (const_int 22) + (if_then_else (eq_attr "cpu" "am34") + (const_int 13) (const_int 24)) + ]) + ] ) -(define_insn "" - [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,dx") +(define_insn "*zero_extendqisi2_mn10300" + [(set (match_operand:SI 0 "register_operand" "=dx,dx,dx") (zero_extend:SI - (match_operand:QI 1 "general_operand" "0,d,m")))] + (match_operand:QI 1 "nonimmediate_operand" "0,d,m")))] "" "@ extbu %0 mov %1,%0\;extbu %0 movbu %1,%0" + [(set_attr_alternative "timings" + [(const_int 11) + (const_int 22) + (if_then_else (eq_attr "cpu" "am34") + (const_int 13) (const_int 24)) + ]) + ] ) (define_expand "zero_extendhisi2" - [(set (match_operand:SI 0 "general_operand") + [(set (match_operand:SI 0 "register_operand") (zero_extend:SI - (match_operand:HI 1 "general_operand")))] + (match_operand:HI 1 "nonimmediate_operand")))] "" "") -(define_insn "" - [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,dx,!dax,!dax,!dax") +(define_insn "*zero_extendhisi2_am33" + [(set (match_operand:SI 0 "register_operand" "=dx,dx,dx,!dax,!dax,!dax") (zero_extend:SI - (match_operand:HI 1 "general_operand" "0,dax,m,0,dax,m")))] + (match_operand:HI 1 "nonimmediate_operand" "0,dax,m,0,dax,m")))] "TARGET_AM33" "@ exthu %0 @@ -2050,77 +2323,99 @@ exthu %0 mov %1,%0\;exthu %0 movhu %1,%0" + [(set_attr_alternative "timings" + [(const_int 11) + (const_int 22) + (if_then_else (eq_attr "cpu" "am34") + (const_int 13) (const_int 24)) + (const_int 11) + (const_int 22) + (if_then_else (eq_attr "cpu" "am34") + (const_int 13) (const_int 24)) + ]) + ] ) -(define_insn "" - [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,dx") +(define_insn "*zero_extendhisi2_mn10300" + [(set (match_operand:SI 0 "register_operand" "=dx,dx,dx") (zero_extend:SI - (match_operand:HI 1 "general_operand" "0,dx,m")))] + (match_operand:HI 1 "nonimmediate_operand" "0,dx,m")))] "" "@ exthu %0 mov %1,%0\;exthu %0 movhu %1,%0" + [(set_attr_alternative "timings" + [(const_int 11) + (const_int 22) + (if_then_else (eq_attr "cpu" "am34") + (const_int 13) (const_int 24)) + ]) + ] ) ;;- sign extension instructions (define_expand "extendqisi2" - [(set (match_operand:SI 0 "general_operand") + [(set (match_operand:SI 0 "register_operand") (sign_extend:SI - (match_operand:QI 1 "general_operand")))] + (match_operand:QI 1 "register_operand")))] "" "") -(define_insn "" - [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,!dax,!dax") +(define_insn "*extendqisi2_am33" + [(set (match_operand:SI 0 "register_operand" "=dx,dx,!dax,!dax") (sign_extend:SI - (match_operand:QI 1 "general_operand" "0,dx,0,dax")))] + (match_operand:QI 1 "register_operand" "0,dx,0,dax")))] "TARGET_AM33" "@ extb %0 mov %1,%0\;extb %0 extb %0 mov %1,%0\;extb %0" + [(set_attr "timings" "11,22,11,22")] ) -(define_insn "" - [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx") +(define_insn "*extendqisi2_mn10300" + [(set (match_operand:SI 0 "register_operand" "=dx,dx") (sign_extend:SI - (match_operand:QI 1 "general_operand" "0,dx")))] + (match_operand:QI 1 "register_operand" "0,dx")))] "" "@ extb %0 mov %1,%0\;extb %0" + [(set_attr "timings" "11,22")] ) (define_expand "extendhisi2" - [(set (match_operand:SI 0 "general_operand") + [(set (match_operand:SI 0 "register_operand") (sign_extend:SI - (match_operand:HI 1 "general_operand")))] + (match_operand:HI 1 "register_operand")))] "" "") -(define_insn "" - [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx,!dax,!dax") +(define_insn "*extendhisi2_am33" + [(set (match_operand:SI 0 "register_operand" "=dx,dx,!dax,!dax") (sign_extend:SI - (match_operand:HI 1 "general_operand" "0,dax,0,dax")))] + (match_operand:HI 1 "register_operand" "0,dax,0,dax")))] "TARGET_AM33" "@ exth %0 mov %1,%0\;exth %0 exth %0 mov %1,%0\;exth %0" + [(set_attr "timings" "11,22,11,22")] ) -(define_insn "" - [(set (match_operand:SI 0 "nonimmediate_operand" "=dx,dx") +(define_insn "*extendhisi2_mn10300" + [(set (match_operand:SI 0 "register_operand" "=dx,dx") (sign_extend:SI - (match_operand:HI 1 "general_operand" "0,dx")))] + (match_operand:HI 1 "register_operand" "0,dx")))] "" "@ exth %0 mov %1,%0\;exth %0" + [(set_attr "timings" "11,22")] ) ;; ---------------------------------------------------------------------- @@ -2147,30 +2442,31 @@ ] "TARGET_AM33" "* -{ - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1) - return \"add %0,%0\"; + { + if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1) + return \"add %0,%0\"; - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 2) - return \"asl2 %0\"; + if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 2) + return \"asl2 %0\"; - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 3 - && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS) - return \"asl2 %0\;add %0,%0\"; + if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 3 + && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS) + return \"asl2 %0\;add %0,%0\"; - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 4 - && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS) - return \"asl2 %0\;asl2 %0\"; + if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 4 + && REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS) + return \"asl2 %0\;asl2 %0\"; - if (true_regnum (operands[1]) == true_regnum (operands[0])) - return \"asl %S2,%0\"; + if (true_regnum (operands[1]) == true_regnum (operands[0])) + return \"asl %S2,%0\"; - if (REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS - && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS - && true_regnum (operands[0]) != true_regnum (operands[2])) - return \"mov %1,%0\;asl %S2,%0\"; - return \"asl %2,%1,%0\"; -}" + if (REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS + && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS + && true_regnum (operands[0]) != true_regnum (operands[2])) + return \"mov %1,%0\;asl %S2,%0\"; + return \"asl %2,%1,%0\"; + }" + [(set_attr "timings" "22")] ) (define_insn "*mn10300_ashlsi3" @@ -2187,6 +2483,7 @@ asl2 %0\;add %0,%0 asl2 %0\;asl2 %0 asl %S2,%0" + [(set_attr "timings" "11,11,22,22,11")] ) (define_expand "lshrsi3" @@ -2209,16 +2506,17 @@ ] "TARGET_AM33" "* -{ - if (true_regnum (operands[1]) == true_regnum (operands[0])) - return \"lsr %S2,%0\"; - - if (REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS - && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS - && true_regnum (operands[0]) != true_regnum (operands[2])) - return \"mov %1,%0\;lsr %S2,%0\"; - return \"lsr %2,%1,%0\"; -}" + { + if (true_regnum (operands[1]) == true_regnum (operands[0])) + return \"lsr %S2,%0\"; + + if (REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS + && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS + && true_regnum (operands[0]) != true_regnum (operands[2])) + return \"mov %1,%0\;lsr %S2,%0\"; + return \"lsr %2,%1,%0\"; + }" + [(set_attr "timings" "22")] ) (define_insn "*mn10300_lshrsi3" @@ -2230,6 +2528,8 @@ ] "" "lsr %S2,%0" + [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") + (const_int 11) (const_int 22)))] ) (define_expand "ashrsi3" @@ -2252,16 +2552,17 @@ ] "TARGET_AM33" "* -{ - if (true_regnum (operands[1]) == true_regnum (operands[0])) - return \"asr %S2,%0\"; - - if (REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS - && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS - && true_regnum (operands[0]) != true_regnum (operands[2])) - return \"mov %1,%0\;asr %S2,%0\"; - return \"asr %2,%1,%0\"; -}" + { + if (true_regnum (operands[1]) == true_regnum (operands[0])) + return \"asr %S2,%0\"; + + if (REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS + && REGNO_REG_CLASS (true_regnum (operands[1])) == DATA_REGS + && true_regnum (operands[0]) != true_regnum (operands[2])) + return \"mov %1,%0\;asr %S2,%0\"; + return \"asr %2,%1,%0\"; + }" + [(set_attr "timings" "22")] ) (define_insn "*mn10300_ashrsi3" @@ -2273,6 +2574,8 @@ ] "" "asr %S2,%0" + [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") + (const_int 11) (const_int 22)))] ) ;; ---------------------------------------------------------------------- @@ -2352,6 +2655,8 @@ "@ fabs %0 fabs %1, %0" + [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") + (const_int 17) (const_int 14)))] ) (define_expand "negdf2" @@ -2421,6 +2726,8 @@ "@ fneg %0 fneg %1, %0" + [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") + (const_int 17) (const_int 14)))] ) (define_expand "sqrtsf2" @@ -2431,13 +2738,13 @@ ] "TARGET_AM33_2 && flag_unsafe_math_optimizations" " -{ - rtx scratch = gen_reg_rtx (SFmode); - emit_insn (gen_rsqrtsf2 (scratch, operands[1], CONST1_RTX (SFmode))); - emit_insn (gen_divsf3 (operands[0], force_reg (SFmode, CONST1_RTX (SFmode)), - scratch)); - DONE; -}") + { + rtx scratch = gen_reg_rtx (SFmode); + emit_insn (gen_rsqrtsf2 (scratch, operands[1], CONST1_RTX (SFmode))); + emit_insn (gen_divsf3 (operands[0], force_reg (SFmode, CONST1_RTX (SFmode)), + scratch)); + DONE; + }") (define_insn "rsqrtsf2" [(set (match_operand:SF 0 "register_operand" "=f,f") @@ -2449,6 +2756,8 @@ "@ frsqrt %0 frsqrt %1, %0" + [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") + (const_int 4753) (const_int 2327)))] ) (define_expand "addsf3" @@ -2471,6 +2780,13 @@ "@ fadd %2, %0 fadd %2, %1, %0" + [(set_attr_alternative "timings" + [(if_then_else (eq_attr "cpu" "am34") + (const_int 17) (const_int 14)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 17) (const_int 25)) + ]) + ] ) (define_expand "subsf3" @@ -2493,6 +2809,13 @@ "@ fsub %2, %0 fsub %2, %1, %0" + [(set_attr_alternative "timings" + [(if_then_else (eq_attr "cpu" "am34") + (const_int 17) (const_int 14)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 17) (const_int 25)) + ]) + ] ) (define_expand "mulsf3" @@ -2515,6 +2838,13 @@ "@ fmul %2, %0 fmul %2, %1, %0" + [(set_attr_alternative "timings" + [(if_then_else (eq_attr "cpu" "am34") + (const_int 17) (const_int 14)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 17) (const_int 25)) + ]) + ] ) (define_insn "divsf3" @@ -2527,6 +2857,13 @@ "@ fdiv %2, %0 fdiv %2, %1, %0" + [(set_attr_alternative "timings" + [(if_then_else (eq_attr "cpu" "am34") + (const_int 2531) (const_int 1216)) + (if_then_else (eq_attr "cpu" "am34") + (const_int 2531) (const_int 1317)) + ]) + ] ) (define_insn "fmaddsf4" @@ -2538,6 +2875,8 @@ ] "TARGET_AM33_2" "fmadd %1, %2, %3, %0" + [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") + (const_int 17) (const_int 24)))] ) (define_insn "fmsubsf4" @@ -2549,6 +2888,8 @@ ] "TARGET_AM33_2" "fmsub %1, %2, %3, %0" + [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") + (const_int 17) (const_int 24)))] ) (define_insn "fnmaddsf4" @@ -2560,6 +2901,8 @@ ] "TARGET_AM33_2" "fnmadd %1, %2, %3, %0" + [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") + (const_int 17) (const_int 24)))] ) (define_insn "fnmsubsf4" @@ -2571,6 +2914,8 @@ ] "TARGET_AM33_2" "fnmsub %1, %2, %3, %0" + [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") + (const_int 17) (const_int 24)))] ) ;; ---------------------------------------------------------------------- @@ -2585,16 +2930,17 @@ [(return)] "" " -{ - mn10300_expand_epilogue (); - DONE; -}") + { + mn10300_expand_epilogue (); + DONE; + }") (define_insn "return_internal" [(const_int 2) (return)] "" "rets" + [(set_attr "timings" "66")] ) ;; This insn restores the callee saved registers and does a return, it @@ -2605,12 +2951,15 @@ (return)] "" "* -{ - fputs (\"\\tret \", asm_out_file); - mn10300_print_reg_list (asm_out_file, mn10300_get_live_callee_saved_regs ()); - fprintf (asm_out_file, \",%d\\n\", (int) INTVAL (operands[0])); - return \"\"; -}" + { + fputs (\"\\tret \", asm_out_file); + mn10300_print_reg_list (asm_out_file, mn10300_get_live_callee_saved_regs ()); + fprintf (asm_out_file, \",%d\\n\", (int) INTVAL (operands[0])); + return \"\"; + }" + ;; Assumes that there will be no more than 8 regs to pop + [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") + (const_int 1414) (const_int 1313)))] ) ;; This instruction matches one generated by mn10300_gen_multiple_store() @@ -2619,14 +2968,17 @@ [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand 1 "" "")))])] "" "* -{ - fputs (\"\\tmovm \", asm_out_file); - mn10300_print_reg_list (asm_out_file, - mn10300_store_multiple_operation (operands[0], - VOIDmode)); - fprintf (asm_out_file, \",(sp)\\n\"); - return \"\"; -}" + { + fputs (\"\\tmovm \", asm_out_file); + mn10300_print_reg_list (asm_out_file, + mn10300_store_multiple_operation (operands[0], + VOIDmode)); + fprintf (asm_out_file, \",(sp)\\n\"); + return \"\"; + }" + ;; Assume that no more than 8 registers will be pushed. + [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") + (const_int 99) (const_int 88)))] ) (define_insn "return" @@ -2643,6 +2995,7 @@ else return \"rets\"; }" + [(set_attr "timings" "66")] ) ;; Try to combine consecutive updates of the stack pointer (or any @@ -2727,7 +3080,9 @@ [(set (mem:SI (reg:SI SP_REG)) (pc)) (use (match_operand 0 "" ""))])] "reload_completed" - "calls %0\;%0:") + "calls %0\;%0:" + [(set_attr "timings" "44")] +) (define_expand "add_GOT_to_pic_reg" [(parallel [(set (reg:SI PIC_REG) |