diff options
Diffstat (limited to 'gcc/config/rs6000/rs6000.md')
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 107 |
1 files changed, 68 insertions, 39 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 99edc3797ed..9c6f08847af 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -64,7 +64,7 @@ ;; Define an insn type attribute. This is used in function unit delay ;; computations. -(define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv" +(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv" (const_string "integer")) ;; Length (in bytes). @@ -1976,7 +1976,8 @@ (match_operand:SI 2 "exact_log2_cint_operand" "N")))] "" "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0" - [(set_attr "length" "8")]) + [(set_attr "type" "two") + (set_attr "length" "8")]) (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") @@ -5483,7 +5484,8 @@ ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\" : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\"; }" - [(set_attr "length" "8")]) + [(set_attr "type" "two") + (set_attr "length" "8")]) (define_insn "*subdi3_noppc64" [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r") @@ -5501,7 +5503,8 @@ ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\" : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\"; }" - [(set_attr "length" "8")]) + [(set_attr "type" "two") + (set_attr "length" "8")]) (define_insn "*negdi2_noppc64" [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") @@ -5513,7 +5516,8 @@ ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\" : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\"; }" - [(set_attr "length" "8")]) + [(set_attr "type" "two") + (set_attr "length" "8")]) (define_expand "mulsidi3" [(set (match_operand:DI 0 "gpc_reg_operand" "") @@ -5796,7 +5800,8 @@ "@ {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2" - [(set_attr "length" "8,12")]) + [(set_attr "type" "two,three") + (set_attr "length" "8,12")]) (define_insn "*ashrdisi3_noppc64" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -6353,7 +6358,8 @@ (match_operand:DI 2 "exact_log2_cint_operand" "N")))] "TARGET_POWERPC64" "sradi %0,%1,%p2\;addze %0,%0" - [(set_attr "length" "8")]) + [(set_attr "type" "two") + (set_attr "length" "8")]) (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") @@ -6812,8 +6818,7 @@ (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")))] "TARGET_POWERPC64" - "sld%I2 %0,%1,%H2" - [(set_attr "length" "8")]) + "sld%I2 %0,%1,%H2") (define_insn "*ashldi3_internal2" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") @@ -8184,7 +8189,7 @@ return \"#\"; } }" - [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*") + [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*") (set_attr "length" "8,16,16,4,4,4,8,12,16")]) (define_insn "*movdf_softfloat32" @@ -8225,7 +8230,7 @@ return \"#\"; } }" - [(set_attr "type" "*,load,store,*,*,*") + [(set_attr "type" "two,load,store,*,*,*") (set_attr "length" "8,8,8,8,12,16")]) ; ld/std require word-aligned displacements -> 'Y' constraint. @@ -11558,7 +11563,8 @@ {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" - [(set_attr "length" "12,8,12,12,12")]) + [(set_attr "type" "three,two,three,three,three") + (set_attr "length" "12,8,12,12,12")]) (define_insn "" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") @@ -11572,7 +11578,8 @@ xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0" - [(set_attr "length" "12,8,12,12,12")]) + [(set_attr "type" "three,two,three,three,three") + (set_attr "length" "12,8,12,12,12")]) (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") @@ -11685,7 +11692,8 @@ {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" - [(set_attr "length" "12,8,12,12,12")]) + [(set_attr "type" "three,two,three,three,three") + (set_attr "length" "12,8,12,12,12")]) (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") @@ -11784,7 +11792,8 @@ {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" - [(set_attr "length" "12,8,12,12,12")]) + [(set_attr "type" "three,two,three,three,three") + (set_attr "length" "12,8,12,12,12")]) ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power, ;; since it nabs/sr is just as fast. @@ -11795,7 +11804,8 @@ (clobber (match_scratch:SI 2 "=&r"))] "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL" "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" - [(set_attr "length" "8")]) + [(set_attr "type" "two") + (set_attr "length" "8")]) (define_insn "" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") @@ -11804,7 +11814,8 @@ (clobber (match_scratch:DI 2 "=&r"))] "TARGET_64BIT" "addic %2,%1,-1\;subfe %0,%2,%1" - [(set_attr "length" "8")]) + [(set_attr "type" "two") + (set_attr "length" "8")]) ;; This is what (plus (ne X (const_int 0)) Y) looks like. (define_insn "" @@ -11816,7 +11827,8 @@ (clobber (match_scratch:SI 3 "=&r"))] "TARGET_32BIT" "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" - [(set_attr "length" "8")]) + [(set_attr "type" "two") + (set_attr "length" "8")]) (define_insn "" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") @@ -11827,7 +11839,8 @@ (clobber (match_scratch:DI 3 "=&r"))] "TARGET_64BIT" "addic %3,%1,-1\;addze %0,%2" - [(set_attr "length" "8")]) + [(set_attr "type" "two") + (set_attr "length" "8")]) (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") @@ -12127,7 +12140,8 @@ (match_operand:SI 2 "reg_or_short_operand" "rI")))] "TARGET_32BIT" "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" - [(set_attr "length" "12")]) + [(set_attr "type" "three") + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") @@ -12135,7 +12149,8 @@ (match_operand:DI 2 "reg_or_short_operand" "rI")))] "TARGET_64BIT" "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0" - [(set_attr "length" "12")]) + [(set_attr "type" "three") + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") @@ -12206,7 +12221,8 @@ (match_operand:SI 3 "gpc_reg_operand" "r")))] "TARGET_32BIT" "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3" - [(set_attr "length" "8")]) + [(set_attr "type" "two") + (set_attr "length" "8")]) (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") @@ -12279,7 +12295,8 @@ (match_operand:SI 2 "reg_or_short_operand" "rI"))))] "TARGET_32BIT" "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" - [(set_attr "length" "12")]) + [(set_attr "type" "three") + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") @@ -12289,7 +12306,8 @@ (match_operand:SI 3 "gpc_reg_operand" "r")))] "TARGET_32BIT" "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" - [(set_attr "length" "12")]) + [(set_attr "type" "three") + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") @@ -12638,7 +12656,7 @@ "@ {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" - [(set_attr "type" "insert_word") + [(set_attr "type" "two") (set_attr "length" "8")]) (define_insn "" @@ -12649,7 +12667,7 @@ "@ {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" - [(set_attr "type" "insert_word") + [(set_attr "type" "two") (set_attr "length" "8")]) (define_insn "" @@ -12785,7 +12803,8 @@ "@ {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" - [(set_attr "length" "12")]) + [(set_attr "type" "three") + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") @@ -12795,7 +12814,8 @@ "@ subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0" - [(set_attr "length" "12")]) + [(set_attr "type" "three") + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") @@ -12872,7 +12892,8 @@ "@ {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3" - [(set_attr "length" "8")]) + [(set_attr "type" "two") + (set_attr "length" "8")]) (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") @@ -12951,7 +12972,8 @@ "@ {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0" - [(set_attr "length" "12")]) + [(set_attr "type" "three") + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") @@ -12963,7 +12985,8 @@ "@ {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" - [(set_attr "length" "12")]) + [(set_attr "type" "three") + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") @@ -13044,7 +13067,8 @@ (const_int 0)))] "TARGET_32BIT" "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31" - [(set_attr "length" "12")]) + [(set_attr "type" "three") + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") @@ -13052,7 +13076,8 @@ (const_int 0)))] "TARGET_64BIT" "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63" - [(set_attr "length" "12")]) + [(set_attr "type" "three") + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") @@ -13162,7 +13187,8 @@ (match_operand:SI 2 "gpc_reg_operand" "r")))] "TARGET_32BIT" "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2" - [(set_attr "length" "12")]) + [(set_attr "type" "three") + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") @@ -13171,7 +13197,8 @@ (match_operand:DI 2 "gpc_reg_operand" "r")))] "TARGET_64BIT" "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2" - [(set_attr "length" "12")]) + [(set_attr "type" "three") + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") @@ -13382,7 +13409,8 @@ (const_int 0))))] "TARGET_32BIT" "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31" - [(set_attr "length" "12")]) + [(set_attr "type" "three") + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") @@ -13390,7 +13418,8 @@ (const_int 0))))] "TARGET_64BIT" "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63" - [(set_attr "length" "12")]) + [(set_attr "type" "three") + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -13652,7 +13681,7 @@ (match_operand:SI 2 "reg_or_short_operand" "rI"))))] "TARGET_32BIT" "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" - [(set_attr "type" "insert_word") + [(set_attr "type" "two") (set_attr "length" "8")]) (define_insn "" @@ -13661,7 +13690,7 @@ (match_operand:DI 2 "reg_or_short_operand" "rI"))))] "TARGET_64BIT" "subf%I2c %0,%1,%2\;subfe %0,%0,%0" - [(set_attr "type" "insert_word") + [(set_attr "type" "two") (set_attr "length" "8")]) ;; Define both directions of branch and return. If we need a reload |