diff options
Diffstat (limited to 'gcc/config/rs6000/rs6000.md')
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 76 |
1 files changed, 59 insertions, 17 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 7a5bce5b931..d83538ba625 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -14017,6 +14017,36 @@ "mtvrsave %1" [(set_attr "type" "altivec")]) +;; Vector clears +(define_insn "*movv4si_const0" + [(set (match_operand:V4SI 0 "altivec_register_operand" "=v") + (match_operand:V4SI 1 "zero_constant" ""))] + "TARGET_ALTIVEC" + "vxor %0,%0,%0" + [(set_attr "type" "vecsimple")]) + +(define_insn "*movv4sf_const0" + [(set (match_operand:V4SF 0 "altivec_register_operand" "=v") + (match_operand:V4SF 1 "zero_constant" ""))] + + "TARGET_ALTIVEC" + "vxor %0,%0,%0" + [(set_attr "type" "vecsimple")]) + +(define_insn "*movv8hi_const0" + [(set (match_operand:V8HI 0 "altivec_register_operand" "=v") + (match_operand:V8HI 1 "zero_constant" ""))] + "TARGET_ALTIVEC" + "vxor %0,%0,%0" + [(set_attr "type" "vecsimple")]) + +(define_insn "*movv16qi_const0" + [(set (match_operand:V16QI 0 "altivec_register_operand" "=v") + (match_operand:V16QI 1 "zero_constant" ""))] + "TARGET_ALTIVEC" + "vxor %0,%0,%0" + [(set_attr "type" "vecsimple")]) + ;; Simple binary operations. (define_insn "addv16qi3" @@ -15481,49 +15511,61 @@ "lvsr %0,%1,%2" [(set_attr "type" "vecload")]) +;; Parallel some of the LVE* and STV*'s with unspecs because some have +;; identical rtl but different instructions-- and gcc gets confused. + (define_insn "altivec_lvebx" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:SI 1 "register_operand" "b") - (match_operand:SI 2 "register_operand" "r")] 196))] + [(parallel + [(set (match_operand:V16QI 0 "register_operand" "=v") + (mem:V16QI (plus:SI (match_operand:SI 1 "register_operand" "b") + (match_operand:SI 2 "register_operand" "r")))) + (unspec [(const_int 0)] 196)])] "TARGET_ALTIVEC" "lvebx %0,%1,%2" [(set_attr "type" "vecload")]) (define_insn "altivec_lvehx" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:SI 1 "register_operand" "b") - (match_operand:SI 2 "register_operand" "r")] 197))] + [(parallel + [(set (match_operand:V8HI 0 "register_operand" "=v") + (mem:V8HI + (and:SI (plus:SI (match_operand:SI 1 "register_operand" "b") + (match_operand:SI 2 "register_operand" "r")) + (const_int -2)))) + (unspec [(const_int 0)] 197)])] "TARGET_ALTIVEC" "lvehx %0,%1,%2" [(set_attr "type" "vecload")]) (define_insn "altivec_lvewx" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:SI 1 "register_operand" "b") - (match_operand:SI 2 "register_operand" "r")] 198))] + [(parallel + [(set (match_operand:V4SI 0 "register_operand" "=v") + (mem:V4SI + (and:SI (plus:SI (match_operand:SI 1 "register_operand" "b") + (match_operand:SI 2 "register_operand" "r")) + (const_int -4)))) + (unspec [(const_int 0)] 198)])] "TARGET_ALTIVEC" "lvewx %0,%1,%2" [(set_attr "type" "vecload")]) (define_insn "altivec_lvxl" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:SI 1 "register_operand" "b") - (match_operand:SI 2 "register_operand" "r")] 199))] + [(parallel + [(set (match_operand:V4SI 0 "register_operand" "=v") + (mem:V4SI (plus:SI (match_operand:SI 1 "register_operand" "b") + (match_operand:SI 2 "register_operand" "r")))) + (unspec [(const_int 0)] 213)])] "TARGET_ALTIVEC" "lvxl %0,%1,%2" [(set_attr "type" "vecload")]) (define_insn "altivec_lvx" [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:SI 1 "register_operand" "b") - (match_operand:SI 2 "register_operand" "r")] 200))] + (mem:V4SI (plus:SI (match_operand:SI 1 "register_operand" "b") + (match_operand:SI 2 "register_operand" "r"))))] "TARGET_ALTIVEC" "lvx %0,%1,%2" [(set_attr "type" "vecload")]) -;; Parallel the STV*'s with unspecs because some of them have -;; identical rtl but are different instructions-- and gcc gets confused. - (define_insn "altivec_stvx" [(parallel [(set (mem:V4SI |