diff options
Diffstat (limited to 'gcc/config')
34 files changed, 368 insertions, 0 deletions
diff --git a/gcc/config/alpha/alpha.h b/gcc/config/alpha/alpha.h index bfb443c7088..14fc731ef24 100644 --- a/gcc/config/alpha/alpha.h +++ b/gcc/config/alpha/alpha.h @@ -511,6 +511,19 @@ enum reg_class { {0x00000000, 0x7fffffff}, /* FLOAT_REGS */ \ {0xffffffff, 0xffffffff} } +/* The following macro defines cover classes for Integrated Register + Allocator. Cover classes is a set of non-intersected register + classes covering all hard registers used for register allocation + purpose. Any move between two registers of a cover class should be + cheaper than load or store of the registers. The macro value is + array of register classes with LIM_REG_CLASSES used as the end + marker. */ + +#define IRA_COVER_CLASSES \ +{ \ + GENERAL_REGS, FLOAT_REGS, LIM_REG_CLASSES \ +} + /* The same information, inverted: Return the class number of the smallest class containing reg number REGNO. This could be a conditional expression diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 276005c3da0..add8eced3ed 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1152,6 +1152,20 @@ enum reg_class or could index an array. */ #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) +/* The following macro defines cover classes for Integrated Register + Allocator. Cover classes is a set of non-intersected register + classes covering all hard registers used for register allocation + purpose. Any move between two registers of a cover class should be + cheaper than load or store of the registers. The macro value is + array of register classes with LIM_REG_CLASSES used as the end + marker. */ + +#define IRA_COVER_CLASSES \ +{ \ + GENERAL_REGS, FPA_REGS, CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS, IWMMXT_REGS,\ + LIM_REG_CLASSES \ +} + /* FPA registers can't do subreg as all values are reformatted to internal precision. In VFPv1, VFP registers could only be accessed in the mode they were set, so subregs would be invalid there too. However, we don't diff --git a/gcc/config/avr/avr.h b/gcc/config/avr/avr.h index 47bb3fba43c..37fb3ed818a 100644 --- a/gcc/config/avr/avr.h +++ b/gcc/config/avr/avr.h @@ -296,6 +296,19 @@ enum reg_class { #define REGNO_REG_CLASS(R) avr_regno_reg_class(R) +/* The following macro defines cover classes for Integrated Register + Allocator. Cover classes is a set of non-intersected register + classes covering all hard registers used for register allocation + purpose. Any move between two registers of a cover class should be + cheaper than load or store of the registers. The macro value is + array of register classes with LIM_REG_CLASSES used as the end + marker. */ + +#define IRA_COVER_CLASSES \ +{ \ + GENERAL_REGS, LIM_REG_CLASSES \ +} + #define BASE_REG_CLASS (reload_completed ? BASE_POINTER_REGS : POINTER_REGS) #define INDEX_REG_CLASS NO_REGS diff --git a/gcc/config/bfin/bfin.h b/gcc/config/bfin/bfin.h index 6ebaa44f566..441e202fc5b 100644 --- a/gcc/config/bfin/bfin.h +++ b/gcc/config/bfin/bfin.h @@ -664,6 +664,19 @@ enum reg_class : (REGNO) >= REG_RETS ? PROLOGUE_REGS \ : NO_REGS) +/* The following macro defines cover classes for Integrated Register + Allocator. Cover classes is a set of non-intersected register + classes covering all hard registers used for register allocation + purpose. Any move between two registers of a cover class should be + cheaper than load or store of the registers. The macro value is + array of register classes with LIM_REG_CLASSES used as the end + marker. */ + +#define IRA_COVER_CLASSES \ +{ \ + MOST_REGS, AREGS, CCREGS, LIM_REG_CLASSES \ +} + /* When this hook returns true for MODE, the compiler allows registers explicitly used in the rtl to be used as spill registers but prevents the compiler from extending the lifetime of these diff --git a/gcc/config/cris/cris.h b/gcc/config/cris/cris.h index c8b7d2ff4c5..e8172bb1195 100644 --- a/gcc/config/cris/cris.h +++ b/gcc/config/cris/cris.h @@ -550,6 +550,8 @@ enum reg_class #define INDEX_REG_CLASS GENERAL_REGS +#define IRA_COVER_CLASSES { GENERAL_REGS, SPECIAL_REGS, LIM_REG_CLASSES } + #define REG_CLASS_FROM_LETTER(C) \ ( \ (C) == 'a' ? ACR_REGS : \ diff --git a/gcc/config/fr30/fr30.h b/gcc/config/fr30/fr30.h index 9f8be86846d..d20d7fb79c3 100644 --- a/gcc/config/fr30/fr30.h +++ b/gcc/config/fr30/fr30.h @@ -290,6 +290,11 @@ enum reg_class #define GENERAL_REGS REAL_REGS #define N_REG_CLASSES ((int) LIM_REG_CLASSES) +#define IRA_COVER_CLASSES \ +{ \ + REAL_REGS, MULTIPLY_64_REG, LIM_REG_CLASSES \ +} + /* An initializer containing the names of the register classes as C string constants. These names are used in writing some of the debugging dumps. */ #define REG_CLASS_NAMES \ diff --git a/gcc/config/frv/frv.h b/gcc/config/frv/frv.h index 2c1abf3de90..299a85676ba 100644 --- a/gcc/config/frv/frv.h +++ b/gcc/config/frv/frv.h @@ -970,6 +970,21 @@ enum reg_class { 0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0x1fff}, /* ALL_REGS */\ } +/* The following macro defines cover classes for Integrated Register + Allocator. Cover classes is a set of non-intersected register + classes covering all hard registers used for register allocation + purpose. Any move between two registers of a cover class should be + cheaper than load or store of the registers. The macro value is + array of register classes with LIM_REG_CLASSES used as the end + marker. */ + +#define IRA_COVER_CLASSES \ +{ \ + GPR_REGS, FPR_REGS, ACC_REGS, ICR_REGS, FCR_REGS, ICC_REGS, FCC_REGS, \ + ACCG_REGS, SPR_REGS, \ + LIM_REG_CLASSES \ +} + /* A C expression whose value is a register class containing hard register REGNO. In general there is more than one such class; choose a class which is "minimal", meaning that no smaller class also contains the register. */ diff --git a/gcc/config/h8300/h8300.h b/gcc/config/h8300/h8300.h index 793f1fa0be8..589b70f89a7 100644 --- a/gcc/config/h8300/h8300.h +++ b/gcc/config/h8300/h8300.h @@ -330,6 +330,19 @@ enum reg_class { { "NO_REGS", "COUNTER_REGS", "SOURCE_REGS", "DESTINATION_REGS", \ "GENERAL_REGS", "MAC_REGS", "ALL_REGS", "LIM_REGS" } +/* The following macro defines cover classes for Integrated Register + Allocator. Cover classes is a set of non-intersected register + classes covering all hard registers used for register allocation + purpose. Any move between two registers of a cover class should be + cheaper than load or store of the registers. The macro value is + array of register classes with LIM_REG_CLASSES used as the end + marker. */ + +#define IRA_COVER_CLASSES \ +{ \ + GENERAL_REGS, MAC_REGS, LIM_REG_CLASSES \ +} + /* Define which registers fit in which classes. This is an initializer for a vector of HARD_REG_SET of length N_REG_CLASSES. */ diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 7e5002172ca..a4ca762228c 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -28434,6 +28434,22 @@ ix86_free_from_memory (enum machine_mode mode) } } +/* Implement TARGET_IRA_COVER_CLASSES. If -mfpmath=sse, we prefer + SSE_REGS to FLOAT_REGS if their costs for a pseudo are the + same. */ +static const reg_class_t * +i386_ira_cover_classes (void) +{ + static const reg_class_t sse_fpmath_classes[] = { + GENERAL_REGS, SSE_REGS, MMX_REGS, FLOAT_REGS, LIM_REG_CLASSES + }; + static const reg_class_t no_sse_fpmath_classes[] = { + GENERAL_REGS, FLOAT_REGS, MMX_REGS, SSE_REGS, LIM_REG_CLASSES + }; + + return TARGET_SSE_MATH ? sse_fpmath_classes : no_sse_fpmath_classes; +} + /* Implement TARGET_PREFERRED_RELOAD_CLASS. Put float CONST_DOUBLE in the constant pool instead of fp regs. @@ -35333,6 +35349,9 @@ ix86_autovectorize_vector_sizes (void) #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p +#undef TARGET_IRA_COVER_CLASSES +#define TARGET_IRA_COVER_CLASSES i386_ira_cover_classes + #undef TARGET_FRAME_POINTER_REQUIRED #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 326b8bc499d..12edeba97f7 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -870,6 +870,9 @@ enum target_cpu_default || ((MODE) == DFmode && !(TARGET_SSE2 && TARGET_SSE_MATH)) \ || (MODE) == XFmode) +/* Cover class containing the stack registers. */ +#define STACK_REG_COVER_CLASS FLOAT_REGS + /* Number of actual hardware registers. The hardware registers are assigned numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER. diff --git a/gcc/config/ia64/ia64.h b/gcc/config/ia64/ia64.h index a894df8dff7..ed618f29fc2 100644 --- a/gcc/config/ia64/ia64.h +++ b/gcc/config/ia64/ia64.h @@ -774,6 +774,19 @@ enum reg_class 0xFFFFFFFF, 0xFFFFFFFF, 0x3FFF }, \ } +/* The following macro defines cover classes for Integrated Register + Allocator. Cover classes is a set of non-intersected register + classes covering all hard registers used for register allocation + purpose. Any move between two registers of a cover class should be + cheaper than load or store of the registers. The macro value is + array of register classes with LIM_REG_CLASSES used as the end + marker. */ + +#define IRA_COVER_CLASSES \ +{ \ + PR_REGS, BR_REGS, AR_M_REGS, AR_I_REGS, GR_REGS, FR_REGS, LIM_REG_CLASSES \ +} + /* A C expression whose value is a register class containing hard register REGNO. In general there is more than one such class; choose a class which is "minimal", meaning that no smaller class also contains the register. */ diff --git a/gcc/config/iq2000/iq2000.h b/gcc/config/iq2000/iq2000.h index 8a3c653c455..62cddea444e 100644 --- a/gcc/config/iq2000/iq2000.h +++ b/gcc/config/iq2000/iq2000.h @@ -209,6 +209,11 @@ enum reg_class #define N_REG_CLASSES (int) LIM_REG_CLASSES +#define IRA_COVER_CLASSES \ +{ \ + GR_REGS, LIM_REG_CLASSES \ +} + #define REG_CLASS_NAMES \ { \ "NO_REGS", \ diff --git a/gcc/config/m32r/m32r.h b/gcc/config/m32r/m32r.h index 31c6cb1e2fb..a43e2956c94 100644 --- a/gcc/config/m32r/m32r.h +++ b/gcc/config/m32r/m32r.h @@ -459,6 +459,11 @@ enum reg_class NO_REGS, CARRY_REG, ACCUM_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES }; +#define IRA_COVER_CLASSES \ +{ \ + ACCUM_REGS, GENERAL_REGS, LIM_REG_CLASSES \ +} + #define N_REG_CLASSES ((int) LIM_REG_CLASSES) /* Give names of register classes as strings for dump file. */ diff --git a/gcc/config/m68k/m68k.h b/gcc/config/m68k/m68k.h index e53737933b4..71b7c4f273f 100644 --- a/gcc/config/m68k/m68k.h +++ b/gcc/config/m68k/m68k.h @@ -496,6 +496,10 @@ extern enum reg_class regno_reg_class[]; #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ ((((CLASS1) == FP_REGS) != ((CLASS2) == FP_REGS)) ? 4 : 2) +#define IRA_COVER_CLASSES \ +{ \ + ALL_REGS, LIM_REG_CLASSES \ +} /* Stack layout; function entry, exit and calling. */ diff --git a/gcc/config/mcore/mcore.h b/gcc/config/mcore/mcore.h index fa3909e628f..54c12ef3dd8 100644 --- a/gcc/config/mcore/mcore.h +++ b/gcc/config/mcore/mcore.h @@ -324,6 +324,11 @@ enum reg_class #define N_REG_CLASSES (int) LIM_REG_CLASSES +#define IRA_COVER_CLASSES \ +{ \ + GENERAL_REGS, C_REGS, LIM_REG_CLASSES \ +} + /* Give names of register classes as strings for dump file. */ #define REG_CLASS_NAMES \ diff --git a/gcc/config/mep/mep.h b/gcc/config/mep/mep.h index ed2d6602d3d..5244bb38a4b 100644 --- a/gcc/config/mep/mep.h +++ b/gcc/config/mep/mep.h @@ -407,6 +407,8 @@ enum reg_class #define REGNO_REG_CLASS(REGNO) (enum reg_class) mep_regno_reg_class (REGNO) +#define IRA_COVER_CLASSES { GENERAL_REGS, CONTROL_REGS, CR_REGS, CCR_REGS, LIM_REG_CLASSES } + #define BASE_REG_CLASS GENERAL_REGS #define INDEX_REG_CLASS GENERAL_REGS diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 643e507fddf..0692902e845 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -11017,6 +11017,29 @@ mips_memory_move_cost (enum machine_mode mode, reg_class_t rclass, bool in) + memory_move_secondary_cost (mode, rclass, in)); } +/* Implement TARGET_IRA_COVER_CLASSES. */ + +static const reg_class_t * +mips_ira_cover_classes (void) +{ + static const reg_class_t acc_classes[] = { + GR_AND_ACC_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS, + ST_REGS, LIM_REG_CLASSES + }; + static const reg_class_t no_acc_classes[] = { + GR_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS, + ST_REGS, LIM_REG_CLASSES + }; + + /* Don't allow the register allocators to use LO and HI in MIPS16 mode, + which has no MTLO or MTHI instructions. Also, using GR_AND_ACC_REGS + as a cover class only works well when we keep per-register costs. + Using it when not optimizing can cause us to think accumulators + have the same cost as GPRs in cases where GPRs are actually much + cheaper. */ + return TARGET_MIPS16 || !optimize ? no_acc_classes : acc_classes; +} + /* Return the register class required for a secondary register when copying between one of the registers in RCLASS and value X, which has mode MODE. X is the source of the move if IN_P, otherwise it @@ -16595,6 +16618,9 @@ mips_shift_truncation_mask (enum machine_mode mode) #undef TARGET_DWARF_REGISTER_SPAN #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span +#undef TARGET_IRA_COVER_CLASSES +#define TARGET_IRA_COVER_CLASSES mips_ira_cover_classes + #undef TARGET_ASM_FINAL_POSTSCAN_INSN #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn diff --git a/gcc/config/mn10300/mn10300.h b/gcc/config/mn10300/mn10300.h index f660dca5aa9..ac23f585861 100644 --- a/gcc/config/mn10300/mn10300.h +++ b/gcc/config/mn10300/mn10300.h @@ -309,6 +309,19 @@ enum reg_class { 0xffffffff, 0xfffff } /* ALL_REGS */ \ } +/* The following macro defines cover classes for Integrated Register + Allocator. Cover classes is a set of non-intersected register + classes covering all hard registers used for register allocation + purpose. Any move between two registers of a cover class should be + cheaper than load or store of the registers. The macro value is + array of register classes with LIM_REG_CLASSES used as the end + marker. */ + +#define IRA_COVER_CLASSES \ +{ \ + GENERAL_REGS, FP_REGS, MDR_REGS, LIM_REG_CLASSES \ +} + /* The same information, inverted: Return the class number of the smallest class containing reg number REGNO. This could be a conditional expression diff --git a/gcc/config/moxie/moxie.h b/gcc/config/moxie/moxie.h index 1b5e0a3f8aa..41f66cb6baa 100644 --- a/gcc/config/moxie/moxie.h +++ b/gcc/config/moxie/moxie.h @@ -135,6 +135,15 @@ enum reg_class }; +/* The following macro defines cover classes for Integrated Register + Allocator. Cover classes is a set of non-intersected register + classes covering all hard registers used for register allocation + purpose. Any move between two registers of a cover class should be + cheaper than load or store of the registers. The macro value is + array of register classes with LIM_REG_CLASSES used as the end + marker. */ +#define IRA_COVER_CLASSES { GENERAL_REGS, LIM_REG_CLASSES } + #define REG_CLASS_CONTENTS \ { { 0x00000000 }, /* Empty */ \ { 0x0003FFFF }, /* $fp, $sp, $r0 to $r13, ?fp */ \ diff --git a/gcc/config/pa/pa32-regs.h b/gcc/config/pa/pa32-regs.h index d207c0a7275..7e8e05df981 100644 --- a/gcc/config/pa/pa32-regs.h +++ b/gcc/config/pa/pa32-regs.h @@ -294,6 +294,19 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS, {0x00000000, 0x00000000, 0x01000000}, /* SHIFT_REGS */ \ {0xfffffffe, 0xffffffff, 0x03ffffff}} /* ALL_REGS */ +/* The following macro defines cover classes for Integrated Register + Allocator. Cover classes is a set of non-intersected register + classes covering all hard registers used for register allocation + purpose. Any move between two registers of a cover class should be + cheaper than load or store of the registers. The macro value is + array of register classes with LIM_REG_CLASSES used as the end + marker. */ + +#define IRA_COVER_CLASSES \ +{ \ + GENERAL_REGS, FP_REGS, SHIFT_REGS, LIM_REG_CLASSES \ +} + /* Defines invalid mode changes. */ #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ diff --git a/gcc/config/pa/pa64-regs.h b/gcc/config/pa/pa64-regs.h index 810e945f6b4..23dc7780e4e 100644 --- a/gcc/config/pa/pa64-regs.h +++ b/gcc/config/pa/pa64-regs.h @@ -230,6 +230,19 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS, {0x00000000, 0x10000000}, /* SHIFT_REGS */ \ {0xfffffffe, 0x3fffffff}} /* ALL_REGS */ +/* The following macro defines cover classes for Integrated Register + Allocator. Cover classes is a set of non-intersected register + classes covering all hard registers used for register allocation + purpose. Any move between two registers of a cover class should be + cheaper than load or store of the registers. The macro value is + array of register classes with LIM_REG_CLASSES used as the end + marker. */ + +#define IRA_COVER_CLASSES \ +{ \ + GENERAL_REGS, FP_REGS, SHIFT_REGS, LIM_REG_CLASSES \ +} + /* Defines invalid mode changes. */ #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ diff --git a/gcc/config/picochip/picochip.h b/gcc/config/picochip/picochip.h index cb0a8f93335..5f6bc7b2c07 100644 --- a/gcc/config/picochip/picochip.h +++ b/gcc/config/picochip/picochip.h @@ -292,6 +292,19 @@ enum reg_class #define N_REG_CLASSES (int) LIM_REG_CLASSES +/* The following macro defines cover classes for Integrated Register + Allocator. Cover classes is a set of non-intersected register + classes covering all hard registers used for register allocation + purpose. Any move between two registers of a cover class should be + cheaper than load or store of the registers. The macro value is + array of register classes with LIM_REG_CLASSES used as the end + marker. */ + +#define IRA_COVER_CLASSES \ +{ \ + GR_REGS, LIM_REG_CLASSES \ +} + /* The names of the register classes */ #define REG_CLASS_NAMES \ diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 8b1d4122d87..b1efc0dc9d3 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -1208,6 +1208,8 @@ static reg_class_t rs6000_secondary_reload (bool, rtx, reg_class_t, enum machine_mode, struct secondary_reload_info *); +static const reg_class_t *rs6000_ira_cover_classes (void); + const int INSN_NOT_AVAILABLE = -1; static enum machine_mode rs6000_eh_return_filter_mode (void); static bool rs6000_can_eliminate (const int, const int); @@ -1634,6 +1636,9 @@ static const struct default_options rs6000_option_optimization_table[] = #undef TARGET_SECONDARY_RELOAD #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload +#undef TARGET_IRA_COVER_CLASSES +#define TARGET_IRA_COVER_CLASSES rs6000_ira_cover_classes + #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p @@ -15283,6 +15288,26 @@ rs6000_secondary_reload_ppc64 (rtx reg, rtx mem, rtx scratch, bool store_p) return; } +/* Target hook to return the cover classes for Integrated Register Allocator. + Cover classes is a set of non-intersected register classes covering all hard + registers used for register allocation purpose. Any move between two + registers of a cover class should be cheaper than load or store of the + registers. The value is array of register classes with LIM_REG_CLASSES used + as the end marker. + + We need two IRA_COVER_CLASSES, one for pre-VSX, and the other for VSX to + account for the Altivec and Floating registers being subsets of the VSX + register set under VSX, but distinct register sets on pre-VSX machines. */ + +static const reg_class_t * +rs6000_ira_cover_classes (void) +{ + static const reg_class_t cover_pre_vsx[] = IRA_COVER_CLASSES_PRE_VSX; + static const reg_class_t cover_vsx[] = IRA_COVER_CLASSES_VSX; + + return (TARGET_VSX) ? cover_vsx : cover_pre_vsx; +} + /* Allocate a 64-bit stack slot to be used for copying SDmode values through if this function has any SDmode references. */ diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 0193db52eb2..49134568b71 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1252,6 +1252,34 @@ enum reg_class { 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff } /* ALL_REGS */ \ } +/* The following macro defines cover classes for Integrated Register + Allocator. Cover classes is a set of non-intersected register + classes covering all hard registers used for register allocation + purpose. Any move between two registers of a cover class should be + cheaper than load or store of the registers. The macro value is + array of register classes with LIM_REG_CLASSES used as the end + marker. + + We need two IRA_COVER_CLASSES, one for pre-VSX, and the other for VSX to + account for the Altivec and Floating registers being subsets of the VSX + register set. */ + +#define IRA_COVER_CLASSES_PRE_VSX \ +{ \ + GENERAL_REGS, SPECIAL_REGS, FLOAT_REGS, ALTIVEC_REGS, /* VSX_REGS, */ \ + /* VRSAVE_REGS,*/ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS, \ + /* MQ_REGS, LINK_REGS, CTR_REGS, */ \ + CR_REGS, CA_REGS, LIM_REG_CLASSES \ +} + +#define IRA_COVER_CLASSES_VSX \ +{ \ + GENERAL_REGS, SPECIAL_REGS, /* FLOAT_REGS, ALTIVEC_REGS, */ VSX_REGS, \ + /* VRSAVE_REGS,*/ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS, \ + /* MQ_REGS, LINK_REGS, CTR_REGS, */ \ + CR_REGS, CA_REGS, LIM_REG_CLASSES \ +} + /* The same information, inverted: Return the class number of the smallest class containing reg number REGNO. This could be a conditional expression diff --git a/gcc/config/rx/rx.h b/gcc/config/rx/rx.h index f9ea2093007..bd54a2b954f 100644 --- a/gcc/config/rx/rx.h +++ b/gcc/config/rx/rx.h @@ -187,6 +187,11 @@ enum reg_class { 0x0000ffff } /* All registers. */ \ } +#define IRA_COVER_CLASSES \ + { \ + GR_REGS, LIM_REG_CLASSES \ + } + #define SMALL_REGISTER_CLASSES 0 #define N_REG_CLASSES (int) LIM_REG_CLASSES #define CLASS_MAX_NREGS(CLASS, MODE) ((GET_MODE_SIZE (MODE) \ diff --git a/gcc/config/s390/s390.h b/gcc/config/s390/s390.h index 8825ae224f4..c6ba4ff2453 100644 --- a/gcc/config/s390/s390.h +++ b/gcc/config/s390/s390.h @@ -468,6 +468,19 @@ enum reg_class { 0xffffffff, 0x0000003f }, /* ALL_REGS */ \ } +/* The following macro defines cover classes for Integrated Register + Allocator. Cover classes is a set of non-intersected register + classes covering all hard registers used for register allocation + purpose. Any move between two registers of a cover class should be + cheaper than load or store of the registers. The macro value is + array of register classes with LIM_REG_CLASSES used as the end + marker. */ + +#define IRA_COVER_CLASSES \ +{ \ + GENERAL_REGS, FP_REGS, CC_REGS, ACCESS_REGS, LIM_REG_CLASSES \ +} + /* In some case register allocation order is not enough for IRA to generate a good code. The following macro (if defined) increases cost of REGNO for a pseudo approximately by pseudo usage frequency diff --git a/gcc/config/score/score.h b/gcc/config/score/score.h index c66e0e934ce..4554e267344 100644 --- a/gcc/config/score/score.h +++ b/gcc/config/score/score.h @@ -390,6 +390,18 @@ enum reg_class also contains the register. */ #define REGNO_REG_CLASS(REGNO) (enum reg_class) score_reg_class (REGNO) +/* The following macro defines cover classes for Integrated Register + Allocator. Cover classes is a set of non-intersected register + classes covering all hard registers used for register allocation + purpose. Any move between two registers of a cover class should be + cheaper than load or store of the registers. The macro value is + array of register classes with LIM_REG_CLASSES used as the end + marker. */ +#define IRA_COVER_CLASSES \ +{ \ + G32_REGS, CE_REGS, SP_REGS, LIM_REG_CLASSES \ +} + /* A macro whose definition is the name of the class to which a valid base register must belong. A base register is one used in an address which is the register value plus a displacement. */ diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h index d45f8c08001..4579af32736 100644 --- a/gcc/config/sh/sh.h +++ b/gcc/config/sh/sh.h @@ -1133,6 +1133,20 @@ enum reg_class extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)] +/* The following macro defines cover classes for Integrated Register + Allocator. Cover classes is a set of non-intersected register + classes covering all hard registers used for register allocation + purpose. Any move between two registers of a cover class should be + cheaper than load or store of the registers. The macro value is + array of register classes with LIM_REG_CLASSES used as the end + marker. */ + +#define IRA_COVER_CLASSES \ +{ \ + GENERAL_REGS, FP_REGS, PR_REGS, T_REGS, MAC_REGS, TARGET_REGS, \ + FPUL_REGS, LIM_REG_CLASSES \ +} + /* When this hook returns true for MODE, the compiler allows registers explicitly used in the rtl to be used as spill registers but prevents the compiler from extending the lifetime of these diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index 93989683704..297844fc0ba 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -1008,6 +1008,19 @@ extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)] +/* The following macro defines cover classes for Integrated Register + Allocator. Cover classes is a set of non-intersected register + classes covering all hard registers used for register allocation + purpose. Any move between two registers of a cover class should be + cheaper than load or store of the registers. The macro value is + array of register classes with LIM_REG_CLASSES used as the end + marker. */ + +#define IRA_COVER_CLASSES \ +{ \ + GENERAL_REGS, EXTRA_FP_REGS, FPCC_REGS, LIM_REG_CLASSES \ +} + /* Defines invalid mode changes. Borrowed from pa64-regs.h. SImode loads to floating-point registers are not zero-extended. diff --git a/gcc/config/spu/spu.h b/gcc/config/spu/spu.h index b3bdcf5abdf..51bfa5131aa 100644 --- a/gcc/config/spu/spu.h +++ b/gcc/config/spu/spu.h @@ -196,6 +196,9 @@ enum reg_class { LIM_REG_CLASSES }; +/* SPU is simple, it really only has one class of registers. */ +#define IRA_COVER_CLASSES { GENERAL_REGS, LIM_REG_CLASSES } + #define N_REG_CLASSES (int) LIM_REG_CLASSES #define REG_CLASS_NAMES \ diff --git a/gcc/config/stormy16/stormy16.h b/gcc/config/stormy16/stormy16.h index 53f4d2d7b65..a838b8acf83 100644 --- a/gcc/config/stormy16/stormy16.h +++ b/gcc/config/stormy16/stormy16.h @@ -179,6 +179,11 @@ enum reg_class #define N_REG_CLASSES ((int) LIM_REG_CLASSES) +#define IRA_COVER_CLASSES \ +{ \ + GENERAL_REGS, LIM_REG_CLASSES \ +} + #define REG_CLASS_NAMES \ { \ "NO_REGS", \ diff --git a/gcc/config/v850/v850.h b/gcc/config/v850/v850.h index 1171399c4cf..d1c4320e39e 100644 --- a/gcc/config/v850/v850.h +++ b/gcc/config/v850/v850.h @@ -304,6 +304,11 @@ enum reg_class #define N_REG_CLASSES (int) LIM_REG_CLASSES +#define IRA_COVER_CLASSES \ +{ \ + GENERAL_REGS, LIM_REG_CLASSES \ +} + /* Give names of register classes as strings for dump file. */ #define REG_CLASS_NAMES \ diff --git a/gcc/config/vax/vax.h b/gcc/config/vax/vax.h index 15b7daa7b7e..272dfbbc342 100644 --- a/gcc/config/vax/vax.h +++ b/gcc/config/vax/vax.h @@ -226,6 +226,15 @@ enum reg_class { NO_REGS, ALL_REGS, LIM_REG_CLASSES }; #define REG_CLASS_NAMES \ { "NO_REGS", "ALL_REGS" } +/* The following macro defines cover classes for Integrated Register + Allocator. Cover classes is a set of non-intersected register + classes covering all hard registers used for register allocation + purpose. Any move between two registers of a cover class should be + cheaper than load or store of the registers. The macro value is + array of register classes with LIM_REG_CLASSES used as the end + marker. */ +#define IRA_COVER_CLASSES { ALL_REGS, LIM_REG_CLASSES } + /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. */ #define CLASS_MAX_NREGS(CLASS, MODE) \ diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h index c9ff80c4664..0a096cdb5e4 100644 --- a/gcc/config/xtensa/xtensa.h +++ b/gcc/config/xtensa/xtensa.h @@ -432,6 +432,11 @@ enum reg_class { 0xffffffff, 0x0000000f } /* all registers */ \ } +#define IRA_COVER_CLASSES \ +{ \ + BR_REGS, FP_REGS, ACC_REG, AR_REGS, LIM_REG_CLASSES \ +} + /* A C expression whose value is a register class containing hard register REGNO. In general there is more that one such class; choose a class which is "minimal", meaning that no smaller class |