diff options
Diffstat (limited to 'gcc/doc/invoke.texi')
| -rw-r--r-- | gcc/doc/invoke.texi | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 0cf383c1a8e..e9b3b4328c2 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -15376,7 +15376,7 @@ Equivalent to @option{-march=mips64r2}. @itemx -mno-mips16 @opindex mips16 @opindex mno-mips16 -Generate (do not generate) MIPS16 code. If GCC is targetting a +Generate (do not generate) MIPS16 code. If GCC is targeting a MIPS32 or MIPS64 architecture, it makes use of the MIPS16e ASE@. MIPS16 code generation can also be controlled on a per-function basis @@ -16929,7 +16929,7 @@ Generate code that tries to avoid (not avoid) the use of indexed load or store instructions. These instructions can incur a performance penalty on Power6 processors in certain situations, such as when stepping through large arrays that cross a 16M boundary. This option -is enabled by default when targetting Power6 and disabled otherwise. +is enabled by default when targeting Power6 and disabled otherwise. @item -mfused-madd @itemx -mno-fused-madd @@ -16948,7 +16948,7 @@ mapped to @option{-ffp-contract=off}. @opindex mno-mulhw Generate code that uses (does not use) the half-word multiply and multiply-accumulate instructions on the IBM 405, 440, 464 and 476 processors. -These instructions are generated by default when targetting those +These instructions are generated by default when targeting those processors. @item -mdlmzb @@ -16957,7 +16957,7 @@ processors. @opindex mno-dlmzb Generate code that uses (does not use) the string-search @samp{dlmzb} instruction on the IBM 405, 440, 464 and 476 processors. This instruction is -generated by default when targetting those processors. +generated by default when targeting those processors. @item -mno-bit-align @itemx -mbit-align @@ -18506,7 +18506,7 @@ Visual Instruction Set extensions. The default is @option{-mno-vis}. @opindex mno-vis2 With @option{-mvis2}, GCC generates code that takes advantage of version 2.0 of the UltraSPARC Visual Instruction Set extensions. The -default is @option{-mvis2} when targetting a cpu that supports such +default is @option{-mvis2} when targeting a cpu that supports such instructions, such as UltraSPARC-III and later. Setting @option{-mvis2} also sets @option{-mvis}. @@ -18516,7 +18516,7 @@ also sets @option{-mvis}. @opindex mno-vis3 With @option{-mvis3}, GCC generates code that takes advantage of version 3.0 of the UltraSPARC Visual Instruction Set extensions. The -default is @option{-mvis3} when targetting a cpu that supports such +default is @option{-mvis3} when targeting a cpu that supports such instructions, such as niagara-3 and later. Setting @option{-mvis3} also sets @option{-mvis2} and @option{-mvis}. @@ -18526,7 +18526,7 @@ also sets @option{-mvis2} and @option{-mvis}. @opindex mno-popc With @option{-mpopc}, GCC generates code that takes advantage of the UltraSPARC population count instruction. The default is @option{-mpopc} -when targetting a cpu that supports such instructions, such as Niagara-2 and +when targeting a cpu that supports such instructions, such as Niagara-2 and later. @item -mfmaf @@ -18535,7 +18535,7 @@ later. @opindex mno-fmaf With @option{-mfmaf}, GCC generates code that takes advantage of the UltraSPARC Fused Multiply-Add Floating-point extensions. The default is @option{-mfmaf} -when targetting a cpu that supports such instructions, such as Niagara-3 and +when targeting a cpu that supports such instructions, such as Niagara-3 and later. @item -mfix-at697f |