diff options
Diffstat (limited to 'gcc/testsuite/gcc.target/arm')
279 files changed, 3525 insertions, 250 deletions
diff --git a/gcc/testsuite/gcc.target/arm/20031108-1.c b/gcc/testsuite/gcc.target/arm/20031108-1.c index d9b6006f442..7923e115139 100644 --- a/gcc/testsuite/gcc.target/arm/20031108-1.c +++ b/gcc/testsuite/gcc.target/arm/20031108-1.c @@ -20,6 +20,9 @@ typedef struct record Rec_Pointer Ptr_Glob; +extern int Proc_7 (int, int, int *); + +void Proc_1 (Ptr_Val_Par) Rec_Pointer Ptr_Val_Par; { diff --git a/gcc/testsuite/gcc.target/arm/README.advsimd-intrinsics b/gcc/testsuite/gcc.target/arm/README.advsimd-intrinsics new file mode 100644 index 00000000000..f246349985b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/README.advsimd-intrinsics @@ -0,0 +1 @@ +Advanced SIMD intrinsics tests are located in gcc.target/aarch64. diff --git a/gcc/testsuite/gcc.target/arm/aapcs/aapcs.exp b/gcc/testsuite/gcc.target/arm/aapcs/aapcs.exp index 746429dadf6..3afb537f27c 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/aapcs.exp +++ b/gcc/testsuite/gcc.target/arm/aapcs/aapcs.exp @@ -1,4 +1,4 @@ -# Copyright (C) 1997-2014 Free Software Foundation, Inc. +# Copyright (C) 1997-2015 Free Software Foundation, Inc. # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/gcc/testsuite/gcc.target/arm/aapcs/abitest.h b/gcc/testsuite/gcc.target/arm/aapcs/abitest.h index 06a92c3ec84..b2f85adad8a 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/abitest.h +++ b/gcc/testsuite/gcc.target/arm/aapcs/abitest.h @@ -49,6 +49,7 @@ extern void abort (void); +extern int memcmp (const void *s1, const void *s2, __SIZE_TYPE__ n); __attribute__((naked)) void dumpregs () __asm("myfunc"); __attribute__((naked)) void dumpregs () diff --git a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect1.c b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect1.c index 47ae2f65fae..64f946614cb 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect1.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect1.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant for Neon types) */ -/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-do run { target arm_eabi } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm_neon_ok } */ /* { dg-require-effective-target arm32 } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect2.c b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect2.c index f7b532a3be1..f5d46096860 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect2.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect2.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant for Neon types) */ -/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-do run { target arm_eabi } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm_neon_ok } */ /* { dg-require-effective-target arm32 } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect3.c b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect3.c index e5426b0ec2b..31fb1da9c6a 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect3.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect3.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant for Neon types) */ -/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-do run { target arm_eabi } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm_neon_ok } */ /* { dg-require-effective-target arm32 } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect4.c b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect4.c index 96bd09c459f..bfefccc0f45 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect4.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect4.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant for Neon types) */ -/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-do run { target arm_eabi } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm_neon_ok } */ /* { dg-require-effective-target arm32 } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect5.c b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect5.c index 59e58c96c5e..ff7a857c309 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect5.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect5.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant for Neon types) */ -/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-do run { target arm_eabi } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm_neon_ok } */ /* { dg-require-effective-target arm32 } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect6.c b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect6.c index fcb3998821a..b952e5d2d5e 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect6.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect6.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant for Neon types) */ -/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-do run { target arm_eabi } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm_neon_ok } */ /* { dg-require-effective-target arm32 } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect7.c b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect7.c index f8d1d073007..782f3a6f905 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect7.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect7.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant for Neon types) */ -/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-do run { target arm_eabi } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm_neon_ok } */ /* { dg-require-effective-target arm32 } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect8.c b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect8.c index f2c295d84fb..578a3d3259a 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect8.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect8.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant for Neon types) */ -/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-do run { target arm_eabi } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm_neon_ok } */ /* { dg-require-effective-target arm32 } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp1.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp1.c index 9fb926dbdfc..ef7c3b5667e 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp1.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp1.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-do run { target arm_eabi } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp10.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp10.c index c3a1b39a949..75b284f1c6b 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp10.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp10.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-do run { target arm_eabi } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp11.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp11.c index a496a3ed5bb..dad041d8d62 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp11.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp11.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-do run { target arm_eabi } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp12.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp12.c index bbfa3df9082..1435fab2e6c 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp12.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp12.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-do run { target arm_eabi } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp13.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp13.c index a46361c0904..482027072d1 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp13.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp13.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-do run { target arm_eabi } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp14.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp14.c index 43c19f2dd2c..b9f5c4c59b8 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp14.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp14.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-do run { target arm_eabi } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp15.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp15.c index c98ca38101d..b58a034d92c 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp15.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp15.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-do run { target arm_eabi } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp16.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp16.c index 956bc0ab5d8..19929006da5 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp16.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp16.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-do run { target arm_eabi } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp17.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp17.c index 9044ec221fc..7f0202e8c90 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp17.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp17.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-do run { target arm_eabi } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp2.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp2.c index bfe90675b23..ad815c6987c 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp2.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp2.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-do run { target arm_eabi } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp3.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp3.c index 0e645d71109..e81ac1c2714 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp3.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp3.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-do run { target arm_eabi } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp4.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp4.c index 46dc4b98a7d..0507074e32b 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp4.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp4.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-do run { target arm_eabi } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp5.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp5.c index 216d98ea8e3..d9d3db175d6 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp5.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp5.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-do run { target arm_eabi } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp6.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp6.c index 4d718da45d0..3fd325ae1d2 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp6.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp6.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-do run { target arm_eabi } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp7.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp7.c index 3e57e45c7de..1eafb434ce7 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp7.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp7.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-do run { target arm_eabi } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp8.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp8.c index e55006885c4..93244dd5833 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp8.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp8.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-do run { target arm_eabi } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp9.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp9.c index c2be6bf4b70..707fb170a49 100644 --- a/gcc/testsuite/gcc.target/arm/aapcs/vfp9.c +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp9.c @@ -1,6 +1,6 @@ /* Test AAPCS layout (VFP variant) */ -/* { dg-do run { target arm*-*-*eabi* } } */ +/* { dg-do run { target arm_eabi } } */ /* { dg-require-effective-target arm_hard_vfp_ok } */ /* { dg-require-effective-target arm32 } */ /* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */ diff --git a/gcc/testsuite/gcc.target/arm/acle/acle.exp b/gcc/testsuite/gcc.target/arm/acle/acle.exp index c8622697ee3..ffcb191c0bd 100644 --- a/gcc/testsuite/gcc.target/arm/acle/acle.exp +++ b/gcc/testsuite/gcc.target/arm/acle/acle.exp @@ -1,4 +1,4 @@ -# Copyright (C) 2013-2014 Free Software Foundation, Inc. +# Copyright (C) 2013-2015 Free Software Foundation, Inc. # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/gcc/testsuite/gcc.target/arm/anddi_notdi-1.c b/gcc/testsuite/gcc.target/arm/anddi_notdi-1.c new file mode 100644 index 00000000000..d9489d3dafa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/anddi_notdi-1.c @@ -0,0 +1,66 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-inline --save-temps" } */ + +extern void abort (void); + +typedef long long s64int; +typedef int s32int; +typedef unsigned long long u64int; +typedef unsigned int u32int; + +s64int +anddi_di_notdi (s64int a, s64int b) +{ + return (a & ~b); +} + +s64int +anddi_di_notzesidi (s64int a, u32int b) +{ + return (a & ~(u64int) b); +} + +s64int +anddi_notdi_zesidi (s64int a, u32int b) +{ + return (~a & (u64int) b); +} + +s64int +anddi_di_notsesidi (s64int a, s32int b) +{ + return (a & ~(s64int) b); +} + +int main () +{ + s64int a64 = 0xdeadbeef0000ffffll; + s64int b64 = 0x000000005f470112ll; + s64int c64 = 0xdeadbeef300f0000ll; + + u32int c32 = 0x01124f4f; + s32int d32 = 0xabbaface; + + s64int z = anddi_di_notdi (c64, b64); + if (z != 0xdeadbeef20080000ll) + abort (); + + z = anddi_di_notzesidi (a64, c32); + if (z != 0xdeadbeef0000b0b0ll) + abort (); + + z = anddi_notdi_zesidi (c64, c32); + if (z != 0x0000000001104f4fll) + abort (); + + z = anddi_di_notsesidi (a64, d32); + if (z != 0x0000000000000531ll) + abort (); + + return 0; +} + +/* { dg-final { scan-assembler-times "bics\t" 6 { target arm_thumb1 } } } */ +/* { dg-final { scan-assembler-times "bic\t" 6 { target { ! arm_thumb1 } } } } */ + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/arm.exp b/gcc/testsuite/gcc.target/arm/arm.exp index 54ff2370ab0..a9c380ad9fd 100644 --- a/gcc/testsuite/gcc.target/arm/arm.exp +++ b/gcc/testsuite/gcc.target/arm/arm.exp @@ -1,4 +1,4 @@ -# Copyright (C) 1997-2014 Free Software Foundation, Inc. +# Copyright (C) 1997-2015 Free Software Foundation, Inc. # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/gcc/testsuite/gcc.target/arm/cold-lc.c b/gcc/testsuite/gcc.target/arm/cold-lc.c index 295c29fe8f0..467a6966bd3 100644 --- a/gcc/testsuite/gcc.target/arm/cold-lc.c +++ b/gcc/testsuite/gcc.target/arm/cold-lc.c @@ -7,6 +7,7 @@ struct thread_info { struct task_struct *task; }; extern struct thread_info *current_thread_info (void); +extern int show_stack (struct task_struct *, unsigned long *); void dump_stack (void) { diff --git a/gcc/testsuite/gcc.target/arm/constant-pool.c b/gcc/testsuite/gcc.target/arm/constant-pool.c new file mode 100644 index 00000000000..8427dfb1a80 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/constant-pool.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ +/* { dg-options "-O1" } */ + +unsigned short v = 0x5678; +int i; +int j = 0; +int *ptr = &j; + +int +func (void) +{ + for (i = 0; i < 1; ++i) + { + *ptr = -1; + v = 0x1234; + } + return v; +} + +int +main (void) +{ + func (); + if (v != 0x1234) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/copysign_softfloat_1.c b/gcc/testsuite/gcc.target/arm/copysign_softfloat_1.c new file mode 100644 index 00000000000..def3fa0cf94 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/copysign_softfloat_1.c @@ -0,0 +1,61 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-skip-if "skip override" { *-*-* } { "-mfloat-abi=softfp" "-mfloat-abi=hard" } { "" } } */ +/* { dg-options "-O2 -mfloat-abi=soft --save-temps" } */ +extern void abort (void); + +#define N 16 + +float a_f[N] = {-0.1f, -3.2f, -6.3f, -9.4f, + -12.5f, -15.6f, -18.7f, -21.8f, + 24.9f, 27.1f, 30.2f, 33.3f, + 36.4f, 39.5f, 42.6f, 45.7f}; + +float b_f[N] = {-1.2f, 3.4f, -5.6f, 7.8f, + -9.0f, 1.0f, -2.0f, 3.0f, + -4.0f, -5.0f, 6.0f, 7.0f, + -8.0f, -9.0f, 10.0f, 11.0f}; + +float c_f[N] = {-0.1f, 3.2f, -6.3f, 9.4f, + -12.5f, 15.6f, -18.7f, 21.8f, + -24.9f, -27.1f, 30.2f, 33.3f, + -36.4f, -39.5f, 42.6f, 45.7f}; + +double a_d[N] = {-0.1, -3.2, -6.3, -9.4, + -12.5, -15.6, -18.7, -21.8, + 24.9, 27.1, 30.2, 33.3, + 36.4, 39.5, 42.6, 45.7}; + +double b_d[N] = {-1.2, 3.4, -5.6, 7.8, + -9.0, 1.0, -2.0, 3.0, + -4.0, -5.0, 6.0, 7.0, + -8.0, -9.0, 10.0, 11.0}; + +double c_d[N] = {-0.1, 3.2, -6.3, 9.4, + -12.5, 15.6, -18.7, 21.8, + -24.9, -27.1, 30.2, 33.3, + -36.4, -39.5, 42.6, 45.7}; + +int +main (int argc, char **argv) +{ + int index = 0; + +/* { dg-final { scan-assembler-times "bfi" 2 } } */ +/* { dg-final { scan-assembler-times "lsr" 1 } } */ + for (index; index < N; index++) + { + if (__builtin_copysignf (a_f[index], b_f[index]) != c_f[index]) + abort(); + } + + for (index = 0; index < N; index++) + { + if (__builtin_copysign (a_d[index], b_d[index]) != c_d[index]) + abort(); + } + + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/eabi1.c b/gcc/testsuite/gcc.target/arm/eabi1.c index c90f5ff0856..0175d79b423 100644 --- a/gcc/testsuite/gcc.target/arm/eabi1.c +++ b/gcc/testsuite/gcc.target/arm/eabi1.c @@ -1,4 +1,4 @@ -/* { dg-do run { target arm*-*-symbianelf* arm*-*-eabi* } } */ +/* { dg-do run { target arm_eabi } } */ /* { dg-options "" } */ /* This file tests most of the non-C++ run-time helper functions diff --git a/gcc/testsuite/gcc.target/arm/frame-pointer-1.c b/gcc/testsuite/gcc.target/arm/frame-pointer-1.c index bb1888e389e..c288fef83b0 100644 --- a/gcc/testsuite/gcc.target/arm/frame-pointer-1.c +++ b/gcc/testsuite/gcc.target/arm/frame-pointer-1.c @@ -1,6 +1,7 @@ /* Check local register variables using a register conventionally used as the frame pointer aren't clobbered under high register pressure. */ /* { dg-do run } */ +/* { dg-skip-if "incompatible options" { ! { arm_thumb1_ok || arm_thumb2_ok } } { "*" } { "" } } */ /* { dg-options "-Os -mthumb -fomit-frame-pointer" } */ #include <stdlib.h> diff --git a/gcc/testsuite/gcc.target/arm/fuse-caller-save.c b/gcc/testsuite/gcc.target/arm/fuse-caller-save.c new file mode 100644 index 00000000000..ef9256dced9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/fuse-caller-save.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fipa-ra" } */ +/* Testing -fipa-ra optimization option. */ + +static int __attribute__((noinline)) +bar (int x) +{ + return x + 3; +} + +int __attribute__((noinline)) +foo (int y) +{ + return y + bar (y); +} + +int +main (void) +{ + return !(foo (5) == 13); +} + +/* For thumb1, r3 is considered likely spilled, and treated differently in + ira_build_conflicts, which inhibits the fipa-ra optimization. */ +/* { dg-final { scan-assembler-times "mov\tr3, r0" 1 { target { ! arm_thumb1 } } } } */ diff --git a/gcc/testsuite/gcc.target/arm/get_address_cost_aligned_max_offset.c b/gcc/testsuite/gcc.target/arm/get_address_cost_aligned_max_offset.c new file mode 100644 index 00000000000..cc3e2f77832 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/get_address_cost_aligned_max_offset.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-mthumb -O2" } */ +/* { dg-require-effective-target arm_thumb1_ok } */ + +unsigned int +test (const short p16[6 * 64]) +{ + unsigned int i = 6; + unsigned int ret = 0; + + do + { + unsigned long long *p64 = (unsigned long long*) p16; + unsigned int *p32 = (unsigned int*) p16; + ret += ret; + if (p16[1] || p32[1]) + ret++; + else if (p64[1] | p64[2] | p64[3]) + ret++; + p16 += 64; + i--; + } while (i != 0); + + return ret; +} + +/* { dg-final { scan-assembler-not "#22" } } */ +/* { dg-final { scan-assembler-not "#14" } } */ diff --git a/gcc/testsuite/gcc.target/arm/identical-invariants.c b/gcc/testsuite/gcc.target/arm/identical-invariants.c new file mode 100644 index 00000000000..f3c7f863947 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/identical-invariants.c @@ -0,0 +1,29 @@ +/* { dg-do compile { target { arm_thumb2_ok } } } */ +/* { dg-options "-O2 -fdump-rtl-loop2_invariant " } */ + +int t1, t2, t3, t4, t5, t6, t7, t8, t9, t10; +extern void foo2 (int *, int *, int *, int *, int *, int *); +extern int foo3 (int, int, int, int, int, int); +int foo (int a, int b, int c, int d) +{ + int i = a; + + for (; i > 0; i += b) + { + if (a > 0x1234567) + foo2 (&t1, &t2, &t3, &t4, &t5, &t6); + foo2 (&t1, &t2, &t3, &t4, &t5, &t6); + if (b > 0x1234567) + foo2 (&t7, &t2, &t8, &t4, &t5, &t6); + foo2 (&t1, &t2, &t3, &t4, &t5, &t6); + if (c > 0x1234567) + foo2 (&t1, &t9, &t10, &t4, &t5, &t6); + t2 = t5 - d; + } + + return foo3 (t1, t2, t3, t4, t5, t6); +} + +/* { dg-final { scan-rtl-dump "Decided to move invariant 0" "loop2_invariant" } } */ +/* { dg-final { cleanup-rtl-dump "loop2_invariant" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/ifcvt-size-check.c b/gcc/testsuite/gcc.target/arm/ifcvt-size-check.c new file mode 100644 index 00000000000..43fa16b82b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/ifcvt-size-check.c @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-options "-mthumb -Os " } */ +/* { dg-require-effective-target arm_thumb1_ok } */ + +int +test (unsigned char iov_len, int count, int i) +{ + unsigned char bytes = 0; + if ((unsigned char) ((char) 127 - bytes) < iov_len) + return 22; + return 0; +} +/* { dg-final { object-size text <= 12 } } */ diff --git a/gcc/testsuite/gcc.target/arm/iordi3-opt.c b/gcc/testsuite/gcc.target/arm/iordi3-opt.c index b3f465b7492..63fbe0bb20b 100644 --- a/gcc/testsuite/gcc.target/arm/iordi3-opt.c +++ b/gcc/testsuite/gcc.target/arm/iordi3-opt.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { arm_arm_ok || arm_thumb2_ok} } } */ /* { dg-options "-O1" } */ unsigned long long or64 (unsigned long long input) diff --git a/gcc/testsuite/gcc.target/arm/iordi_notdi-1.c b/gcc/testsuite/gcc.target/arm/iordi_notdi-1.c new file mode 100644 index 00000000000..249f0806ab2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/iordi_notdi-1.c @@ -0,0 +1,65 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-inline --save-temps" } */ + +extern void abort (void); + +typedef long long s64int; +typedef int s32int; +typedef unsigned long long u64int; +typedef unsigned int u32int; + +s64int +iordi_di_notdi (s64int a, s64int b) +{ + return (a | ~b); +} + +s64int +iordi_di_notzesidi (s64int a, u32int b) +{ + return (a | ~(u64int) b); +} + +s64int +iordi_notdi_zesidi (s64int a, u32int b) +{ + return (~a | (u64int) b); +} + +s64int +iordi_di_notsesidi (s64int a, s32int b) +{ + return (a | ~(s64int) b); +} + +int main () +{ + s64int a64 = 0xdeadbeef00000000ll; + s64int b64 = 0x000000004f4f0112ll; + s64int c64 = 0xdeadbeef000f0000ll; + + u32int c32 = 0x01124f4f; + s32int d32 = 0xabbaface; + + s64int z = iordi_di_notdi (a64, b64); + if (z != 0xffffffffb0b0feedll) + abort (); + + z = iordi_di_notzesidi (a64, c32); + if (z != 0xfffffffffeedb0b0ll) + abort (); + + z = iordi_notdi_zesidi (c64, c32); + if (z != 0x21524110fff2ffffll) + abort (); + + z = iordi_di_notsesidi (a64, d32); + if (z != 0xdeadbeef54450531ll) + abort (); + + return 0; +} + +/* { dg-final { scan-assembler-times "orn\t" 6 { target arm_thumb2 } } } */ + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/lceil-vcvt_1.c b/gcc/testsuite/gcc.target/arm/lceil-vcvt_1.c new file mode 100644 index 00000000000..bbe42717ad9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/lceil-vcvt_1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2 -march=armv8-a" } */ +/* { dg-add-options arm_v8_vfp } */ + +int +foofloat (float x) +{ + return __builtin_lceilf (x); +} + +/* { dg-final { scan-assembler-times "vcvtp.s32.f32\ts\[0-9\]+, s\[0-9\]+" 1 } } */ + + +int +foodouble (double x) +{ + return __builtin_lceil (x); +} + +/* { dg-final { scan-assembler-times "vcvtp.s32.f64\ts\[0-9\]+, d\[0-9\]+" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/ldrd-strd-pair-1.c b/gcc/testsuite/gcc.target/arm/ldrd-strd-pair-1.c new file mode 100644 index 00000000000..7a0bff5f841 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/ldrd-strd-pair-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_prefer_ldrd_strd } */ +/* { dg-options "-O2 -mthumb" } */ + +struct +{ + int x; + int y; + char c; + int d; +}a; + +int foo(int x, int y) +{ + int c; + a.x = x; + c = a.x; + a.d = c; + a.y = y; + + return 0; +} +/* { dg-final { scan-assembler "strd\t" { target { arm_thumb2_ok } } } } */ diff --git a/gcc/testsuite/gcc.target/arm/lfloor-vcvt_1.c b/gcc/testsuite/gcc.target/arm/lfloor-vcvt_1.c new file mode 100644 index 00000000000..88671d36960 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/lfloor-vcvt_1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2 -march=armv8-a" } */ +/* { dg-add-options arm_v8_vfp } */ + +int +foofloat (float x) +{ + return __builtin_lfloorf (x); +} + +/* { dg-final { scan-assembler-times "vcvtm.s32.f32\ts\[0-9\]+, s\[0-9\]+" 1 } } */ + + +int +foodouble (double x) +{ + return __builtin_lfloor (x); +} + +/* { dg-final { scan-assembler-times "vcvtm.s32.f64\ts\[0-9\]+, d\[0-9\]+" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/lp1243022.c b/gcc/testsuite/gcc.target/arm/lp1243022.c index cb405908e05..5f26994a74c 100644 --- a/gcc/testsuite/gcc.target/arm/lp1243022.c +++ b/gcc/testsuite/gcc.target/arm/lp1243022.c @@ -47,6 +47,7 @@ dma_addr_t xhci_trb_virt_to_dma (struct xhci_segment * seg, union xhci_trb * trb); struct xhci_segment *trb_in_td (struct xhci_segment *start_seg, dma_addr_t suspect_dma); +int xhci_test_trb_in_td (struct xhci_hcd *xhci, struct xhci_segment *input_seg, union xhci_trb *start_trb, union xhci_trb *end_trb, dma_addr_t input_dma, struct xhci_segment *result_seg, @@ -64,6 +65,7 @@ xhci_test_trb_in_td (struct xhci_hcd *xhci, struct xhci_segment *input_seg, "Expected seg %p, got seg %p\n", result_seg, seg); } } +int xhci_check_trb_in_td_math (struct xhci_hcd *xhci, gfp_t mem_flags) { struct diff --git a/gcc/testsuite/gcc.target/arm/lround-vcvt_1.c b/gcc/testsuite/gcc.target/arm/lround-vcvt_1.c new file mode 100644 index 00000000000..8b1f6a7c3a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/lround-vcvt_1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2 -march=armv8-a -ffast-math" } */ +/* { dg-add-options arm_v8_vfp } */ + +int +foofloat (float x) +{ + return __builtin_lroundf (x); +} + +/* { dg-final { scan-assembler-times "vcvta.s32.f32\ts\[0-9\]+, s\[0-9\]+" 1 } } */ + + +int +foodouble (double x) +{ + return __builtin_lround (x); +} + +/* { dg-final { scan-assembler-times "vcvta.s32.f64\ts\[0-9\]+, d\[0-9\]+" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/lto/lto.exp b/gcc/testsuite/gcc.target/arm/lto/lto.exp new file mode 100644 index 00000000000..d35058bd9bc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/lto/lto.exp @@ -0,0 +1,63 @@ +# Copyright (C) 2009-2015 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. +# +# Contributed by Diego Novillo <dnovillo@google.com> + +# Exit immediately if this isn't an ARM target. +if ![istarget arm*-*-*] then { + return +} + +# Test link-time optimization across multiple files. +# +# Programs are broken into multiple files. Each one is compiled +# separately with LTO information. The final executable is generated +# by collecting all the generated object files using regular LTO or WHOPR. + +if $tracelevel then { + strace $tracelevel +} + +# Load procedures from common libraries. +load_lib standard.exp +load_lib gcc.exp + +# Load the language-independent compabibility support procedures. +load_lib lto.exp + +# If LTO has not been enabled, bail. +if { ![check_effective_target_lto] } { + return +} + +gcc_init +lto_init no-mathlib + +# Define an identifier for use with this suite to avoid name conflicts +# with other lto tests running at the same time. +set sid "c_lto" + +# Main loop. +foreach src [lsort [find $srcdir/$subdir *_0.c]] { + # If we're only testing specific files and this isn't one of them, skip it. + if ![runtest_file_p $runtests $src] then { + continue + } + + lto-execute $src $sid +} + +lto_finish diff --git a/gcc/testsuite/gcc.target/arm/lto/pr61123-enum-size_0.c b/gcc/testsuite/gcc.target/arm/lto/pr61123-enum-size_0.c new file mode 100644 index 00000000000..c23f9d85760 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/lto/pr61123-enum-size_0.c @@ -0,0 +1,22 @@ +/* { dg-lto-do link } */ +/* { dg-lto-options { { -fno-short-enums -Wl,-Ur,--no-enum-size-warning -Os -nostdlib -flto } } } */ + +#include <stdlib.h> + +enum enum_size_attribute +{ + small_size, int_size +}; + +struct debug_ABI_enum_size +{ + enum enum_size_attribute es; +}; + +int +foo1 (struct debug_ABI_enum_size *x) +{ + return sizeof (x->es); +} + +/* { dg-final { object-readelf Tag_ABI_enum_size int { target arm_eabi } } } */ diff --git a/gcc/testsuite/gcc.target/arm/lto/pr61123-enum-size_1.c b/gcc/testsuite/gcc.target/arm/lto/pr61123-enum-size_1.c new file mode 100644 index 00000000000..9561efaf3e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/lto/pr61123-enum-size_1.c @@ -0,0 +1,5 @@ +int +foo2 (int y) +{ + return y*10; +} diff --git a/gcc/testsuite/gcc.target/arm/max-insns-skipped.c b/gcc/testsuite/gcc.target/arm/max-insns-skipped.c new file mode 100644 index 00000000000..0a11554b52b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/max-insns-skipped.c @@ -0,0 +1,21 @@ +/* { dg-do assemble { target arm_thumb2 } } */ +/* { dg-options " -Os " } */ + +int t (int a, int b, int c, int d) +{ + int r; + if (a > 0) { + r = a + b; + r += 0x456; + r *= 0x1234567; + } + else { + r = b - a; + r -= 0x123; + r *= 0x12387; + r += d; + } + return r; +} + +/* { dg-final { object-size text <= 40 } } */ diff --git a/gcc/testsuite/gcc.target/arm/memset-inline-1.c b/gcc/testsuite/gcc.target/arm/memset-inline-1.c new file mode 100644 index 00000000000..1fe760c1b73 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/memset-inline-1.c @@ -0,0 +1,39 @@ +/* { dg-do run } */ +/* { dg-options "-save-temps -O2 -fno-inline" } */ + +#include <string.h> +#include <stdlib.h> + +#define LEN (100) +short a[LEN]; +void +foo (void) +{ + memset (a, -1, 14); + return; +} + +void +check (signed char *arr, int idx, int len, int v) +{ + int i; + for (i = 0; i < idx; i++) + if (arr[i] != v) + abort (); + + for (i = idx; i < len; i++) + if (arr[i] != 0) + abort (); +} + +int +main(void) +{ + foo (); + check ((signed char *)a, 14, sizeof (a), -1); + + return 0; +} + +/* { dg-final { scan-assembler-not "bl?\[ \t\]*memset" { target { arm_thumb2_ok } } } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/memset-inline-10.c b/gcc/testsuite/gcc.target/arm/memset-inline-10.c new file mode 100644 index 00000000000..d3b777c3eaf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/memset-inline-10.c @@ -0,0 +1,95 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv7-a -mfloat-abi=hard -mfpu=neon -O2" } */ + +#define BUF 100 +long a[BUF]; + +typedef unsigned int size_t; +typedef unsigned int wchar_t; +void *memset (void *s, int c, size_t n); +struct printf_info +{ + int prec; + int width; + wchar_t spec; + unsigned int is_long_double:1; + unsigned int is_short:1; + unsigned int is_long:1; + unsigned int alt:1; + unsigned int space:1; + unsigned int left:1; + unsigned int showsign:1; + unsigned int group:1; + unsigned int extra:1; + unsigned int is_char:1; + unsigned int wide:1; + unsigned int i18n:1; + unsigned int __pad:4; + unsigned short int user; + wchar_t pad; +}; + +void bar (int *alt, int *space, int *left, int *showsign, + int *group, + int *is_long_double, + int *is_short, + int *is_long, + int *width, + int *prec, + int *use_outdigits, + unsigned int *pad, + wchar_t *spec); +void __printf_fp (char *s, struct printf_info *pinfo); +int foo(char *s) +{ + int alt = 0; + int space = 0; + int left = 0; + int showsign = 0; + int group = 0; + int is_long_double = 0; + int is_short = 0; + int is_long = 0; + int width = 0; + int prec = -1; + int use_outdigits = 0; + unsigned int pad = L' '; + wchar_t spec; + + bar (&alt, &space, &left, &showsign, &group, &is_long_double, + &is_short, &is_long, &width, &prec, &use_outdigits, &pad, &spec); + + a[1] = a[0] + a[2] + a[3] + a[4] + a[5] + a[6]; + a[2] = a[1] + a[3] + a[5] + a[5] + a[6] + a[7]; + a[3] = a[2] + a[5] + a[7] + a[6] + a[7] + a[8]; + a[4] = a[3] + a[7] + a[11] + a[7] + a[8] + a[9]; + a[5] = a[5] + a[11] + a[13] + a[8] + a[9] + a[10]; + a[6] = a[7] + a[13] + a[17] + a[9] + a[10] + a[11]; + a[7] = a[11] + a[17] + a[19] + a[10] + a[11] + a[12]; + a[8] = a[17] + a[19] + a[23] + a[29] + a[31] + a[37]; + + { + struct printf_info info; + memset (&info, 0, sizeof (struct printf_info)); + info.prec = prec; + info.width = width; + info.spec = spec; + info.is_long_double = is_long_double; + info.is_short = is_short; + info.is_long = is_long; + info.alt = alt; + info.space = space; + info.left = left; + info.showsign = showsign; + info.group = group; + info.pad = pad; + info.extra = 0; + info.i18n = use_outdigits; + info.wide = sizeof (wchar_t) != 1; + + __printf_fp (s, &info); + } + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/arm/memset-inline-2.c b/gcc/testsuite/gcc.target/arm/memset-inline-2.c new file mode 100644 index 00000000000..6deaffe232d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/memset-inline-2.c @@ -0,0 +1,38 @@ +/* { dg-do run } */ +/* { dg-options "-save-temps -Os -fno-inline" } */ + +#include <string.h> +#include <stdlib.h> + +#define LEN (100) +short a[LEN]; +void +foo (void) +{ + memset (a, -1, 14); + return; +} + +void +check (signed char *arr, int idx, int len, int v) +{ + int i; + for (i = 0; i < idx; i++) + if (arr[i] != v) + abort (); + + for (i = idx; i < len; i++) + if (arr[i] != 0) + abort (); +} + +int +main(void) +{ + foo (); + check ((signed char *)a, 14, sizeof (a), -1); + + return 0; +} +/* { dg-final { scan-assembler "bl?\[ \t\]*memset" { target { ! arm_neon } } } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/memset-inline-3.c b/gcc/testsuite/gcc.target/arm/memset-inline-3.c new file mode 100644 index 00000000000..0cb0ccd8eec --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/memset-inline-3.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-save-temps -O2 -fno-inline" } */ + +#include <string.h> +#include <stdlib.h> + +#define LEN (100) +short a[LEN]; +void +foo (void) +{ + memset (a, -1, 7); + return; +} + +void +check (signed char *arr, int idx, int len, int v) +{ + int i; + for (i = 0; i < idx; i++) + if (arr[i] != v) + abort (); + + for (i = idx; i < len; i++) + if (arr[i] != 0) + abort (); +} + +int +main(void) +{ + foo (); + check ((signed char *)a, 7, sizeof (a), -1); + + return 0; +} + +/* { dg-final { scan-assembler-not "bl?\[ \t\]*memset" { target { ! arm_thumb1_ok } } } } */ +/* { dg-final { scan-assembler-not "strh" { target { arm_unaligned } } } } */ +/* { dg-final { scan-assembler-not "strb" { target { arm_unaligned } } } } */ diff --git a/gcc/testsuite/gcc.target/arm/memset-inline-4.c b/gcc/testsuite/gcc.target/arm/memset-inline-4.c new file mode 100644 index 00000000000..381a2c2099b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/memset-inline-4.c @@ -0,0 +1,68 @@ +/* { dg-do run } */ +/* { dg-skip-if "Don't inline memset using neon instructions on cortex-a9" { *-*-* } { "-mcpu=cortex-a9" } { "" } } */ +/* { dg-skip-if "Don't inline memset using neon instructions on cortex-a9" { *-*-* } { "-mtune=cortex-a9" } { "" } } */ +/* { dg-options "-save-temps -O2 -fno-inline" } */ +/* { dg-add-options "arm_neon" } */ + +#include <string.h> +#include <stdlib.h> + +#define LEN (100) +int a[LEN]; +int b[LEN]; +int c[LEN]; +void +foo1 (void) +{ + memset (a, -1, 8); + return; +} + +void +foo2 (void) +{ + memset (b, 1, 12); + return; +} + +void +foo3 (void) +{ + memset (c, 1, 13); + return; +} + +void +check (signed char *arr, int idx, int len, int v) +{ + int i; + for (i = 0; i < idx; i++) + if (arr[i] != v) + abort (); + + for (i = idx; i < len; i++) + if (arr[i] != 0) + abort (); +} + +int +main(void) +{ + int i; + + foo1 (); + check ((signed char *)a, 8, sizeof (a), -1); + + foo2 (); + check ((signed char *)b, 12, sizeof (b), 1); + + foo3 (); + check ((signed char *)c, 13, sizeof (c), 1); + + return 0; +} + +/* { dg-final { scan-assembler-not "bl?\[ \t\]+memset" { target { ! arm_thumb1_ok } } } } */ +/* { dg-final { scan-assembler-times "vst1\.8" 1 { target { arm_little_endian && arm_neon } } } } */ +/* { dg-final { scan-assembler "vstr" { target { arm_little_endian && arm_neon } } } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/memset-inline-5.c b/gcc/testsuite/gcc.target/arm/memset-inline-5.c new file mode 100644 index 00000000000..9107d811a94 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/memset-inline-5.c @@ -0,0 +1,78 @@ +/* { dg-do run } */ +/* { dg-skip-if "Don't inline memset using neon instructions on cortex-a9" { *-*-* } { "-mcpu=cortex-a9" } { "" } } */ +/* { dg-skip-if "Don't inline memset using neon instructions on cortex-a9" { *-*-* } { "-mtune=cortex-a9" } { "" } } */ +/* { dg-options "-save-temps -O2 -fno-inline" } */ +/* { dg-add-options "arm_neon" } */ + +#include <string.h> +#include <stdlib.h> + +#define LEN (100) +int a[LEN]; +int b[LEN]; +int c[LEN]; +int d[LEN]; +void +foo1 (void) +{ + memset (a, -1, 16); + return; +} + +void +foo2 (void) +{ + memset (b, 1, 25); + return; +} + +void +foo3 (void) +{ + memset (c, -1, 19); + return; +} + +void +foo4 (void) +{ + memset (d, 1, 23); + return; +} + +void +check (signed char *arr, int idx, int len, int v) +{ + int i; + for (i = 0; i < idx; i++) + if (arr[i] != v) + abort (); + + for (i = idx; i < len; i++) + if (arr[i] != 0) + abort (); +} + +int +main(void) +{ + foo1 (); + check ((signed char *)a, 16, sizeof (a), -1); + + foo2 (); + check ((signed char *)b, 25, sizeof (b), 1); + + foo3 (); + check ((signed char *)c, 19, sizeof (c), -1); + + foo4 (); + check ((signed char *)d, 23, sizeof (d), 1); + + return 0; +} + +/* { dg-final { scan-assembler-not "bl?\[ \t\]+memset" { target { arm_little_endian && arm_neon } } } } */ +/* { dg-final { scan-assembler "vst1" { target { arm_little_endian && arm_neon } } } } */ +/* { dg-final { scan-assembler-not "vstr" { target { arm_little_endian && arm_neon } } } } */ +/* { dg-final { cleanup-saved-temps } } */ + diff --git a/gcc/testsuite/gcc.target/arm/memset-inline-6.c b/gcc/testsuite/gcc.target/arm/memset-inline-6.c new file mode 100644 index 00000000000..fcb2e26a95d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/memset-inline-6.c @@ -0,0 +1,68 @@ +/* { dg-do run } */ +/* { dg-skip-if "Don't inline memset using neon instructions on cortex-a9" { *-*-* } { "-mcpu=cortex-a9" } { "" } } */ +/* { dg-skip-if "Don't inline memset using neon instructions on cortex-a9" { *-*-* } { "-mtune=cortex-a9" } { "" } } */ +/* { dg-options "-save-temps -O2 -fno-inline" } */ +/* { dg-add-options "arm_neon" } */ + +#include <string.h> +#include <stdlib.h> + +#define LEN (100) +int a[LEN]; +int b[LEN]; +int c[LEN]; +void +foo1 (void) +{ + memset (a, -1, 20); + return; +} + +void +foo2 (void) +{ + memset (b, 1, 24); + return; +} + +void +foo3 (void) +{ + memset (c, -1, 32); + return; +} + +void +check (signed char *arr, int idx, int len, int v) +{ + int i; + for (i = 0; i < idx; i++) + if (arr[i] != v) + abort (); + + for (i = idx; i < len; i++) + if (arr[i] != 0) + abort (); +} + +int +main(void) +{ + foo1 (); + check ((signed char *)a, 20, sizeof (a), -1); + + foo2 (); + check ((signed char *)b, 24, sizeof (b), 1); + + foo3 (); + check ((signed char *)c, 32, sizeof (c), -1); + + return 0; +} + +/* { dg-final { scan-assembler-not "bl?\[ \t\]+memset" { target { arm_little_endian && arm_neon } } } } */ +/* { dg-final { scan-assembler-times "vst1" 3 { target { arm_little_endian && arm_neon } } } } */ +/* { dg-final { scan-assembler-times "vstr" 4 { target { arm_little_endian && arm_neon } } } } */ +/* { dg-final { cleanup-saved-temps } } */ + + diff --git a/gcc/testsuite/gcc.target/arm/memset-inline-7.c b/gcc/testsuite/gcc.target/arm/memset-inline-7.c new file mode 100644 index 00000000000..7326c5f857c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/memset-inline-7.c @@ -0,0 +1,171 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +#include <string.h> +#include <stdlib.h> + +#define LEN (100) +short a[LEN]; +int b[LEN]; + +void +init (signed char *arr, int len) +{ + int i; + for (i = 0; i < len; i++) + arr[i] = 0; +} + +void +check (signed char *arr, int idx, int len, int v) +{ + int i; + for (i = 0; i < idx; i++) + if (arr[i] != v) + abort (); + + for (i = idx; i < len; i++) + if (arr[i] != 0) + abort (); +} + +#define TEST(a,l,v) \ + init ((signed char*)(a), sizeof (a)); \ + memset ((a), (v), (l)); \ + check ((signed char *)(a), (l), sizeof (a), (v)); +int +main(void) +{ + TEST (a, 1, -1); + TEST (a, 2, -1); + TEST (a, 3, -1); + TEST (a, 4, -1); + TEST (a, 5, -1); + TEST (a, 6, -1); + TEST (a, 7, -1); + TEST (a, 8, -1); + TEST (a, 9, 1); + TEST (a, 10, -1); + TEST (a, 11, 1); + TEST (a, 12, -1); + TEST (a, 13, 1); + TEST (a, 14, -1); + TEST (a, 15, 1); + TEST (a, 16, -1); + TEST (a, 17, 1); + TEST (a, 18, -1); + TEST (a, 19, 1); + TEST (a, 20, -1); + TEST (a, 21, 1); + TEST (a, 22, -1); + TEST (a, 23, 1); + TEST (a, 24, -1); + TEST (a, 25, 1); + TEST (a, 26, -1); + TEST (a, 27, 1); + TEST (a, 28, -1); + TEST (a, 29, 1); + TEST (a, 30, -1); + TEST (a, 31, 1); + TEST (a, 32, -1); + TEST (a, 33, 1); + TEST (a, 34, -1); + TEST (a, 35, 1); + TEST (a, 36, -1); + TEST (a, 37, 1); + TEST (a, 38, -1); + TEST (a, 39, 1); + TEST (a, 40, -1); + TEST (a, 41, 1); + TEST (a, 42, -1); + TEST (a, 43, 1); + TEST (a, 44, -1); + TEST (a, 45, 1); + TEST (a, 46, -1); + TEST (a, 47, 1); + TEST (a, 48, -1); + TEST (a, 49, 1); + TEST (a, 50, -1); + TEST (a, 51, 1); + TEST (a, 52, -1); + TEST (a, 53, 1); + TEST (a, 54, -1); + TEST (a, 55, 1); + TEST (a, 56, -1); + TEST (a, 57, 1); + TEST (a, 58, -1); + TEST (a, 59, 1); + TEST (a, 60, -1); + TEST (a, 61, 1); + TEST (a, 62, -1); + TEST (a, 63, 1); + TEST (a, 64, -1); + + TEST (b, 1, -1); + TEST (b, 2, -1); + TEST (b, 3, -1); + TEST (b, 4, -1); + TEST (b, 5, -1); + TEST (b, 6, -1); + TEST (b, 7, -1); + TEST (b, 8, -1); + TEST (b, 9, 1); + TEST (b, 10, -1); + TEST (b, 11, 1); + TEST (b, 12, -1); + TEST (b, 13, 1); + TEST (b, 14, -1); + TEST (b, 15, 1); + TEST (b, 16, -1); + TEST (b, 17, 1); + TEST (b, 18, -1); + TEST (b, 19, 1); + TEST (b, 20, -1); + TEST (b, 21, 1); + TEST (b, 22, -1); + TEST (b, 23, 1); + TEST (b, 24, -1); + TEST (b, 25, 1); + TEST (b, 26, -1); + TEST (b, 27, 1); + TEST (b, 28, -1); + TEST (b, 29, 1); + TEST (b, 30, -1); + TEST (b, 31, 1); + TEST (b, 32, -1); + TEST (b, 33, 1); + TEST (b, 34, -1); + TEST (b, 35, 1); + TEST (b, 36, -1); + TEST (b, 37, 1); + TEST (b, 38, -1); + TEST (b, 39, 1); + TEST (b, 40, -1); + TEST (b, 41, 1); + TEST (b, 42, -1); + TEST (b, 43, 1); + TEST (b, 44, -1); + TEST (b, 45, 1); + TEST (b, 46, -1); + TEST (b, 47, 1); + TEST (b, 48, -1); + TEST (b, 49, 1); + TEST (b, 50, -1); + TEST (b, 51, 1); + TEST (b, 52, -1); + TEST (b, 53, 1); + TEST (b, 54, -1); + TEST (b, 55, 1); + TEST (b, 56, -1); + TEST (b, 57, 1); + TEST (b, 58, -1); + TEST (b, 59, 1); + TEST (b, 60, -1); + TEST (b, 61, 1); + TEST (b, 62, -1); + TEST (b, 63, 1); + TEST (b, 64, -1); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/arm/memset-inline-8.c b/gcc/testsuite/gcc.target/arm/memset-inline-8.c new file mode 100644 index 00000000000..b6e04773ffc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/memset-inline-8.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-skip-if "Don't inline memset using neon instructions on cortex-a9" { *-*-* } { "-mcpu=cortex-a9" } { "" } } */ +/* { dg-skip-if "Don't inline memset using neon instructions on cortex-a9" { *-*-* } { "-mtune=cortex-a9" } { "" } } */ +/* { dg-options "-save-temps -O2 -fno-inline" } */ +/* { dg-add-options "arm_neon" } */ + +#include <string.h> +#include <stdlib.h> + +#define LEN (100) +short a[LEN]; +void +foo (void) +{ + memset (a, -1, 14); + return; +} + +void +check (signed char *arr, int idx, int len, int v) +{ + int i; + for (i = 0; i < idx; i++) + if (arr[i] != v) + abort (); + + for (i = idx; i < len; i++) + if (arr[i] != 0) + abort (); +} + +int +main(void) +{ + foo (); + check ((signed char *)a, 14, sizeof (a), -1); + + return 0; +} + +/* { dg-final { scan-assembler-not "bl?\[ \t\]*memset" { target { arm_thumb2_ok } } } } */ +/* { dg-final { scan-assembler "vst1" { target { arm_little_endian && arm_neon } } } } */ +/* { dg-final { scan-assembler-not "vstr" { target { arm_little_endian && arm_neon } } } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/memset-inline-9.c b/gcc/testsuite/gcc.target/arm/memset-inline-9.c new file mode 100644 index 00000000000..be9323aae51 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/memset-inline-9.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-skip-if "Don't inline memset using neon instructions on cortex-a9" { *-*-* } { "-mcpu=cortex-a9" } { "" } } */ +/* { dg-skip-if "Don't inline memset using neon instructions on cortex-a9" { *-*-* } { "-mtune=cortex-a9" } { "" } } */ +/* { dg-options "-save-temps -Os -fno-inline" } */ +/* { dg-add-options "arm_neon" } */ + +#include <string.h> +#include <stdlib.h> + +#define LEN (100) +short a[LEN]; +void +foo (void) +{ + memset (a, -1, 14); + return; +} + +void +check (signed char *arr, int idx, int len, int v) +{ + int i; + for (i = 0; i < idx; i++) + if (arr[i] != v) + abort (); + + for (i = idx; i < len; i++) + if (arr[i] != 0) + abort (); +} + +int +main(void) +{ + foo (); + check ((signed char *)a, 14, sizeof (a), -1); + + return 0; +} +/* { dg-final { scan-assembler-not "bl?\[ \t\]*memset" { target { arm_little_endian && arm_neon } } } } */ +/* { dg-final { scan-assembler "vst1" { target { arm_little_endian && arm_neon } } } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon-modes-2.c b/gcc/testsuite/gcc.target/arm/neon-modes-2.c index 40f1bba363b..16319bb2a1f 100644 --- a/gcc/testsuite/gcc.target/arm/neon-modes-2.c +++ b/gcc/testsuite/gcc.target/arm/neon-modes-2.c @@ -11,6 +11,8 @@ #define MANY(A) A (0), A (1), A (2), A (3), A (4), A (5) +extern void foo (int *, int *); + void bar (uint32_t *ptr, int y) { diff --git a/gcc/testsuite/gcc.target/arm/neon-vext-execute.c b/gcc/testsuite/gcc.target/arm/neon-vext-execute.c index 3d6c28cca89..8e44d9ad555 100644 --- a/gcc/testsuite/gcc.target/arm/neon-vext-execute.c +++ b/gcc/testsuite/gcc.target/arm/neon-vext-execute.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target arm_neon_ok } */ +/* { dg-require-effective-target arm_neon_hw } */ /* { dg-require-effective-target arm_little_endian } */ /* { dg-options "-O2" } */ /* { dg-add-options arm_neon } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/neon.exp b/gcc/testsuite/gcc.target/arm/neon/neon.exp index 746429dadf6..3afb537f27c 100644 --- a/gcc/testsuite/gcc.target/arm/neon/neon.exp +++ b/gcc/testsuite/gcc.target/arm/neon/neon.exp @@ -1,4 +1,4 @@ -# Copyright (C) 1997-2014 Free Software Foundation, Inc. +# Copyright (C) 1997-2015 Free Software Foundation, Inc. # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c b/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c index e15a260ef11..c8c026f015f 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +int16x8_t out_int16x8_t; +int16x8_t arg0_int16x8_t; +int16x8_t arg1_int16x8_t; void test_vbicQs16 (void) { - int16x8_t out_int16x8_t; - int16x8_t arg0_int16x8_t; - int16x8_t arg1_int16x8_t; out_int16x8_t = vbicq_s16 (arg0_int16x8_t, arg1_int16x8_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c b/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c index f376bf077ca..3b858576ac1 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +int32x4_t out_int32x4_t; +int32x4_t arg0_int32x4_t; +int32x4_t arg1_int32x4_t; void test_vbicQs32 (void) { - int32x4_t out_int32x4_t; - int32x4_t arg0_int32x4_t; - int32x4_t arg1_int32x4_t; out_int32x4_t = vbicq_s32 (arg0_int32x4_t, arg1_int32x4_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c b/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c index 87049f129dc..d71da8737a5 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +int64x2_t out_int64x2_t; +int64x2_t arg0_int64x2_t; +int64x2_t arg1_int64x2_t; void test_vbicQs64 (void) { - int64x2_t out_int64x2_t; - int64x2_t arg0_int64x2_t; - int64x2_t arg1_int64x2_t; out_int64x2_t = vbicq_s64 (arg0_int64x2_t, arg1_int64x2_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c b/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c index 4f64e881782..4cbfe9fde64 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +int8x16_t out_int8x16_t; +int8x16_t arg0_int8x16_t; +int8x16_t arg1_int8x16_t; void test_vbicQs8 (void) { - int8x16_t out_int8x16_t; - int8x16_t arg0_int8x16_t; - int8x16_t arg1_int8x16_t; out_int8x16_t = vbicq_s8 (arg0_int8x16_t, arg1_int8x16_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c b/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c index f92f9b38498..6661c510d80 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +uint16x8_t out_uint16x8_t; +uint16x8_t arg0_uint16x8_t; +uint16x8_t arg1_uint16x8_t; void test_vbicQu16 (void) { - uint16x8_t out_uint16x8_t; - uint16x8_t arg0_uint16x8_t; - uint16x8_t arg1_uint16x8_t; out_uint16x8_t = vbicq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c b/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c index 06d10da2355..ca8391e9248 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +uint32x4_t out_uint32x4_t; +uint32x4_t arg0_uint32x4_t; +uint32x4_t arg1_uint32x4_t; void test_vbicQu32 (void) { - uint32x4_t out_uint32x4_t; - uint32x4_t arg0_uint32x4_t; - uint32x4_t arg1_uint32x4_t; out_uint32x4_t = vbicq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c b/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c index 7cd63c0358c..d565333d6ec 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +uint64x2_t out_uint64x2_t; +uint64x2_t arg0_uint64x2_t; +uint64x2_t arg1_uint64x2_t; void test_vbicQu64 (void) { - uint64x2_t out_uint64x2_t; - uint64x2_t arg0_uint64x2_t; - uint64x2_t arg1_uint64x2_t; out_uint64x2_t = vbicq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c b/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c index 3f44418d704..d9f18edb490 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +uint8x16_t out_uint8x16_t; +uint8x16_t arg0_uint8x16_t; +uint8x16_t arg1_uint8x16_t; void test_vbicQu8 (void) { - uint8x16_t out_uint8x16_t; - uint8x16_t arg0_uint8x16_t; - uint8x16_t arg1_uint8x16_t; out_uint8x16_t = vbicq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vbics16.c b/gcc/testsuite/gcc.target/arm/neon/vbics16.c index 943e3053417..7247878fa70 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vbics16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vbics16.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +int16x4_t out_int16x4_t; +int16x4_t arg0_int16x4_t; +int16x4_t arg1_int16x4_t; void test_vbics16 (void) { - int16x4_t out_int16x4_t; - int16x4_t arg0_int16x4_t; - int16x4_t arg1_int16x4_t; out_int16x4_t = vbic_s16 (arg0_int16x4_t, arg1_int16x4_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vbics32.c b/gcc/testsuite/gcc.target/arm/neon/vbics32.c index 30df639e305..585d2ef16dc 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vbics32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vbics32.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +int32x2_t out_int32x2_t; +int32x2_t arg0_int32x2_t; +int32x2_t arg1_int32x2_t; void test_vbics32 (void) { - int32x2_t out_int32x2_t; - int32x2_t arg0_int32x2_t; - int32x2_t arg1_int32x2_t; out_int32x2_t = vbic_s32 (arg0_int32x2_t, arg1_int32x2_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vbics64.c b/gcc/testsuite/gcc.target/arm/neon/vbics64.c index 379db45f4db..8932a287138 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vbics64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vbics64.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +int64x1_t out_int64x1_t; +int64x1_t arg0_int64x1_t; +int64x1_t arg1_int64x1_t; void test_vbics64 (void) { - int64x1_t out_int64x1_t; - int64x1_t arg0_int64x1_t; - int64x1_t arg1_int64x1_t; out_int64x1_t = vbic_s64 (arg0_int64x1_t, arg1_int64x1_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vbics8.c b/gcc/testsuite/gcc.target/arm/neon/vbics8.c index 3b4bc8a8d87..9a1839a1c8a 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vbics8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vbics8.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +int8x8_t out_int8x8_t; +int8x8_t arg0_int8x8_t; +int8x8_t arg1_int8x8_t; void test_vbics8 (void) { - int8x8_t out_int8x8_t; - int8x8_t arg0_int8x8_t; - int8x8_t arg1_int8x8_t; out_int8x8_t = vbic_s8 (arg0_int8x8_t, arg1_int8x8_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicu16.c b/gcc/testsuite/gcc.target/arm/neon/vbicu16.c index e9952bc52c4..3f3002b7af7 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vbicu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vbicu16.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +uint16x4_t out_uint16x4_t; +uint16x4_t arg0_uint16x4_t; +uint16x4_t arg1_uint16x4_t; void test_vbicu16 (void) { - uint16x4_t out_uint16x4_t; - uint16x4_t arg0_uint16x4_t; - uint16x4_t arg1_uint16x4_t; out_uint16x4_t = vbic_u16 (arg0_uint16x4_t, arg1_uint16x4_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicu32.c b/gcc/testsuite/gcc.target/arm/neon/vbicu32.c index 9334f403f64..0653d6df038 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vbicu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vbicu32.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +uint32x2_t out_uint32x2_t; +uint32x2_t arg0_uint32x2_t; +uint32x2_t arg1_uint32x2_t; void test_vbicu32 (void) { - uint32x2_t out_uint32x2_t; - uint32x2_t arg0_uint32x2_t; - uint32x2_t arg1_uint32x2_t; out_uint32x2_t = vbic_u32 (arg0_uint32x2_t, arg1_uint32x2_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicu64.c b/gcc/testsuite/gcc.target/arm/neon/vbicu64.c index c276d65ebe3..7d0571388a5 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vbicu64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vbicu64.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +uint64x1_t out_uint64x1_t; +uint64x1_t arg0_uint64x1_t; +uint64x1_t arg1_uint64x1_t; void test_vbicu64 (void) { - uint64x1_t out_uint64x1_t; - uint64x1_t arg0_uint64x1_t; - uint64x1_t arg1_uint64x1_t; out_uint64x1_t = vbic_u64 (arg0_uint64x1_t, arg1_uint64x1_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicu8.c b/gcc/testsuite/gcc.target/arm/neon/vbicu8.c index 5e42c52374f..10c70b0b0eb 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vbicu8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vbicu8.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +uint8x8_t out_uint8x8_t; +uint8x8_t arg0_uint8x8_t; +uint8x8_t arg1_uint8x8_t; void test_vbicu8 (void) { - uint8x8_t out_uint8x8_t; - uint8x8_t arg0_uint8x8_t; - uint8x8_t arg1_uint8x8_t; out_uint8x8_t = vbic_u8 (arg0_uint8x8_t, arg1_uint8x8_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQs16.c b/gcc/testsuite/gcc.target/arm/neon/vornQs16.c index 519da3cccb0..2e635643785 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vornQs16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vornQs16.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +int16x8_t out_int16x8_t; +int16x8_t arg0_int16x8_t; +int16x8_t arg1_int16x8_t; void test_vornQs16 (void) { - int16x8_t out_int16x8_t; - int16x8_t arg0_int16x8_t; - int16x8_t arg1_int16x8_t; out_int16x8_t = vornq_s16 (arg0_int16x8_t, arg1_int16x8_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQs32.c b/gcc/testsuite/gcc.target/arm/neon/vornQs32.c index cec659911a3..339514b7c88 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vornQs32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vornQs32.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +int32x4_t out_int32x4_t; +int32x4_t arg0_int32x4_t; +int32x4_t arg1_int32x4_t; void test_vornQs32 (void) { - int32x4_t out_int32x4_t; - int32x4_t arg0_int32x4_t; - int32x4_t arg1_int32x4_t; out_int32x4_t = vornq_s32 (arg0_int32x4_t, arg1_int32x4_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQs64.c b/gcc/testsuite/gcc.target/arm/neon/vornQs64.c index 05166ba4e8d..64d62698f3e 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vornQs64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vornQs64.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +int64x2_t out_int64x2_t; +int64x2_t arg0_int64x2_t; +int64x2_t arg1_int64x2_t; void test_vornQs64 (void) { - int64x2_t out_int64x2_t; - int64x2_t arg0_int64x2_t; - int64x2_t arg1_int64x2_t; out_int64x2_t = vornq_s64 (arg0_int64x2_t, arg1_int64x2_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQs8.c b/gcc/testsuite/gcc.target/arm/neon/vornQs8.c index 99982aefdb2..c8b1ed2624d 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vornQs8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vornQs8.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +int8x16_t out_int8x16_t; +int8x16_t arg0_int8x16_t; +int8x16_t arg1_int8x16_t; void test_vornQs8 (void) { - int8x16_t out_int8x16_t; - int8x16_t arg0_int8x16_t; - int8x16_t arg1_int8x16_t; out_int8x16_t = vornq_s8 (arg0_int8x16_t, arg1_int8x16_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQu16.c b/gcc/testsuite/gcc.target/arm/neon/vornQu16.c index 761e72d7b26..c0663672087 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vornQu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vornQu16.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +uint16x8_t out_uint16x8_t; +uint16x8_t arg0_uint16x8_t; +uint16x8_t arg1_uint16x8_t; void test_vornQu16 (void) { - uint16x8_t out_uint16x8_t; - uint16x8_t arg0_uint16x8_t; - uint16x8_t arg1_uint16x8_t; out_uint16x8_t = vornq_u16 (arg0_uint16x8_t, arg1_uint16x8_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQu32.c b/gcc/testsuite/gcc.target/arm/neon/vornQu32.c index 18a9685397f..7a278e07b00 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vornQu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vornQu32.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +uint32x4_t out_uint32x4_t; +uint32x4_t arg0_uint32x4_t; +uint32x4_t arg1_uint32x4_t; void test_vornQu32 (void) { - uint32x4_t out_uint32x4_t; - uint32x4_t arg0_uint32x4_t; - uint32x4_t arg1_uint32x4_t; out_uint32x4_t = vornq_u32 (arg0_uint32x4_t, arg1_uint32x4_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQu64.c b/gcc/testsuite/gcc.target/arm/neon/vornQu64.c index 84c9f895db5..7948e10e290 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vornQu64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vornQu64.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +uint64x2_t out_uint64x2_t; +uint64x2_t arg0_uint64x2_t; +uint64x2_t arg1_uint64x2_t; void test_vornQu64 (void) { - uint64x2_t out_uint64x2_t; - uint64x2_t arg0_uint64x2_t; - uint64x2_t arg1_uint64x2_t; out_uint64x2_t = vornq_u64 (arg0_uint64x2_t, arg1_uint64x2_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQu8.c b/gcc/testsuite/gcc.target/arm/neon/vornQu8.c index ffe6766d468..31aa62cbd22 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vornQu8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vornQu8.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +uint8x16_t out_uint8x16_t; +uint8x16_t arg0_uint8x16_t; +uint8x16_t arg1_uint8x16_t; void test_vornQu8 (void) { - uint8x16_t out_uint8x16_t; - uint8x16_t arg0_uint8x16_t; - uint8x16_t arg1_uint8x16_t; out_uint8x16_t = vornq_u8 (arg0_uint8x16_t, arg1_uint8x16_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vorns16.c b/gcc/testsuite/gcc.target/arm/neon/vorns16.c index b860142dc68..375a0e99761 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vorns16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vorns16.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +int16x4_t out_int16x4_t; +int16x4_t arg0_int16x4_t; +int16x4_t arg1_int16x4_t; void test_vorns16 (void) { - int16x4_t out_int16x4_t; - int16x4_t arg0_int16x4_t; - int16x4_t arg1_int16x4_t; out_int16x4_t = vorn_s16 (arg0_int16x4_t, arg1_int16x4_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vorns32.c b/gcc/testsuite/gcc.target/arm/neon/vorns32.c index 826e0d28864..502b9acfbf5 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vorns32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vorns32.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +int32x2_t out_int32x2_t; +int32x2_t arg0_int32x2_t; +int32x2_t arg1_int32x2_t; void test_vorns32 (void) { - int32x2_t out_int32x2_t; - int32x2_t arg0_int32x2_t; - int32x2_t arg1_int32x2_t; out_int32x2_t = vorn_s32 (arg0_int32x2_t, arg1_int32x2_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vorns64.c b/gcc/testsuite/gcc.target/arm/neon/vorns64.c index d7b8e60d208..090e9d44fab 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vorns64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vorns64.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +int64x1_t out_int64x1_t; +int64x1_t arg0_int64x1_t; +int64x1_t arg1_int64x1_t; void test_vorns64 (void) { - int64x1_t out_int64x1_t; - int64x1_t arg0_int64x1_t; - int64x1_t arg1_int64x1_t; out_int64x1_t = vorn_s64 (arg0_int64x1_t, arg1_int64x1_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vorns8.c b/gcc/testsuite/gcc.target/arm/neon/vorns8.c index c71a6bb0a3e..d50afc8a263 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vorns8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vorns8.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +int8x8_t out_int8x8_t; +int8x8_t arg0_int8x8_t; +int8x8_t arg1_int8x8_t; void test_vorns8 (void) { - int8x8_t out_int8x8_t; - int8x8_t arg0_int8x8_t; - int8x8_t arg1_int8x8_t; out_int8x8_t = vorn_s8 (arg0_int8x8_t, arg1_int8x8_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vornu16.c b/gcc/testsuite/gcc.target/arm/neon/vornu16.c index d4983eebfea..d20bffc272e 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vornu16.c +++ b/gcc/testsuite/gcc.target/arm/neon/vornu16.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +uint16x4_t out_uint16x4_t; +uint16x4_t arg0_uint16x4_t; +uint16x4_t arg1_uint16x4_t; void test_vornu16 (void) { - uint16x4_t out_uint16x4_t; - uint16x4_t arg0_uint16x4_t; - uint16x4_t arg1_uint16x4_t; out_uint16x4_t = vorn_u16 (arg0_uint16x4_t, arg1_uint16x4_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vornu32.c b/gcc/testsuite/gcc.target/arm/neon/vornu32.c index aba68841a47..f17394f5bb8 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vornu32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vornu32.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +uint32x2_t out_uint32x2_t; +uint32x2_t arg0_uint32x2_t; +uint32x2_t arg1_uint32x2_t; void test_vornu32 (void) { - uint32x2_t out_uint32x2_t; - uint32x2_t arg0_uint32x2_t; - uint32x2_t arg1_uint32x2_t; out_uint32x2_t = vorn_u32 (arg0_uint32x2_t, arg1_uint32x2_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vornu64.c b/gcc/testsuite/gcc.target/arm/neon/vornu64.c index 6fb3a9502a6..86af5c56f9b 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vornu64.c +++ b/gcc/testsuite/gcc.target/arm/neon/vornu64.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +uint64x1_t out_uint64x1_t; +uint64x1_t arg0_uint64x1_t; +uint64x1_t arg1_uint64x1_t; void test_vornu64 (void) { - uint64x1_t out_uint64x1_t; - uint64x1_t arg0_uint64x1_t; - uint64x1_t arg1_uint64x1_t; out_uint64x1_t = vorn_u64 (arg0_uint64x1_t, arg1_uint64x1_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vornu8.c b/gcc/testsuite/gcc.target/arm/neon/vornu8.c index 6fdb7331c0b..347f9c8fc93 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vornu8.c +++ b/gcc/testsuite/gcc.target/arm/neon/vornu8.c @@ -3,16 +3,16 @@ /* { dg-do assemble } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ +/* { dg-options "-save-temps -O2" } */ /* { dg-add-options arm_neon } */ #include "arm_neon.h" +uint8x8_t out_uint8x8_t; +uint8x8_t arg0_uint8x8_t; +uint8x8_t arg1_uint8x8_t; void test_vornu8 (void) { - uint8x8_t out_uint8x8_t; - uint8x8_t arg0_uint8x8_t; - uint8x8_t arg1_uint8x8_t; out_uint8x8_t = vorn_u8 (arg0_uint8x8_t, arg1_uint8x8_t); } diff --git a/gcc/testsuite/gcc.target/arm/neon/vrndqaf32.c b/gcc/testsuite/gcc.target/arm/neon/vrndaqf32.c index b7b5d73c485..c1acb64e8e7 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vrndqaf32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vrndaqf32.c @@ -1,4 +1,4 @@ -/* Test the `vrndqaf32' ARM Neon intrinsic. */ +/* Test the `vrndaq_f32' ARM Neon intrinsic. */ /* This file was autogenerated by neon-testgen. */ /* { dg-do assemble } */ @@ -8,12 +8,12 @@ #include "arm_neon.h" -void test_vrndqaf32 (void) +void test_vrndaqf32 (void) { float32x4_t out_float32x4_t; float32x4_t arg0_float32x4_t; - out_float32x4_t = vrndqa_f32 (arg0_float32x4_t); + out_float32x4_t = vrndaq_f32 (arg0_float32x4_t); } /* { dg-final { scan-assembler "vrinta\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrndqmf32.c b/gcc/testsuite/gcc.target/arm/neon/vrndmqf32.c index 6d16bfc9334..306d4f8b03b 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vrndqmf32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vrndmqf32.c @@ -1,4 +1,4 @@ -/* Test the `vrndqmf32' ARM Neon intrinsic. */ +/* Test the `vrndmq_f32' ARM Neon intrinsic. */ /* This file was autogenerated by neon-testgen. */ /* { dg-do assemble } */ @@ -8,12 +8,12 @@ #include "arm_neon.h" -void test_vrndqmf32 (void) +void test_vrndmqf32 (void) { float32x4_t out_float32x4_t; float32x4_t arg0_float32x4_t; - out_float32x4_t = vrndqm_f32 (arg0_float32x4_t); + out_float32x4_t = vrndmq_f32 (arg0_float32x4_t); } /* { dg-final { scan-assembler "vrintm\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrndqnf32.c b/gcc/testsuite/gcc.target/arm/neon/vrndnqf32.c index b31ca95db42..0a70529bd66 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vrndqnf32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vrndnqf32.c @@ -1,4 +1,4 @@ -/* Test the `vrndqnf32' ARM Neon intrinsic. */ +/* Test the `vrndnq_f32' ARM Neon intrinsic. */ /* This file was autogenerated by neon-testgen. */ /* { dg-do assemble } */ @@ -8,12 +8,12 @@ #include "arm_neon.h" -void test_vrndqnf32 (void) +void test_vrndnqf32 (void) { float32x4_t out_float32x4_t; float32x4_t arg0_float32x4_t; - out_float32x4_t = vrndqn_f32 (arg0_float32x4_t); + out_float32x4_t = vrndnq_f32 (arg0_float32x4_t); } /* { dg-final { scan-assembler "vrintn\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrndqpf32.c b/gcc/testsuite/gcc.target/arm/neon/vrndpqf32.c index 5c4a8669069..723fee4e576 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vrndqpf32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vrndpqf32.c @@ -1,4 +1,4 @@ -/* Test the `vrndqpf32' ARM Neon intrinsic. */ +/* Test the `vrndpq_f32' ARM Neon intrinsic. */ /* This file was autogenerated by neon-testgen. */ /* { dg-do assemble } */ @@ -8,12 +8,12 @@ #include "arm_neon.h" -void test_vrndqpf32 (void) +void test_vrndpqf32 (void) { float32x4_t out_float32x4_t; float32x4_t arg0_float32x4_t; - out_float32x4_t = vrndqp_f32 (arg0_float32x4_t); + out_float32x4_t = vrndpq_f32 (arg0_float32x4_t); } /* { dg-final { scan-assembler "vrintp\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pr40956.c b/gcc/testsuite/gcc.target/arm/pr40956.c index 167cdc6ece0..4fefa49a587 100644 --- a/gcc/testsuite/gcc.target/arm/pr40956.c +++ b/gcc/testsuite/gcc.target/arm/pr40956.c @@ -1,7 +1,8 @@ /* { dg-options "-Os -fpic" } */ /* { dg-require-effective-target fpic } */ /* Make sure the constant "0" is loaded into register only once. */ -/* { dg-final { scan-assembler-times "mov\[\\t \]*r., #0" 1 } } */ +/* { dg-final { scan-assembler-times "movs\[\\t \]*r., #0" 1 { target arm_thumb1 } } } */ +/* { dg-final { scan-assembler-times "mov\[\\t \]*r., #0" 1 { target { ! arm_thumb1 } } } } */ int foo(int p, int* q) { diff --git a/gcc/testsuite/gcc.target/arm/pr43920-2.c b/gcc/testsuite/gcc.target/arm/pr43920-2.c index f647165bd63..f5e8f4837c6 100644 --- a/gcc/testsuite/gcc.target/arm/pr43920-2.c +++ b/gcc/testsuite/gcc.target/arm/pr43920-2.c @@ -4,6 +4,8 @@ #include <stdio.h> +extern int lseek(int, long, int); + int getFileStartAndLength (int fd, int *start_, size_t *length_) { int start, end; diff --git a/gcc/testsuite/gcc.target/arm/pr44788.c b/gcc/testsuite/gcc.target/arm/pr44788.c index eb4bc11af9f..9ce44a8e765 100644 --- a/gcc/testsuite/gcc.target/arm/pr44788.c +++ b/gcc/testsuite/gcc.target/arm/pr44788.c @@ -2,6 +2,8 @@ /* { dg-require-effective-target arm_thumb2_ok } */ /* { dg-options "-Os -fno-strict-aliasing -fPIC -mthumb -march=armv7-a -mfpu=vfp3 -mfloat-abi=softfp" } */ +extern void foo (float *); + void joint_decode(float* mlt_buffer1, int t) { int i; float decode_buffer[1060]; diff --git a/gcc/testsuite/gcc.target/arm/pr45094.c b/gcc/testsuite/gcc.target/arm/pr45094.c index f35e7bb2d7f..7cebf4d50cc 100644 --- a/gcc/testsuite/gcc.target/arm/pr45094.c +++ b/gcc/testsuite/gcc.target/arm/pr45094.c @@ -1,7 +1,6 @@ /* { dg-do run } */ -/* { dg-skip-if "incompatible options" { arm*-*-* } { "-march=*" } { "-march=armv7-a" } } */ /* { dg-require-effective-target arm_neon_hw } */ -/* { dg-options "-O2 -mcpu=cortex-a8" } */ +/* { dg-options "-O2" } */ /* { dg-add-options arm_neon } */ #include <stdlib.h> diff --git a/gcc/testsuite/gcc.target/arm/pr48252.c b/gcc/testsuite/gcc.target/arm/pr48252.c index 17f729bb341..250d5e4d6f9 100644 --- a/gcc/testsuite/gcc.target/arm/pr48252.c +++ b/gcc/testsuite/gcc.target/arm/pr48252.c @@ -15,7 +15,6 @@ int main(void) uint8x8x2_t vd1, vd2; union {uint8x8_t v; uint8_t buf[8];} d1, d2, d3, d4; int i; - uint8_t odd, even; vd1 = vzip_u8(v1, vdup_n_u8(0)); vd2 = vzip_u8(v2, vdup_n_u8(0)); @@ -25,17 +24,9 @@ int main(void) vst1_u8(d3.buf, vd2.val[0]); vst1_u8(d4.buf, vd2.val[1]); -#ifdef __ARMEL__ - odd = 1; - even = 0; -#else - odd = 0; - even = 1; -#endif - for (i = 0; i < 8; i++) - if ((i % 2 == even && d4.buf[i] != 2) - || (i % 2 == odd && d4.buf[i] != 0)) + if ((i % 2 == 0 && d4.buf[i] != 2) + || (i % 2 == 1 && d4.buf[i] != 0)) abort (); return 0; diff --git a/gcc/testsuite/gcc.target/arm/pr51835.c b/gcc/testsuite/gcc.target/arm/pr51835.c index 6d462d91596..128b9d5d596 100644 --- a/gcc/testsuite/gcc.target/arm/pr51835.c +++ b/gcc/testsuite/gcc.target/arm/pr51835.c @@ -13,5 +13,5 @@ unsigned int func2 (double d) return (unsigned int)d; } -/* { dg-final { scan-assembler-times "fmrrd\[\\t \]+r0,\[\\t \]*r1,\[\\t \]*d0" 2 { target { arm_little_endian } } } } */ -/* { dg-final { scan-assembler-times "fmrrd\[\\t \]+r1,\[\\t \]*r0,\[\\t \]*d0" 2 { target { ! arm_little_endian } } } } */ +/* { dg-final { scan-assembler-times "vmov\[\\t \]+r0,\[\\t \]*r1,\[\\t \]*d0" 2 { target { arm_little_endian } } } } */ +/* { dg-final { scan-assembler-times "vmov\[\\t \]+r1,\[\\t \]*r0,\[\\t \]*d0" 2 { target { ! arm_little_endian } } } } */ diff --git a/gcc/testsuite/gcc.target/arm/pr51968.c b/gcc/testsuite/gcc.target/arm/pr51968.c index f0506c267fe..99bdb961757 100644 --- a/gcc/testsuite/gcc.target/arm/pr51968.c +++ b/gcc/testsuite/gcc.target/arm/pr51968.c @@ -1,6 +1,6 @@ /* PR target/51968 */ /* { dg-do compile } */ -/* { dg-options "-O2 -march=armv7-a -mfloat-abi=softfp -mfpu=neon" } */ +/* { dg-options "-O2 -Wno-implicit-function-declaration -march=armv7-a -mfloat-abi=softfp -mfpu=neon" } */ /* { dg-require-effective-target arm_neon_ok } */ typedef __builtin_neon_qi int8x8_t __attribute__ ((__vector_size__ (8))); @@ -24,7 +24,7 @@ foo (int8x8_t z, int8x8_t x, int16x8_t b, int8x8_t n) int8x16_t g; int8x8_t h, j, k; struct T m; - j = __builtin_neon_vqmovunv8hi (b, 1); + j = __builtin_neon_vqmovunv8hi (b); g = __builtin_neon_vcombinev8qi (j, h); k = __builtin_neon_vget_lowv16qi (g); __builtin_neon_vuzpv8qi (&m.val[0], k, n); diff --git a/gcc/testsuite/gcc.target/arm/pr55642.c b/gcc/testsuite/gcc.target/arm/pr55642.c index 10f2daa252d..a7defa77d52 100644 --- a/gcc/testsuite/gcc.target/arm/pr55642.c +++ b/gcc/testsuite/gcc.target/arm/pr55642.c @@ -2,6 +2,8 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_thumb2_ok } */ +extern int abs (int); + int foo (int v) { diff --git a/gcc/testsuite/gcc.target/arm/pr56184.C b/gcc/testsuite/gcc.target/arm/pr56184.C index d44c1b432da..5d23c40c582 100644 --- a/gcc/testsuite/gcc.target/arm/pr56184.C +++ b/gcc/testsuite/gcc.target/arm/pr56184.C @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-skip-if "incompatible options" { ! { arm_thumb1_ok || arm_thumb2_ok } } { "*" } { "" } } */ /* { dg-options "-fno-short-enums -O2 -mthumb -march=armv7-a -mfpu=neon -mfloat-abi=softfp -mtune=cortex-a9 -fno-section-anchors" } */ typedef unsigned int size_t; diff --git a/gcc/testsuite/gcc.target/arm/pr58784.c b/gcc/testsuite/gcc.target/arm/pr58784.c index e3ef950b499..4ee3ef5a4fb 100644 --- a/gcc/testsuite/gcc.target/arm/pr58784.c +++ b/gcc/testsuite/gcc.target/arm/pr58784.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-skip-if "incompatible options" { arm_thumb1 } { "*" } { "" } } */ /* { dg-options "-march=armv7-a -mfloat-abi=hard -mfpu=neon -marm -O2" } */ typedef struct __attribute__ ((__packed__)) @@ -10,6 +11,9 @@ typedef struct __attribute__ ((__packed__)) char stepsRemoved; ptp_tlv_t tlv[1]; } ptp_message_announce_t; + +extern void f (ptp_message_announce_t *); + int ptplib_send_announce(int sequenceId, int i) { ptp_message_announce_t tx_packet; diff --git a/gcc/testsuite/gcc.target/arm/pr59896.c b/gcc/testsuite/gcc.target/arm/pr59896.c index 5896e73799d..ea6dc248b98 100644 --- a/gcc/testsuite/gcc.target/arm/pr59896.c +++ b/gcc/testsuite/gcc.target/arm/pr59896.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-skip-if "incompatible options" { ! { arm_thumb1_ok || arm_thumb2_ok } } { "*" } { "" } } */ /* { dg-options "-mthumb -O2" } */ typedef unsigned int size_t; diff --git a/gcc/testsuite/gcc.target/arm/pr59985.C b/gcc/testsuite/gcc.target/arm/pr59985.C index cc688a96533..1351c486fe3 100644 --- a/gcc/testsuite/gcc.target/arm/pr59985.C +++ b/gcc/testsuite/gcc.target/arm/pr59985.C @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-skip-if "incompatible options" { arm_thumb1 } { "*" } { "" } } */ /* { dg-options "-g -fcompare-debug -O2 -march=armv7-a -mtune=cortex-a9 -mfpu=vfpv3-d16 -mfloat-abi=hard" } */ extern void *f1 (unsigned long, unsigned long); diff --git a/gcc/testsuite/gcc.target/arm/pr60606-2.c b/gcc/testsuite/gcc.target/arm/pr60606-2.c new file mode 100644 index 00000000000..7baf88126f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr60606-2.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +int +f (void) +{ + register unsigned pc asm ("pc"); /* { dg-error "not general enough" } */ + + return pc > 0x12345678; +} diff --git a/gcc/testsuite/gcc.target/arm/pr60606-3.c b/gcc/testsuite/gcc.target/arm/pr60606-3.c new file mode 100644 index 00000000000..60ae27db53d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr60606-3.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +int +f (void) +{ + register unsigned int r asm ("cc"); /* { dg-error "not general enough|suitable for data type" } */ + return r; +} diff --git a/gcc/testsuite/gcc.target/arm/pr60606-4.c b/gcc/testsuite/gcc.target/arm/pr60606-4.c new file mode 100644 index 00000000000..5288777a77b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr60606-4.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +int +f (void) +{ + register unsigned int r[50] asm ("r1"); /* { dg-error "suitable for a register" } */ + return r[1]; +} diff --git a/gcc/testsuite/gcc.target/arm/pr60650-2.c b/gcc/testsuite/gcc.target/arm/pr60650-2.c index 19467607b6e..c8d46152423 100644 --- a/gcc/testsuite/gcc.target/arm/pr60650-2.c +++ b/gcc/testsuite/gcc.target/arm/pr60650-2.c @@ -4,17 +4,19 @@ int a, h, j; long long d, e, i; int f; +int fn1 (void *p1, int p2) { switch (p2) case 8: { - register b = *(long long *) p1, c asm ("r2"); + register int b = *(long long *) p1, c asm ("r2"); asm ("%0": "=r" (a), "=r" (c):"r" (b), "r" (0)); *(long long *) p1 = c; } } +int fn2 () { int k; @@ -27,8 +29,8 @@ fn2 () case 0: ( { - register l asm ("r4"); - register m asm ("r0"); + register int l asm ("r4"); + register int m asm ("r0"); asm (" .err .endif\n\t": "=r" (h), "=r" (j):"r" (m), "r" (l));; diff --git a/gcc/testsuite/gcc.target/arm/pr60650.c b/gcc/testsuite/gcc.target/arm/pr60650.c index 17a5ed448cf..734b41f001a 100644 --- a/gcc/testsuite/gcc.target/arm/pr60650.c +++ b/gcc/testsuite/gcc.target/arm/pr60650.c @@ -20,6 +20,10 @@ struct btrfs_root int a, c, d; long long e; +extern int foo1 (struct btrfs_root *, int, int, int); +extern int foo2 (struct btrfs_root *, int, int); + +int truncate_one_csum (struct btrfs_root *p1, long long p2, long long p3) { int f, g, i = p1->fs_info->sb->s_blocksize_bits; diff --git a/gcc/testsuite/gcc.target/arm/pr60663.c b/gcc/testsuite/gcc.target/arm/pr60663.c new file mode 100644 index 00000000000..b79b830e1a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr60663.c @@ -0,0 +1,11 @@ +/* PR rtl-optimization/60663 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv7-a" } */ + +int +foo (void) +{ + unsigned i, j; + asm ("%0 %1" : "=r" (i), "=r" (j)); + return i; +} diff --git a/gcc/testsuite/gcc.target/arm/pr61948.c b/gcc/testsuite/gcc.target/arm/pr61948.c new file mode 100644 index 00000000000..411e898ea77 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr61948.c @@ -0,0 +1,16 @@ +/* PR target/61948 */ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-options "-O2 -mthumb" } */ +/* { dg-add-options arm_neon } */ + +long long f (long long *c) +{ + long long t = c[0]; + asm ("nop" : : : "r0", "r3", "r4", "r5", + "r6", "r7", "r8", "r9", + "r10", "r11", "r12", "memory"); + return t >> 1; +} + diff --git a/gcc/testsuite/gcc.target/arm/pr63210.c b/gcc/testsuite/gcc.target/arm/pr63210.c new file mode 100644 index 00000000000..c3ae92801f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr63210.c @@ -0,0 +1,12 @@ +/* { dg-do assemble } */ +/* { dg-options "-mthumb -Os " } */ +/* { dg-require-effective-target arm_thumb1_ok } */ + +int foo1 (int c); +int foo2 (int c); + +int test (int c) +{ + return (foo1 (c) || foo2 (c)); +} +/* { dg-final { object-size text <= 28 } } */ diff --git a/gcc/testsuite/gcc.target/arm/pr64453.c b/gcc/testsuite/gcc.target/arm/pr64453.c new file mode 100644 index 00000000000..17155afc9d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr64453.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mthumb -Os " } */ +/* { dg-require-effective-target arm_thumb1_ok } */ + +void save_regs () { + __asm volatile ("" ::: "r8"); +} + +/* { dg-final { scan-assembler "\tmov\tr., r8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pr64460_1.c b/gcc/testsuite/gcc.target/arm/pr64460_1.c new file mode 100644 index 00000000000..ee6ad4a214f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr64460_1.c @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune=xscale" } */ + +typedef unsigned int size_t; +typedef short unsigned int __uint16_t; +typedef long unsigned int __uint32_t; +typedef unsigned int __uintptr_t; +typedef __uint16_t uint16_t ; +typedef __uint32_t uint32_t ; +typedef __uintptr_t uintptr_t; +typedef uint32_t Objects_Id; +typedef uint16_t Objects_Maximum; +typedef struct { } Objects_Control; + +static __inline__ void *_Addresses_Align_up (void *address, size_t alignment) +{ + uintptr_t mask = alignment - (uintptr_t)1; + return (void*)(((uintptr_t)address + mask) & ~mask); +} + +typedef struct { + Objects_Id minimum_id; + Objects_Maximum maximum; + _Bool + auto_extend; + Objects_Maximum allocation_size; + void **object_blocks; +} Objects_Information; + +extern uint32_t _Objects_Get_index (Objects_Id); +extern void** _Workspace_Allocate (size_t); + +void _Objects_Extend_information (Objects_Information *information) +{ + uint32_t block_count; + uint32_t minimum_index; + uint32_t maximum; + size_t block_size; + _Bool + do_extend = + minimum_index = _Objects_Get_index( information->minimum_id ); + if ( information->object_blocks == + ((void *)0) + ) + block_count = 0; + else { + block_count = information->maximum / information->allocation_size; + } + if ( do_extend ) { + void **object_blocks; + uintptr_t object_blocks_size; + uintptr_t inactive_per_block_size; + object_blocks_size = (uintptr_t)_Addresses_Align_up( + (void*)(block_count * sizeof(void*)), + 8 + ); + inactive_per_block_size = + (uintptr_t)_Addresses_Align_up( + (void*)(block_count * sizeof(uint32_t)), + 8 + ); + block_size = object_blocks_size + inactive_per_block_size + + ((maximum + minimum_index) * sizeof(Objects_Control *)); + if ( information->auto_extend ) { + object_blocks = _Workspace_Allocate( block_size ); + } else { + } + } +} diff --git a/gcc/testsuite/gcc.target/arm/rev16.c b/gcc/testsuite/gcc.target/arm/rev16.c new file mode 100644 index 00000000000..1c869b3067a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/rev16.c @@ -0,0 +1,35 @@ +/* { dg-options "-O2" } */ +/* { dg-do run } */ + +extern void abort (void); + +typedef unsigned int __u32; + +__u32 +__rev16_32_alt (__u32 x) +{ + return (((__u32)(x) & (__u32)0xff00ff00UL) >> 8) + | (((__u32)(x) & (__u32)0x00ff00ffUL) << 8); +} + +__u32 +__rev16_32 (__u32 x) +{ + return (((__u32)(x) & (__u32)0x00ff00ffUL) << 8) + | (((__u32)(x) & (__u32)0xff00ff00UL) >> 8); +} + +int +main (void) +{ + volatile __u32 in32 = 0x12345678; + volatile __u32 expected32 = 0x34127856; + + if (__rev16_32 (in32) != expected32) + abort (); + + if (__rev16_32_alt (in32) != expected32) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/scd42-1.c b/gcc/testsuite/gcc.target/arm/scd42-1.c index 2cd1eeb8f50..f2bd6297c97 100644 --- a/gcc/testsuite/gcc.target/arm/scd42-1.c +++ b/gcc/testsuite/gcc.target/arm/scd42-1.c @@ -13,4 +13,4 @@ unsigned load1(void) return 17; } -/* { dg-final { scan-assembler "mov\[ ].*17" } } */ +/* { dg-final { scan-assembler "movs\[ ].*17" } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/neon-vrndx_f32_1.c b/gcc/testsuite/gcc.target/arm/simd/neon-vrndx_f32_1.c new file mode 100644 index 00000000000..3d2f27fa666 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/neon-vrndx_f32_1.c @@ -0,0 +1,17 @@ +/* Test the `vrndx_f32' ARM Neon intrinsic. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O2" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +float32x2_t +test_vrndx_f32 (float32x2_t in) +{ + return vrndx_f32 (in); +} + +/* { dg-final { scan-assembler "vrintx\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/neon-vrndxq_f32_1.c b/gcc/testsuite/gcc.target/arm/simd/neon-vrndxq_f32_1.c new file mode 100644 index 00000000000..c89cb248284 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/neon-vrndxq_f32_1.c @@ -0,0 +1,17 @@ +/* Test the `vrndxq_f32' ARM Neon intrinsic. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O2" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +float32x4_t +test_vrndxq_f32 (float32x4_t in) +{ + return vrndxq_f32 (in); +} + +/* { dg-final { scan-assembler "vrintx\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/simd.exp b/gcc/testsuite/gcc.target/arm/simd/simd.exp new file mode 100644 index 00000000000..3afb537f27c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/simd.exp @@ -0,0 +1,35 @@ +# Copyright (C) 1997-2015 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't an ARM target. +if ![istarget arm*-*-*] then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# Initialize `dg'. +dg-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \ + "" "" + +# All done. +dg-finish diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQf32_1.c new file mode 100644 index 00000000000..c1da6d38a5d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextQf32_1.c @@ -0,0 +1,12 @@ +/* Test the `vextQf32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/extq_f32.x" + +/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 3 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQp16_1.c new file mode 100644 index 00000000000..adc086181b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextQp16_1.c @@ -0,0 +1,12 @@ +/* Test the `vextQp16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/extq_p16.x" + +/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 7 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQp64_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQp64_1.c new file mode 100644 index 00000000000..e8b688da2b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextQp64_1.c @@ -0,0 +1,33 @@ +/* Test the `vextQp64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +extern void abort (void); + +poly64x2_t +test_vextq_p64_1 (poly64x2_t a, poly64x2_t b) +{ + return vextq_p64(a, b, 1); +} + +int +main (int argc, char **argv) +{ + int i, off; + poly64x2_t in1 = {0, 1}; + poly64x2_t in2 = {2, 3}; + poly64x2_t actual = test_vextq_p64_1 (in1, in2); + for (i = 0; i < 2; i++) + if (actual[i] != i + 1) + abort (); + + return 0; +} + +/* { dg-final { scan-assembler-times "vext\.64\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQp8_1.c new file mode 100644 index 00000000000..5f2cc53e367 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextQp8_1.c @@ -0,0 +1,12 @@ +/* Test the `vextQp8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/extq_p8.x" + +/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 15 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQs16_1.c new file mode 100644 index 00000000000..c0d791dcef3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextQs16_1.c @@ -0,0 +1,12 @@ +/* Test the `vextQs16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/extq_s16.x" + +/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 7 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQs32_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQs32_1.c new file mode 100644 index 00000000000..ed5b21091cc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextQs32_1.c @@ -0,0 +1,12 @@ +/* Test the `vextQs32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/extq_s32.x" + +/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 3 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQs64_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQs64_1.c new file mode 100644 index 00000000000..dbbee47c58b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextQs64_1.c @@ -0,0 +1,12 @@ +/* Test the `vextQs64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/extq_s64.x" + +/* { dg-final { scan-assembler-times "vext\.64\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQs8_1.c new file mode 100644 index 00000000000..0ebdce38165 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextQs8_1.c @@ -0,0 +1,12 @@ +/* Test the `vextQs8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/extq_s8.x" + +/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 15 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQu16_1.c new file mode 100644 index 00000000000..136f2b8741f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextQu16_1.c @@ -0,0 +1,12 @@ +/* Test the `vextQu16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/extq_u16.x" + +/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 7 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQu32_1.c new file mode 100644 index 00000000000..66ce035c5a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextQu32_1.c @@ -0,0 +1,12 @@ +/* Test the `vextQu32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/extq_u32.x" + +/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 3 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQu64_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQu64_1.c new file mode 100644 index 00000000000..ebe4abd069f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextQu64_1.c @@ -0,0 +1,12 @@ +/* Test the `vextQu64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/extq_u64.x" + +/* { dg-final { scan-assembler-times "vext\.64\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQu8_1.c new file mode 100644 index 00000000000..432ac0a5674 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextQu8_1.c @@ -0,0 +1,12 @@ +/* Test the `vextQu8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/extq_u8.x" + +/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 15 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vextf32_1.c new file mode 100644 index 00000000000..99e0bad0ed0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextf32_1.c @@ -0,0 +1,12 @@ +/* Test the `vextf32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/ext_f32.x" + +/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vextp16_1.c new file mode 100644 index 00000000000..00695bf6419 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextp16_1.c @@ -0,0 +1,12 @@ +/* Test the `vextp16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/ext_p16.x" + +/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 3 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextp64_1.c b/gcc/testsuite/gcc.target/arm/simd/vextp64_1.c new file mode 100644 index 00000000000..8783e166ea7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextp64_1.c @@ -0,0 +1,26 @@ +/* Test the `vextp64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +extern void abort (void); + +int +main (int argc, char **argv) +{ + int i; + poly64x1_t in1 = {0}; + poly64x1_t in2 = {1}; + poly64x1_t actual = vext_p64 (in1, in2, 0); + if (actual != in1) + abort (); + + return 0; +} + +/* Don't scan assembler for vext - it can be optimized into a move from r0. +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vextp8_1.c new file mode 100644 index 00000000000..2ba72c1ac0c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextp8_1.c @@ -0,0 +1,12 @@ +/* Test the `vextp8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/ext_p8.x" + +/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 7 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vexts16_1.c b/gcc/testsuite/gcc.target/arm/simd/vexts16_1.c new file mode 100644 index 00000000000..4fa57d6b696 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vexts16_1.c @@ -0,0 +1,12 @@ +/* Test the `vexts16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/ext_s16.x" + +/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 3 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vexts32_1.c b/gcc/testsuite/gcc.target/arm/simd/vexts32_1.c new file mode 100644 index 00000000000..3cd59360e28 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vexts32_1.c @@ -0,0 +1,12 @@ +/* Test the `vexts32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/ext_s32.x" + +/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vexts64_1.c b/gcc/testsuite/gcc.target/arm/simd/vexts64_1.c new file mode 100644 index 00000000000..10053a5e398 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vexts64_1.c @@ -0,0 +1,27 @@ +/* Test the `vexts64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +extern void abort (void); + +int +main (int argc, char **argv) +{ + int64_t arr1[] = {0}; + int64x1_t in1 = vld1_s64 (arr1); + int64_t arr2[] = {1}; + int64x1_t in2 = vld1_s64 (arr2); + int64x1_t actual = vext_s64 (in1, in2, 0); + if (actual != in1) + abort (); + + return 0; +} + +/* Don't scan assembler for vext - it can be optimized into a move from r0. */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vexts8_1.c b/gcc/testsuite/gcc.target/arm/simd/vexts8_1.c new file mode 100644 index 00000000000..194e198b98e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vexts8_1.c @@ -0,0 +1,12 @@ +/* Test the `vexts8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/ext_s8.x" + +/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 7 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vextu16_1.c new file mode 100644 index 00000000000..f69c2bdc77f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextu16_1.c @@ -0,0 +1,12 @@ +/* Test the `vextu16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/ext_u16.x" + +/* { dg-final { scan-assembler-times "vext\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 3 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vextu32_1.c new file mode 100644 index 00000000000..b76e383cadb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextu32_1.c @@ -0,0 +1,12 @@ +/* Test the `vextu32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/ext_u32.x" + +/* { dg-final { scan-assembler-times "vext\.32\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextu64_1.c b/gcc/testsuite/gcc.target/arm/simd/vextu64_1.c new file mode 100644 index 00000000000..eeb0be2732c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextu64_1.c @@ -0,0 +1,27 @@ +/* Test the `vextu64' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +extern void abort (void); + +int +main (int argc, char **argv) +{ + uint64_t arr1[] = {0}; + uint64x1_t in1 = vld1_u64 (arr1); + uint64_t arr2[] = {1}; + uint64x1_t in2 = vld1_u64 (arr2); + uint64x1_t actual = vext_u64 (in1, in2, 0); + if (actual != in1) + abort (); + + return 0; +} + +/* Don't scan assembler for vext - it can be optimized into a move from r0. */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vextu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vextu8_1.c new file mode 100644 index 00000000000..a9d62b31dff --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vextu8_1.c @@ -0,0 +1,12 @@ +/* Test the `vextu8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/ext_u8.x" + +/* { dg-final { scan-assembler-times "vext\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 7 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c new file mode 100644 index 00000000000..fddb32fbb8b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev16p8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev16p8.x" + +/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c new file mode 100644 index 00000000000..b4634b8dbde --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev16q_p8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev16qp8.x" + +/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c new file mode 100644 index 00000000000..691799b6b94 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev16q_s8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev16qs8.x" + +/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c new file mode 100644 index 00000000000..f6ab4ac5cd1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev16q_u8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev16qu8.x" + +/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c new file mode 100644 index 00000000000..0a03721f29c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev16s8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev16s8.x" + +/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c new file mode 100644 index 00000000000..7e5f54808ac --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev16u8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev16u8.x" + +/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c new file mode 100644 index 00000000000..f3643fa96da --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32p16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32p16.x" + +/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c new file mode 100644 index 00000000000..d823e59ff1c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32p8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32p8.x" + +/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c new file mode 100644 index 00000000000..f8ba8a916ef --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32q_p16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32qp16.x" + +/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c new file mode 100644 index 00000000000..0ddf6081a82 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32q_p8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32qp8.x" + +/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c new file mode 100644 index 00000000000..30d0314c202 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32q_s16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32qs16.x" + +/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c new file mode 100644 index 00000000000..03ddd2be25c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32q_s8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32qs8.x" + +/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c new file mode 100644 index 00000000000..71765437b65 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32q_u16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32qu16.x" + +/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c new file mode 100644 index 00000000000..403292c7cd8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32q_u8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32qu8.x" + +/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c new file mode 100644 index 00000000000..e182ab988ce --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32s16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32s16.x" + +/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c new file mode 100644 index 00000000000..a48c4155176 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32s8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32s8.x" + +/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c new file mode 100644 index 00000000000..076f8ab885b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32u16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32u16.x" + +/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c new file mode 100644 index 00000000000..240d4596e8c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev32u8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev32u8.x" + +/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c new file mode 100644 index 00000000000..f5d3bcae564 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64f32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64f32.x" + +/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c new file mode 100644 index 00000000000..8c685c0f8ca --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64p16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64p16.x" + +/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c new file mode 100644 index 00000000000..67ac1e49117 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64p8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64p8.x" + +/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c new file mode 100644 index 00000000000..74130b7d821 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64q_f32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64qf32.x" + +/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c new file mode 100644 index 00000000000..71f3b4ba4b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64q_p16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64qp16.x" + +/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c new file mode 100644 index 00000000000..324a738c660 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64q_p8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64qp8.x" + +/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c new file mode 100644 index 00000000000..9a373ec4100 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64q_s16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64qs16.x" + +/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c new file mode 100644 index 00000000000..0f10c6cb078 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64q_s32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64qs32.x" + +/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c new file mode 100644 index 00000000000..cf380143be6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64q_s8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64qs8.x" + +/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c new file mode 100644 index 00000000000..010d6dbb805 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64q_u16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64qu16.x" + +/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c new file mode 100644 index 00000000000..908769cc682 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64q_u32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64qu32.x" + +/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c new file mode 100644 index 00000000000..2fa07d12980 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64q_u8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64qu8.x" + +/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c new file mode 100644 index 00000000000..f14319c3214 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64s16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64s16.x" + +/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c new file mode 100644 index 00000000000..ead57225f3e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64s32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64s32.x" + +/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c new file mode 100644 index 00000000000..29d684dcd1c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64s8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64s8.x" + +/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c new file mode 100644 index 00000000000..feddacce2b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64u16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64u16.x" + +/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c new file mode 100644 index 00000000000..92a81f44041 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64u32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64u32.x" + +/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c new file mode 100644 index 00000000000..f904af5ca77 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c @@ -0,0 +1,12 @@ +/* Test the `vrev64u8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vrev64u8.x" + +/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnf32_1.c new file mode 100644 index 00000000000..0f9b6c9b8bd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnf32_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnf32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnf32.x" + +/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnp16_1.c new file mode 100644 index 00000000000..0ff43198109 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnp16_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnp16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnp16.x" + +/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnp8_1.c new file mode 100644 index 00000000000..2b047e4d759 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnp8_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnp8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnp8.x" + +/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqf32_1.c new file mode 100644 index 00000000000..dd4e8836f3c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqf32_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnQf32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnqf32.x" + +/* { dg-final { scan-assembler-times "vtrn\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqp16_1.c new file mode 100644 index 00000000000..374eee396de --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqp16_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnQp16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnqp16.x" + +/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqp8_1.c new file mode 100644 index 00000000000..b252fd5f3b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqp8_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnQp8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnqp8.x" + +/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqs16_1.c new file mode 100644 index 00000000000..5f06d2a3b12 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqs16_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnQs16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnqs16.x" + +/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqs32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqs32_1.c new file mode 100644 index 00000000000..221175c46c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqs32_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnQs32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnqs32.x" + +/* { dg-final { scan-assembler-times "vtrn\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqs8_1.c new file mode 100644 index 00000000000..9352b37a783 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqs8_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnQs8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnqs8.x" + +/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqu16_1.c new file mode 100644 index 00000000000..7f40109b2a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqu16_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnQu16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnqu16.x" + +/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqu32_1.c new file mode 100644 index 00000000000..1c61fc34f7c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqu32_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnQu32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnqu32.x" + +/* { dg-final { scan-assembler-times "vtrn\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqu8_1.c new file mode 100644 index 00000000000..82f911d5a78 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqu8_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnQu8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnqu8.x" + +/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrns16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrns16_1.c new file mode 100644 index 00000000000..af2c68f381f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrns16_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrns16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrns16.x" + +/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrns32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrns32_1.c new file mode 100644 index 00000000000..35a98ea9551 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrns32_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrns32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrns32.x" + +/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrns8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrns8_1.c new file mode 100644 index 00000000000..395015d1330 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrns8_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrns8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrns8.x" + +/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnu16_1.c new file mode 100644 index 00000000000..df0d963a5fa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnu16_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnu16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnu16.x" + +/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnu32_1.c new file mode 100644 index 00000000000..764ed623f07 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnu32_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnu32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnu32.x" + +/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnu8_1.c new file mode 100644 index 00000000000..f5b4d68966e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnu8_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnu8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnu8.x" + +/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpf32_1.c new file mode 100644 index 00000000000..723c86a16be --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpf32_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpf32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpf32.x" + +/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpp16_1.c new file mode 100644 index 00000000000..c7ad757b55e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpp16_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpp16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpp16.x" + +/* { dg-final { scan-assembler-times "vuzp\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpp8_1.c new file mode 100644 index 00000000000..670b5506779 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpp8_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpp8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpp8.x" + +/* { dg-final { scan-assembler-times "vuzp\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqf32_1.c new file mode 100644 index 00000000000..53147f1a43e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqf32_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpQf32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpqf32.x" + +/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqp16_1.c new file mode 100644 index 00000000000..feef15af27e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqp16_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpQp16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpqp16.x" + +/* { dg-final { scan-assembler-times "vuzp\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqp8_1.c new file mode 100644 index 00000000000..db98f353354 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqp8_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpQp8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpqp8.x" + +/* { dg-final { scan-assembler-times "vuzp\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqs16_1.c new file mode 100644 index 00000000000..808d562732b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqs16_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpQs16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpqs16.x" + +/* { dg-final { scan-assembler-times "vuzp\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqs32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqs32_1.c new file mode 100644 index 00000000000..7adf5f9b91f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqs32_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpQs32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpqs32.x" + +/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqs8_1.c new file mode 100644 index 00000000000..9d0256a632a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqs8_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpQs8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpqs8.x" + +/* { dg-final { scan-assembler-times "vuzp\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqu16_1.c new file mode 100644 index 00000000000..23106edf529 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqu16_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpQu16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpqu16.x" + +/* { dg-final { scan-assembler-times "vuzp\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqu32_1.c new file mode 100644 index 00000000000..0002fdfcbd9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqu32_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpQu32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpqu32.x" + +/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqu8_1.c new file mode 100644 index 00000000000..f8d19dc5582 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqu8_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpQu8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpqu8.x" + +/* { dg-final { scan-assembler-times "vuzp\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzps16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzps16_1.c new file mode 100644 index 00000000000..6e3f2eb118b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzps16_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzps16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzps16.x" + +/* { dg-final { scan-assembler-times "vuzp\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzps32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzps32_1.c new file mode 100644 index 00000000000..372c3938754 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzps32_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzps32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzps32.x" + +/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzps8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzps8_1.c new file mode 100644 index 00000000000..3338477778e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzps8_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzps8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzps8.x" + +/* { dg-final { scan-assembler-times "vuzp\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpu16_1.c new file mode 100644 index 00000000000..378b5a9df91 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpu16_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpu16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpu16.x" + +/* { dg-final { scan-assembler-times "vuzp\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpu32_1.c new file mode 100644 index 00000000000..ebb0d6b5fa6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpu32_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpu32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpu32.x" + +/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpu8_1.c new file mode 100644 index 00000000000..82719a503c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vuzpu8_1.c @@ -0,0 +1,12 @@ +/* Test the `vuzpu8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vuzpu8.x" + +/* { dg-final { scan-assembler-times "vuzp\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipf32_1.c new file mode 100644 index 00000000000..efaa96ea955 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipf32_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipf32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipf32.x" + +/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipp16_1.c new file mode 100644 index 00000000000..4154333a7f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipp16_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipp16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipp16.x" + +/* { dg-final { scan-assembler-times "vzip\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipp8_1.c new file mode 100644 index 00000000000..9fe2384c9f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipp8_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipp8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipp8.x" + +/* { dg-final { scan-assembler-times "vzip\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqf32_1.c new file mode 100644 index 00000000000..8c547a79f5b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqf32_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipQf32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipqf32.x" + +/* { dg-final { scan-assembler-times "vzip\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqp16_1.c new file mode 100644 index 00000000000..e2af10b2af1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqp16_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipQp16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipqp16.x" + +/* { dg-final { scan-assembler-times "vzip\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqp8_1.c new file mode 100644 index 00000000000..11a13298563 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqp8_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipQp8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipqp8.x" + +/* { dg-final { scan-assembler-times "vzip\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqs16_1.c new file mode 100644 index 00000000000..0576c0033e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqs16_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipQs16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipqs16.x" + +/* { dg-final { scan-assembler-times "vzip\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqs32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqs32_1.c new file mode 100644 index 00000000000..6cf24396d20 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqs32_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipQs32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipqs32.x" + +/* { dg-final { scan-assembler-times "vzip\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqs8_1.c new file mode 100644 index 00000000000..0244374e001 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqs8_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipQs8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipqs8.x" + +/* { dg-final { scan-assembler-times "vzip\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqu16_1.c new file mode 100644 index 00000000000..3c406f514d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqu16_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipQu16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipqu16.x" + +/* { dg-final { scan-assembler-times "vzip\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqu32_1.c new file mode 100644 index 00000000000..ba1393c6c92 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqu32_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipQu32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipqu32.x" + +/* { dg-final { scan-assembler-times "vzip\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqu8_1.c new file mode 100644 index 00000000000..023ecac3a52 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqu8_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipQu8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipqu8.x" + +/* { dg-final { scan-assembler-times "vzip\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzips16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzips16_1.c new file mode 100644 index 00000000000..b6c3c2fe897 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzips16_1.c @@ -0,0 +1,12 @@ +/* Test the `vzips16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzips16.x" + +/* { dg-final { scan-assembler-times "vzip\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzips32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzips32_1.c new file mode 100644 index 00000000000..1a6f1709342 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzips32_1.c @@ -0,0 +1,12 @@ +/* Test the `vzips32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzips32.x" + +/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzips8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzips8_1.c new file mode 100644 index 00000000000..8569357817b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzips8_1.c @@ -0,0 +1,12 @@ +/* Test the `vzips8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzips8.x" + +/* { dg-final { scan-assembler-times "vzip\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipu16_1.c new file mode 100644 index 00000000000..23bfcc4d962 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipu16_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipu16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipu16.x" + +/* { dg-final { scan-assembler-times "vzip\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipu32_1.c new file mode 100644 index 00000000000..6a753f25a9c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipu32_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipu32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipu32.x" + +/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipu8_1.c new file mode 100644 index 00000000000..972af74237f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipu8_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipu8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipu8.x" + +/* { dg-final { scan-assembler-times "vzip\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/small-multiply-m0-1.c b/gcc/testsuite/gcc.target/arm/small-multiply-m0-1.c new file mode 100644 index 00000000000..49132e3e83d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/small-multiply-m0-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-skip-if "Test is specific to cortex-m0.small-multiply" { arm*-*-* } { "*" } { "-mcpu=cortex-m0.small-multiply" } } */ +/* { dg-options "-mcpu=cortex-m0.small-multiply -mthumb -O2" } */ + +int +test (int a) +{ + return a * 0x123456; +} + +/* { dg-final { scan-assembler-not "\[\\t \]+mul" } } */ diff --git a/gcc/testsuite/gcc.target/arm/small-multiply-m0-2.c b/gcc/testsuite/gcc.target/arm/small-multiply-m0-2.c new file mode 100644 index 00000000000..7f1bf7bd604 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/small-multiply-m0-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-skip-if "Test is specific to cortex-m0.small-multiply" { arm*-*-* } { "*" } { "-mcpu=cortex-m0.small-multiply" } } */ +/* { dg-options "-mcpu=cortex-m0.small-multiply -mthumb -Os" } */ + +int +test (int a) +{ + return a * 0x123456; +} + +/* { dg-final { scan-assembler "\[\\t \]+mul" } } */ diff --git a/gcc/testsuite/gcc.target/arm/small-multiply-m0-3.c b/gcc/testsuite/gcc.target/arm/small-multiply-m0-3.c new file mode 100644 index 00000000000..aca39d746dc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/small-multiply-m0-3.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-skip-if "Test is specific to cortex-m0.small-multiply" { arm*-*-* } { "*" } { "-mcpu=cortex-m0.small-multiply" } } */ +/* { dg-options "-mcpu=cortex-m0.small-multiply -mthumb -Os" } */ + +int +test (int a) +{ + return a * 0x13; +} + +/* { dg-final { scan-assembler-not "\[\\t \]+mul" } } */ diff --git a/gcc/testsuite/gcc.target/arm/small-multiply-m0plus-1.c b/gcc/testsuite/gcc.target/arm/small-multiply-m0plus-1.c new file mode 100644 index 00000000000..12e8839753c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/small-multiply-m0plus-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-skip-if "Test is specific to cortex-m0plus.small-multiply" { arm*-*-* } { "*" } { "-mcpu=cortex-m0plus.small-multiply" } } */ +/* { dg-options "-mcpu=cortex-m0plus.small-multiply -mthumb -O2" } */ + +int +test (int a) +{ + return a * 0x123456; +} + +/* { dg-final { scan-assembler-not "\[\\t \]+mul" } } */ diff --git a/gcc/testsuite/gcc.target/arm/small-multiply-m0plus-2.c b/gcc/testsuite/gcc.target/arm/small-multiply-m0plus-2.c new file mode 100644 index 00000000000..3e3c9b26e3c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/small-multiply-m0plus-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-skip-if "Test is specific to cortex-m0plus.small-multiply" { arm*-*-* } { "*" } { "-mcpu=cortex-m0plus.small-multiply" } } */ +/* { dg-options "-mcpu=cortex-m0plus.small-multiply -mthumb -Os" } */ + +int +test (int a) +{ + return a * 0x123456; +} + +/* { dg-final { scan-assembler "\[\\t \]+mul" } } */ diff --git a/gcc/testsuite/gcc.target/arm/small-multiply-m0plus-3.c b/gcc/testsuite/gcc.target/arm/small-multiply-m0plus-3.c new file mode 100644 index 00000000000..75e34321ec2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/small-multiply-m0plus-3.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-skip-if "Test is specific to cortex-m0plus.small-multiply" { arm*-*-* } { "*" } { "-mcpu=cortex-m0plus.small-multiply" } } */ +/* { dg-options "-mcpu=cortex-m0plus.small-multiply -mthumb -Os" } */ + +int +test (int a) +{ + return a * 0x13; +} + +/* { dg-final { scan-assembler-not "\[\\t \]+mul" } } */ diff --git a/gcc/testsuite/gcc.target/arm/small-multiply-m1-1.c b/gcc/testsuite/gcc.target/arm/small-multiply-m1-1.c new file mode 100644 index 00000000000..fbe90cc4a54 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/small-multiply-m1-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-skip-if "Test is specific to cortex-m1.small-multiply" { arm*-*-* } { "*" } { "-mcpu=cortex-m1.small-multiply" } } */ +/* { dg-options "-mcpu=cortex-m1.small-multiply -mthumb -O2" } */ + +int +test (int a) +{ + return a * 0x123456; +} + +/* { dg-final { scan-assembler-not "\[\\t \]+mul" } } */ diff --git a/gcc/testsuite/gcc.target/arm/small-multiply-m1-2.c b/gcc/testsuite/gcc.target/arm/small-multiply-m1-2.c new file mode 100644 index 00000000000..6fca40564ee --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/small-multiply-m1-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-skip-if "Test is specific to cortex-m1.small-multiply" { arm*-*-* } { "*" } { "-mcpu=cortex-m1.small-multiply" } } */ +/* { dg-options "-mcpu=cortex-m1.small-multiply -mthumb -Os" } */ + +int +test (int a) +{ + return a * 0x123456; +} + +/* { dg-final { scan-assembler "\[\\t \]+mul" } } */ diff --git a/gcc/testsuite/gcc.target/arm/small-multiply-m1-3.c b/gcc/testsuite/gcc.target/arm/small-multiply-m1-3.c new file mode 100644 index 00000000000..bc732c32346 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/small-multiply-m1-3.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-skip-if "Test is specific to cortex-m1.small-multiply" { arm*-*-* } { "*" } { "-mcpu=cortex-m1.small-multiply" } } */ +/* { dg-options "-mcpu=cortex-m1.small-multiply -mthumb -Os" } */ + +int +test (int a) +{ + return a * 0x13; +} + +/* { dg-final { scan-assembler-not "\[\\t \]+mul" } } */ diff --git a/gcc/testsuite/gcc.target/arm/split-live-ranges-for-shrink-wrap.c b/gcc/testsuite/gcc.target/arm/split-live-ranges-for-shrink-wrap.c new file mode 100644 index 00000000000..e36000b19a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/split-live-ranges-for-shrink-wrap.c @@ -0,0 +1,14 @@ +/* { dg-do assemble } */ +/* { dg-options "-mthumb -Os -fdump-rtl-ira " } */ +/* { dg-require-effective-target arm_thumb1_ok } */ + +int foo (char *, char *, int); +int test (int d, char * out, char *in, int len) +{ + if (out != in) + foo (out, in, len); + return 0; +} +/* { dg-final { object-size text <= 20 } } */ +/* { dg-final { scan-rtl-dump-not "Split live-range of register" "ira" } } */ +/* { dg-final { cleanup-rtl-dump "ira" } } */ diff --git a/gcc/testsuite/gcc.target/arm/stack-red-zone.c b/gcc/testsuite/gcc.target/arm/stack-red-zone.c index b9f0f99371e..8db2e2c092a 100644 --- a/gcc/testsuite/gcc.target/arm/stack-red-zone.c +++ b/gcc/testsuite/gcc.target/arm/stack-red-zone.c @@ -1,4 +1,5 @@ /* No stack red zone. PR38644. */ +/* { dg-skip-if "incompatible options" { ! { arm_thumb1_ok || arm_thumb2_ok } } { "*" } { "" } } */ /* { dg-options "-mthumb -O2" } */ /* { dg-final { scan-assembler "ldrb\[^\n\]*\\n\[\t \]*add\[\t \]*sp" } } */ diff --git a/gcc/testsuite/gcc.target/arm/tail-long-call.c b/gcc/testsuite/gcc.target/arm/tail-long-call.c new file mode 100644 index 00000000000..9b274686849 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/tail-long-call.c @@ -0,0 +1,12 @@ +/* { dg-skip-if "need at least armv5te" { *-*-* } { "-march=armv[234]*" "-mthumb" } { "" } } */ +/* { dg-options "-O2 -march=armv5te -marm" } */ +/* { dg-final { scan-assembler "bx" } } */ +/* { dg-final { scan-assembler-not "blx" } } */ + +int lcal (int) __attribute__ ((long_call)); + +int +dec (int a) +{ + return lcal (a); +} diff --git a/gcc/testsuite/gcc.target/arm/thumb-find-work-register.c b/gcc/testsuite/gcc.target/arm/thumb-find-work-register.c index f2c0225a4d2..e67a627ea31 100644 --- a/gcc/testsuite/gcc.target/arm/thumb-find-work-register.c +++ b/gcc/testsuite/gcc.target/arm/thumb-find-work-register.c @@ -1,5 +1,6 @@ /* Wrong method to get number of arg reg will cause argument corruption. */ /* { dg-do run } */ +/* { dg-skip-if "incompatible options" { ! { arm_thumb1_ok || arm_thumb2_ok } } { "*" } { "" } } */ /* { dg-require-effective-target arm_eabi } */ /* { dg-options "-mthumb -O1" } */ diff --git a/gcc/testsuite/gcc.target/arm/thumb1-Os-mult.c b/gcc/testsuite/gcc.target/arm/thumb1-Os-mult.c index 31b8bd69227..08d735c6ca0 100644 --- a/gcc/testsuite/gcc.target/arm/thumb1-Os-mult.c +++ b/gcc/testsuite/gcc.target/arm/thumb1-Os-mult.c @@ -9,4 +9,4 @@ mymul3 (int x) return x * 0x555; } -/* { dg-final { scan-assembler "mul\[\\t \]*r.,\[\\t \]*r." } } */ +/* { dg-final { scan-assembler "muls\[\\t \]*r.,\[\\t \]*r." } } */ diff --git a/gcc/testsuite/gcc.target/arm/thumb1-load-64bit-constant-1.c b/gcc/testsuite/gcc.target/arm/thumb1-load-64bit-constant-1.c new file mode 100644 index 00000000000..9537aafa1ba --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/thumb1-load-64bit-constant-1.c @@ -0,0 +1,14 @@ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-do compile } */ +/* { dg-options "-Os" } */ +/* { dg-skip-if "" { ! { arm_thumb1 } } } */ + +extern long long madd (long long a, long long b); + +long long +foo () +{ + return madd (0x0000000100000001LL, 0x0000011100000001LL); +} + +/* { dg-final { scan-assembler-not "ldr" } } */ diff --git a/gcc/testsuite/gcc.target/arm/thumb1-load-64bit-constant-2.c b/gcc/testsuite/gcc.target/arm/thumb1-load-64bit-constant-2.c new file mode 100644 index 00000000000..836682b475d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/thumb1-load-64bit-constant-2.c @@ -0,0 +1,14 @@ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-skip-if "" { ! { arm_thumb1 } } } */ + +extern long long madd (long long a); + +long long +foo () +{ + return madd (0x0000000100000001LL); +} + +/* { dg-final { scan-assembler-not "ldr" } } */ diff --git a/gcc/testsuite/gcc.target/arm/thumb1-load-64bit-constant-3.c b/gcc/testsuite/gcc.target/arm/thumb1-load-64bit-constant-3.c new file mode 100644 index 00000000000..b53ed8b6edd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/thumb1-load-64bit-constant-3.c @@ -0,0 +1,14 @@ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-do compile } */ +/* { dg-options "-Os" } */ +/* { dg-skip-if "" { ! { arm_thumb1 } } } */ + +long long +foo (int len) +{ + return (long long) (((long long) 1 << len) - 1); +} + +/* { dg-final { scan-assembler-not "ldr" } } */ +/* { dg-final { scan-assembler-times "rsbs" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/arm/thumb1-ual-1.c b/gcc/testsuite/gcc.target/arm/thumb1-ual-1.c new file mode 100644 index 00000000000..a2e439c6c4b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/thumb1-ual-1.c @@ -0,0 +1,87 @@ +/* Test Thumb1 insn pattern addsi3_cbranch_scratch. */ +/* { dg-options "-O2" } */ +/* { dg-skip-if "" { ! { arm_thumb1 } } } */ + +struct real_value { + + unsigned int cl : 2; + unsigned int decimal : 1; + unsigned int sign : 1; + unsigned int signalling : 1; + unsigned int canonical : 1; + unsigned int uexp : (32 - 6); + unsigned long sig[((128 + (8 * 4)) / (8 * 4))]; +}; + +enum real_value_class { + rvc_zero, + rvc_normal, + rvc_inf, + rvc_nan +}; + +extern void exit(int); +extern int foo(long long *, int, int); + +int +real_to_integer (const struct real_value *r, int *fail, int precision) +{ + long long val[2 * (((64*(8)) + 64) / 64)]; + int exp; + int words, w; + int result; + + switch (r->cl) + { + case rvc_zero: + underflow: + return 100; + + case rvc_inf: + case rvc_nan: + overflow: + *fail = 1; + + if (r->sign) + return 200; + else + return 300; + + case rvc_normal: + if (r->decimal) + return 400; + + exp = ((int)((r)->uexp ^ (unsigned int)(1 << ((32 - 6) - 1))) - (1 << ((32 - 6) - 1))); + if (exp <= 0) + goto underflow; + + + if (exp > precision) + goto overflow; + words = (precision + 64 - 1) / 64; + w = words * 64; + for (int i = 0; i < words; i++) + { + int j = ((128 + (8 * 4)) / (8 * 4)) - (words * 2) + (i * 2); + if (j < 0) + val[i] = 0; + else + val[i] = r->sig[j]; + j += 1; + if (j >= 0) + val[i] |= (unsigned long long) r->sig[j] << (8 * 4); + } + + + result = foo(val, words, w); + + if (r->sign) + return -result; + else + return result; + + default: + exit(2); + } +} + diff --git a/gcc/testsuite/gcc.target/arm/vect-copysignf.c b/gcc/testsuite/gcc.target/arm/vect-copysignf.c new file mode 100644 index 00000000000..b35dd1f1853 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/vect-copysignf.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details" } */ +/* { dg-add-options "arm_neon" } */ + +extern void abort (); + +#define N 16 +float a[N] = {-0.1f, -3.2f, -6.3f, -9.4f, + -12.5f, -15.6f, -18.7f, -21.8f, + 24.9f, 27.1f, 30.2f, 33.3f, + 36.4f, 39.5f, 42.6f, 45.7f}; +float b[N] = {-1.2f, 3.4f, -5.6f, 7.8f, + -9.0f, 1.0f, -2.0f, 3.0f, + -4.0f, -5.0f, 6.0f, 7.0f, + -8.0f, -9.0f, 10.0f, 11.0f}; +float r[N]; + +int +main (void) +{ + int i; + + for (i = 0; i < N; i++) + r[i] = __builtin_copysignf (a[i], b[i]); + + /* check results: */ + for (i = 0; i < N; i++) + if (r[i] != __builtin_copysignf (a[i], b[i])) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.target/arm/vect-lceilf_1.c b/gcc/testsuite/gcc.target/arm/vect-lceilf_1.c new file mode 100644 index 00000000000..5e98b74ee4c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/vect-lceilf_1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -fdump-tree-vect-all" } */ +/* { dg-add-options arm_v8_neon } */ + +#define N 32 + +float __attribute__((aligned(16))) input[N]; +int __attribute__((aligned(16))) output[N]; + +void +foo () +{ + int i = 0; + /* Vectorizable. */ + for (i = 0; i < N; i++) + output[i] = __builtin_lceilf (input[i]); +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.target/arm/vect-lfloorf_1.c b/gcc/testsuite/gcc.target/arm/vect-lfloorf_1.c new file mode 100644 index 00000000000..655f43720ce --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/vect-lfloorf_1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -fdump-tree-vect-all" } */ +/* { dg-add-options arm_v8_neon } */ + +#define N 32 + +float __attribute__((aligned(16))) input[N]; +int __attribute__((aligned(16))) output[N]; + +void +foo () +{ + int i = 0; + /* Vectorizable. */ + for (i = 0; i < N; i++) + output[i] = __builtin_lfloorf (input[i]); +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.target/arm/vect-lroundf_1.c b/gcc/testsuite/gcc.target/arm/vect-lroundf_1.c new file mode 100644 index 00000000000..92a722ed099 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/vect-lroundf_1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-O2 -ffast-math -ftree-vectorize -fdump-tree-vect-all" } */ +/* { dg-add-options arm_v8_neon } */ + +#define N 32 + +float __attribute__((aligned(16))) input[N]; +int __attribute__((aligned(16))) output[N]; + +void +foo () +{ + int i = 0; + /* Vectorizable. */ + for (i = 0; i < N; i++) + output[i] = __builtin_lroundf (input[i]); +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.target/arm/vect-noalign.c b/gcc/testsuite/gcc.target/arm/vect-noalign.c index a934233a33d..d507175cc6c 100644 --- a/gcc/testsuite/gcc.target/arm/vect-noalign.c +++ b/gcc/testsuite/gcc.target/arm/vect-noalign.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target arm_neon_hw } */ -/* { dg-options "-mfpu=neon -ffast-math -ftree-vectorize -fno-common -O2 -mno-unaligned-access" } */ +/* { dg-options "-O2 -fno-common -ftree-vectorize -mno-unaligned-access" } */ +/* { dg-add-options arm_neon } */ /* Test for-mno-unaligned-access and -ftree-vectorize and results bus error. */ diff --git a/gcc/testsuite/gcc.target/arm/vect-rounding-btruncf.c b/gcc/testsuite/gcc.target/arm/vect-rounding-btruncf.c index ff033d437e6..29b16cc26ce 100644 --- a/gcc/testsuite/gcc.target/arm/vect-rounding-btruncf.c +++ b/gcc/testsuite/gcc.target/arm/vect-rounding-btruncf.c @@ -5,8 +5,11 @@ #define N 32 +float __attribute__((aligned(16))) input[N]; +float __attribute__((aligned(16))) output[N]; + void -foo (float *output, float *input) +foo () { int i = 0; /* Vectorizable. */ diff --git a/gcc/testsuite/gcc.target/arm/vect-rounding-ceilf.c b/gcc/testsuite/gcc.target/arm/vect-rounding-ceilf.c index b54f358f71b..36d6a42f1db 100644 --- a/gcc/testsuite/gcc.target/arm/vect-rounding-ceilf.c +++ b/gcc/testsuite/gcc.target/arm/vect-rounding-ceilf.c @@ -5,8 +5,11 @@ #define N 32 +float __attribute__((aligned(16))) input[N]; +float __attribute__((aligned(16))) output[N]; + void -foo (float *output, float *input) +foo () { int i = 0; /* Vectorizable. */ diff --git a/gcc/testsuite/gcc.target/arm/vect-rounding-floorf.c b/gcc/testsuite/gcc.target/arm/vect-rounding-floorf.c index 02e188d9654..82427007b05 100644 --- a/gcc/testsuite/gcc.target/arm/vect-rounding-floorf.c +++ b/gcc/testsuite/gcc.target/arm/vect-rounding-floorf.c @@ -5,8 +5,11 @@ #define N 32 +float __attribute__((aligned(16))) input[N]; +float __attribute__((aligned(16))) output[N]; + void -foo (float *output, float *input) +foo () { int i = 0; /* Vectorizable. */ diff --git a/gcc/testsuite/gcc.target/arm/vect-rounding-roundf.c b/gcc/testsuite/gcc.target/arm/vect-rounding-roundf.c index 85e205806a4..d550174e3e6 100644 --- a/gcc/testsuite/gcc.target/arm/vect-rounding-roundf.c +++ b/gcc/testsuite/gcc.target/arm/vect-rounding-roundf.c @@ -5,8 +5,11 @@ #define N 32 +float __attribute__((aligned(16))) input[N]; +float __attribute__((aligned(16))) output[N]; + void -foo (float *output, float *input) +foo () { int i = 0; /* Vectorizable. */ diff --git a/gcc/testsuite/gcc.target/arm/vfp-1.c b/gcc/testsuite/gcc.target/arm/vfp-1.c index d6d9c46425b..b6bb7be9995 100644 --- a/gcc/testsuite/gcc.target/arm/vfp-1.c +++ b/gcc/testsuite/gcc.target/arm/vfp-1.c @@ -11,40 +11,40 @@ volatile float f1, f2, f3; void test_sf() { /* abssf2_vfp */ - /* { dg-final { scan-assembler "fabss" } } */ + /* { dg-final { scan-assembler "vabs.f32" } } */ f1 = fabsf (f1); /* negsf2_vfp */ - /* { dg-final { scan-assembler "fnegs" } } */ + /* { dg-final { scan-assembler "vneg.f32" } } */ f1 = -f1; /* addsf3_vfp */ - /* { dg-final { scan-assembler "fadds" } } */ + /* { dg-final { scan-assembler "vadd.f32" } } */ f1 = f2 + f3; /* subsf3_vfp */ - /* { dg-final { scan-assembler "fsubs" } } */ + /* { dg-final { scan-assembler "vsub.f32" } } */ f1 = f2 - f3; /* divsf3_vfp */ - /* { dg-final { scan-assembler "fdivs" } } */ + /* { dg-final { scan-assembler "vdiv.f32" } } */ f1 = f2 / f3; /* mulsf3_vfp */ - /* { dg-final { scan-assembler "fmuls" } } */ + /* { dg-final { scan-assembler "vmul.f32" } } */ f1 = f2 * f3; /* mulsf3negsf_vfp */ - /* { dg-final { scan-assembler "fnmuls" } } */ + /* { dg-final { scan-assembler "vnmul.f32" } } */ f1 = -f2 * f3; /* mulsf3addsf_vfp */ - /* { dg-final { scan-assembler "fmacs" } } */ + /* { dg-final { scan-assembler "vmla.f32" } } */ f1 = f2 * f3 + f1; /* mulsf3subsf_vfp */ - /* { dg-final { scan-assembler "fmscs" } } */ + /* { dg-final { scan-assembler "vnmls.f32" } } */ f1 = f2 * f3 - f1; /* mulsf3negsfaddsf_vfp */ - /* { dg-final { scan-assembler "fnmacs" } } */ + /* { dg-final { scan-assembler "vmls.f32" } } */ f1 = f2 - f3 * f1; /* mulsf3negsfsubsf_vfp */ - /* { dg-final { scan-assembler "fnmscs" } } */ + /* { dg-final { scan-assembler "vnmla.f32" } } */ f1 = -f2 * f3 - f1; /* sqrtsf2_vfp */ - /* { dg-final { scan-assembler "fsqrts" } } */ + /* { dg-final { scan-assembler "vsqrt.f32" } } */ f1 = sqrtf (f1); } @@ -52,40 +52,40 @@ volatile double d1, d2, d3; void test_df() { /* absdf2_vfp */ - /* { dg-final { scan-assembler "fabsd" } } */ + /* { dg-final { scan-assembler "vabs.f64" } } */ d1 = fabs (d1); /* negdf2_vfp */ - /* { dg-final { scan-assembler "fnegd" } } */ + /* { dg-final { scan-assembler "vneg.f64" } } */ d1 = -d1; /* adddf3_vfp */ - /* { dg-final { scan-assembler "faddd" } } */ + /* { dg-final { scan-assembler "vadd.f64" } } */ d1 = d2 + d3; /* subdf3_vfp */ - /* { dg-final { scan-assembler "fsubd" } } */ + /* { dg-final { scan-assembler "vsub.f64" } } */ d1 = d2 - d3; /* divdf3_vfp */ - /* { dg-final { scan-assembler "fdivd" } } */ + /* { dg-final { scan-assembler "vdiv.f64" } } */ d1 = d2 / d3; /* muldf3_vfp */ - /* { dg-final { scan-assembler "fmuld" } } */ + /* { dg-final { scan-assembler "vmul.f64" } } */ d1 = d2 * d3; /* muldf3negdf_vfp */ - /* { dg-final { scan-assembler "fnmuld" } } */ + /* { dg-final { scan-assembler "vnmul.f64" } } */ d1 = -d2 * d3; /* muldf3adddf_vfp */ - /* { dg-final { scan-assembler "fmacd" } } */ + /* { dg-final { scan-assembler "vmla.f64" } } */ d1 = d2 * d3 + d1; /* muldf3subdf_vfp */ - /* { dg-final { scan-assembler "fmscd" } } */ + /* { dg-final { scan-assembler "vnmls.f64" } } */ d1 = d2 * d3 - d1; /* muldf3negdfadddf_vfp */ - /* { dg-final { scan-assembler "fnmacd" } } */ + /* { dg-final { scan-assembler "vmls.f64" } } */ d1 = d2 - d3 * d1; /* muldf3negdfsubdf_vfp */ - /* { dg-final { scan-assembler "fnmscd" } } */ + /* { dg-final { scan-assembler "vnmla.f64" } } */ d1 = -d2 * d3 - d1; /* sqrtdf2_vfp */ - /* { dg-final { scan-assembler "fsqrtd" } } */ + /* { dg-final { scan-assembler "vsqrt.f64" } } */ d1 = sqrt (d1); } @@ -94,46 +94,46 @@ volatile unsigned int u1; void test_convert () { /* extendsfdf2_vfp */ - /* { dg-final { scan-assembler "fcvtds" } } */ + /* { dg-final { scan-assembler "vcvt.f64.f32" } } */ d1 = f1; /* truncdfsf2_vfp */ - /* { dg-final { scan-assembler "fcvtsd" } } */ + /* { dg-final { scan-assembler "vcvt.f32.f64" } } */ f1 = d1; /* truncsisf2_vfp */ - /* { dg-final { scan-assembler "ftosizs" } } */ + /* { dg-final { scan-assembler "vcvt.s32.f32" } } */ i1 = f1; /* truncsidf2_vfp */ - /* { dg-final { scan-assembler "ftosizd" } } */ + /* { dg-final { scan-assembler "vcvt.s32.f64" } } */ i1 = d1; /* fixuns_truncsfsi2 */ - /* { dg-final { scan-assembler "ftouizs" } } */ + /* { dg-final { scan-assembler "vcvt.u32.f32" } } */ u1 = f1; /* fixuns_truncdfsi2 */ - /* { dg-final { scan-assembler "ftouizd" } } */ + /* { dg-final { scan-assembler "vcvt.u32.f64" } } */ u1 = d1; /* floatsisf2_vfp */ - /* { dg-final { scan-assembler "fsitos" } } */ + /* { dg-final { scan-assembler "vcvt.f32.s32" } } */ f1 = i1; /* floatsidf2_vfp */ - /* { dg-final { scan-assembler "fsitod" } } */ + /* { dg-final { scan-assembler "vcvt.f64.s32" } } */ d1 = i1; /* floatunssisf2 */ - /* { dg-final { scan-assembler "fuitos" } } */ + /* { dg-final { scan-assembler "vcvt.f32.u32" } } */ f1 = u1; /* floatunssidf2 */ - /* { dg-final { scan-assembler "fuitod" } } */ + /* { dg-final { scan-assembler "vcvt.f64.u32" } } */ d1 = u1; } void test_ldst (float f[], double d[]) { - /* { dg-final { scan-assembler "flds.+ \\\[r0, #1020\\\]" } } */ - /* { dg-final { scan-assembler "flds.+ \\\[r\[0-9\], #-1020\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */ + /* { dg-final { scan-assembler "vldr.32.+ \\\[r0, #-?\[0-9\]+\\\]" } } */ + /* { dg-final { scan-assembler "vldr.32.+ \\\[r\[0-9\], #-1020\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */ /* { dg-final { scan-assembler "add.+ r0, #1024" } } */ - /* { dg-final { scan-assembler "fsts.+ \\\[r\[0-9\]\\\]\n" } } */ + /* { dg-final { scan-assembler "vstr.32.+ \\\[r\[0-9\]\\\]\n" } } */ f[256] = f[255] + f[-255]; - /* { dg-final { scan-assembler "fldd.+ \\\[r1, #1016\\\]" } } */ - /* { dg-final { scan-assembler "fldd.+ \\\[r\[1-9\], #-1016\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */ - /* { dg-final { scan-assembler "fstd.+ \\\[r1, #256\\\]" } } */ + /* { dg-final { scan-assembler "vldr.64.+ \\\[r1, #1016\\\]" } } */ + /* { dg-final { scan-assembler "vldr.64.+ \\\[r\[1-9\], #-1016\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */ + /* { dg-final { scan-assembler "vstr.64.+ \\\[r1, #256\\\]" } } */ d[32] = d[127] + d[-127]; } diff --git a/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c b/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c index 28047149670..704157979aa 100644 --- a/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c +++ b/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c @@ -13,4 +13,4 @@ foo (double *p, double a, int n) while (n--); } -/* { dg-final { scan-assembler "fldmdbd" } } */ +/* { dg-final { scan-assembler "vldmdb.64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c b/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c index f5940ef975a..0187c01606c 100644 --- a/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c +++ b/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c @@ -3,7 +3,7 @@ /* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */ /* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ -extern void baz (float); +extern void bar (float); void foo (float *p, float a, int n) @@ -13,4 +13,4 @@ foo (float *p, float a, int n) while (n--); } -/* { dg-final { scan-assembler "fldmdbs" } } */ +/* { dg-final { scan-assembler "vldmdb.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c b/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c index 6f052671299..9c22f1f463c 100644 --- a/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c +++ b/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c @@ -13,4 +13,4 @@ foo (double *p, double a, int n) while (n--); } -/* { dg-final { scan-assembler "fldmiad" } } */ +/* { dg-final { scan-assembler "vldmia.64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/vfp-ldmias.c b/gcc/testsuite/gcc.target/arm/vfp-ldmias.c index 79ad7bf174c..92051fd1827 100644 --- a/gcc/testsuite/gcc.target/arm/vfp-ldmias.c +++ b/gcc/testsuite/gcc.target/arm/vfp-ldmias.c @@ -3,7 +3,7 @@ /* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */ /* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */ -extern void baz (float); +extern void bar (float); void foo (float *p, float a, int n) @@ -13,4 +13,4 @@ foo (float *p, float a, int n) while (n--); } -/* { dg-final { scan-assembler "fldmias" } } */ +/* { dg-final { scan-assembler "vldmia.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c b/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c index d8093d9d4b6..53383b5cf0a 100644 --- a/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c +++ b/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c @@ -12,4 +12,4 @@ foo (double *p, double a, double b, int n) while (n--); } -/* { dg-final { scan-assembler "fstmdbd" } } */ +/* { dg-final { scan-assembler "vstmdb.64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c b/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c index bb19d902b5d..6570defa71e 100644 --- a/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c +++ b/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c @@ -12,4 +12,4 @@ foo (float *p, float a, float b, int n) while (n--); } -/* { dg-final { scan-assembler "fstmdbs" } } */ +/* { dg-final { scan-assembler "vstmdb.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/vfp-stmiad.c b/gcc/testsuite/gcc.target/arm/vfp-stmiad.c index 1b6d22bd800..28e9d73b3f6 100644 --- a/gcc/testsuite/gcc.target/arm/vfp-stmiad.c +++ b/gcc/testsuite/gcc.target/arm/vfp-stmiad.c @@ -12,4 +12,4 @@ foo (double *p, double a, double b, int n) while (n--); } -/* { dg-final { scan-assembler "fstmiad" } } */ +/* { dg-final { scan-assembler "vstmia.64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/vfp-stmias.c b/gcc/testsuite/gcc.target/arm/vfp-stmias.c index 3da632745f4..efa5fbe57f6 100644 --- a/gcc/testsuite/gcc.target/arm/vfp-stmias.c +++ b/gcc/testsuite/gcc.target/arm/vfp-stmias.c @@ -12,4 +12,4 @@ foo (float *p, float a, float b, int n) while (n--); } -/* { dg-final { scan-assembler "fstmias" } } */ +/* { dg-final { scan-assembler "vstmia.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/xordi3-opt.c b/gcc/testsuite/gcc.target/arm/xordi3-opt.c index 7e031c3af2c..53b2bab80d7 100644 --- a/gcc/testsuite/gcc.target/arm/xordi3-opt.c +++ b/gcc/testsuite/gcc.target/arm/xordi3-opt.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { arm_arm_ok || arm_thumb2_ok} } } */ /* { dg-options "-O1" } */ unsigned long long xor64 (unsigned long long input) |