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-rw-r--r--gcc/testsuite/gcc.target/mips/oddspreg-6.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/mips/oddspreg-6.c b/gcc/testsuite/gcc.target/mips/oddspreg-6.c
new file mode 100644
index 00000000000..955dea90140
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/oddspreg-6.c
@@ -0,0 +1,10 @@
+/* Check that we disable odd-numbered single precision registers for FPXX. */
+/* { dg-skip-if "needs asm output" { *-*-* } { "-fno-fat-lto-objects" } { "" } } */
+/* { dg-options "-mabi=32 -mfpxx -mhard-float" } */
+
+void
+foo ()
+{
+ register float foo asm ("$f1"); /* { dg-error "isn't suitable for" } */
+ asm volatile ("" : "=f" (foo));
+}