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-rw-r--r--gcc/testsuite/gcc.target/powerpc/vec-extract-1.c27
1 files changed, 27 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-1.c
new file mode 100644
index 00000000000..ef34e2bec2c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-1.c
@@ -0,0 +1,27 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-di" } */
+
+#include <altivec.h>
+
+double
+add_double (vector double a, int n)
+{
+ return vec_extract (a, n) + 1.0;
+}
+
+long
+add_long (vector long a, int n)
+{
+ return vec_extract (a, n) + 1;
+}
+
+/* { dg-final { scan-assembler "vslo" } } */
+/* { dg-final { scan-assembler "mtvsrd" } } */
+/* { dg-final { scan-assembler "mfvsrd" } } */
+/* { dg-final { scan-assembler-not "stxvd2x" } } */
+/* { dg-final { scan-assembler-not "stxvx" } } */
+/* { dg-final { scan-assembler-not "stxv" } } */
+/* { dg-final { scan-assembler-not "ldx" } } */