diff options
Diffstat (limited to 'gcc/testsuite/gcc.target/powerpc')
87 files changed, 4348 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/powerpc/20020118-1.c b/gcc/testsuite/gcc.target/powerpc/20020118-1.c new file mode 100644 index 00000000000..393f3c2aa5b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/20020118-1.c @@ -0,0 +1,17 @@ +/* { dg-do run { target powerpc*-*-* } }*/ + +/* Test local alignment. Test new target macro STARTING_FRAME_PHASE. */ +/* Origin: Aldy Hernandez <aldyh@redhat.com>. */ + +extern void abort(void); + +int main () +{ + int darisa[4] __attribute__((aligned(16))) ; + int *stephanie = (int *) darisa; + + if ((unsigned long) stephanie % 16 != 0) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/20030218-1.c b/gcc/testsuite/gcc.target/powerpc/20030218-1.c new file mode 100644 index 00000000000..6296d31bfce --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/20030218-1.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target powerpc-*-eabi* } } */ +/* { dg-options "-mspe=yes" } */ + +/* Test vectors that can interconvert without a cast. */ + +__ev64_opaque__ opp; +int vint __attribute__((vector_size (8))); +short vshort __attribute__((vector_size (8))); +float vfloat __attribute__((vector_size (8))); + +int +main (void) +{ + __ev64_opaque__ george = { 1, 2 }; /* { dg-error "opaque vector types cannot be initialized" } */ + + opp = vfloat; + vshort = opp; + vfloat = vshort; /* { dg-error "incompatible types in assignment" } */ + + /* Just because this is a V2SI, it doesn't make it an opaque. */ + vint = vshort; /* { dg-error "incompatible types in assignment" } */ + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/20030505.c b/gcc/testsuite/gcc.target/powerpc/20030505.c new file mode 100644 index 00000000000..0df1c0335eb --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/20030505.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target powerpc-*-eabispe* } } */ +/* { dg-options "-W" } */ + +#define __vector __attribute__((vector_size(8))) + +typedef float __vector __ev64_fs__; + +__ev64_opaque__ *p1; +__ev64_fs__ *p2; +int *x; + +extern void f (__ev64_opaque__ *); + +int main () +{ + f (x); /* { dg-warning "incompatible pointer type" } */ + f (p1); + f (p2); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/20040121-1.c b/gcc/testsuite/gcc.target/powerpc/20040121-1.c new file mode 100644 index 00000000000..f819a4949aa --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/20040121-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-options "-O2 -mcpu=G5 " } */ + +long long (*y)(int t); +long long get_alias_set (int t) +{ + return y(t); +} diff --git a/gcc/testsuite/gcc.target/powerpc/20040622-1.c b/gcc/testsuite/gcc.target/powerpc/20040622-1.c new file mode 100644 index 00000000000..4562fe6eaa1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/20040622-1.c @@ -0,0 +1,13 @@ +/* { dg-options "-Os -mlong-double-128" } */ +/* { dg-do compile { target rs6000-*-* powerpc-*-* } } */ +/* Make sure compiler doesn't generate [reg+reg] address mode + for long doubles. */ +union arg { + int intarg; + long double longdoublearg; +}; +long double d; +int va(int n, union arg **argtable) +{ + (*argtable)[n].longdoublearg = d; +} diff --git a/gcc/testsuite/gcc.target/powerpc/20041111-1.c b/gcc/testsuite/gcc.target/powerpc/20041111-1.c new file mode 100644 index 00000000000..94de2f03ad6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/20041111-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-mcpu=power4 -O2" } */ + +extern unsigned long long set_mask[65]; +extern unsigned long long xyzzy(int) __attribute__((pure)); + +int valid (int x) +{ + return(xyzzy(x) & set_mask[x]); +} diff --git a/gcc/testsuite/gcc.target/powerpc/20050603-1.c b/gcc/testsuite/gcc.target/powerpc/20050603-1.c new file mode 100644 index 00000000000..041551ba5ae --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/20050603-1.c @@ -0,0 +1,24 @@ +/* { dg-do run { target powerpc*-*-* } } */ +/* { dg-options "-O2" } */ +#include <locale.h> +#include <stdlib.h> +register int *testreg asm ("r29"); + +int x; +int y; +int *ext_func (int *p) { return p; } + +void test_reg_save_restore (int*) __attribute__((noinline)); +void +test_reg_save_restore (int *p) +{ + setlocale (LC_ALL, "C"); + testreg = ext_func(p); +} +main() { + testreg = &x; + test_reg_save_restore (&y); + if (testreg != &y) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/20050603-3.c b/gcc/testsuite/gcc.target/powerpc/20050603-3.c new file mode 100644 index 00000000000..35be6602155 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/20050603-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target "powerpc-*-*" } } */ +/* { dg-options "-O2" } */ +struct Q +{ + long x:20; + long y:4; + long z:8; +}b; +/* This should generate a single rl[w]imi. */ +void rotins (unsigned int x) +{ + b.y = (x<<12) | (x>>20); +} + +/* { dg-final { scan-assembler-not "inm" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/20050830-1.c b/gcc/testsuite/gcc.target/powerpc/20050830-1.c new file mode 100644 index 00000000000..edbf6b8e43a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/20050830-1.c @@ -0,0 +1,13 @@ +/* Make sure the doloop optimization is done for this loop. */ +/* { dg-do compile { target powerpc-*-* } } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler "bdn" } } */ +extern int a[]; +int foo(int w) { + int n = w; + while (n >= 512) + { + a[n] = 42; + n -= 256; + } + } diff --git a/gcc/testsuite/gcc.target/powerpc/980827-1.c b/gcc/testsuite/gcc.target/powerpc/980827-1.c new file mode 100644 index 00000000000..84ba5ee4d5f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/980827-1.c @@ -0,0 +1,29 @@ +/* { dg-do run { target rs6000-*-linux* powerpc-*-linux*} } */ +/* { dg-options -O2 } */ + +extern void exit (int); +extern void abort (void); + +double dval = 0; + +void splat (double d); + +int main(void) +{ + splat(0); + if (dval == 0) + abort(); + exit (0); +} + +void splat (double d) +{ + union { + double f; + unsigned int l[2]; + } u; + + u.f = d + d; + u.l[1] |= 1; + asm volatile ("stfd %0,dval@sdarel(13)" : : "f" (u.f)); +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-1.c b/gcc/testsuite/gcc.target/powerpc/altivec-1.c new file mode 100644 index 00000000000..65c8fa79bf9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-1.c @@ -0,0 +1,42 @@ +/* { dg-do run { target powerpc*-*-* } } */ +/* { dg-xfail-if "" { "powerpc-*-eabispe*" "powerpc-ibm-aix*" } { "-maltivec" } { "" } } */ +/* { dg-options "-maltivec" } */ + +/* Program to test PowerPC AltiVec instructions. */ + +#include <altivec.h> +#include "altivec_check.h" + +extern void abort (void); + +vector int a1 = { 100, 200, 300, 400 }; +vector int a2 = { 500, 600, 700, 800 }; +vector int addi = { 600, 800, 1000, 1200 }; +vector int avgi = { 300, 400, 500, 600 }; + +vector float f1 = { 1.0, 2.0, 3.0, 4.0 }; +vector float f2 = { 5.0, 6.0, 7.0, 8.0 }; +vector float f3; +vector float addf = { 6.0, 8.0, 10.0, 12.0 }; + +vector int k; +vector float f, g, h; + +int main () +{ + altivec_check(); /* Exits if AltiVec not supported */ + + k = vec_add (a1, a2); + if (!vec_all_eq (addi, k)) + abort (); + + k = vec_avg (a1, a2); + if (!vec_all_eq (k, avgi)) + abort (); + + h = vec_add (f1, f2); + if (!vec_all_eq (h, addf)) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-10.c b/gcc/testsuite/gcc.target/powerpc/altivec-10.c new file mode 100644 index 00000000000..f65ea71ed49 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-10.c @@ -0,0 +1,80 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-xfail-if "" { "powerpc-ibm-aix*" } { "-maltivec" } { "" } } */ +/* { dg-options "-maltivec -mabi=altivec -fno-inline" } */ + +#include <altivec.h> +#include <signal.h> + +#include "altivec_check.h" + +typedef union +{ + float f[4]; + unsigned int i[4]; + vector float v; +} vec_float_t; + +void +check_vec_all_num () +{ + vec_float_t a, b, c; + + a.i[0] = 0xfffa5a5a; + a.f[1] = 1.0; + a.f[2] = 1.0; + a.f[3] = 1.0; + + b.f[0] = 1.0; + b.f[1] = 1.0; + b.f[2] = 1.0; + b.f[3] = 1.0; + + c.i[0] = 0xfffa5a5a; + c.i[1] = 0xfffa5a5a; + c.i[2] = 0xfffa5a5a; + c.i[3] = 0xfffa5a5a; + + if (vec_all_numeric (a.v)) + abort (); + + if (vec_all_nan (a.v)) + abort (); + + if (!vec_all_numeric (b.v)) + abort (); + + if (vec_all_nan (b.v)) + abort (); + + if (vec_all_numeric (c.v)) + abort (); + + if (!vec_all_nan (c.v)) + abort (); + +} + +void +check_cmple() +{ + vector float a = {1.0, 2.0, 3.0, 4.0}; + vector float b = {1.0, 3.0, 2.0, 5.0}; + vector bool int aux; + vector signed int le = {-1, -1, 0, -1}; + + aux = vec_cmple (a, b); + + if (!vec_all_eq (aux, le)) + abort (); +} + + +int +main() +{ + altivec_check (); + + check_cmple (); + check_vec_all_num (); + exit (0); +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-11.c b/gcc/testsuite/gcc.target/powerpc/altivec-11.c new file mode 100644 index 00000000000..82ea51a3644 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-11.c @@ -0,0 +1,59 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-xfail-if "" { "powerpc-ibm-aix*" } { "-maltivec" } { "" } } */ +/* { dg-options "-O2 -maltivec -mabi=altivec" } */ +/* { dg-final { scan-assembler-not "lvx" } } */ +#include <altivec.h> + +void foo (vector int); +void foo_s (vector short); +void foo_c (vector char); + +/* All constants should be loaded into vector register without + load from memory. */ +void +bar (void) +{ + foo ((vector int) {0, 0, 0, 0}); + foo ((vector int) {1, 1, 1, 1}); + foo ((vector int) {15, 15, 15, 15}); + foo ((vector int) {-16, -16, -16, -16}); + foo ((vector int) {0x10001, 0x10001, 0x10001, 0x10001}); + foo ((vector int) {0xf000f, 0xf000f, 0xf000f, 0xf000f}); + foo ((vector int) {0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0}); + foo ((vector int) {0x1010101, 0x1010101, 0x1010101, 0x1010101}); + foo ((vector int) {0xf0f0f0f, 0xf0f0f0f, 0xf0f0f0f, 0xf0f0f0f}); + foo ((vector int) {0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0}); + foo ((vector int) {0x10101010, 0x10101010, 0x10101010, 0x10101010}); + foo ((vector int) {0x1e1e1e1e, 0x1e1e1e1e, 0x1e1e1e1e, 0x1e1e1e1e}); + foo ((vector int) {0x100010, 0x100010, 0x100010, 0x100010}); + foo ((vector int) {0x1e001e, 0x1e001e, 0x1e001e, 0x1e001e}); + foo ((vector int) {0x10, 0x10, 0x10, 0x10}); + foo ((vector int) {0x1e, 0x1e, 0x1e, 0x1e}); + + foo_s ((vector short int) {0, 0, 0, 0, 0, 0, 0, 0}); + foo_s ((vector short int) {1, 1, 1, 1, 1, 1, 1, 1}); + foo_s ((vector short int) {15, 15, 15, 15, 15, 15, 15, 15}); + foo_s ((vector short int) {-16, -16, -16, -16, -16, -16, -16, -16}); + foo_s ((vector short int) {0xf0f0, 0xf0f0, 0xf0f0, 0xf0f0, + 0xf0f0, 0xf0f0, 0xf0f0, 0xf0f0}); + foo_s ((vector short int) {0xf0f, 0xf0f, 0xf0f, 0xf0f, + 0xf0f, 0xf0f, 0xf0f, 0xf0f}); + foo_s ((vector short int) {0x1010, 0x1010, 0x1010, 0x1010, + 0x1010, 0x1010, 0x1010, 0x1010}); + foo_s ((vector short int) {0x1e1e, 0x1e1e, 0x1e1e, 0x1e1e, + 0x1e1e, 0x1e1e, 0x1e1e, 0x1e1e}); + + foo_c ((vector char) {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}); + foo_c ((vector char) {1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1}); + foo_c ((vector char) {15, 15, 15, 15, 15, 15, 15, 15, + 15, 15, 15, 15, 15, 15, 15, 15}); + foo_c ((vector char) {-16, -16, -16, -16, -16, -16, -16, -16, + -16, -16, -16, -16, -16, -16, -16, -16}); + foo_c ((vector char) {16, 16, 16, 16, 16, 16, 16, 16, + 16, 16, 16, 16, 16, 16, 16, 16}); + foo_c ((vector char) {30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30}); + +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-12.c b/gcc/testsuite/gcc.target/powerpc/altivec-12.c new file mode 100644 index 00000000000..0a32b64fe87 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-12.c @@ -0,0 +1,96 @@ +/* { dg-do run { target powerpc*-*-* } } */ +/* { dg-xfail-if "" { "powerpc-ibm-aix*" } { "-maltivec" } { "" } } */ +/* { dg-options "-maltivec" } */ + +/* Program to test PowerPC AltiVec instructions. */ + +#include <altivec.h> +#include "altivec_check.h" + +extern void abort (void); +#define CHECK_IF(E) if(!(E)) abort() + +vector int a1 = (vector int){ 100, 200, 300, 400 }; +vector int a2 = (vector int){ 500, 600, 700, 800 }; +vector int addi = (vector int){ 600, 800, 1000, 1200 }; +vector int avgi = (vector int){ 300, 400, 500, 600 }; + +vector float f1 = (vector float){ 1.0, 2.0, 3.0, 4.0 }; +vector float f2 = (vector float){ 5.0, 6.0, 7.0, 8.0 }; +vector float f3; +vector float addf1 = (vector float){ 6.0, 8.0, 10.0, 12.0 }; +vector float addf2 = (vector float){ 6.1, 8.1, 10.1, 12.1 }; +vector float addf3 = (vector float){ 6.0, 8.0, 9.9, 12.1 }; +vector int k; +vector float f, g, h; + +int main () +{ + + altivec_check(); /* Exit if AltiVec not available. */ + + k = vec_add (a1, a2); + CHECK_IF (vec_all_eq (addi, k)); + CHECK_IF (vec_all_ge (addi, k)); + CHECK_IF (vec_all_le (addi, k)); + CHECK_IF (vec_any_eq (addi, k)); + CHECK_IF (vec_any_ge (addi, k)); + CHECK_IF (vec_any_le (addi, k)); + CHECK_IF (!vec_any_ne (addi, k)); + CHECK_IF (!vec_any_lt (addi, k)); + CHECK_IF (!vec_any_gt (addi, k)); + CHECK_IF (!vec_any_ne (addi, k)); + CHECK_IF (!vec_any_lt (addi, k)); + CHECK_IF (!vec_any_gt (addi, k)); + + k = vec_avg (a1, a2); + CHECK_IF (vec_all_eq (k, avgi)); + + h = vec_add (f1, f2); + CHECK_IF (vec_all_eq (h, addf1)); + CHECK_IF (vec_all_ge (h, addf1)); + CHECK_IF (vec_all_le (h, addf1)); + CHECK_IF (vec_any_eq (h, addf1)); + CHECK_IF (vec_any_ge (h, addf1)); + CHECK_IF (vec_any_le (h, addf1)); + CHECK_IF (!vec_any_ne (h, addf1)); + CHECK_IF (!vec_any_lt (h, addf1)); + CHECK_IF (!vec_any_gt (h, addf1)); + CHECK_IF (!vec_any_ne (h, addf1)); + CHECK_IF (!vec_any_lt (h, addf1)); + CHECK_IF (!vec_any_gt (h, addf1)); + + CHECK_IF (vec_all_gt (addf2, addf1)); + CHECK_IF (vec_any_gt (addf2, addf1)); + CHECK_IF (vec_all_ge (addf2, addf1)); + CHECK_IF (vec_any_ge (addf2, addf1)); + CHECK_IF (vec_all_ne (addf2, addf1)); + CHECK_IF (vec_any_ne (addf2, addf1)); + CHECK_IF (!vec_all_lt (addf2, addf1)); + CHECK_IF (!vec_any_lt (addf2, addf1)); + CHECK_IF (!vec_all_le (addf2, addf1)); + CHECK_IF (!vec_any_le (addf2, addf1)); + CHECK_IF (!vec_all_eq (addf2, addf1)); + CHECK_IF (!vec_any_eq (addf2, addf1)); + + CHECK_IF (vec_any_eq (addf3, addf1)); + CHECK_IF (vec_any_ne (addf3, addf1)); + CHECK_IF (vec_any_lt (addf3, addf1)); + CHECK_IF (vec_any_le (addf3, addf1)); + CHECK_IF (vec_any_gt (addf3, addf1)); + CHECK_IF (vec_any_ge (addf3, addf1)); + CHECK_IF (!vec_all_eq (addf3, addf1)); + CHECK_IF (!vec_all_ne (addf3, addf1)); + CHECK_IF (!vec_all_lt (addf3, addf1)); + CHECK_IF (!vec_all_le (addf3, addf1)); + CHECK_IF (!vec_all_gt (addf3, addf1)); + CHECK_IF (!vec_all_ge (addf3, addf1)); + + CHECK_IF (vec_all_numeric (addf3)); + CHECK_IF (vec_all_in (addf1, addf2)); + + CHECK_IF (vec_step (vector bool char) == 16); + CHECK_IF (vec_step (addf3) == 4); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-13.c b/gcc/testsuite/gcc.target/powerpc/altivec-13.c new file mode 100644 index 00000000000..8675e2c7cc7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-13.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-xfail-if "" { "powerpc-ibm-aix*" } { "-maltivec" } { "" } } */ +/* { dg-options "-maltivec" } */ +/* Author: Ziemowit Laski <zlaski@apple.com> */ + +/* This test case exercises intrinsic/argument combinations that, + while not in the Motorola AltiVec PIM, have nevertheless crept + into the AltiVec vernacular over the years. */ + +#include <altivec.h> + +void foo (void) +{ + vector bool int boolVec1 = (vector bool int) vec_splat_u32(3); + vector bool short boolVec2 = (vector bool short) vec_splat_u16(3); + vector bool char boolVec3 = (vector bool char) vec_splat_u8(3); + + boolVec1 = vec_sld( boolVec1, boolVec1, 4 ); + boolVec2 = vec_sld( boolVec2, boolVec2, 2 ); + boolVec3 = vec_sld( boolVec3, boolVec3, 1 ); +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-14.c b/gcc/testsuite/gcc.target/powerpc/altivec-14.c new file mode 100644 index 00000000000..b67c529377b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-14.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target powerpc-*-* } } */ +/* { dg-xfail-if "" { "powerpc-ibm-aix*" } { "-maltivec" } { "" } } */ +/* { dg-options "-maltivec" } */ + +#include <altivec.h> + +vector bool long vbl; /* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */ +vector signed long vsl; /* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */ +vector unsigned long vul; /* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */ +vector bool long *pvbl; /* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */ +vector signed long *pvsl; /* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */ +vector unsigned long *pvul; /* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */ + +void fvbl (vector bool long v) { } /* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */ +void fvsl (vector signed long v) { } /* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */ +void fvul (vector unsigned long v) { } /* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */ + +int main () +{ + vector bool long lvbl; /* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */ + vector signed long lvsl; /* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */ + vector unsigned long lvul; /* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */ + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-15.c b/gcc/testsuite/gcc.target/powerpc/altivec-15.c new file mode 100644 index 00000000000..5d9f9ff37da --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-15.c @@ -0,0 +1,30 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-xfail-if "" { "powerpc-ibm-aix*" } { "-maltivec" } { "" } } */ +/* { dg-options "-maltivec" } */ + +#include <altivec.h> + +/* Test whether the C front-end is not excessively picky about + the integral types and literals that AltiVec instrinsics will + accept. */ + +vector int vi = { 1, 2, 3, 4 }; + +int +main (void) +{ + unsigned long ul = 2; + signed long sl = 2; + unsigned int ui = 2; + signed int si = 2; + float fl = 2.0; + + vec_dst (&vi, ul, '\0'); + vec_dst (&vi, sl, 0); + vec_dst (&vi, ui, '\0'); + vec_dst (&vi, si, 0); + vec_dstst (&vi, (short)fl, '\0'); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-16.c b/gcc/testsuite/gcc.target/powerpc/altivec-16.c new file mode 100644 index 00000000000..0be609431ce --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-16.c @@ -0,0 +1,22 @@ +/* This is a compile-only test for interaction of "-maltivec" and "-save-temps". */ +/* Author: Ziemowit Laski <zlaski@apple.com>. */ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-xfail-if "" { "powerpc-ibm-aix*" } { "-maltivec" } { "" } } */ +/* { dg-options "-save-temps -maltivec" } */ + +#include <altivec.h> + +#define vector_float vector float +#define vector_float_foo vector float foo +#define vector_float_bar_eq vector float bar = + +/* NB: Keep the following split across three lines. */ +vector +int +a1 = { 100, 200, 300, 400 }; + +vector_float f1 = { 1.0, 2.0, 3.0, 4.0 }; +vector_float_foo = { 3.0, 4.0, 5.0, 6.0 }; +vector_float_bar_eq { 8.0, 7.0, 6.0, 5.0 }; + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-17.c b/gcc/testsuite/gcc.target/powerpc/altivec-17.c new file mode 100644 index 00000000000..463062ef086 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-17.c @@ -0,0 +1,11 @@ +/* Verify a statement in the GCC Manual that GCC allows the use of a + typedef name as a vector type specifier. */ + +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-xfail-if "" { "powerpc-ibm-aix*" } { "-maltivec" } { "" } } */ +/* { dg-options "-maltivec -mabi=altivec" } */ + +typedef unsigned int ui; +typedef signed char sc; +__vector ui vui; +__vector sc vsc; diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-18.c b/gcc/testsuite/gcc.target/powerpc/altivec-18.c new file mode 100644 index 00000000000..9a3ee33f63d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-18.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-xfail-if "" { "powerpc-ibm-aix*" } { "-maltivec" } { "" } } */ +/* { dg-options "-maltivec -mabi=altivec" } */ +/* { dg-final { scan-assembler "vcmpgtub" { target *-*-linux* } } } */ +/* { dg-final { scan-assembler "vcmpgtsb" { target *-*-darwin* } } } */ +/* { dg-final { scan-assembler "vcmpgtsh" } } */ +/* { dg-final { scan-assembler "vcmpgtsw" } } */ + +/* Verify a statement in the GCC Manual that vector type specifiers can + omit "signed" or "unsigned". The default is the default signedness + of the base type, which differs depending on the ABI. */ + +#include <altivec.h> + +extern vector char vc1, vc2; +extern vector short vs1, vs2; +extern vector int vi1, vi2; + +int signedness (void) +{ + return vec_all_le (vc1, vc2) + && vec_all_le (vs1, vs2) + && vec_all_le (vi1, vi2); +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-19.c b/gcc/testsuite/gcc.target/powerpc/altivec-19.c new file mode 100644 index 00000000000..1693a5488ee --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-19.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-maltivec" } */ +/* { dg-final { scan-assembler "dst" } } */ + +void foo ( char* image ) +{ + while ( 1 ) + { + __builtin_altivec_dst( (void *)( (long)image & ~0x0f ), 0, 0 ); + image += 48; + } +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-2.c b/gcc/testsuite/gcc.target/powerpc/altivec-2.c new file mode 100644 index 00000000000..f64081ff813 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-2.c @@ -0,0 +1,35 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-maltivec" } */ + +/* Program to test the vector_size attribute. This needs to run on a + target that has vectors, so use AltiVec. */ + +#define vector __attribute__((vector_size(16))) + +vector int foobar; + +/* Only floats and integrals allowed. We don't care if they map to SIs. */ +struct X { int frances; }; +vector struct X hotdog; /* { dg-error "invalid vector type" } */ + +/* Arrays of vectors. */ +vector char b[10], ouch; + +/* Pointers of vectors. */ +vector short *shoe, polish; + +int xxx[sizeof(foobar) == 16 ? 69 : -1]; + +int nc17[sizeof(shoe) == sizeof (char *) ? 69 : -1]; + +code () +{ + *shoe = polish; + b[1] = ouch; +} + +vector short +hoop () +{ + return polish; +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-20.c b/gcc/testsuite/gcc.target/powerpc/altivec-20.c new file mode 100644 index 00000000000..f733d18214c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-20.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-maltivec -mcpu=G5 -O2" } */ + +#include <altivec.h> + +void foo( float scalar) +{ + unsigned long width; + unsigned long x; + vector float vColor; + vector unsigned int selectMask; + vColor = vec_perm( vec_ld( 0, &scalar), vec_ld( 3, &scalar), vec_lvsl( 0, &scalar) ); + + float *destRow; + vector float store, load0; + + for( ; x < width; x++) + { + load0 = vec_sel( vColor, load0, selectMask ); + vec_st( store, 0, destRow ); + store = load0; + } +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-21.c b/gcc/testsuite/gcc.target/powerpc/altivec-21.c new file mode 100644 index 00000000000..736cd74feb6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-21.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-maltivec" } */ + +#include <altivec.h> + +extern void preansi(); + +typedef void (*pvecfunc) (); + +void foo(pvecfunc pvf) { + vector int v = (vector int){1, 2, 3, 4}; +#ifndef __LP64__ + preansi (4, 4.0, v); /* { dg-error "AltiVec argument passed to unprototyped function" "" { target ilp32 } } */ + (*pvf) (4, 4.0, v); /* { dg-error "AltiVec argument passed to unprototyped function" "" { target ilp32 } } */ +#endif /* __LP64__ */ +} + diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-22.c b/gcc/testsuite/gcc.target/powerpc/altivec-22.c new file mode 100644 index 00000000000..5c8c96b6b69 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-22.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target powerpc-*-* } } */ +/* { dg-options "-O3 -maltivec" } */ +/* { dg-final { scan-assembler-not "mfcr" } } */ + +#include <altivec.h> + +int foo(vector float x, vector float y) { + if (vec_all_eq(x,y)) return 3245; + else return 12; +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-3.c b/gcc/testsuite/gcc.target/powerpc/altivec-3.c new file mode 100644 index 00000000000..f1105d51b26 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-3.c @@ -0,0 +1,79 @@ +/* { dg-do run { target powerpc*-*-* } } */ +/* { dg-xfail-if "" { "powerpc-*-eabispe*" "powerpc-ibm-aix*" } { "-maltivec" } { "" } } */ +/* { dg-options "-maltivec" } */ + +#include "altivec_check.h" + +typedef int int4 __attribute__ ((vector_size (16))); +typedef float float4 __attribute__ ((vector_size (16))); + +int4 a1 = (int4) { 100, 200, 300, 400 }; +int4 a2 = (int4) { 500, 600, 700, 800 }; + +float4 f1 = (float4) { 1.0, 2.0, 3.0, 4.0 }; +float4 f2 = (float4) { 5.0, 6.0, 7.0, 8.0 }; + +int i3[4] __attribute__((aligned(16))); +int j3[4] __attribute__((aligned(16))); +float h3[4] __attribute__((aligned(16))); +float g3[4] __attribute__((aligned(16))); + +#define vec_store(dst, src) \ + __builtin_vec_st (src, 0, (__typeof__ (src) *) dst) + +#define vec_add_int4(x, y) \ + __builtin_altivec_vaddsws (x, y) + +#define vec_add_float4(x, y) \ + __builtin_altivec_vaddfp (x, y) + +#define my_abs(x) (x > 0.0F ? x : -x) + +void +compare_int4 (int *a, int *b) +{ + int i; + + for (i = 0; i < 4; ++i) + if (a[i] != b[i]) + abort (); +} + +void +compare_float4 (float *a, float *b) +{ + int i; + + for (i = 0; i < 4; ++i) + if (my_abs(a[i] - b[i]) >= 1.0e-6) + abort (); +} + +void +main1 () +{ + int loc1 = 600, loc2 = 800; + int4 a3 = (int4) { loc1, loc2, 1000, 1200 }; + int4 itmp; + double locf = 12.0; + float4 f3 = (float4) { 6.0, 8.0, 10.0, 12.0 }; + float4 ftmp; + + vec_store (i3, a3); + itmp = vec_add_int4 (a1, a2); + vec_store (j3, itmp); + compare_int4 (i3, j3); + + vec_store (g3, f3); + ftmp = vec_add_float4 (f1, f2); + vec_store (h3, ftmp); + compare_float4 (g3, h3); +} + +int +main () +{ + altivec_check (); + main1 (); + exit (0); +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-4.c b/gcc/testsuite/gcc.target/powerpc/altivec-4.c new file mode 100644 index 00000000000..c2d4356a9a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-4.c @@ -0,0 +1,65 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-xfail-if "" { "powerpc-ibm-aix*" } { "-maltivec" } { "" } } */ +/* { dg-options "-maltivec -O0 -Wall" } */ + +#define vector __attribute__((vector_size(16))) + +static int vector x, y; + +static vector signed int i,j; +static vector signed short s,t; +static vector signed char c,d; +static vector float f,g; + +static vector unsigned char uc; + +static vector signed int *pi; + +static int int1, int2; + +void +b() +{ + __builtin_altivec_vadduwm (x, y); + + /* Make sure the predicates accept correct argument types. */ + + int1 = __builtin_altivec_vcmpbfp_p (0, f, g); + int1 = __builtin_altivec_vcmpeqfp_p (0, f, g); + int1 = __builtin_altivec_vcmpequb_p (0, c, d); + int1 = __builtin_altivec_vcmpequh_p (0, s, t); + int1 = __builtin_altivec_vcmpequw_p (0, i, j); + int1 = __builtin_altivec_vcmpgefp_p (0, f, g); + int1 = __builtin_altivec_vcmpgtfp_p (0, f, g); + int1 = __builtin_altivec_vcmpgtsb_p (0, c, d); + int1 = __builtin_altivec_vcmpgtsh_p (0, s, t); + int1 = __builtin_altivec_vcmpgtsw_p (0, i, j); + int1 = __builtin_altivec_vcmpgtub_p (0, c, d); + int1 = __builtin_altivec_vcmpgtuh_p (0, s, t); + int1 = __builtin_altivec_vcmpgtuw_p (0, i, j); + + __builtin_altivec_mtvscr (i); + __builtin_altivec_dssall (); + s = __builtin_altivec_mfvscr (); + __builtin_altivec_dss (3); + + __builtin_altivec_dst (pi, int1 + int2, 3); + __builtin_altivec_dstst (pi, int1 + int2, 3); + __builtin_altivec_dststt (pi, int1 + int2, 3); + __builtin_altivec_dstt (pi, int1 + int2, 3); + + uc = (vector unsigned char) __builtin_altivec_lvsl (int1 + 69, pi); + uc = (vector unsigned char) __builtin_altivec_lvsr (int1 + 69, pi); + + c = __builtin_altivec_lvebx (int1, pi); + s = __builtin_altivec_lvehx (int1, pi); + i = __builtin_altivec_lvewx (int1, pi); + i = __builtin_altivec_lvxl (int1, pi); + i = __builtin_altivec_lvx (int1, pi); + + __builtin_altivec_stvx (i, int2, pi); + __builtin_altivec_stvebx (c, int2, pi); + __builtin_altivec_stvehx (s, int2, pi); + __builtin_altivec_stvewx (i, int2, pi); + __builtin_altivec_stvxl (i, int2, pi); +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-5.c b/gcc/testsuite/gcc.target/powerpc/altivec-5.c new file mode 100644 index 00000000000..0adfdb84d19 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-5.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-maltivec -O2" } */ + +#define vector __attribute__((vector_size(16))) + +void foo (const unsigned long x, + vector signed int a, vector signed int b) +{ + unsigned char d[64]; + + __builtin_altivec_stvewx (b, 0, d); +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-6.c b/gcc/testsuite/gcc.target/powerpc/altivec-6.c new file mode 100644 index 00000000000..e0193546679 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-6.c @@ -0,0 +1,66 @@ +/* { dg-do compile { target powerpc-*-* } } */ +/* { dg-xfail-if "" { "powerpc-ibm-aix*" } { "-maltivec" } { "" } } */ +/* { dg-options "-maltivec -O0 -Wall" } */ + +#include <altivec.h> + +/* These denote "generic" GCC vectors. */ +static int __attribute__((vector_size(16))) x, y; + +static vector signed int i,j; +static vector signed short s,t; +static vector signed char c,d; +static vector float f,g; + +static vector unsigned char uc; + +static vector signed int *pi; + +static int int1, int2; + +void +b() +{ + vec_add (x, y); + + /* Make sure the predicates accept correct argument types. */ + + int1 = vec_all_in (f, g); + int1 = vec_all_ge (f, g); + int1 = vec_all_eq (c, d); + int1 = vec_all_ne (s, t); + int1 = vec_any_eq (i, j); + int1 = vec_any_ge (f, g); + int1 = vec_all_ngt (f, g); + int1 = vec_any_ge (c, d); + int1 = vec_any_ge (s, t); + int1 = vec_any_ge (i, j); + int1 = vec_any_ge (c, d); + int1 = vec_any_ge (s, t); + int1 = vec_any_ge (i, j); + + vec_mtvscr (i); + vec_dssall (); + s = (vector signed short) vec_mfvscr (); + vec_dss (3); + + vec_dst (pi, int1 + int2, 3); + vec_dstst (pi, int1 + int2, 3); + vec_dststt (pi, int1 + int2, 3); + vec_dstt (pi, int1 + int2, 3); + + uc = (vector unsigned char) vec_lvsl (int1 + 69, (signed int *) pi); + uc = (vector unsigned char) vec_lvsr (int1 + 69, (signed int *) pi); + + c = vec_lde (int1, (signed char *) pi); + s = vec_lde (int1, (signed short *) pi); + i = vec_lde (int1, (signed int *) pi); + i = vec_ldl (int1, pi); + i = vec_ld (int1, pi); + + vec_st (i, int2, pi); + vec_ste (c, int2, (signed char *) pi); + vec_ste (s, int2, (signed short *) pi); + vec_ste (i, int2, (signed int *) pi); + vec_stl (i, int2, pi); +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-7.c b/gcc/testsuite/gcc.target/powerpc/altivec-7.c new file mode 100644 index 00000000000..9a23940d271 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-7.c @@ -0,0 +1,46 @@ +/* Origin: Aldy Hernandez <aldyh@redhat.com> */ + +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-xfail-if "" { "powerpc-ibm-aix*" } { "-maltivec" } { "" } } */ +/* { dg-options "-maltivec" } */ + +#include <altivec.h> + +int **intp; +int *var_int; +unsigned int **uintp; +vector pixel *varpixel; +vector signed char *vecchar; +vector signed int *vecint; +vector signed short *vecshort; +vector unsigned char *vecuchar; +vector unsigned int *vecuint; +vector unsigned short *vecushort; +vector float *vecfloat; + +int main () +{ + *vecfloat++ = vec_andc((vector bool int)vecint[0], vecfloat[1]); + *vecfloat++ = vec_andc(vecfloat[0], (vector bool int)vecint[1]); + *vecfloat++ = vec_vxor((vector bool int)vecint[0], vecfloat[1]); + *vecfloat++ = vec_vxor(vecfloat[0], (vector bool int)vecint[1]); + *varpixel++ = vec_packpx(vecuint[0], vecuint[1]); + *varpixel++ = vec_vpkpx(vecuint[0], vecuint[1]); + *vecshort++ = vec_vmulosb(vecchar[0], vecchar[1]); + *vecint++ = vec_ld(var_int[0], intp[1]); + *vecint++ = vec_lde(var_int[0], intp[1]); + *vecint++ = vec_ldl(var_int[0], intp[1]); + *vecint++ = vec_lvewx(var_int[0], intp[1]); + *vecint++ = vec_unpackh(vecshort[0]); + *vecint++ = vec_unpackl(vecshort[0]); + *vecushort++ = vec_andc((vector bool short)vecshort[0], vecushort[1]); + *vecushort++ = vec_andc(vecushort[0], (vector bool short)vecshort[1]); + *vecushort++ = vec_vxor((vector bool short)vecshort[0], vecushort[1]); + *vecushort++ = vec_vxor(vecushort[0], (vector bool short)vecshort[1]); + *vecuint++ = vec_ld(var_int[0], uintp[1]); + *vecuint++ = vec_lvx(var_int[0], uintp[1]); + *vecuint++ = vec_vmsumubm(vecuchar[0], vecuchar[1], vecuint[2]); + *vecuchar++ = vec_xor(vecuchar[0], (vector unsigned char)vecchar[1]); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-8.c b/gcc/testsuite/gcc.target/powerpc/altivec-8.c new file mode 100644 index 00000000000..661cce76221 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-8.c @@ -0,0 +1,19 @@ +/* Origin: Aldy Hernandez <aldyh@redhat.com> */ +/* Test rs6000_legitimate_address. PRE_INC should be invalid. */ + +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-xfail-if "" { "powerpc-ibm-aix*" } { "-maltivec" } { "" } } */ +/* { dg-options "-maltivec" } */ + +#include <altivec.h> + +vector signed short *hannah; + +int +main () +{ + *hannah++ = __builtin_altivec_vspltish (5); + *hannah++ = __builtin_altivec_vspltish (6); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-9.c b/gcc/testsuite/gcc.target/powerpc/altivec-9.c new file mode 100644 index 00000000000..36c79d3453b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-9.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-maltivec -mabi=altivec -g" } */ + +/* PR9564 */ + +extern int vfork(void); + +void +boom (void) +{ + char buf[65536]; + vfork(); +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-pr22085.c b/gcc/testsuite/gcc.target/powerpc/altivec-pr22085.c new file mode 100644 index 00000000000..5f0b5df5401 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-pr22085.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-maltivec -fpreprocessed" } */ + +/* Program to test AltiVec with -fpreprocessed. */ +int foo(__attribute__((altivec(vector__))) float x, + __attribute__((altivec(vector__))) float y) +{ + if (__builtin_vec_vcmpeq_p (2, (x), (y))) + return 3245; + else + return 12; +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-types-1.c b/gcc/testsuite/gcc.target/powerpc/altivec-types-1.c new file mode 100644 index 00000000000..0772abcf7d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-types-1.c @@ -0,0 +1,87 @@ +/* { dg-do compile { target powerpc*-*-linux* } } */ +/* { dg-options "-maltivec" } */ + +/* Valid AltiVec vector types should be accepted with no warnings. */ + +__vector char vc; +__vector unsigned char vuc; +__vector signed char vsc; +__vector __bool char vbc; +__vector short vh; +__vector signed short vsh; +__vector unsigned short vuh; +__vector short int vhi; +__vector signed short int vshi; +__vector unsigned short int vuhi; +__vector __bool short vbh; +__vector __bool short int vbhi; +__vector int vi; +__vector unsigned int vui; +__vector signed int vsi; +__vector __bool int vbi; +__vector unsigned vuj; +__vector signed vsj; +__vector __bool vbj; +__vector float vf; + +/* These should be rejected as invalid AltiVec types. */ + +__vector long long vll; /* { dg-error "AltiVec types" "" } */ +__vector unsigned long long vull; /* { dg-error "AltiVec types" "" } */ +__vector signed long long vsll; /* { dg-error "AltiVec types" "" } */ +__vector __bool long long vbll; /* { dg-error "AltiVec types" "" } */ +__vector long long int vlli; /* { dg-error "AltiVec types" "" } */ +__vector unsigned long long int vulli; /* { dg-error "AltiVec types" "" } */ +__vector signed long long int vslli; /* { dg-error "AltiVec types" "" } */ +__vector __bool long long int vblli; /* { dg-error "AltiVec types" "" } */ +__vector double vd1; /* { dg-error "AltiVec types" "" } */ +__vector long double vld; /* { dg-error "AltiVec types" "" } */ +__vector _Bool vb; /* { dg-error "AltiVec types" "" } */ +__vector _Complex float vcf; /* { dg-error "AltiVec types" "" } */ +__vector _Complex double vcd; /* { dg-error "AltiVec types" "" } */ +__vector _Complex long double vcld; /* { dg-error "AltiVec types" "" } */ +__vector _Complex signed char vcsc; /* { dg-error "AltiVec types" "" } */ +__vector _Complex unsigned char vcuc; /* { dg-error "AltiVec types" "" } */ +__vector _Complex short vcss; /* { dg-error "AltiVec types" "" } */ +__vector _Complex unsigned short vcus; /* { dg-error "AltiVec types" "" } */ +__vector _Complex int vcsi; /* { dg-error "AltiVec types" "" } */ +__vector _Complex unsigned int vcui; /* { dg-error "AltiVec types" "" } */ +__vector _Complex long vcsl; /* { dg-error "AltiVec types" "" } */ +__vector _Complex unsigned long vcul; /* { dg-error "AltiVec types" "" } */ +__vector _Complex long long vcsll; /* { dg-error "AltiVec types" "" } */ +__vector _Complex unsigned long long vcull; /* { dg-error "AltiVec types" "" } */ +__vector __complex float v_cf; /* { dg-error "AltiVec types" "" } */ +__vector __complex double v_cd; /* { dg-error "AltiVec types" "" } */ +__vector __complex long double v_cld; /* { dg-error "AltiVec types" "" } */ +__vector __complex signed char v_csc; /* { dg-error "AltiVec types" "" } */ +__vector __complex unsigned char v_cuc; /* { dg-error "AltiVec types" "" } */ +__vector __complex short v_css; /* { dg-error "AltiVec types" "" } */ +__vector __complex unsigned short v_cus; /* { dg-error "AltiVec types" "" } */ +__vector __complex int v_csi; /* { dg-error "AltiVec types" "" } */ +__vector __complex unsigned int v_cui; /* { dg-error "AltiVec types" "" } */ +__vector __complex long v_csl; /* { dg-error "AltiVec types" "" } */ +__vector __complex unsigned long v_cul; /* { dg-error "AltiVec types" "" } */ +__vector __complex long long v_csll; /* { dg-error "AltiVec types" "" } */ +__vector __complex unsigned long long v_cull; /* { dg-error "AltiVec types" "" } */ + +/* These should be rejected because the component types are invalid. We + don't care about the actual error messages here. */ + +__vector __bool unsigned char vbuc; /* { dg-error "error" "" } */ +__vector __bool signed char vbsc; /* { dg-error "error" "" } */ +__vector __bool unsigned short vbuh; /* { dg-error "error" "" } */ +__vector __bool signed short vbsh; /* { dg-error "error" "" } */ +__vector __bool unsigned int vbui; /* { dg-error "error" "" } */ +__vector __bool signed int vbsi; /* { dg-error "error" "" } */ +__vector __bool unsigned vbuj; /* { dg-error "error" "" } */ +__vector __bool signed vbsj; /* { dg-error "error" "" } */ +__vector signed float vsf; /* { dg-error "error" "" } */ +__vector unsigned float vuf; /* { dg-error "error" "" } */ +__vector short float vsf; /* { dg-error "error" "" } */ +__vector signed double vsd; /* { dg-error "error" "" } */ +__vector unsigned double vud; /* { dg-error "error" "" } */ +__vector short double vsd; /* { dg-error "error" "" } */ +__vector __bool float vbf; /* { dg-error "error" "" } */ +__vector __bool double vbd; /* { dg-error "error" "" } */ +__vector __bool short float blf; /* { dg-error "error" "" } */ +__vector __bool short double vlbd; /* { dg-error "error" "" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-types-2.c b/gcc/testsuite/gcc.target/powerpc/altivec-types-2.c new file mode 100644 index 00000000000..4f4d3f3a123 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-types-2.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target powerpc*-*-linux* } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-maltivec" } */ + +/* These should get warnings for 32-bit code. */ + +__vector long vl; /* { dg-warning "deprecated" "" } */ +__vector unsigned long vul; /* { dg-warning "deprecated" "" } */ +__vector signed long vsl; /* { dg-warning "deprecated" "" } */ +__vector __bool long int vbli; /* { dg-warning "deprecated" "" } */ +__vector long int vli; /* { dg-warning "deprecated" "" } */ +__vector unsigned long int vuli; /* { dg-warning "deprecated" "" } */ +__vector signed long int vsli; /* { dg-warning "deprecated" "" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-types-3.c b/gcc/testsuite/gcc.target/powerpc/altivec-types-3.c new file mode 100644 index 00000000000..42fd3ca359c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-types-3.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target powerpc*-*-linux* } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-maltivec" } */ + +/* These should be rejected for 64-bit code. */ + +__vector long vl; /* { dg-error "invalid for 64" "" } */ +__vector unsigned long vul; /* { dg-error "invalid for 64" "" } */ +__vector signed long vsl; /* { dg-error "invalid for 64" "" } */ +__vector __bool long int vbli; /* { dg-error "invalid for 64" "" } */ +__vector long int vli; /* { dg-error "invalid for 64" "" } */ +__vector unsigned long int vuli; /* { dg-error "invalid for 64" "" } */ +__vector signed long int vsli; /* { dg-error "invalid for 64" "" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-types-4.c b/gcc/testsuite/gcc.target/powerpc/altivec-types-4.c new file mode 100644 index 00000000000..bc2296cc15e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-types-4.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target powerpc*-*-linux* } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-maltivec -mno-warn-altivec-long" } */ + +/* These should not get warnings for 32-bit code when the warning is + disabled. */ + +__vector long vl; +__vector unsigned long vul; +__vector signed long vsl; +__vector __bool long int vbli; +__vector long int vli; +__vector unsigned long int vuli; +__vector signed long int vsli; diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-varargs-1.c b/gcc/testsuite/gcc.target/powerpc/altivec-varargs-1.c new file mode 100644 index 00000000000..135d3a9230f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-varargs-1.c @@ -0,0 +1,84 @@ +/* { dg-do run { target powerpc*-*-* } } */ +/* { dg-xfail-if "" { "powerpc-*-eabispe*" "powerpc-ibm-aix*" } { "-maltivec" } { "" } } */ +/* { dg-options "-maltivec -mabi=altivec -fno-inline" } */ + +#include <stdarg.h> +#include <signal.h> + +#include "altivec_check.h" + +#define vector __attribute__((vector_size (16))) + +const vector unsigned int v1 = {10,11,12,13}; +const vector unsigned int v2 = {20,21,22,23}; +const vector unsigned int v3 = {30,31,32,33}; +const vector unsigned int v4 = {40,41,42,43}; + +void foo(vector unsigned int a, ...) +{ + va_list args; + vector unsigned int v; + + va_start (args, a); + if (memcmp (&a, &v1, sizeof (v)) != 0) + abort (); + v = va_arg (args, vector unsigned int); + if (memcmp (&v, &v2, sizeof (v)) != 0) + abort (); + v = va_arg (args, vector unsigned int); + if (memcmp (&v, &v3, sizeof (v)) != 0) + abort (); + v = va_arg (args, vector unsigned int); + if (memcmp (&v, &v4, sizeof (v)) != 0) + abort (); + va_end (args); +} + +void bar(vector unsigned int a, ...) +{ + va_list args; + vector unsigned int v; + int b; + + va_start (args, a); + if (memcmp (&a, &v1, sizeof (v)) != 0) + abort (); + b = va_arg (args, int); + if (b != 2) + abort (); + v = va_arg (args, vector unsigned int); + if (memcmp (&v, &v2, sizeof (v)) != 0) + abort (); + v = va_arg (args, vector unsigned int); + if (memcmp (&v, &v3, sizeof (v)) != 0) + abort (); + va_end (args); +} + + +int main1(void) +{ + /* In this call, in the Darwin ABI, the first argument goes into v2 + the second one into r9-r10 and memory, + and the next two in memory. */ + foo ((vector unsigned int){10,11,12,13}, + (vector unsigned int){20,21,22,23}, + (vector unsigned int){30,31,32,33}, + (vector unsigned int){40,41,42,43}); + /* In this call, in the Darwin ABI, the first argument goes into v2 + the second one into r9, then r10 is reserved and + there are two words of padding in memory, and the next two arguments + go after the padding. */ + bar ((vector unsigned int){10,11,12,13}, 2, + (vector unsigned int){20,21,22,23}, + (vector unsigned int){30,31,32,33}); + return 0; +} + +int main (void) +{ + /* Exit on systems without AltiVec. */ + altivec_check (); + + return main1 (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c b/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c new file mode 100644 index 00000000000..19a682facea --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c @@ -0,0 +1,605 @@ +/* { dg-do run { target powerpc*-*-* } } */ +/* { dg-options "-maltivec -O2" } */ + +#include <altivec.h> +#include "altivec_check.h" + +int printf(const char * , ...); +extern void abort(); + +void foo(char *bS, char *bS_edge, int field_MBAFF, int top){ + char intra[16] __attribute__ ((aligned(16))); + signed short mv_const[8] __attribute__((aligned(16))); + + vector signed short v_three, v_ref_mask00, v_ref_mask01, v_vec_maskv, v_vec_maskh; + vector unsigned char v_permv, v_permh, v_bS, v_bSh, v_bSv, v_cbp_maskv, v_cbp_maskvn, v_cbp_maskh, v_cbp_maskhn, v_intra_maskh, v_intra_maskv, v_intra_maskhn, v_intra_maskvn; + vector unsigned char tmp7, tmp8, tmp9, tmp10, v_c1, v_cbp1, v_cbp2, v_pocl, v_poch; + vector signed short v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6; + vector signed short idx0; + vector signed short tmp00, tmp01, tmp02, tmp03; + vector unsigned char v_zero = (vector unsigned char) {'a','b','c','d','e','f','g','h','i','j','k','l','m','n','o','p'}; + v_three = (vector signed short) vec_ld (0, (vector signed short *) mv_const); + + vector unsigned char v_coef_mask = vec_ld(0, (vector unsigned char *)mv_const); + vector unsigned char v_coef_mask_hi = vec_splat(v_coef_mask, 0); + vector unsigned char v_coef_mask_lo = vec_splat(v_coef_mask, 1); + v_coef_mask = vec_sld(v_coef_mask_hi, v_coef_mask_lo, 8); + vector unsigned char v_bit_mask = vec_sub(vec_splat_u8(7), vec_lvsl(0, (unsigned char *)0)); + v_bit_mask = vec_sld(vec_sld(v_bit_mask, v_bit_mask, 8), v_bit_mask, 8); + v_bit_mask = vec_sl(vec_splat_u8(1), v_bit_mask); + tmp5 = (vector signed short) vec_and(v_coef_mask, v_bit_mask); + + intra[0] = 1; + tmp8 = vec_ld (0, (vector unsigned char *) intra); + tmp9 = vec_ld (0, (vector unsigned char *) mv_const); + tmp10 = vec_ld (0, (vector unsigned char *) mv_const); + v_permv = vec_ld (0, (vector unsigned char *) mv_const); + v_permh = vec_ld (0, (vector unsigned char *) mv_const); + tmp6 = vec_ld (0, (vector signed short *) mv_const); + + tmp8 = vec_splat((vector unsigned char) tmp8, 0); + tmp9 = vec_splat((vector unsigned char) tmp9, 12); + tmp10 = vec_splat((vector unsigned char) tmp10, 12); + tmp9 = vec_sld ((vector unsigned char) tmp9,(vector unsigned char) tmp8, 12); + tmp10 = vec_sld ((vector unsigned char) tmp10, (vector unsigned char) tmp8, 12); + v_intra_maskv = vec_or (tmp9, tmp8); + v_intra_maskh = vec_or (tmp10, tmp8); + v_intra_maskv = (vector unsigned char) vec_cmpgt ((vector unsigned char) v_intra_maskv, (vector unsigned char) v_zero); + v_intra_maskh = (vector unsigned char) vec_cmpgt ((vector unsigned char) v_intra_maskh, (vector unsigned char) v_zero); + + tmp9 = vec_lvsl (4 + (top<<2), (unsigned char *) 0x0); + v_cbp1 = vec_perm ((vector unsigned char) tmp6, (vector unsigned char) tmp6, tmp9); + v_cbp2 = (vector unsigned char) vec_perm ((vector unsigned char) tmp5, (vector unsigned char) tmp5, (vector unsigned char) v_permv); + v_cbp1 = (vector unsigned char) vec_sld ((vector unsigned char) v_cbp1,(vector unsigned char) v_cbp2, 12); + v_cbp_maskv = vec_or (v_cbp1, v_cbp2); + + tmp9 = vec_lvsl (12 + (top<<2), (unsigned char *) 0x0); + v_cbp1 = vec_perm ((vector unsigned char) tmp6, (vector unsigned char) tmp6, tmp9); + v_cbp2 = (vector unsigned char) vec_perm ((vector unsigned char) tmp5, (vector unsigned char) tmp5, (vector unsigned char) v_permh); + v_cbp1 = (vector unsigned char) vec_sld ((vector unsigned char) v_cbp1,(vector unsigned char) v_cbp2, 12); + v_cbp_maskh = vec_or (v_cbp1, v_cbp2); + + v_cbp_maskv = (vector unsigned char) vec_cmpgt ((vector unsigned char) v_cbp_maskv, (vector unsigned char) v_zero); + v_cbp_maskh = (vector unsigned char) vec_cmpgt ((vector unsigned char) v_cbp_maskh, (vector unsigned char) v_zero); + + intra[0] =0; + intra[1] =1; + intra[2] =2; + intra[3] =3; + intra[4] =4; + intra[5] = 5; + intra[6] =6; + intra[7] =7; + intra[8] =8; + intra[9] =9; + intra[10] =9; + intra[11] =9; + intra[12] = 0xff; + + idx0 = vec_ld (0, (signed short *) intra); + + v_c1 = (vector unsigned char) {'1','2','3','4','5','6','7','8','1','2','3','4','5','6','7','8'}; + + if (field_MBAFF){ + v0 = (vector signed short) vec_and ((vector unsigned char) idx0, v_c1); + idx0 = (vector signed short) vec_sra ((vector unsigned char) idx0, v_c1); + + v1 = vec_sld (v0, v0, 15); + v1 = (vector signed short) vec_pack (v1, v0); + + v2 = vec_sld (v1, v1, 2); + v3 = vec_sld (v1, v1, 10); + + v4 = (vector signed short) vec_cmpeq ((vector signed char) v1, (vector signed char) v2); + v5 = (vector signed short) vec_cmpeq ((vector signed char) v1, (vector signed char) v3); + v6 = (vector signed short) vec_cmpeq ((vector signed char) v2, (vector signed char) v3); + } + else { + v4 = v5 = v6 = vec_nor (v_zero, v_zero); + } + + tmp1 = (vector signed short) vec_sl ((vector unsigned char) idx0, v_c1); + v_c1 = vec_mergeh ((vector unsigned char) v_zero, v_c1); + tmp1 = (vector signed short) vec_add (tmp1, (vector signed short) v_c1); + + v_pocl = vec_ld (0, (vector unsigned char *) mv_const); + v_poch = vec_ld (0, (vector unsigned char *) mv_const); + tmp2 = (vector signed short) vec_perm (v_pocl, v_poch, (vector unsigned char) tmp1); + + v_pocl = vec_ld (0, (vector unsigned char *) mv_const); + v_poch = vec_ld (16, (vector unsigned char *) mv_const); + tmp1 = (vector signed short) vec_perm (v_pocl, v_poch, (vector unsigned char) tmp1); + tmp1 = vec_sel (tmp1, tmp2, (vector unsigned short) {0xffff,0xffff,0,0,0,0,0,0}); + + tmp3 = (vector signed short) vec_splat ((vector unsigned char) idx0, 12); + v_c1 = (vector unsigned char) vec_nor (v_zero, v_zero); + tmp0 = (vector signed short) vec_cmpeq ((vector signed char) idx0, (vector signed char) v_c1); + tmp1 = vec_sel (tmp1, (vector signed short) tmp3, (vector unsigned short) tmp0); + + tmp2 = vec_sld (tmp1, tmp1, 15); + tmp1 = (vector signed short) vec_pack (tmp2, tmp1); + + tmp2 = vec_sld (tmp1, tmp1, 2); + tmp3 = vec_sld (tmp1, tmp1, 10); + + tmp0 = (vector signed short) vec_cmpeq ((vector signed char) tmp1, (vector signed char) tmp2); + tmp4 = (vector signed short) vec_cmpeq ((vector signed char) tmp1, (vector signed char) tmp3); + tmp1 = (vector signed short) vec_cmpeq ((vector signed char) tmp2, (vector signed char) tmp3); + tmp0 = vec_and (tmp0, v4); + tmp4 = vec_and (tmp4, v5); + tmp1 = vec_and (tmp1, v6); + tmp2 = vec_sld ((vector signed short) tmp0, (vector signed short) tmp0, 8); + tmp3 = vec_sld ((vector signed short) tmp4, (vector signed short) tmp4, 8); + tmp5 = vec_sld ((vector signed short) tmp1, (vector signed short) tmp1, 8); + tmp0 = vec_and (tmp0, tmp2); + tmp4 = vec_and (tmp4, tmp3); + tmp1 = vec_and (tmp1, tmp5); + v_ref_mask00 = vec_mergeh ((vector signed short) tmp0, (vector signed short) v_c1); + v_ref_mask01 = vec_mergeh ((vector signed short) tmp4, (vector signed short) tmp1); + v_ref_mask00 = (vector signed short) vec_mergeh ((vector unsigned char) v_ref_mask00, (vector unsigned char) v_ref_mask00); + v_ref_mask01 = (vector signed short) vec_mergeh ((vector unsigned char) v_ref_mask01, (vector unsigned char) v_ref_mask01); + + v0 = vec_ld (0, (vector signed short *) mv_const); + v1 = vec_ld (16, (vector signed short *) mv_const); + v4 = vec_ld (64, (vector signed short *) mv_const); + v5 = vec_ld (80, (vector signed short *) mv_const); + v8 = vec_ld (0, (vector signed short *) mv_const); + v9 = vec_ld (16, (vector signed short *) mv_const); + + tmp0 = (vector signed short) vec_perm ((vector unsigned char) v8, + (vector unsigned char) v8, (vector unsigned char) {0,1,2,3,8,9,10,11,4,5,6,7,12,13,14,15}); + tmp1 = (vector signed short) vec_mergeh ((vector signed int) v0, (vector signed int) v1); + tmp2 = vec_sld (tmp1, tmp1, 8); + tmp3 = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1)); + tmp4 = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2)); + tmp3 = (vector signed short) vec_cmpgt (tmp3, v_three); + tmp4 = (vector signed short) vec_cmpgt (tmp4, v_three); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + tmp0 = (vector signed short) vec_perm ((vector unsigned char) v9, (vector unsigned char) v9, + (vector unsigned char) {0,1,2,3,8,9,10,11,4,5,6,7,12,13,14,15}); + tmp1 = (vector signed short) vec_mergeh ((vector signed int) v4, (vector signed int) v5); + tmp2 = vec_sld (tmp1, tmp1, 8); + tmp5 = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1)); + tmp6 = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2)); + tmp5 = (vector signed short) vec_cmpgt (tmp5, v_three); + tmp6 = (vector signed short) vec_cmpgt (tmp6, v_three); + tmp0 = vec_sld (tmp5, tmp5, 14); + tmp1 = vec_sld (tmp6, tmp6, 14); + tmp5 = vec_or (tmp0, tmp5); + tmp6 = vec_or (tmp1, tmp6); + + tmp3 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5); + tmp4 = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6); + tmp5 = vec_sld (tmp3, tmp3, 12); + tmp6 = vec_sld (tmp4, tmp4, 12); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + tmp00 = (vector signed short) vec_pack ((vector unsigned short) tmp3, (vector unsigned short) tmp4); + + tmp0 = (vector signed short) vec_mergeh ((vector signed int) v0, (vector signed int) v1); + tmp1 = (vector signed short) vec_mergel ((vector signed int) v0, (vector signed int) v1); + tmp2 = vec_sld (tmp1, tmp1, 8); + tmp3 = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1)); + tmp4 = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2)); + tmp3 = (vector signed short) vec_cmpgt (tmp3, v_three); + tmp4 = (vector signed short) vec_cmpgt (tmp4, v_three); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + + tmp0 = (vector signed short) vec_mergeh ((vector signed int) v4, (vector signed int) v5); + tmp1 = (vector signed short) vec_mergel ((vector signed int) v4, (vector signed int) v5); + tmp2 = vec_sld (tmp1, tmp1, 8); + tmp5 = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1)); + tmp6 = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2)); + tmp5 = (vector signed short) vec_cmpgt (tmp5, v_three); + tmp6 = (vector signed short) vec_cmpgt (tmp6, v_three); + tmp0 = vec_sld (tmp5, tmp5, 14); + tmp1 = vec_sld (tmp6, tmp6, 14); + tmp5 = vec_or (tmp0, tmp5); + tmp6 = vec_or (tmp1, tmp6); + + tmp3 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5); + tmp4 = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6); + tmp5 = vec_sld (tmp3, tmp3, 12); + tmp6 = vec_sld (tmp4, tmp4, 12); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + tmp01 = (vector signed short) vec_pack ((vector unsigned short) tmp3, (vector unsigned short) tmp4); + + v2 = vec_ld (32, (vector signed short *) mv_const); + v3 = vec_ld (48, (vector signed short *) mv_const); + v6 = vec_ld (96, (vector signed short *) mv_const); + v7 = vec_ld (112,(vector signed short *) mv_const); + + tmp0 = (vector signed short) vec_mergel ((vector signed int) v0, (vector signed int) v1); + tmp1 = (vector signed short) vec_mergeh ((vector signed int) v2, (vector signed int) v3); + tmp2 = vec_sld (tmp1, tmp1, 8); + tmp3 = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1)); + tmp4 = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2)); + tmp3 = (vector signed short) vec_cmpgt (tmp3, v_three); + tmp4 = (vector signed short) vec_cmpgt (tmp4, v_three); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + + tmp0 = (vector signed short) vec_mergel ((vector signed int) v4, (vector signed int) v5); + tmp1 = (vector signed short) vec_mergeh ((vector signed int) v6, (vector signed int) v7); + tmp2 = vec_sld (tmp1, tmp1, 8); + tmp5 = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1)); + tmp6 = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2)); + tmp5 = (vector signed short) vec_cmpgt (tmp5, v_three); + tmp6 = (vector signed short) vec_cmpgt (tmp6, v_three); + tmp0 = vec_sld (tmp5, tmp5, 14); + tmp1 = vec_sld (tmp6, tmp6, 14); + tmp5 = vec_or (tmp0, tmp5); + tmp6 = vec_or (tmp1, tmp6); + + tmp3 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5); + tmp4 = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6); + tmp5 = vec_sld (tmp3, tmp3, 12); + tmp6 = vec_sld (tmp4, tmp4, 12); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + tmp02 = (vector signed short) vec_pack ((vector unsigned short) tmp3, (vector unsigned short) tmp4); + + tmp0 = (vector signed short) vec_mergeh ((vector signed int) v2, (vector signed int) v3); + tmp1 = (vector signed short) vec_mergel ((vector signed int) v2, (vector signed int) v3); + tmp2 = vec_sld (tmp1, tmp1, 8); + tmp3 = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1)); + tmp4 = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2)); + tmp3 = (vector signed short) vec_cmpgt (tmp3, v_three); + tmp4 = (vector signed short) vec_cmpgt (tmp4, v_three); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + + tmp0 = (vector signed short) vec_mergeh ((vector signed int) v6, (vector signed int) v7); + tmp1 = (vector signed short) vec_mergel ((vector signed int) v6, (vector signed int) v7); + tmp2 = vec_sld (tmp1, tmp1, 8); + tmp5 = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1)); + tmp6 = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2)); + tmp5 = (vector signed short) vec_cmpgt (tmp5, v_three); + tmp6 = (vector signed short) vec_cmpgt (tmp6, v_three); + tmp0 = vec_sld (tmp5, tmp5, 14); + tmp1 = vec_sld (tmp6, tmp6, 14); + tmp5 = vec_or (tmp0, tmp5); + tmp6 = vec_or (tmp1, tmp6); + + tmp3 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5); + tmp4 = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6); + tmp5 = vec_sld (tmp3, tmp3, 12); + tmp6 = vec_sld (tmp4, tmp4, 12); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + tmp03 = (vector signed short) vec_pack ((vector unsigned short) tmp3, (vector unsigned short) tmp4); + + tmp0 = (vector signed short) vec_pack ((vector unsigned int) tmp00, (vector unsigned int) tmp01); + tmp1 = (vector signed short) vec_pack ((vector unsigned int) tmp02, (vector unsigned int) tmp03); + tmp2 = (vector signed short) vec_mergeh ((vector signed int) tmp0, (vector signed int) tmp1); + tmp3 = (vector signed short) vec_mergel ((vector signed int) tmp0, (vector signed int) tmp1); + tmp4 = (vector signed short) vec_mergeh ((vector signed int) tmp2, (vector signed int) tmp3); + tmp5 = (vector signed short) vec_mergel ((vector signed int) tmp2, (vector signed int) tmp3); + tmp4 = vec_and (v_ref_mask00, tmp4); + tmp5 = vec_and (v_ref_mask01, tmp5); + + tmp0 = vec_nor (v_ref_mask00, v_ref_mask01); + tmp1 = vec_and (v_ref_mask00, v_ref_mask01); + tmp2 = vec_and (tmp4, tmp5); + tmp2 = vec_and (tmp2, tmp1); + tmp3 = vec_nor (tmp4, tmp5); + tmp3 = vec_nor (tmp3, tmp1); + v_vec_maskv = vec_or (tmp0, tmp2); + v_vec_maskv = vec_or (v_vec_maskv, tmp3); + + intra[0] = 1; + intra[1] = 1; + intra[2] = 2; + intra[3] = 3; + intra[4] = 2; + intra[5] = 2; + intra[6] = 2; + intra[7] = 1; + intra[8] = 1; + intra[9] = 5; + intra[10] = 5; + intra[11] = 5; + + intra[13] = 0; + intra[14] = 0; + intra[15] = 0; + + idx0 = vec_ld (0, (signed short *) intra); + + v_c1 = (vector unsigned char) {'1','2','3','4','5','6','7','8','1','2','3','4','5','6','7','8'}; + + if (field_MBAFF){ + v8 = (vector signed short) vec_and ((vector unsigned char) idx0, v_c1); + idx0 = (vector signed short) vec_sra ((vector unsigned char) idx0, v_c1); + + v9 = vec_sld (v8, v8, 15); + v9 = (vector signed short) vec_pack (v9, v8); + + v10 = vec_sld (v9, v9, 2); + v11 = vec_sld (v9, v9, 10); + + v8 = (vector signed short) vec_cmpeq ((vector signed char) v9, (vector signed char) v10); + v9 = (vector signed short) vec_cmpeq ((vector signed char) v9, (vector signed char) v11); + v10 = (vector signed short) vec_cmpeq ((vector signed char) v10, (vector signed char) v11); + } + else { + v8 = v9 = v10 = vec_nor (v_zero, v_zero); + } + + tmp1 = (vector signed short) vec_sl ((vector unsigned char) idx0, v_c1); + +if (1){ + int m; + unsigned char toto2[16] __attribute__((aligned(16))); + + printf("vc1\n"); + vec_st(v_c1, 0, (unsigned char *) toto2); + for (m=0; m<16;m++) {printf("%c ", toto2[m]);} + + printf("\nv_zero\n"); + + vec_st (v_zero, 0, (unsigned char *) toto2); + for (m=0; m< 16; m++) {printf("%c ", toto2[m]);} + printf("\n"); +} + + v_c1 = vec_mergeh ((vector unsigned char) v_zero, v_c1); + tmp1 = (vector signed short) vec_add (tmp1, (vector signed short) v_c1); + +if (1){ + vector unsigned char vres = + (vector unsigned char){'a','1','b','2','c','3','d','4','e','5','f','6','g','7','h','8'}; + unsigned char toto2[16] __attribute__((aligned(16))); + int m; + + printf("vc1\n"); + vec_st(v_c1, 0, (unsigned char *) toto2); + for (m=0; m<16;m++) {printf("%c ", toto2[m]);} + printf("\n"); + if (!vec_all_eq (vres, v_c1)) + abort(); +} + + v_pocl = vec_ld (32, (vector unsigned char *) mv_const); + v_poch = vec_ld (48, (vector unsigned char *) mv_const); + tmp2 = (vector signed short) vec_perm (v_pocl, v_poch, (vector unsigned char) tmp1); + + v_pocl = vec_ld (0, (vector unsigned char *) mv_const); + v_poch = vec_ld (16, (vector unsigned char *) mv_const); + + tmp1 = (vector signed short) vec_perm (v_pocl, v_poch, (vector unsigned char) tmp1); + + tmp1 = vec_sel (tmp1, tmp2, (vector unsigned short) {0xffff,0xffff,0,0,0,0,0,0}); + + + tmp3 = (vector signed short) vec_splat ((vector unsigned char) idx0, 12); + v_c1 = (vector unsigned char) vec_nor (v_zero, v_zero); + tmp0 = (vector signed short) vec_cmpeq ((vector signed char) idx0, (vector signed char) v_c1); + tmp1 = vec_sel (tmp1, (vector signed short) tmp3, (vector unsigned short) tmp0); + + tmp2 = vec_sld (tmp1, tmp1, 15); + tmp1 = (vector signed short) vec_pack (tmp2, tmp1); + + + tmp2 = vec_sld (tmp1, tmp1, 2); + tmp3 = vec_sld (tmp1, tmp1, 10); + + tmp0 = (vector signed short) vec_cmpeq ((vector signed char) tmp1, (vector signed char) tmp2); + tmp4 = (vector signed short) vec_cmpeq ((vector signed char) tmp1, (vector signed char) tmp3); + tmp1 = (vector signed short) vec_cmpeq ((vector signed char) tmp2, (vector signed char) tmp3); + tmp0 = vec_and (tmp0, v8); + tmp4 = vec_and (tmp4, v9); + tmp1 = vec_and (tmp1, v10); + tmp2 = vec_sld ((vector signed short) tmp0, (vector signed short) tmp0, 8); + tmp3 = vec_sld ((vector signed short) tmp4, (vector signed short) tmp4, 8); + tmp5 = vec_sld ((vector signed short) tmp1, (vector signed short) tmp1, 8); + tmp0 = vec_and (tmp0, tmp2); + tmp4 = vec_and (tmp4, tmp3); + tmp1 = vec_and (tmp1, tmp5); + v_ref_mask00 = vec_mergeh ((vector signed short) tmp0, (vector signed short) v_c1); + v_ref_mask01 = vec_mergeh ((vector signed short) tmp4, (vector signed short) tmp1); + v_ref_mask00 = (vector signed short) vec_mergeh ((vector unsigned char) v_ref_mask00, (vector unsigned char) v_ref_mask00); + v_ref_mask01 = (vector signed short) vec_mergeh ((vector unsigned char) v_ref_mask01, (vector unsigned char) v_ref_mask01); + + + v_permv= vec_ld (0, (vector unsigned char *) mv_const); + v8 = vec_ld (0, (vector signed short *) mv_const); + v9 = vec_ld (16, (vector signed short *) mv_const); + tmp2 = vec_perm (v0, v0, v_permv); + tmp3 = vec_sub (vec_max (v8, v0), vec_min (v8, v0)); + tmp4 = vec_sub (vec_max (v8, tmp2), vec_min (v8, tmp2)); + tmp3 = (vector signed short) vec_cmpgt (tmp3, v_three); + tmp4 = (vector signed short) vec_cmpgt (tmp4, v_three); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + + tmp2 = vec_perm (v2, v2, v_permv); + tmp5 = vec_sub (vec_max (v9, v2), vec_min (v9, v2)); + tmp6 = vec_sub (vec_max (v9, tmp2), vec_min (v9, tmp2)); + tmp5 = (vector signed short) vec_cmpgt (tmp5, v_three); + tmp6 = (vector signed short) vec_cmpgt (tmp6, v_three); + tmp0 = vec_sld (tmp5, tmp5, 14); + tmp1 = vec_sld (tmp6, tmp6, 14); + tmp5 = vec_or (tmp0, tmp5); + tmp6 = vec_or (tmp1, tmp6); + + tmp3 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5); + tmp4 = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + tmp00 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp4); + + tmp2 = vec_perm (v1, v1, v_permv); + tmp3 = vec_sub (vec_max (v0, v1), vec_min (v0, v1)); + tmp4 = vec_sub (vec_max (v0, tmp2), vec_min (v0, tmp2)); + tmp3 = (vector signed short) vec_cmpgt (tmp3, v_three); + tmp4 = (vector signed short) vec_cmpgt (tmp4, v_three); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + + tmp2 = vec_perm (v3, v3, v_permv); + tmp5 = vec_sub (vec_max (v2, v3), vec_min (v2, v3)); + tmp6 = vec_sub (vec_max (v2, tmp2), vec_min (v2, tmp2)); + tmp5 = (vector signed short) vec_cmpgt (tmp5, v_three); + tmp6 = (vector signed short) vec_cmpgt (tmp6, v_three); + tmp0 = vec_sld (tmp5, tmp5, 14); + tmp1 = vec_sld (tmp6, tmp6, 14); + tmp5 = vec_or (tmp0, tmp5); + tmp6 = vec_or (tmp1, tmp6); + + tmp3 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5); + tmp4 = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + tmp01 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp4); + + tmp2 = vec_perm (v4, v4, v_permv); + tmp3 = vec_sub (vec_max (v1, v4), vec_min (v1, v4)); + tmp4 = vec_sub (vec_max (v1, tmp2), vec_min (v1, tmp2)); + tmp3 = (vector signed short) vec_cmpgt (tmp3, v_three); + tmp4 = (vector signed short) vec_cmpgt (tmp4, v_three); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + + tmp2 = vec_perm (v6, v6, v_permv); + tmp5 = vec_sub (vec_max (v3, v6), vec_min (v3, v6)); + tmp6 = vec_sub (vec_max (v3, tmp2), vec_min (v3, tmp2)); + tmp5 = (vector signed short) vec_cmpgt (tmp5, v_three); + tmp6 = (vector signed short) vec_cmpgt (tmp6, v_three); + tmp0 = vec_sld (tmp5, tmp5, 14); + tmp1 = vec_sld (tmp6, tmp6, 14); + tmp5 = vec_or (tmp0, tmp5); + tmp6 = vec_or (tmp1, tmp6); + + tmp3 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5); + tmp4 = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + tmp02 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp4); + + + tmp2 = vec_perm (v5, v5, v_permv); + tmp3 = vec_sub (vec_max (v4, v5), vec_min (v4, v5)); + tmp4 = vec_sub (vec_max (v4, tmp2), vec_min (v4, tmp2)); + tmp3 = (vector signed short) vec_cmpgt (tmp3, v_three); + tmp4 = (vector signed short) vec_cmpgt (tmp4, v_three); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + + tmp2 = vec_perm (v7, v7, v_permv); + tmp5 = vec_sub (vec_max (v6, v7), vec_min (v6, v7)); + tmp6 = vec_sub (vec_max (v6, tmp2), vec_min (v6, tmp2)); + tmp5 = (vector signed short) vec_cmpgt (tmp5, v_three); + tmp6 = (vector signed short) vec_cmpgt (tmp6, v_three); + tmp0 = vec_sld (tmp5, tmp5, 14); + tmp1 = vec_sld (tmp6, tmp6, 14); + tmp5 = vec_or (tmp0, tmp5); + tmp6 = vec_or (tmp1, tmp6); + + tmp3 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5); + tmp4 = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + tmp03 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp4); + + tmp0 = (vector signed short) vec_pack ((vector unsigned short) tmp00, (vector unsigned short) tmp01); + tmp1 = (vector signed short) vec_pack ((vector unsigned short) tmp02, (vector unsigned short) tmp03); + tmp2 = (vector signed short) vec_mergeh ((vector signed int) tmp0, (vector signed int) tmp1); + tmp3 = (vector signed short) vec_mergel ((vector signed int) tmp0, (vector signed int) tmp1); + tmp4 = (vector signed short) vec_mergeh ((vector signed int) tmp2, (vector signed int) tmp3); + tmp5 = (vector signed short) vec_mergel ((vector signed int) tmp2, (vector signed int) tmp3); + tmp4 = vec_and (v_ref_mask00, tmp4); + tmp5 = vec_and (v_ref_mask01, tmp5); + + tmp0 = vec_nor (v_ref_mask00, v_ref_mask01); + tmp1 = vec_and (v_ref_mask00, v_ref_mask01); + tmp2 = vec_and (tmp4, tmp5); + tmp2 = vec_and (tmp2, tmp1); + tmp3 = vec_nor (tmp4, tmp5); + tmp3 = vec_nor (tmp3, tmp1); + v_vec_maskh = vec_or (tmp0, tmp2); + v_vec_maskh = vec_or (v_vec_maskh, tmp3); + + + v_intra_maskvn = vec_nor (v_intra_maskv, v_intra_maskv); + v_intra_maskhn = vec_nor (v_intra_maskh, v_intra_maskh); + v_cbp_maskvn = (vector unsigned char) vec_cmpeq ((vector unsigned char) v_cbp_maskv, (vector unsigned char) v_zero); + v_cbp_maskhn = (vector unsigned char) vec_cmpeq ((vector unsigned char) v_cbp_maskh, (vector unsigned char) v_zero); + + v_cbp_maskv = vec_and (v_cbp_maskv, v_intra_maskvn); + v_cbp_maskh = vec_and (v_cbp_maskh, v_intra_maskhn); + v_vec_maskv = vec_and (v_vec_maskv, (vector signed short) v_intra_maskvn); + v_vec_maskv = vec_and (v_vec_maskv, (vector signed short) v_cbp_maskvn); + v_vec_maskh = vec_and (v_vec_maskh, (vector signed short) v_intra_maskhn); + v_vec_maskh = vec_and (v_vec_maskh, (vector signed short) v_cbp_maskhn); + + tmp9 = vec_splat_u8(2); + tmp8 = vec_splat_u8(1); + v_bS = vec_ld (0, (vector unsigned char *) mv_const); + + v_bSv = vec_and ((vector unsigned char) v_bS, (vector unsigned char)v_intra_maskv); + tmp7 = vec_and ((vector unsigned char)tmp9, (vector unsigned char)v_cbp_maskv); + tmp6 = (vector signed short) vec_and ((vector unsigned char)tmp8, (vector unsigned char)v_vec_maskv); + tmp7 = vec_or ((vector unsigned char)tmp7, (vector unsigned char)tmp6); + v_bSv = vec_or ((vector unsigned char)tmp7, (vector unsigned char)v_bSv); + + v_bS = vec_ld (0, (vector unsigned char *) mv_const); + v_bSh = vec_and ((vector unsigned char) v_bS, (vector unsigned char)v_intra_maskh); + tmp7 = vec_and ((vector unsigned char)tmp9, (vector unsigned char)v_cbp_maskh); + tmp6 = (vector signed short) vec_and ((vector unsigned char)tmp8, (vector unsigned char)v_vec_maskh); + tmp7 = vec_or ((vector unsigned char)tmp7, (vector unsigned char)tmp6); + v_bSh = vec_or ((vector unsigned char)tmp7, (vector unsigned char)v_bSh); + + v_permh = (vector unsigned char) vec_ld (0 , (vector unsigned char *) mv_const); + v_permv = (vector unsigned char) vec_ld (0, (vector unsigned char *) mv_const); + v_bSv = vec_and (v_bSv, v_permv); + v_bSh = vec_and (v_bSh, v_permh); + + vec_st (v_bSv, 0, (unsigned char *) mv_const); + vec_st (v_bSh, 0, (unsigned char *) mv_const); + + v_bSv = vec_mergeh (v_bSv, v_bSv); + v_bSv = vec_mergeh (v_bSv, v_bSv); + v_bSh = vec_mergeh (v_bSh, v_bSh); + v_bSh = vec_mergeh (v_bSh, v_bSh); + + vec_st (v_bSv, 0, (vector unsigned char *) mv_const); + vec_st (v_bSh, 0,(vector unsigned char *) mv_const); +} + + +int main(int argc, char **argv) +{ + char toto[32] __attribute__((aligned(16))); + + altivec_check (); /* Exit if hardware doesn't support AltiVec. */ + foo(toto, toto, 0, 0); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/altivec_check.h b/gcc/testsuite/gcc.target/powerpc/altivec_check.h new file mode 100644 index 00000000000..736054821f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/altivec_check.h @@ -0,0 +1,24 @@ +/* A runtime check for AltiVec capability. */ +/* Contributed by Ziemowit Laski <zlaski@apple.com> */ + +#include <signal.h> +extern void exit (int); +extern void abort (void); + +void +sig_ill_handler (int sig) +{ + exit (0); +} + +void altivec_check(void) { + + /* Exit on systems without AltiVec. */ + signal (SIGILL, sig_ill_handler); +#ifdef __MACH__ + asm volatile ("vor v0,v0,v0"); +#else + asm volatile ("vor 0,0,0"); +#endif + signal (SIGILL, SIG_DFL); +} diff --git a/gcc/testsuite/gcc.target/powerpc/compress-float-ppc-pic.c b/gcc/testsuite/gcc.target/powerpc/compress-float-ppc-pic.c new file mode 100644 index 00000000000..2f67d6962f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/compress-float-ppc-pic.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-O2 -fpic" } */ +double foo (double x) { + return x + 1.75; +} +/* { dg-final { scan-assembler "lfs" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/compress-float-ppc.c b/gcc/testsuite/gcc.target/powerpc/compress-float-ppc.c new file mode 100644 index 00000000000..e3f443ec80e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/compress-float-ppc.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-O2" } */ +double foo (double x) { + return x + 1.75; +} +/* { dg-final { scan-assembler "lfs" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-abi-1.c b/gcc/testsuite/gcc.target/powerpc/darwin-abi-1.c new file mode 100644 index 00000000000..3b13c6236b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darwin-abi-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-options "-O" } */ +/* { dg-final { scan-assembler "li r3,12345\n\t(bl|jbsr) " } } */ + +/* Check that zero-size structures don't affect parameter passing. */ + +struct empty { }; +extern void foo (struct empty e, int a); +void bar (void) { + struct empty e; + foo (e, 12345); +} diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-abi-2.c b/gcc/testsuite/gcc.target/powerpc/darwin-abi-2.c new file mode 100644 index 00000000000..4764831e847 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darwin-abi-2.c @@ -0,0 +1,24 @@ +/* { dg-do run { target powerpc*-*-darwin* } } */ + +/* You might think you'd need -maltivec for this, but actually you + don't; GCC will happily do everything in GPRs, and it still + tests that the ABI is correct. */ + +#include <stdio.h> +#include <stdlib.h> + +#define vector __attribute__((vector_size(16))) + +int main(void) +{ + vector unsigned int v = { 100, 200, 300, 400 }; + vector unsigned int w = { 4, 5, 6, 7 }; + char x[64]; + sprintf (x, "%lvu,%d,%lvu", v, 1, w); + if (strcmp (x, "100 200 300 400,1,4 5 6 7") != 0) + { + puts (x); + abort (); + } + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-bool-1.c b/gcc/testsuite/gcc.target/powerpc/darwin-bool-1.c new file mode 100644 index 00000000000..ef1e98b6ef2 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darwin-bool-1.c @@ -0,0 +1,11 @@ +/* Check that sizeof(bool) is 4 if we don't use special options. */ +/* Matt Austern <austern@apple.com> */ +/* { dg-do run { target powerpc*-*-darwin* } } */ + +int dummy1[sizeof(_Bool) - 3]; +int dummy2[5 - sizeof(_Bool)]; + +int main() +{ + return sizeof(_Bool) == 4 ? 0 : 1; +} diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-bool-2.c b/gcc/testsuite/gcc.target/powerpc/darwin-bool-2.c new file mode 100644 index 00000000000..fdbe1a2a4b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darwin-bool-2.c @@ -0,0 +1,12 @@ +/* Check that sizeof(bool) is 1 if we use the -mone-byte-bool option. */ +/* Matt Austern <austern@apple.com> */ +/* { dg-do run { target powerpc*-*-darwin* } } */ +/* { dg-options "-mone-byte-bool" } */ + +int dummy1[sizeof(_Bool)]; +int dummy2[2 - sizeof(_Bool)]; + +int main() +{ + return sizeof(_Bool) == 1 ? 0 : 1; +} diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-longdouble.c b/gcc/testsuite/gcc.target/powerpc/darwin-longdouble.c new file mode 100644 index 00000000000..8e4259af350 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darwin-longdouble.c @@ -0,0 +1,119 @@ +/* { dg-do run { target powerpc*-*-darwin* } } */ +/* { dg-options "" } */ +/* No options so 'long long' can be used. */ + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> + +typedef unsigned long long uint64_t; +typedef uint64_t ldbits[2]; + +union ldu +{ + ldbits lb; + long double ld; +}; + +static const struct { + ldbits a; + ldbits b; + ldbits result; +} single_tests[] = { + /* Test of values that add to near +Inf. */ + { { 0x7FEFFFFFFFFFFFFFLL, 0xFC88000000000000LL }, + { 0x7C94000000000000LL, 0x0000000000000000LL }, + { 0x7FEFFFFFFFFFFFFFLL, 0x7C80000000000000LL } }, + { { 0x7FEFFFFFFFFFFFFFLL, 0x7C8FFFFFFFFFFFFFLL }, + { 0x792FFFFFFFFFFFFFLL, 0x0000000000000000LL }, + { 0x7FEFFFFFFFFFFFFFLL, 0x7C8FFFFFFFFFFFFFLL } }, + { { 0x7FEFFFFFFFFFFFFFLL, 0x7C8FFFFFFFFFFFFFLL }, + { 0x7930000000000000LL, 0xF5DFFFFFFFFFFFFFLL }, + /* correct result is: { 0x7FEFFFFFFFFFFFFFLL, 0x7C8FFFFFFFFFFFFFLL } */ + { 0x7FF0000000000000LL, 0x0000000000000000LL } }, + /* Test of values that add to +Inf. */ + { { 0x7FEFFFFFFFFFFFFFLL, 0x7C8FFFFFFFFFFFFFLL }, + { 0x7930000000000000LL, 0x0000000000000000LL }, + { 0x7FF0000000000000LL, 0x0000000000000000LL } }, + /* Tests of Inf addition. */ + { { 0x7FF0000000000000LL, 0x0000000000000000LL }, + { 0x0000000000000000LL, 0x0000000000000000LL }, + { 0x7FF0000000000000LL, 0x0000000000000000LL } }, + { { 0x7FF0000000000000LL, 0x0000000000000000LL }, + { 0x7FF0000000000000LL, 0x0000000000000000LL }, + { 0x7FF0000000000000LL, 0x0000000000000000LL } }, + /* Test of Inf addition producing NaN. */ + { { 0x7FF0000000000000LL, 0x0000000000000000LL }, + { 0xFFF0000000000000LL, 0x0000000000000000LL }, + { 0x7FF8000000000000LL, 0x0000000000000000LL } }, + /* Tests of NaN addition. */ + { { 0x7FF8000000000000LL, 0x0000000000000000LL }, + { 0x0000000000000000LL, 0x0000000000000000LL }, + { 0x7FF8000000000000LL, 0x7FF8000000000000LL } }, + { { 0x7FF8000000000000LL, 0x0000000000000000LL }, + { 0x7FF0000000000000LL, 0x0000000000000000LL }, + { 0x7FF8000000000000LL, 0x7FF8000000000000LL } }, + /* Addition of positive integers, with interesting rounding properties. */ + { { 0x4690000000000000LL, 0x4330000000000000LL }, + { 0x4650000000000009LL, 0xC2FFFFFFFFFFFFF2LL }, + /* correct result is: { 0x4691000000000001LL, 0xC32C000000000000LL } */ + { 0x4691000000000001LL, 0xc32bfffffffffffeLL } }, + { { 0x4690000000000000LL, 0x4330000000000000LL }, + { 0x4650000000000008LL, 0x42F0000000000010LL }, + { 0x4691000000000001LL, 0xC32E000000000000LL } }, + { { 0x469FFFFFFFFFFFFFLL, 0x433FFFFFFFFFFFFFLL }, + { 0x4340000000000000LL, 0x3FF0000000000000LL }, + { 0x46A0000000000000LL, 0x0000000000000000LL } }, + { { 0x469FFFFFFFFFFFFFLL, 0x433FFFFFFFFFFFFFLL }, + { 0x4340000000000000LL, 0x0000000000000000LL }, + { 0x46A0000000000000LL, 0xBFF0000000000000LL } }, + /* Subtraction of integers, with cancellation. */ + { { 0x4690000000000000LL, 0x4330000000000000LL }, + { 0xC690000000000000LL, 0xC330000000000000LL }, + { 0x0000000000000000LL, 0x0000000000000000LL } }, + { { 0x4690000000000000LL, 0x4330000000000000LL }, + { 0xC330000000000000LL, 0x0000000000000000LL }, + { 0x4690000000000000LL, 0x0000000000000000LL } }, + { { 0x4690000000000000LL, 0x4330000000000000LL }, + { 0xC330000000000000LL, 0x3FA0000000000000LL }, + { 0x4690000000000000LL, 0x3FA0000000000000LL } }, + { { 0x4690000000000000LL, 0x4330000000000000LL }, + { 0xC690000000000000LL, 0x3FA0000000000000LL }, + /* correct result is: { 0x4330000000000000LL, 0x3FA0000000000000LL } */ + { 0x4330000000000000LL, 0x0000000000000000LL } } +}; + +static int fail = 0; + +static void +run_single_tests (void) +{ + size_t i; + for (i = 0; i < sizeof (single_tests) / sizeof (single_tests[0]); i++) + { + union ldu a, b, result, expected; + memcpy (a.lb, single_tests[i].a, sizeof (ldbits)); + memcpy (b.lb, single_tests[i].b, sizeof (ldbits)); + memcpy (expected.lb, single_tests[i].result, sizeof (ldbits)); + result.ld = a.ld + b.ld; + if (memcmp (result.lb, expected.lb, + result.ld == result.ld ? sizeof (ldbits) : sizeof (double)) + != 0) + { + printf ("FAIL: %016llx %016llx + %016llx %016llx\n", + a.lb[0], a.lb[1], b.lb[0], b.lb[1]); + printf (" = %016llx %016llx not %016llx %016llx\n", + result.lb[0], result.lb[1], expected.lb[0], expected.lb[1]); + fail = 1; + } + } +} + +int main(void) +{ + run_single_tests(); + if (fail) + abort (); + else + exit (0); +} diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c b/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c new file mode 100644 index 00000000000..b9392c0c37b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c @@ -0,0 +1,40 @@ +/* { dg-do run { target powerpc*-*-* } } */ +/* { dg-xfail-if "" { "powerpc-*-eabispe*" "powerpc-ibm-aix*" } { "-mcpu=G5" } { "" } } */ +/* { dg-options "-mcpu=G5" } */ + +#include <signal.h> +#include <stdlib.h> + +void +sig_ill_handler (int sig) +{ + exit(0); +} + + +int msw(long long in) +{ + union { + long long ll; + int i[2]; + } ud; + ud.ll = in; + return ud.i[0]; +} + +int main() +{ + + /* Exit on systems without 64bit instructions. */ + signal (SIGILL, sig_ill_handler); +#ifdef __MACH__ + asm volatile ("extsw r0,r0"); +#else + asm volatile ("extsw 0,0"); +#endif + signal (SIGILL, SIG_DFL); + + if (msw(1) != 0) + abort(); + exit(0); +} diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-misaligned.c b/gcc/testsuite/gcc.target/powerpc/darwin-misaligned.c new file mode 100644 index 00000000000..9e53b7b2224 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/darwin-misaligned.c @@ -0,0 +1,32 @@ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-options "-O2 -mpowerpc64" } */ + +typedef struct Nlm_rect { + short sh1; + short sh2; + short sh3; + short sh4; +} S8; + +typedef struct udv_mouse_select { + short Action_type; + S8 rcClip; + int pgp; + } UDVselect; + +UDVselect ms; +int UDV(S8 rcClip); + +int main() +{ + ms.rcClip.sh1 = 1; + ms.rcClip.sh4 = 4; + return UDV(ms.rcClip); +} + +int UDV(S8 rcClip){ + + return !(rcClip.sh1 == 1 && rcClip.sh4 == 4); +} + + diff --git a/gcc/testsuite/gcc.target/powerpc/doloop-1.c b/gcc/testsuite/gcc.target/powerpc/doloop-1.c new file mode 100644 index 00000000000..036239969e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/doloop-1.c @@ -0,0 +1,17 @@ +/* Make sure both loops are recognized as doloops. + If so, "bdnz" will be generated on ppc; if not, + you will get "ble" or "blt" or "bge". */ + +/* { dg-do compile { target powerpc-*-* } } */ +/* { dg-options "-O2" } */ +void foo (int count, char* pca, char* pcb) { + int i; + if (count > 10) + for (i = 0; i < count; ++i) + pcb += i; + else + for (i = 0; i < count; ++i) + pca += i; + *pca = *pcb; +} +/* { dg-final { scan-assembler "bdnz" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/macho-lo-sum.c b/gcc/testsuite/gcc.target/powerpc/macho-lo-sum.c new file mode 100644 index 00000000000..9e0b8656c23 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/macho-lo-sum.c @@ -0,0 +1,29 @@ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-options "-O2 -mpowerpc64 -mdynamic-no-pic" } */ + +long long knight_attacks[64]; +long long InitializeAttackBoards(void); + +int main() +{ + return InitializeAttackBoards(); +} + +long long InitializeAttackBoards(void) +{ + + int i,j; + + for(i=0;i<64;i++) { } + + for(i=0;i<64;i++) { + knight_attacks[i]=0; + for(j=0;j<8;j++) { + knight_attacks[i]= 0; + } + } + + return knight_attacks[0]; + +} + diff --git a/gcc/testsuite/gcc.target/powerpc/powerpc.exp b/gcc/testsuite/gcc.target/powerpc/powerpc.exp new file mode 100644 index 00000000000..999234634fd --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/powerpc.exp @@ -0,0 +1,41 @@ +# Copyright (C) 2005 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + +# GCC testsuite that uses the 'dg.exp' driver. + +# Exit immediately if this isn't a PowerPC target. +if { ![istarget powerpc*-*-*] && ![istarget rs6000-*-*] } then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# If a testcase doesn't have special options, use these. +global DEFAULT_CFLAGS +if ![info exists DEFAULT_CFLAGS] then { + set DEFAULT_CFLAGS " -ansi -pedantic-errors" +} + +# Initialize 'dg'. +dg-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS + +# All done. +dg-finish diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-and-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-and-1.c new file mode 100644 index 00000000000..7f1c618ff52 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-and-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target powerpc64-*-* } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler "rlwinm \[0-9\]+,\[0-9\]+,0,0,30" } } */ +/* { dg-final { scan-assembler "rlwinm \[0-9\]+,\[0-9\]+,0,29,30" } } */ +/* { dg-final { scan-assembler-not "rldicr" } } */ + +/* Origin:Pete Steinmetz <steinmtz@us.ibm.com> */ + +/* PR 16457 - use rlwinm insn. */ + +char *foo1 (char *p, unsigned int x) +{ + return p - (x & ~1); +} + +char *foo2 (char *p, unsigned int x) +{ + return p - (x & 6); +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-bitfield1.c b/gcc/testsuite/gcc.target/powerpc/ppc-bitfield1.c new file mode 100644 index 00000000000..6af77541f7c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-bitfield1.c @@ -0,0 +1,68 @@ +/* { dg-do compile { target powerpc64-*-* } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler-not "rlwinm \[0-9\]+,\[0-9\]+,\[0-9\]+,1,31" } } */ +/* { dg-final { scan-assembler-not "rlwinm \[0-9\]+,\[0-9\]+,\[0-9\]+,0xffffffff" } } */ + +/* Origin:Pete Steinmetz <steinmtz@us.ibm.com> */ + +/* PR 17104 many sign extends added. */ + +struct { + int f1 : 1; + int f2 : 1; + int f3 : 1; + int f4 : 1; + int f5 : 1; + int f6 : 1; + int f7 : 1; + int f8 : 1; + int f9 : 1; + int f10 : 1; + int f11 : 1; + int f12 : 1; + int f13 : 1; + int f14 : 1; + int f15 : 1; + int f16 : 1; + int f17 : 2; + int f18 : 2; + int f19 : 2; + int f20 : 2; + int f21 : 2; + int f22 : 2; + int f23 : 2; + int f24 : 2; + } s; + +void foo () +{ + + s.f1 = 0; + s.f2 = 0; + s.f3 = 0; + s.f4 = 0; + s.f5 = 0; + s.f6 = 0; + s.f7 = 0; + s.f8 = 0; + s.f9 = 0; + s.f10 = 0; + s.f11 = 0; + s.f12 = 0; + s.f13 = 0; + s.f14 = 0; + s.f15 = 0; + s.f16 = 0; + s.f17 = 0; + s.f18 = 0; + s.f19 = 0; + s.f20 = 0; + s.f21 = 0; + s.f22 = 0; + s.f23 = 0; + s.f24 = 0; + +} + diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-compare-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-compare-1.c new file mode 100644 index 00000000000..b5670ab53b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-compare-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target powerpc64-*-* } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler-not "cmpw" } } */ + +/* Origin:Pete Steinmetz <steinmtz@us.ibm.com> */ + +/* PR 16458: Extraneous compare. */ + +int foo (unsigned a, unsigned b) +{ + if (a == b) return 1; + if (a > b) return 2; + if (a < b) return 3; + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-eabi.c b/gcc/testsuite/gcc.target/powerpc/ppc-eabi.c new file mode 100644 index 00000000000..47ba1a73390 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-eabi.c @@ -0,0 +1,4 @@ +/* PR target/16952 */ +/* { dg-do compile { target { powerpc*-*-linux* && ilp32 } } } */ +/* { dg-options "-meabi -mrelocatable" } */ +char *s = "boo"; diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-1.c new file mode 100644 index 00000000000..ff959f2d131 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-1.c @@ -0,0 +1,43 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-ffast-math -O2" } */ +/* { dg-final { scan-assembler-not "f(add|sub|mul|neg)" } } */ + +void foo(double *a, double *b, double *c, double *d) +{ + a[0] = b[0] + c[0] * d[0]; // fmadd + a[1] = b[1] - c[1] * d[1]; // fnmsub with fast-math + a[2] = -b[2] + c[2] * d[2]; // fmsub + a[3] = -b[3] - c[3] * d[3]; // fnmadd with fast-math + a[4] = -( b[4] + c[4] * d[4]); // fnmadd + a[5] = -( b[5] - c[5] * d[5]); // fmsub with fast-math + a[6] = -(-b[6] + c[6] * d[6]); // fnmsub + a[7] = -(-b[7] - c[7] * d[7]); // fmadd with fast-math + a[10] = b[10] - c[10] * -d[10]; // fmadd + a[11] = b[11] + c[11] * -d[11]; // fnmsub with fast-math + a[12] = -b[12] - c[12] * -d[12]; // fmsub + a[13] = -b[13] + c[13] * -d[13]; // fnmadd with fast-math + a[14] = -( b[14] - c[14] * -d[14]); // fnmadd + a[15] = -( b[15] + c[15] * -d[15]); // fmsub with fast-math + a[16] = -(-b[16] - c[16] * -d[16]); // fnmsub + a[17] = -(-b[17] + c[17] * -d[17]); // fmadd with fast-math +} + +void foos(float *a, float *b, float *c, float *d) +{ + a[0] = b[0] + c[0] * d[0]; // fmadd + a[1] = b[1] - c[1] * d[1]; // fnmsub with fast-math + a[2] = -b[2] + c[2] * d[2]; // fmsub + a[3] = -b[3] - c[3] * d[3]; // fnmadd with fast-math + a[4] = -( b[4] + c[4] * d[4]); // fnmadd + a[5] = -( b[5] - c[5] * d[5]); // fmsub with fast-math + a[6] = -(-b[6] + c[6] * d[6]); // fnmsub + a[7] = -(-b[7] - c[7] * d[7]); // fmadd with fast-math + a[10] = b[10] - c[10] * -d[10]; // fmadd + a[11] = b[11] + c[11] * -d[11]; // fnmsub with fast-math + a[12] = -b[12] - c[12] * -d[12]; // fmsub + a[13] = -b[13] + c[13] * -d[13]; // fnmadd with fast-math + a[14] = -( b[14] - c[14] * -d[14]); // fnmadd + a[15] = -( b[15] + c[15] * -d[15]); // fmsub with fast-math + a[16] = -(-b[16] - c[16] * -d[16]); // fnmsub + a[17] = -(-b[17] + c[17] * -d[17]); // fmadd with fast-math +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-2.c b/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-2.c new file mode 100644 index 00000000000..02ed811dace --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-2.c @@ -0,0 +1,27 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-not "f(add|sub|mul|neg)" } } */ + +void foo(double *a, double *b, double *c, double *d) +{ + a[0] = b[0] + c[0] * d[0]; // fmadd + a[2] = -b[2] + c[2] * d[2]; // fmsub + a[4] = -( b[4] + c[4] * d[4]); // fnmadd + a[6] = -(-b[6] + c[6] * d[6]); // fnmsub + a[10] = b[10] - c[10] * -d[10]; // fmadd + a[12] = -b[12] - c[12] * -d[12]; // fmsub + a[14] = -( b[14] - c[14] * -d[14]); // fnmadd + a[16] = -(-b[16] - c[16] * -d[16]); // fnmsub +} + +void foos(float *a, float *b, float *c, float *d) +{ + a[0] = b[0] + c[0] * d[0]; // fmadd + a[2] = -b[2] + c[2] * d[2]; // fmsub + a[4] = -( b[4] + c[4] * d[4]); // fnmadd + a[6] = -(-b[6] + c[6] * d[6]); // fnmsub + a[10] = b[10] - c[10] * -d[10]; // fmadd + a[12] = -b[12] - c[12] * -d[12]; // fmsub + a[14] = -( b[14] - c[14] * -d[14]); // fnmadd + a[16] = -(-b[16] - c[16] * -d[16]); // fnmsub +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-3.c b/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-3.c new file mode 100644 index 00000000000..d4205225caf --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-3.c @@ -0,0 +1,36 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-not "f(add|sub|mul)" } } */ + +void foo(double *a, double *b, double *c, double *d) +{ +#if 0 + a[1] = b[1] - c[1] * d[1]; // fneg, fmadd without fast-math +#endif + a[3] = -b[3] - c[3] * d[3]; // fneg, fmsub without fast-math +#if 0 + a[5] = -( b[5] - c[5] * d[5]); // fneg, fnmadd without fast-math +#endif + a[7] = -(-b[7] - c[7] * d[7]); // fneg, fnmsub without fast-math + a[11] = b[11] + c[11] * -d[11]; // fneg, fmadd without fast-math + a[13] = -b[13] + c[13] * -d[13]; // fneg, fmsub without fast-math + a[15] = -( b[15] + c[15] * -d[15]); // fneg, fnmadd without fast-math + a[17] = -(-b[17] + c[17] * -d[17]); // fneg, fnmsub without fast-math +} + +void foos(float *a, float *b, float *c, float *d) +{ +#if 0 + a[1] = b[1] - c[1] * d[1]; // fneg, fmadd without fast-math +#endif + a[3] = -b[3] - c[3] * d[3]; // fneg, fmsub without fast-math +#if 0 + a[5] = -( b[5] - c[5] * d[5]); // fneg, fnmadd without fast-math +#endif + a[7] = -(-b[7] - c[7] * d[7]); // fneg, fnmsub without fast-math + a[11] = b[11] + c[11] * -d[11]; // fneg, fmadd without fast-math + a[13] = -b[13] + c[13] * -d[13]; // fneg, fmsub without fast-math + a[15] = -( b[15] + c[15] * -d[15]); // fneg, fnmadd without fast-math + a[17] = -(-b[17] + c[17] * -d[17]); // fneg, fnmsub without fast-math +} + diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fsel-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-fsel-1.c new file mode 100644 index 00000000000..8d364352ac9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fsel-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-O -mpowerpc-gfxopt -fno-trapping-math" } */ +/* { dg-final { scan-assembler "fsel" } } */ + +/* If the user doesn't care about signals, fsel can be used in many cases. */ + +double foo(double a, double b, double c, double d) +{ + return a < b ? c : d; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fsel-2.c b/gcc/testsuite/gcc.target/powerpc/ppc-fsel-2.c new file mode 100644 index 00000000000..9768b165c24 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fsel-2.c @@ -0,0 +1,80 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-O -mpowerpc-gfxopt -g0 -ffinite-math-only" } */ +/* { dg-final { scan-assembler-not "^L" } } */ + +/* Every single one of these should be compiled into straight-line + code using fsel (or, in a few cases, hardwired to 'true' or + 'false'), no branches anywhere. */ + +double +test_isunordered(double x, double y, double a, double b) +{ + return __builtin_isunordered(x, y) ? a : b; +} + +double +test_not_isunordered(double x, double y, double a, double b) +{ + return !__builtin_isunordered(x, y) ? a : b; +} + +double +test_isless(double x, double y, double a, double b) +{ + return __builtin_isless(x, y) ? a : b; +} + +double +test_not_isless(double x, double y, double a, double b) +{ + return !__builtin_isless(x, y) ? a : b; +} + +double +test_islessequal(double x, double y, double a, double b) +{ + return __builtin_islessequal(x, y) ? a : b; +} + +double +test_not_islessequal(double x, double y, double a, double b) +{ + return !__builtin_islessequal(x, y) ? a : b; +} + +double +test_isgreater(double x, double y, double a, double b) +{ + return __builtin_isgreater(x, y) ? a : b; +} + +double +test_not_isgreater(double x, double y, double a, double b) +{ + return !__builtin_isgreater(x, y) ? a : b; +} + +double +test_isgreaterequal(double x, double y, double a, double b) +{ + return __builtin_isgreaterequal(x, y) ? a : b; +} + +double +test_not_isgreaterequal(double x, double y, double a, double b) +{ + return !__builtin_isgreaterequal(x, y) ? a : b; +} + +double +test_islessgreater(double x, double y, double a, double b) +{ + return __builtin_islessgreater(x, y) ? a : b; +} + +double +test_not_islessgreater(double x, double y, double a, double b) +{ + return !__builtin_islessgreater(x, y) ? a : b; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fsel-3.c b/gcc/testsuite/gcc.target/powerpc/ppc-fsel-3.c new file mode 100644 index 00000000000..1d07c528eb1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fsel-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-O -mpowerpc-gfxopt" } */ +/* { dg-final { scan-assembler-not "fsub" } } */ + +/* Check that an fsub isn't generated when no arithmetic was requested; + such an fsub might incorrectly set floating-point exception flags. */ + +double foo(double a, double b, double c, double d) +{ + return a < b ? c : d; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-ldstruct.c b/gcc/testsuite/gcc.target/powerpc/ppc-ldstruct.c new file mode 100644 index 00000000000..da6001fcd3c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-ldstruct.c @@ -0,0 +1,21 @@ +/* { dg-do run { target powerpc*-*-eabi* powerpc*-*-elf* powerpc*-*-linux* } } */ +/* { dg-options "-O -mlong-double-128" } */ + +#include <stdlib.h> + +/* SVR4 and EABI both specify that 'long double' is aligned to a 128-bit + boundary in structures. */ + +struct { + int x; + long double d; +} s; + +int main(void) +{ + if (sizeof (s) != 32) + abort (); + if ((char *)&s.d - (char *)&s != 16) + abort (); + exit (0); +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-mov-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-mov-1.c new file mode 100644 index 00000000000..7b541e258a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-mov-1.c @@ -0,0 +1,53 @@ +/* { dg-do compile { target powerpc64-*-* } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler-not "fmr \[0-9\]+,\[0-9\]+" } } + +/* Origin:Pete Steinmetz <steinmtz@us.ibm.com> */ + +/* PR 16796: Extraneous move. */ + +static const double huge = 1.0e300; +typedef int int64_t __attribute__ ((__mode__ (__DI__))); +typedef unsigned int u_int64_t __attribute__ ((__mode__ (__DI__))); + +double __floor(double x) +{ + union { + double dbl_val; + long int long_val; + } temp; + + int64_t i0,j0; + u_int64_t i; + temp.dbl_val = x; + i0 = temp.long_val; + + j0 = ((i0>>52)&0x7ff)-0x3ff; + if(j0<52) { + if(j0<0) { + if(huge+x>0.0) { + if(i0>=0) {i0=0;} + else if((i0&0x7fffffffffffffff)!=0) + { i0=0xbff0000000000000;} + } + } else { + i = (0x000fffffffffffff)>>j0; + if((i0&i)==0) return x; + if(huge+x>0.0) { + if(i0<0) i0 += (0x0010000000000000)>>j0; + i0 &= (~i); + } + } + } else { + if (j0==0x400) + return x+x; + else + return x; + } + temp.long_val = i0; + x = temp.dbl_val; + return x; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-sdata-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-sdata-1.c new file mode 100644 index 00000000000..bd9fa6e8e34 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-sdata-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target powerpc-*-linux* powerpc-*-sysv* powerpc-*-eabi* } } */ +/* { dg-options "-O2 -fno-common -G 8 -meabi -msdata=eabi" } */ +/* { dg-final { scan-assembler "\\.section\[ \t\]\\.sdata," } } */ +/* { dg-final { scan-assembler "\\.section\[ \t\]\\.sdata2," } } */ +/* { dg-final { scan-assembler "sdat@sda21\\((13|0)\\)" } } */ +/* { dg-final { scan-assembler "sdat2@sda21\\((2|0)\\)" } } */ + + +int sdat = 2; +const char sdat2[] = "1234"; + +const char * test (void) +{ + return sdat ? sdat2 : 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-sdata-2.c b/gcc/testsuite/gcc.target/powerpc/ppc-sdata-2.c new file mode 100644 index 00000000000..6aa96141e4f --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-sdata-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target powerpc-*-linux* powerpc-*-sysv* powerpc-*-eabi* } } */ +/* { dg-options "-O2 -fno-common -G 8 -msdata=sysv" } */ +/* { dg-final { scan-assembler "\\.section\[ \t\]\\.sdata," } } */ +/* { dg-final { scan-assembler-not "\\.section\[ \t\]\\.sdata2," } } */ +/* { dg-final { scan-assembler "sdat@sdarel\\(13\\)" } } */ +/* { dg-final { scan-assembler "sdat2@sdarel\\(13\\)" } } */ + + +int sdat = 2; +const char sdat2[] = "1234"; + +const char * test (void) +{ + return sdat ? sdat2 : 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-spe.c b/gcc/testsuite/gcc.target/powerpc/ppc-spe.c new file mode 100644 index 00000000000..b35b2e9da50 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-spe.c @@ -0,0 +1,662 @@ +/* { dg-do compile { target powerpc-*-eabispe } } */ +/* { dg-options "-mcpu=8540 -mabi=spe -O0" } */ + +/* (Test with -O0 so we don't optimize any of them away). */ + +#include <spe.h> + +/* Test PowerPC SPE extensions. */ + +#define vector __attribute__((vector_size(8))) + +vector int a, b, c, *ap; +vector float f, g, h; +unsigned int *uip; +unsigned short *usp; +int i, j, *ip; +uint64_t ull; +int64_t sll; +unsigned ui; +float fl; +uint16_t u16; +int16_t s16; + +/* These are the only documented/supported accesor functions for the + SPE builtins. */ +void +test_api () +{ + c = __ev_addw (a, b); + c = __ev_addiw (a, 8); + c = __ev_subfw (a, b); + c = __ev_subifw (8, a); + c = __ev_abs (a); + c = __ev_neg (a); + c = __ev_extsb (a); + c = __ev_extsh (a); + c = __ev_and (a, b); + c = __ev_or (a, b); + c = __ev_xor (a, b); + c = __ev_nand (a, b); + c = __ev_nor (a, b); + c = __ev_eqv (a, b); + c = __ev_andc (a, b); + c = __ev_orc (a, b); + c = __ev_rlw (a, b); + c = __ev_rlwi (a, 8); + c = __ev_slw (a, b); + c = __ev_slwi (a, 8); + c = __ev_srws (a, b); + c = __ev_srwu (a, b); + c = __ev_srwis (a, 8); + c = __ev_srwiu (a, 8); + c = __ev_cntlzw (a); + c = __ev_cntlsw (a); + c = __ev_rndw (a); + c = __ev_mergehi (a, b); + c = __ev_mergelo (a, b); + c = __ev_mergelohi (a, b); + c = __ev_mergehilo (a, b); + c = __ev_splati (5); + c = __ev_splatfi (6); + c = __ev_divws (a, b); + c = __ev_divwu (a, b); + c = __ev_mra (a); + i = __brinc (5, 6); + + /* Loads. */ + c = __ev_lddx (ap, i); + c = __ev_ldwx (ap, i); + c = __ev_ldhx (ap, i); + + c = __ev_lwhex (uip, i); + c = __ev_lwhoux (uip, i); + c = __ev_lwhosx (uip, i); + c = __ev_lwwsplatx (uip, i); + c = __ev_lwhsplatx (uip, i); + + c = __ev_lhhesplatx (usp, i); + c = __ev_lhhousplatx (usp, i); + c = __ev_lhhossplatx (usp, i); + + c = __ev_ldd (ap, 5); + c = __ev_ldw (ap, 6); + c = __ev_ldh (ap, 7); + c = __ev_lwhe (uip, 6); + c = __ev_lwhou (uip, 6); + c = __ev_lwhos (uip, 7); + c = __ev_lwwsplat (uip, 7); + c = __ev_lwhsplat (uip, 7); + c = __ev_lhhesplat (usp, 7); + c = __ev_lhhousplat (usp, 7); + c = __ev_lhhossplat (usp, 7); + + /* Stores. */ + __ev_stddx (a, ap, 9); + __ev_stdwx (a, ap, 9); + __ev_stdhx (a, ap, 9); + __ev_stwwex (a, uip, 9); + __ev_stwwox (a, uip, 9); + __ev_stwhex (a, uip, 9); + __ev_stwhox (a, uip, 9); + __ev_stdd (a, ap, 9); + __ev_stdw (a, ap, 9); + __ev_stdh (a, ap, 9); + __ev_stwwe (a, uip, 9); + __ev_stwwo (a, uip, 9); + __ev_stwhe (a, uip, 9); + __ev_stwho (a, uip, 9); + + /* Fixed point complex. */ + c = __ev_mhossf (a, b); + c = __ev_mhosmf (a, b); + c = __ev_mhosmi (a, b); + c = __ev_mhoumi (a, b); + c = __ev_mhessf (a, b); + c = __ev_mhesmf (a, b); + c = __ev_mhesmi (a, b); + c = __ev_mheumi (a, b); + c = __ev_mhossfa (a, b); + c = __ev_mhosmfa (a, b); + c = __ev_mhosmia (a, b); + c = __ev_mhoumia (a, b); + c = __ev_mhessfa (a, b); + c = __ev_mhesmfa (a, b); + c = __ev_mhesmia (a, b); + c = __ev_mheumia (a, b); + + c = __ev_mhoumf (a, b); + c = __ev_mheumf (a, b); + c = __ev_mhoumfa (a, b); + c = __ev_mheumfa (a, b); + + c = __ev_mhossfaaw (a, b); + c = __ev_mhossiaaw (a, b); + c = __ev_mhosmfaaw (a, b); + c = __ev_mhosmiaaw (a, b); + c = __ev_mhousiaaw (a, b); + c = __ev_mhoumiaaw (a, b); + c = __ev_mhessfaaw (a, b); + c = __ev_mhessiaaw (a, b); + c = __ev_mhesmfaaw (a, b); + c = __ev_mhesmiaaw (a, b); + c = __ev_mheusiaaw (a, b); + c = __ev_mheumiaaw (a, b); + + c = __ev_mhousfaaw (a, b); + c = __ev_mhoumfaaw (a, b); + c = __ev_mheusfaaw (a, b); + c = __ev_mheumfaaw (a, b); + + c = __ev_mhossfanw (a, b); + c = __ev_mhossianw (a, b); + c = __ev_mhosmfanw (a, b); + c = __ev_mhosmianw (a, b); + c = __ev_mhousianw (a, b); + c = __ev_mhoumianw (a, b); + c = __ev_mhessfanw (a, b); + c = __ev_mhessianw (a, b); + c = __ev_mhesmfanw (a, b); + c = __ev_mhesmianw (a, b); + c = __ev_mheusianw (a, b); + c = __ev_mheumianw (a, b); + + c = __ev_mhousfanw (a, b); + c = __ev_mhoumfanw (a, b); + c = __ev_mheusfanw (a, b); + c = __ev_mheumfanw (a, b); + + c = __ev_mhogsmfaa (a, b); + c = __ev_mhogsmiaa (a, b); + c = __ev_mhogumiaa (a, b); + c = __ev_mhegsmfaa (a, b); + c = __ev_mhegsmiaa (a, b); + c = __ev_mhegumiaa (a, b); + + c = __ev_mhogumfaa (a, b); + c = __ev_mhegumfaa (a, b); + + c = __ev_mhogsmfan (a, b); + c = __ev_mhogsmian (a, b); + c = __ev_mhogumian (a, b); + c = __ev_mhegsmfan (a, b); + c = __ev_mhegsmian (a, b); + c = __ev_mhegumian (a, b); + + c = __ev_mhogumfan (a, b); + c = __ev_mhegumfan (a, b); + + c = __ev_mwhssf (a, b); + c = __ev_mwhsmf (a, b); + c = __ev_mwhsmi (a, b); + c = __ev_mwhumi (a, b); + c = __ev_mwhssfa (a, b); + c = __ev_mwhsmfa (a, b); + c = __ev_mwhsmia (a, b); + c = __ev_mwhumia (a, b); + + c = __ev_mwhumf (a, b); + c = __ev_mwhumfa (a, b); + + c = __ev_mwlumi (a, b); + c = __ev_mwlumia (a, b); + c = __ev_mwlumiaaw (a, b); + + c = __ev_mwlssiaaw (a, b); + c = __ev_mwlsmiaaw (a, b); + c = __ev_mwlusiaaw (a, b); + c = __ev_mwlusiaaw (a, b); + + c = __ev_mwlssianw (a, b); + c = __ev_mwlsmianw (a, b); + c = __ev_mwlusianw (a, b); + c = __ev_mwlumianw (a, b); + + c = __ev_mwssf (a, b); + c = __ev_mwsmf (a, b); + c = __ev_mwsmi (a, b); + c = __ev_mwumi (a, b); + c = __ev_mwssfa (a, b); + c = __ev_mwsmfa (a, b); + c = __ev_mwsmia (a, b); + c = __ev_mwumia (a, b); + c = __ev_mwumf (a, b); + c = __ev_mwumfa (a, b); + c = __ev_mwssfaa (a, b); + c = __ev_mwsmfaa (a, b); + c = __ev_mwsmiaa (a, b); + c = __ev_mwumiaa (a, b); + c = __ev_mwumfaa (a, b); + c = __ev_mwssfan (a, b); + c = __ev_mwsmfan (a, b); + c = __ev_mwsmian (a, b); + c = __ev_mwumian (a, b); + c = __ev_mwumfan (a, b); + c = __ev_addssiaaw (a); + c = __ev_addsmiaaw (a); + c = __ev_addusiaaw (a); + c = __ev_addumiaaw (a); + c = __ev_addusfaaw (a); + c = __ev_addumfaaw (a); + c = __ev_addsmfaaw (a); + c = __ev_addssfaaw (a); + c = __ev_subfssiaaw (a); + c = __ev_subfsmiaaw (a); + c = __ev_subfusiaaw (a); + c = __ev_subfumiaaw (a); + c = __ev_subfusfaaw (a); + c = __ev_subfumfaaw (a); + c = __ev_subfsmfaaw (a); + c = __ev_subfssfaaw (a); + + /* Floating point SIMD instructions. */ + c = __ev_fsabs (a); + c = __ev_fsnabs (a); + c = __ev_fsneg (a); + c = __ev_fsadd (a, b); + c = __ev_fssub (a, b); + c = __ev_fsmul (a, b); + c = __ev_fsdiv (a, b); + c = __ev_fscfui (a); + c = __ev_fscfsi (a); + c = __ev_fscfuf (a); + c = __ev_fscfsf (a); + c = __ev_fsctui (a); + c = __ev_fsctsi (a); + c = __ev_fsctuf (a); + c = __ev_fsctsf (a); + c = __ev_fsctuiz (a); + c = __ev_fsctsiz (a); + + /* Non supported sythetic instructions made from two instructions. */ + + c = __ev_mwhssfaaw (a, b); + c = __ev_mwhssiaaw (a, b); + c = __ev_mwhsmfaaw (a, b); + c = __ev_mwhsmiaaw (a, b); + c = __ev_mwhusiaaw (a, b); + c = __ev_mwhumiaaw (a, b); + c = __ev_mwhusfaaw (a, b); + c = __ev_mwhumfaaw (a, b); + c = __ev_mwhssfanw (a, b); + c = __ev_mwhssianw (a, b); + c = __ev_mwhsmfanw (a, b); + c = __ev_mwhsmianw (a, b); + c = __ev_mwhusianw (a, b); + c = __ev_mwhumianw (a, b); + c = __ev_mwhusfanw (a, b); + c = __ev_mwhumfanw (a, b); + + c = __ev_mwhgssfaa (a, b); + c = __ev_mwhgsmfaa (a, b); + c = __ev_mwhgsmiaa (a, b); + c = __ev_mwhgumiaa (a, b); + c = __ev_mwhgssfan (a, b); + c = __ev_mwhgsmfan (a, b); + c = __ev_mwhgsmian (a, b); + c = __ev_mwhgumian (a, b); + + /* Creating, insertion, and extraction. */ + + a = __ev_create_u64 ((uint64_t) 55); + a = __ev_create_s64 ((int64_t) 66); + a = __ev_create_fs (3.14F, 2.18F); + a = __ev_create_u32 ((uint32_t) 5, (uint32_t) i); + a = __ev_create_s32 ((int32_t) 5, (int32_t) 6); + a = __ev_create_u16 ((uint16_t) 6, (uint16_t) 6, (uint16_t) 7, (uint16_t) 1); + a = __ev_create_s16 ((int16_t) 6, (int16_t) 6, (int16_t) 7, (int16_t) 9); + a = __ev_create_sfix32_fs (3.0F, 2.0F); + a = __ev_create_ufix32_fs (3.0F, 2.0F); + a = __ev_create_ufix32_u32 (3U, 5U); + a = __ev_create_sfix32_s32 (6, 9); + ull = __ev_convert_u64 (a); + sll = __ev_convert_s64 (a); + i = __ev_get_upper_u32 (a); + ui = __ev_get_lower_u32 (a); + i = __ev_get_upper_s32 (a); + i = __ev_get_lower_s32 (a); + fl = __ev_get_upper_fs (a); + fl = __ev_get_lower_fs (a); + u16 = __ev_get_u16 (a, 5U); + s16 = __ev_get_s16 (a, 5U); + ui = __ev_get_upper_ufix32_u32 (a); + ui = __ev_get_lower_ufix32_u32 (a); + i = __ev_get_upper_sfix32_s32 (a); + i = __ev_get_lower_sfix32_s32 (a); + fl = __ev_get_upper_sfix32_fs (a); + fl = __ev_get_lower_sfix32_fs (a); + fl = __ev_get_upper_ufix32_fs (a); + fl = __ev_get_lower_ufix32_fs (a); + a = __ev_set_upper_u32 (a, 5U); + a = __ev_set_lower_u32 (a, 5U); + a = __ev_set_upper_s32 (a, 5U); + a = __ev_set_lower_s32 (a, 6U); + a = __ev_set_upper_fs (a, 6U); + a = __ev_set_lower_fs (a, fl); + a = __ev_set_upper_ufix32_u32 (a, 5U); + a = __ev_set_lower_ufix32_u32 (a, 5U); + a = __ev_set_upper_sfix32_s32 (a, 5); + a = __ev_set_lower_sfix32_s32 (a, 5); + a = __ev_set_upper_sfix32_fs (a, fl); + a = __ev_set_lower_sfix32_fs (a, fl); + a = __ev_set_upper_ufix32_fs (a, fl); + a = __ev_set_lower_ufix32_fs (a, fl); + a = __ev_set_acc_u64 ((uint64_t) 640); + a = __ev_set_acc_s64 ((int64_t) 460); + a = __ev_set_acc_vec64 (b); + a = __ev_set_u32 (a, 5, 6); + a = __ev_set_s32 (a, 5, 6); + a = __ev_set_fs (a, fl, 5); + a = __ev_set_u16 (a, 5U, 3); + a = __ev_set_s16 (a, 5, 6); + a = __ev_set_ufix32_u32 (a, 5U, 6U); + a = __ev_set_sfix32_s32 (a, 3, 6); + a = __ev_set_ufix32_fs (a, fl, 5); + a = __ev_set_sfix32_fs (a, fl, 5); + ui = __ev_get_u32 (a, 1); + i = __ev_get_s32 (a, 0); + fl = __ev_get_fs (a, 1); + u16 = __ev_get_u16 (a, 2); + s16 = __ev_get_s16 (a, 2); + ui = __ev_get_ufix32_u32 (a, 1); + i = __ev_get_sfix32_s32 (a, 0); + fl = __ev_get_ufix32_fs (a, 1); + fl = __ev_get_sfix32_fs (a, 0); + + /* Predicates. */ + i = __ev_any_gts (a, b); + i = __ev_all_gts (a, b); + i = __ev_upper_gts (a, b); + i = __ev_lower_gts (a, b); + a = __ev_select_gts (a, b, c, c); + + i = __ev_any_gtu (a, b); + i = __ev_all_gtu (a, b); + i = __ev_upper_gtu (a, b); + i = __ev_lower_gtu (a, b); + a = __ev_select_gtu (a, b, c, c); + + i = __ev_any_lts (a, b); + i = __ev_all_lts (a, b); + i = __ev_upper_lts (a, b); + i = __ev_lower_lts (a, b); + a = __ev_select_lts (a, b, c, c); + + i = __ev_any_ltu (a, b); + i = __ev_all_ltu (a, b); + i = __ev_upper_ltu (a, b); + i = __ev_lower_ltu (a, b); + a = __ev_select_ltu (a, b, c, c); + + i = __ev_any_eq (a, b); + i = __ev_all_eq (a, b); + i = __ev_upper_eq (a, b); + i = __ev_lower_eq (a, b); + a = __ev_select_eq (a, b, c, c); + + i = __ev_any_fs_gt (a, b); + i = __ev_all_fs_gt (a, b); + i = __ev_upper_fs_gt (a, b); + i = __ev_lower_fs_gt (a, b); + a = __ev_select_fs_gt (a, b, c, c); + + i = __ev_any_fs_lt (a, b); + i = __ev_all_fs_lt (a, b); + i = __ev_upper_fs_lt (a, b); + i = __ev_lower_fs_lt (a, b); + a = __ev_select_fs_lt (a, b, c, b); + + i = __ev_any_fs_eq (a, b); + i = __ev_all_fs_eq (a, b); + i = __ev_upper_fs_eq (a, b); + i = __ev_lower_fs_eq (a, b); + a = __ev_select_fs_eq (a, b, c, c); + + i = __ev_any_fs_tst_gt (a, b); + i = __ev_all_fs_tst_gt (a, b); + i = __ev_upper_fs_tst_gt (a, b); + i = __ev_lower_fs_tst_gt (a, b); + a = __ev_select_fs_tst_gt (a, b, c, c); + + i = __ev_any_fs_tst_lt (a, b); + i = __ev_all_fs_tst_lt (a, b); + i = __ev_upper_fs_tst_lt (a, b); + i = __ev_lower_fs_tst_lt (a, b); + a = __ev_select_fs_tst_lt (a, b, c, c); + + i = __ev_any_fs_tst_eq (a, b); + i = __ev_all_fs_tst_eq (a, b); + i = __ev_upper_fs_tst_eq (a, b); + i = __ev_lower_fs_tst_eq (a, b); + a = __ev_select_fs_tst_eq (a, b, c, c); +} + +int +main (void) +{ + /* Generic binary operations. */ + c = __builtin_spe_evaddw (a, b); + c = __builtin_spe_evand (a, b); + c = __builtin_spe_evandc (a, b); + c = __builtin_spe_evdivws (a, b); + c = __builtin_spe_evdivwu (a, b); + c = __builtin_spe_eveqv (a, b); + h = __builtin_spe_evfsadd (f, g); + h = __builtin_spe_evfsdiv (f, g); + h = __builtin_spe_evfsmul (f, g); + h = __builtin_spe_evfssub (f, g); + c = __builtin_spe_evlddx (ap, j); + c = __builtin_spe_evldhx (ap, j); + c = __builtin_spe_evldwx (ap, j); + c = __builtin_spe_evlhhesplatx (usp, j); + c = __builtin_spe_evlhhossplatx (usp, j); + c = __builtin_spe_evlhhousplatx (usp, j); + c = __builtin_spe_evlwhex (uip, j); + c = __builtin_spe_evlwhosx (uip, j); + c = __builtin_spe_evlwhoux (uip, j); + c = __builtin_spe_evlwhsplatx (uip, j); + c = __builtin_spe_evlwwsplatx (uip, j); + c = __builtin_spe_evmergehi (a, b); + c = __builtin_spe_evmergehilo (a, b); + c = __builtin_spe_evmergelo (a, b); + c = __builtin_spe_evmergelohi (a, b); + c = __builtin_spe_evmhegsmfaa (a, b); + c = __builtin_spe_evmhegsmfan (a, b); + c = __builtin_spe_evmhegsmiaa (a, b); + c = __builtin_spe_evmhegsmian (a, b); + c = __builtin_spe_evmhegumiaa (a, b); + c = __builtin_spe_evmhegumian (a, b); + c = __builtin_spe_evmhesmf (a, b); + c = __builtin_spe_evmhesmfa (a, b); + c = __builtin_spe_evmhesmfaaw (a, b); + c = __builtin_spe_evmhesmfanw (a, b); + c = __builtin_spe_evmhesmi (a, b); + c = __builtin_spe_evmhesmia (a, b); + c = __builtin_spe_evmhesmiaaw (a, b); + c = __builtin_spe_evmhesmianw (a, b); + c = __builtin_spe_evmhessf (a, b); + c = __builtin_spe_evmhessfa (a, b); + c = __builtin_spe_evmhessfaaw (a, b); + c = __builtin_spe_evmhessfanw (a, b); + c = __builtin_spe_evmhessiaaw (a, b); + c = __builtin_spe_evmhessianw (a, b); + c = __builtin_spe_evmheumi (a, b); + c = __builtin_spe_evmheumia (a, b); + c = __builtin_spe_evmheumiaaw (a, b); + c = __builtin_spe_evmheumianw (a, b); + c = __builtin_spe_evmheusiaaw (a, b); + c = __builtin_spe_evmheusianw (a, b); + c = __builtin_spe_evmhogsmfaa (a, b); + c = __builtin_spe_evmhogsmfan (a, b); + c = __builtin_spe_evmhogsmiaa (a, b); + c = __builtin_spe_evmhogsmian (a, b); + c = __builtin_spe_evmhogumiaa (a, b); + c = __builtin_spe_evmhogumian (a, b); + c = __builtin_spe_evmhosmf (a, b); + c = __builtin_spe_evmhosmfa (a, b); + c = __builtin_spe_evmhosmfaaw (a, b); + c = __builtin_spe_evmhosmfanw (a, b); + c = __builtin_spe_evmhosmi (a, b); + c = __builtin_spe_evmhosmia (a, b); + c = __builtin_spe_evmhosmiaaw (a, b); + c = __builtin_spe_evmhosmianw (a, b); + c = __builtin_spe_evmhossf (a, b); + c = __builtin_spe_evmhossfa (a, b); + c = __builtin_spe_evmhossfaaw (a, b); + c = __builtin_spe_evmhossfanw (a, b); + c = __builtin_spe_evmhossiaaw (a, b); + c = __builtin_spe_evmhossianw (a, b); + c = __builtin_spe_evmhoumi (a, b); + c = __builtin_spe_evmhoumia (a, b); + c = __builtin_spe_evmhoumiaaw (a, b); + c = __builtin_spe_evmhoumianw (a, b); + c = __builtin_spe_evmhousiaaw (a, b); + c = __builtin_spe_evmhousianw (a, b); + c = __builtin_spe_evmwhsmf (a, b); + c = __builtin_spe_evmwhsmfa (a, b); + c = __builtin_spe_evmwhsmi (a, b); + c = __builtin_spe_evmwhsmia (a, b); + c = __builtin_spe_evmwhssf (a, b); + c = __builtin_spe_evmwhssfa (a, b); + c = __builtin_spe_evmwhumi (a, b); + c = __builtin_spe_evmwhumia (a, b); + c = __builtin_spe_evmwlsmiaaw (a, b); + c = __builtin_spe_evmwlsmianw (a, b); + c = __builtin_spe_evmwlssiaaw (a, b); + c = __builtin_spe_evmwlssianw (a, b); + c = __builtin_spe_evmwlumi (a, b); + c = __builtin_spe_evmwlumia (a, b); + c = __builtin_spe_evmwlumiaaw (a, b); + c = __builtin_spe_evmwlumianw (a, b); + c = __builtin_spe_evmwlusiaaw (a, b); + c = __builtin_spe_evmwlusianw (a, b); + c = __builtin_spe_evmwsmf (a, b); + c = __builtin_spe_evmwsmfa (a, b); + c = __builtin_spe_evmwsmfaa (a, b); + c = __builtin_spe_evmwsmfan (a, b); + c = __builtin_spe_evmwsmi (a, b); + c = __builtin_spe_evmwsmia (a, b); + c = __builtin_spe_evmwsmiaa (a, b); + c = __builtin_spe_evmwsmian (a, b); + c = __builtin_spe_evmwssf (a, b); + c = __builtin_spe_evmwssfa (a, b); + c = __builtin_spe_evmwssfaa (a, b); + c = __builtin_spe_evmwssfan (a, b); + c = __builtin_spe_evmwumi (a, b); + c = __builtin_spe_evmwumia (a, b); + c = __builtin_spe_evmwumiaa (a, b); + c = __builtin_spe_evmwumian (a, b); + c = __builtin_spe_evnand (a, b); + c = __builtin_spe_evnor (a, b); + c = __builtin_spe_evor (a, b); + c = __builtin_spe_evorc (a, b); + c = __builtin_spe_evrlw (a, b); + c = __builtin_spe_evslw (a, b); + c = __builtin_spe_evsrws (a, b); + c = __builtin_spe_evsrwu (a, b); + c = __builtin_spe_evsubfw (a, b); + c = __builtin_spe_evxor (a, b); + + c = __builtin_spe_evmwhssfaa (a, b); + c = __builtin_spe_evmwhssmaa (a, b); + c = __builtin_spe_evmwhsmfaa (a, b); + c = __builtin_spe_evmwhsmiaa (a, b); + c = __builtin_spe_evmwhusiaa (a, b); + c = __builtin_spe_evmwhumiaa (a, b); + c = __builtin_spe_evmwhssfan (a, b); + c = __builtin_spe_evmwhssian (a, b); + c = __builtin_spe_evmwhsmfan (a, b); + c = __builtin_spe_evmwhsmian (a, b); + c = __builtin_spe_evmwhusian (a, b); + c = __builtin_spe_evmwhumian (a, b); + c = __builtin_spe_evmwhgssfaa (a, b); + c = __builtin_spe_evmwhgsmfaa (a, b); + c = __builtin_spe_evmwhgsmiaa (a, b); + c = __builtin_spe_evmwhgumiaa (a, b); + c = __builtin_spe_evmwhgssfan (a, b); + c = __builtin_spe_evmwhgsmfan (a, b); + c = __builtin_spe_evmwhgsmian (a, b); + c = __builtin_spe_evmwhgumian (a, b); + i = __builtin_spe_brinc (i, j); + + /* Generic unary operations. */ + a = __builtin_spe_evabs (b); + a = __builtin_spe_evaddsmiaaw (b); + a = __builtin_spe_evaddssiaaw (b); + a = __builtin_spe_evaddumiaaw (b); + a = __builtin_spe_evaddusiaaw (b); + a = __builtin_spe_evcntlsw (b); + a = __builtin_spe_evcntlzw (b); + a = __builtin_spe_evextsb (b); + a = __builtin_spe_evextsh (b); + f = __builtin_spe_evfsabs (g); + f = __builtin_spe_evfscfsf (g); + a = __builtin_spe_evfscfsi (g); + f = __builtin_spe_evfscfuf (g); + f = __builtin_spe_evfscfui (a); + f = __builtin_spe_evfsctsf (g); + a = __builtin_spe_evfsctsi (g); + a = __builtin_spe_evfsctsiz (g); + f = __builtin_spe_evfsctuf (g); + a = __builtin_spe_evfsctui (g); + a = __builtin_spe_evfsctuiz (g); + f = __builtin_spe_evfsnabs (g); + f = __builtin_spe_evfsneg (g); + a = __builtin_spe_evmra (b); + a = __builtin_spe_evneg (b); + a = __builtin_spe_evrndw (b); + a = __builtin_spe_evsubfsmiaaw (b); + a = __builtin_spe_evsubfssiaaw (b); + a = __builtin_spe_evsubfumiaaw (b); + a = __builtin_spe_evsubfusiaaw (b); + + /* Unary operations of the form: X = foo (5_bit_signed_immediate). */ + a = __builtin_spe_evsplatfi (5); + a = __builtin_spe_evsplati (5); + + /* Binary operations of the form: X = foo(Y, 5_bit_immediate). */ + a = __builtin_spe_evaddiw (b, 13); + a = __builtin_spe_evldd (ap, 13); + a = __builtin_spe_evldh (ap, 13); + a = __builtin_spe_evldw (ap, 13); + a = __builtin_spe_evlhhesplat (usp, 13); + a = __builtin_spe_evlhhossplat (usp, 13); + a = __builtin_spe_evlhhousplat (usp, 13); + a = __builtin_spe_evlwhe (uip, 13); + a = __builtin_spe_evlwhos (uip, 13); + a = __builtin_spe_evlwhou (uip, 13); + a = __builtin_spe_evlwhsplat (uip, 13); + a = __builtin_spe_evlwwsplat (uip, 13); + + a = __builtin_spe_evrlwi (b, 13); + a = __builtin_spe_evslwi (b, 13); + a = __builtin_spe_evsrwis (b, 13); + a = __builtin_spe_evsrwiu (b, 13); + a = __builtin_spe_evsubifw (b, 13); + + /* Store indexed builtins. */ + __builtin_spe_evstddx (b, ap, j); + __builtin_spe_evstdhx (b, ap, j); + __builtin_spe_evstdwx (b, ap, j); + __builtin_spe_evstwhex (b, uip, j); + __builtin_spe_evstwhox (b, uip, j); + __builtin_spe_evstwwex (b, uip, j); + __builtin_spe_evstwwox (b, uip, j); + + /* Store indexed immediate builtins. */ + __builtin_spe_evstdd (b, ap, 5); + __builtin_spe_evstdh (b, ap, 5); + __builtin_spe_evstdw (b, ap, 5); + __builtin_spe_evstwhe (b, uip, 5); + __builtin_spe_evstwho (b, uip, 5); + __builtin_spe_evstwwe (b, uip, 5); + __builtin_spe_evstwwo (b, uip, 5); + + /* SPEFSCR builtins. */ + i = __builtin_spe_mfspefscr (); + __builtin_spe_mtspefscr (j); + + test_api (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-spe64-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-spe64-1.c new file mode 100644 index 00000000000..8055668d1c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-spe64-1.c @@ -0,0 +1,6 @@ +/* Test that SPE targets do not permit -m64. */ +/* Origin: Joseph Myers <joseph@codesourcery.com> */ +/* { dg-do compile { target powerpc-*-*spe } } */ +/* { dg-options "-m64" } */ + +/* { dg-error "-m64 not supported in this configuration" "SPE not 64-bit" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-stackalign-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-stackalign-1.c new file mode 100644 index 00000000000..e73e895706e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-stackalign-1.c @@ -0,0 +1,35 @@ +/* { dg-do run { target powerpc-*-linux* powerpc-*-sysv* } } */ +/* { dg-options {} } */ + +/* Test stack pointer alignment against variable alloca. */ +/* Inspired by PR libgcj/10610. */ +/* Origin: Franz Sirl <Franz.Sirl-kernel@lauterbach.com>. */ + +extern void abort (void); +extern void exit (int); + +register unsigned long sp __asm__ ("r1"); + +void g (int * val __attribute__ ((unused))) +{ + if (sp & 0xf) + abort (); +} + +void f (int val) +{ + int *val1 = __builtin_alloca (val); + + g (val1); + return; +} + +int main (void) +{ + int i; + + for (i = 1; i < 32; i++) + f (i); + + exit (0); +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-stfiwx.c b/gcc/testsuite/gcc.target/powerpc/ppc-stfiwx.c new file mode 100644 index 00000000000..47a29ed3f17 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-stfiwx.c @@ -0,0 +1,8 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-mpowerpc-gfxopt" } */ +/* { dg-final { scan-assembler "stfiwx" } } */ + +int foo (double x) +{ + return x; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-vector-memcpy.c b/gcc/testsuite/gcc.target/powerpc/ppc-vector-memcpy.c new file mode 100644 index 00000000000..99ca85e972c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-vector-memcpy.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-xfail-if "" { "powerpc-*-eabispe*" "powerpc-ibm-aix*" } { "*" } { "" } } */ +/* { dg-options "-O -maltivec" } */ +/* { dg-final { scan-assembler "lvx" } } */ + +void foo(void) +{ + int x[8] __attribute__((aligned(128))) = { 1, 1, 1, 1, 1, 1, 1, 1 }; + bar (x); +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-vector-memset.c b/gcc/testsuite/gcc.target/powerpc/ppc-vector-memset.c new file mode 100644 index 00000000000..0297e893180 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc-vector-memset.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-xfail-if "" { "powerpc-*-eabispe*" "powerpc-ibm-aix*" } { "*" } { "" } } */ +/* { dg-options "-O -maltivec" } */ +/* { dg-final { scan-assembler "stvx" } } */ + +#include <string.h> + +void foo(void) +{ + int x[8] __attribute__((aligned(128))); + memset (x, 0, sizeof (x)); + bar (x); +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c b/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c new file mode 100644 index 00000000000..d0cb9cd6c90 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c @@ -0,0 +1,364 @@ +/* { dg-do run { target powerpc64-*-* } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2" } */ +#include <stdarg.h> +#include <signal.h> +#include <stdio.h> + +/* Testcase to check for ABI compliance of parameter passing + for the PowerPC64 ABI. + Parameter passing of integral and floating point is tested. */ + +extern void abort (void); + +typedef struct +{ + unsigned long gprs[8]; + double fprs[13]; +} reg_parms_t; + +reg_parms_t gparms; + + +/* Testcase could break on future gcc's, if parameter regs + are changed before this asm. */ + +#ifndef __MACH__ +#define save_parms(lparms) \ + asm volatile ("ld 11,gparms@got(2)\n\t" \ + "std 3,0(11)\n\t" \ + "std 4,8(11)\n\t" \ + "std 5,16(11)\n\t" \ + "std 6,24(11)\n\t" \ + "std 7,32(11)\n\t" \ + "std 8,40(11)\n\t" \ + "std 9,48(11)\n\t" \ + "std 10,56(11)\n\t" \ + "stfd 1,64(11)\n\t" \ + "stfd 2,72(11)\n\t" \ + "stfd 3,80(11)\n\t" \ + "stfd 4,88(11)\n\t" \ + "stfd 5,96(11)\n\t" \ + "stfd 6,104(11)\n\t" \ + "stfd 7,112(11)\n\t" \ + "stfd 8,120(11)\n\t" \ + "stfd 9,128(11)\n\t" \ + "stfd 10,136(11)\n\t" \ + "stfd 11,144(11)\n\t" \ + "stfd 12,152(11)\n\t" \ + "stfd 13,160(11)\n\t":::"11", "memory"); \ + lparms = gparms; +#else +#define save_parms(lparms) \ + asm volatile ("ld r11,gparms@got(r2)\n\t" \ + "std r3,0(r11)\n\t" \ + "std r4,8(r11)\n\t" \ + "std r5,16(r11)\n\t" \ + "std r6,24(r11)\n\t" \ + "std r7,32(r11)\n\t" \ + "std r8,40(r11)\n\t" \ + "std r9,48(r11)\n\t" \ + "std r10,56(r11)\n\t" \ + "stfd f1,64(r11)\n\t" \ + "stfd f2,72(r11)\n\t" \ + "stfd f3,80(r11)\n\t" \ + "stfd f4,88(r11)\n\t" \ + "stfd f5,96(r11)\n\t" \ + "stfd f6,104(r11)\n\t" \ + "stfd f7,112(r11)\n\t" \ + "stfd f8,120(r11)\n\t" \ + "stfd f9,128(r11)\n\t" \ + "stfd f10,136(r11)\n\t" \ + "stfd f11,144(r11)\n\t" \ + "stfd f12,152(r11)\n\t" \ + "stfd f13,160(r11)\n\t":::"r11", "memory"); \ + lparms = gparms; +#endif + +/* Stackframe structure relevant for parameter passing. */ +typedef union +{ + double d; + unsigned long l; + unsigned int i[2]; +} parm_t; + +typedef struct sf +{ + struct sf *backchain; + long a1; + long a2; + long a3; + long a4; + long a5; + parm_t slot[100]; +} stack_frame_t; + + +/* Paramter passing. + s : gpr 3 + l : gpr 4 + d : fpr 1 +*/ +void __attribute__ ((noinline)) fcld (char *s, long l, double d) +{ + reg_parms_t lparms; + save_parms (lparms); + + if (s != (char *) lparms.gprs[0]) + abort (); + + if (l != lparms.gprs[1]) + abort (); + + if (d != lparms.fprs[0]) + abort (); +} + +/* Paramter passing. + s : gpr 3 + l : gpr 4 + d : fpr 2 + i : gpr 5 +*/ +void __attribute__ ((noinline)) +fcldi (char *s, long l, double d, signed int i) +{ + reg_parms_t lparms; + save_parms (lparms); + + if (s != (char *) lparms.gprs[0]) + abort (); + + if (l != lparms.gprs[1]) + abort (); + + if (d != lparms.fprs[0]) + abort (); + + if ((signed long) i != lparms.gprs[3]) + abort (); +} + +/* Paramter passing. + s : gpr 3 + l : gpr 4 + d : fpr 2 + i : gpr 5 +*/ +void __attribute__ ((noinline)) +fcldu (char *s, long l, float d, unsigned int i) +{ + reg_parms_t lparms; + save_parms (lparms); + + if (s != (char *) lparms.gprs[0]) + abort (); + + if (l != lparms.gprs[1]) + abort (); + + if ((double) d != lparms.fprs[0]) + abort (); + + if ((unsigned long) i != lparms.gprs[3]) + abort (); +} + +/* Paramter passing. + s : gpr 3 + l : slot 1 + d : slot 2 +*/ + +void __attribute__ ((noinline)) fceld (char *s, ...) +{ + stack_frame_t *sp; + reg_parms_t lparms; + va_list arg; + double d; + long l; + save_parms (lparms); + + va_start (arg, s); + + if (s != (char *) lparms.gprs[0]) + abort (); + + l = va_arg (arg, long); + d = va_arg (arg, double); + + /* Go back one frame. */ + sp = __builtin_frame_address (0); + sp = sp->backchain; + + if (sp->slot[1].l != l) + abort (); + + if (sp->slot[2].d != d) + abort (); +} + +/* Paramter passing. + s : gpr 3 + i : gpr 4 + j : gpr 5 + d : slot 3 + l : slot 4 +*/ +void __attribute__ ((noinline)) fciiedl (char *s, int i, int j, ...) +{ + stack_frame_t *sp; + reg_parms_t lparms; + va_list arg; + double d; + long l; + save_parms (lparms); + + va_start (arg, j); + + if (s != (char *) lparms.gprs[0]) + abort (); + + if ((long) i != lparms.gprs[1]) + abort (); + + if ((long) j != lparms.gprs[2]) + abort (); + + d = va_arg (arg, double); + l = va_arg (arg, long); + + sp = __builtin_frame_address (0); + sp = sp->backchain; + + if (sp->slot[3].d != d) + abort (); + + if (sp->slot[4].l != l) + abort (); +} + +/* +Parameter Register Offset in parameter save area +c r3 0-7 (not stored in parameter save area) +ff f1 8-15 (not stored) +d r5 16-23 (not stored) +ld f2 24-31 (not stored) +f r7 32-39 (not stored) +s r8,r9 40-55 (not stored) +gg f3 56-63 (not stored) +t (none) 64-79 (stored in parameter save area) +e (none) 80-87 (stored) +hh f4 88-95 (stored) + +*/ + +typedef struct +{ + int a; + double dd; +} sparm; + +typedef union +{ + int i[2]; + long l; + double d; +} double_t; + +/* Example from ABI documentation with slight changes. + Paramter passing. + c : gpr 3 + ff : fpr 1 + d : gpr 5 + ld : fpr 2 + f : gpr 7 + s : gpr 8 - 9 + gg : fpr 3 + t : save area offset 64 - 79 + e : save area offset 80 - 88 + hh : fpr 4 +*/ + +void __attribute__ ((noinline)) +fididisdsid (int c, double ff, int d, double ld, int f, + sparm s, double gg, sparm t, int e, double hh) +{ + stack_frame_t *sp; + reg_parms_t lparms; + double_t dx, dy; + + save_parms (lparms); + + /* Parm 0: int. */ + if ((long) c != lparms.gprs[0]) + abort (); + + /* Parm 1: double. */ + if (ff != lparms.fprs[0]) + abort (); + + /* Parm 2: int. */ + if ((long) d != lparms.gprs[2]) + abort (); + + /* Parm 3: double. */ + if (ld != lparms.fprs[1]) + abort (); + + /* Parm 4: int. */ + if ((long) f != lparms.gprs[4]) + abort (); + + /* Parm 5: struct sparm. */ + dx.l = lparms.gprs[5]; + dy.l = lparms.gprs[6]; + + if (s.a != dx.i[0]) + abort (); + if (s.dd != dy.d) + abort (); + + /* Parm 6: double. */ + if (gg != lparms.fprs[2]) + abort (); + + sp = __builtin_frame_address (0); + sp = sp->backchain; + + /* Parm 7: struct sparm. */ + dx.l = sp->slot[8].l; + dy.l = sp->slot[9].l; + if (t.a != dx.i[0]) + abort (); + if (t.dd != dy.d) + abort (); + + /* Parm 8: int. */ + if (e != sp->slot[10].l) + abort (); + + /* Parm 9: double. */ + + if (hh != lparms.fprs[3]) + abort (); +} + +int +main () +{ + char *s = "ii"; + + fcld (s, 1, 1.0); + fcldi (s, 1, 1.0, -2); + fcldu (s, 1, 1.0, 2); + fceld (s, 1, 1.0); + fciiedl (s, 1, 2, 1.0, 3); + fididisdsid (1, 1.0, 2, 2.0, -1, (sparm) + { + 3, 3.0}, 4.0, (sparm) + { + 5, 5.0}, 6, 7.0); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c b/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c new file mode 100644 index 00000000000..93ce7195d0c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c @@ -0,0 +1,404 @@ +/* { dg-do run { target powerpc64-*-linux* } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -fprofile -mprofile-kernel -maltivec -mabi=altivec" } */ +#include <stdarg.h> +#include <signal.h> +#include <altivec.h> +#include <stdlib.h> + +/* Testcase to check for ABI compliance of parameter passing + for the PowerPC64 ABI. */ + +void __attribute__((no_instrument_function)) +sig_ill_handler (int sig) +{ + exit(0); +} + +extern void abort (void); + +typedef struct +{ + unsigned long gprs[8]; + double fprs[13]; + long pad; + vector int vrs[12]; +} reg_parms_t; + +reg_parms_t gparms; + +/* _mcount call is done on Linux ppc64 early in the prologue. + my_mcount will provide a entry point _mcount, + which will save all register to gparms. + Note that _mcount need to restore lr to original value, + therefor use ctr to return. +*/ + +void __attribute__((no_instrument_function)) +my_mcount() +{ + asm volatile (".type _mcount,@function\n\t" + ".globl _mcount\n\t" + "_mcount:\n\t" + "mflr 0\n\t" + "mtctr 0\n\t" + "ld 0,16(1)\n\t" + "mtlr 0\n\t" + "ld 11,gparms@got(2)\n\t" + "std 3,0(11)\n\t" + "std 4,8(11)\n\t" + "std 5,16(11)\n\t" + "std 6,24(11)\n\t" + "std 7,32(11)\n\t" + "std 8,40(11)\n\t" + "std 9,48(11)\n\t" + "std 10,56(11)\n\t" + "stfd 1,64(11)\n\t" + "stfd 2,72(11)\n\t" + "stfd 3,80(11)\n\t" + "stfd 4,88(11)\n\t" + "stfd 5,96(11)\n\t" + "stfd 6,104(11)\n\t" + "stfd 7,112(11)\n\t" + "stfd 8,120(11)\n\t" + "stfd 9,128(11)\n\t" + "stfd 10,136(11)\n\t" + "stfd 11,144(11)\n\t" + "stfd 12,152(11)\n\t" + "stfd 13,160(11)\n\t" + "li 3,176\n\t" + "stvx 2,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 3,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 4,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 5,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 6,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 7,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 8,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 9,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 10,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 11,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 12,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 13,3,11\n\t" + "ld 3,0(11)\n\t" + "bctr"); +} + +/* Stackframe structure relevant for parameter passing. */ +typedef union +{ + double d; + unsigned long l; + unsigned int i[2]; +} parm_t; + +typedef struct sf +{ + struct sf *backchain; + long a1; + long a2; + long a3; + long a4; + long a5; + parm_t slot[100]; +} stack_frame_t; + +typedef union +{ + unsigned int i[4]; + unsigned long l[2]; + vector int v; +} vector_int_t; + +/* Paramter passing. + s : gpr 3 + v : vpr 2 + i : gpr 7 +*/ +void __attribute__ ((noinline)) +fcvi (char *s, vector int v, int i) +{ + reg_parms_t lparms = gparms; + + if (s != (char *) lparms.gprs[0]) + abort(); + + if (!vec_all_eq (v, lparms.vrs[0])) + abort (); + + if ((long) i != lparms.gprs[4]) + abort(); +} +/* Paramter passing. + s : gpr 3 + v : vpr 2 + w : vpr 3 +*/ + +void __attribute__ ((noinline)) +fcvv (char *s, vector int v, vector int w) +{ + vector int a, c = {6, 8, 10, 12}; + reg_parms_t lparms = gparms; + + if (s != (char *) lparms.gprs[0]) + abort(); + + if (!vec_all_eq (v, lparms.vrs[0])) + abort (); + + if (!vec_all_eq (w, lparms.vrs[1])) + abort (); + + a = vec_add (v,w); + + if (!vec_all_eq (a, c)) + abort (); +} + +/* Paramter passing. + s : gpr 3 + i : gpr 4 + v : vpr 2 + w : vpr 3 +*/ +void __attribute__ ((noinline)) +fcivv (char *s, int i, vector int v, vector int w) +{ + vector int a, c = {6, 8, 10, 12}; + reg_parms_t lparms = gparms; + + if (s != (char *) lparms.gprs[0]) + abort(); + + if ((long) i != lparms.gprs[1]) + abort(); + + if (!vec_all_eq (v, lparms.vrs[0])) + abort (); + + if (!vec_all_eq (w, lparms.vrs[1])) + abort (); + + a = vec_add (v,w); + + if (!vec_all_eq (a, c)) + abort (); +} + +/* Paramter passing. + s : gpr 3 + v : slot 2-3 + w : slot 4-5 +*/ + +void __attribute__ ((noinline)) +fcevv (char *s, ...) +{ + vector int a, c = {6, 8, 10, 12}; + vector int v,w; + stack_frame_t *sp; + reg_parms_t lparms = gparms; + va_list arg; + + va_start (arg, s); + + if (s != (char *) lparms.gprs[0]) + abort(); + + v = va_arg(arg, vector int); + w = va_arg(arg, vector int); + a = vec_add (v,w); + + if (!vec_all_eq (a, c)) + abort (); + + /* Go back one frame. */ + sp = __builtin_frame_address(0); + sp = sp->backchain; + + if (sp->slot[2].l != 0x100000002ULL + || sp->slot[4].l != 0x500000006ULL) + abort(); +} + +/* Paramter passing. + s : gpr 3 + i : gpr 4 + j : gpr 5 + v : slot 4-5 + w : slot 6-7 +*/ +void __attribute__ ((noinline)) +fciievv (char *s, int i, int j, ...) +{ + vector int a, c = {6, 8, 10, 12}; + vector int v,w; + stack_frame_t *sp; + reg_parms_t lparms = gparms; + va_list arg; + + va_start (arg, j); + + if (s != (char *) lparms.gprs[0]) + abort(); + + if ((long) i != lparms.gprs[1]) + abort(); + + if ((long) j != lparms.gprs[2]) + abort(); + + v = va_arg(arg, vector int); + w = va_arg(arg, vector int); + a = vec_add (v,w); + + if (!vec_all_eq (a, c)) + abort (); + + sp = __builtin_frame_address(0); + sp = sp->backchain; + + if (sp->slot[4].l != 0x100000002ULL + || sp->slot[6].l != 0x500000006ULL) + abort(); +} + +void __attribute__ ((noinline)) +fcvevv (char *s, vector int x, ...) +{ + vector int a, c = {7, 10, 13, 16}; + vector int v,w; + stack_frame_t *sp; + reg_parms_t lparms = gparms; + va_list arg; + + va_start (arg, x); + + v = va_arg(arg, vector int); + w = va_arg(arg, vector int); + + a = vec_add (v,w); + a = vec_add (a, x); + + if (!vec_all_eq (a, c)) + abort (); + + sp = __builtin_frame_address(0); + sp = sp->backchain; + + if (sp->slot[4].l != 0x100000002ULL + || sp->slot[6].l != 0x500000006ULL) + abort(); +} + +int __attribute__((no_instrument_function, noinline)) +main1() +{ + char *s = "vv"; + vector int v = {1, 2, 3, 4}; + vector int w = {5, 6, 7, 8}; + + fcvi (s, v, 2); + fcvv (s, v, w); + fcivv (s, 1, v, w); + fcevv (s, v, w); + fciievv (s, 1, 2, v, w); + fcvevv (s, v, v, w); + return 0; +} + +int __attribute__((no_instrument_function)) +main() +{ + /* Exit on systems without altivec. */ + signal (SIGILL, sig_ill_handler); + /* Altivec instruction, 'vor %v0,%v0,%v0'. */ + asm volatile (".long 0x10000484"); + signal (SIGILL, SIG_DFL); + + return main1 (); +} + +/* Paramter passing. + Function called with no prototype. + s : gpr 3 + v : vpr 2 gpr 5-6 + w : vpr 3 gpr 7-8 + x : vpr 4 gpr 9-10 + y : vpr 5 slot 8-9 +*/ +void +fnp_cvvvv (char *s, vector int v, vector int w, + vector int x, vector int y) +{ + vector int a, c = {12, 16, 20, 24}; + reg_parms_t lparms = gparms; + stack_frame_t *sp; + vector_int_t v0, v1, v2, v3; + + if (s != (char *) lparms.gprs[0]) + abort(); + + if (!vec_all_eq (v, lparms.vrs[0])) + abort (); + + if (!vec_all_eq (w, lparms.vrs[1])) + abort (); + + if (!vec_all_eq (x, lparms.vrs[2])) + abort (); + + if (!vec_all_eq (y, lparms.vrs[3])) + abort (); + + a = vec_add (v,w); + a = vec_add (a,x); + a = vec_add (a,y); + + if (!vec_all_eq (a, c)) + abort (); + + v0.v = lparms.vrs[0]; + v1.v = lparms.vrs[1]; + v2.v = lparms.vrs[2]; + v3.v = lparms.vrs[3]; + + if (v0.l[0] != lparms.gprs[2]) + abort (); + + if (v0.l[1] != lparms.gprs[3]) + abort (); + + if (v1.l[0] != lparms.gprs[4]) + abort (); + + if (v1.l[1] != lparms.gprs[5]) + abort (); + + if (v2.l[0] != lparms.gprs[6]) + abort (); + + if (v2.l[1] != lparms.gprs[7]) + abort (); + + sp = __builtin_frame_address(0); + sp = sp->backchain; + + if (sp->slot[8].l != v3.l[0]) + abort (); + + if (sp->slot[9].l != v3.l[1]) + abort (); +} + diff --git a/gcc/testsuite/gcc.target/powerpc/ppc64-abi-3.c b/gcc/testsuite/gcc.target/powerpc/ppc64-abi-3.c new file mode 100644 index 00000000000..346839c4f89 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc64-abi-3.c @@ -0,0 +1,30 @@ +/* { dg-do compile { target powerpc64-*-linux* } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-Wall" } */ +/* Testcase to check for ABI compliance of parameter passing + for the PowerPC64 ABI. */ + +typedef int __attribute__((vector_size(16))) v4si; +typedef int __attribute__((vector_size(8))) v2si; + +v4si +f(v4si v) +{ /* { dg-error "altivec instructions are disabled" "PR18631" { xfail *-*-* } } */ + return v; +} + +v2si +g(v2si v) +{ + return v; +} + +int +main() +{ + v4si v; + v2si w; + v = f (v); /* { dg-error "altivec instructions are disabled" "PR18631" { xfail *-*-* } } */ + w = g (w); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/ppc64-toc.c b/gcc/testsuite/gcc.target/powerpc/ppc64-toc.c new file mode 100644 index 00000000000..ed555a9b6d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ppc64-toc.c @@ -0,0 +1,22 @@ +/* { dg-do link } */ +/* { dg-options "-mminimal-toc" { target { powerpc64-*-* && lp64 } } } */ + +char *strchr (const char *, int); + +int +foo (int a) +{ + int b; + + b = 0; + if ("/"[1] != '\0') + if (strchr ("/", a)) + b = 1; + return b; +} + +int +main (void) +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr16155.c b/gcc/testsuite/gcc.target/powerpc/pr16155.c new file mode 100644 index 00000000000..64df264d0b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr16155.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-maltivec -ansi" } */ + +/* PR 16155 + * Compilation of a simple altivec test program fails if the -ansi flag is + * given to gcc, when compiling with -maltivec. + */ + +#include <altivec.h> + +void foo(void) +{ + vector unsigned short a, b; + a = vec_splat(b, 0); +} + +/* { dg-bogus "parse error before \"typeof\"" "-maltivec -mansi" { target powerpc*-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr16286.c b/gcc/testsuite/gcc.target/powerpc/pr16286.c new file mode 100644 index 00000000000..99b52d7f9cd --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr16286.c @@ -0,0 +1,26 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-maltivec" } */ + +/* PR 16286 + Compilation of a simple Altivec test program fails if vector, pixel + and/or bool are #undefined when compiling with -maltivec. This may be + done for building C++ programs that use the STL <vector>. */ + +#include <altivec.h> +#undef vector +#undef pixel +#undef bool + +void test(void) +{ + __vector unsigned int a, b; + __vector __pixel v0; + __vector __bool v1; + + a = vec_and(a, b); + vec_step (b); +} + +/* { dg-bogus "(syntax|parse) error before \"vector\"" "-maltivec" { target powerpc*-*-* } 0 } */ +/* { dg-bogus "(syntax|parse) error before \"pixel\"" "-maltivec" { target powerpc*-*-* } 0 } */ +/* { dg-bogus "(syntax|parse) error before \"bool\"" "-maltivec" { target powerpc*-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr18096-1.c b/gcc/testsuite/gcc.target/powerpc/pr18096-1.c new file mode 100644 index 00000000000..b11f71ae984 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr18096-1.c @@ -0,0 +1,12 @@ +/* PR middle-end/18096 */ +/* { dg-do compile { target powerpc-*-* } } */ +/* { dg-options "-O2" } */ + +void f(char*); + +void mkcatdefs(char *fname) +{ + char line [2147483647]; + f(line); +} /* { dg-warning "stack frame too large" "stack frame too large" } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/rs6000-fpint-2.c b/gcc/testsuite/gcc.target/powerpc/rs6000-fpint-2.c new file mode 100644 index 00000000000..66bb61d2536 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rs6000-fpint-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target powerpc*-*-darwin* powerpc*-*-linux* } } */ +/* { dg-options "-mno-powerpc-gfxopt -mpowerpc64" } */ +extern void bar (void *); +extern double x; +void +foo (void) +{ + char buf2 [32][1024]; + bar (buf2 [(int) x]); +} + diff --git a/gcc/testsuite/gcc.target/powerpc/rs6000-fpint.c b/gcc/testsuite/gcc.target/powerpc/rs6000-fpint.c new file mode 100644 index 00000000000..410f780de8b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rs6000-fpint.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target powerpc*-*-* rs6000-*-* } } */ +/* { dg-options "-mno-powerpc-gfxopt" } */ +/* { dg-final { scan-assembler-not "stfiwx" } } */ + +/* A basic test of the old-style (not stfiwx) fp -> int conversion. */ +int f(double a, double b) +{ + int a1 = a; + int b1 = b; + return a1+b1; +} diff --git a/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-1.c b/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-1.c new file mode 100644 index 00000000000..0c11a271a80 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-1.c @@ -0,0 +1,26 @@ +/* { dg-do run { target powerpc*-*-darwin* powerpc*-*-aix* powerpc64-*-linux rs6000-*-* } } */ +/* { dg-options "-mlong-double-128" } */ + +/* Check that long double values are rounded correctly when being converted + to 32-bit integers. All these values are of the form +/- 2 +/- 2^-60. */ + +extern void abort(void); +extern void exit(int); + +int main(void) +{ + long double l1 = 1.9999999999999999991326382620115964527941L; + long double l2 = 2.0000000000000000008673617379884035472059L; + long double l3 = -2.0000000000000000008673617379884035472059L; + long double l4 = -1.9999999999999999991326382620115964527941L; + + if ((int) l1 != 1) + abort (); + if ((int) l2 != 2) + abort (); + if ((int) l3 != -2) + abort (); + if ((int) l4 != -1) + abort (); + exit (0); +} diff --git a/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-2.c b/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-2.c new file mode 100644 index 00000000000..3ef5131b966 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-2.c @@ -0,0 +1,22 @@ +/* { dg-do run { target powerpc*-*-darwin* powerpc*-*-aix* powerpc64-*-linux rs6000-*-* } } */ +/* { dg-options "-mlong-double-128" } */ + +/* Check that LDBL_EPSILON is right for 'long double'. */ + +#include <float.h> + +extern void abort (void); + +int main(void) +{ + volatile long double ee = 1.0; + long double eps = ee; + while (ee + 1.0 != 1.0) + { + eps = ee; + ee = eps / 2; + } + if (eps != LDBL_EPSILON) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/rs6000-power2-1.c b/gcc/testsuite/gcc.target/powerpc/rs6000-power2-1.c new file mode 100644 index 00000000000..193647ef781 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rs6000-power2-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target powerpc-*-* rs6000-*-* } } */ +/* { dg-options "-O3 -mcpu=power2 -fno-schedule-insns -w -mhard-float" } */ +/* This used to ICE as the peephole was not checking to see + if the register is a floating point one (I think this cannot + happen in real life except in this example). */ + +register volatile double t1 __asm__("r14"); +register volatile double t2 __asm__("r15"); +register volatile double t3 __asm__("r16"), t4 __asm__("r17"); +void t(double *a, double *b) +{ + t1 = a[-1]; + t2 = a[0]; + t3 = a[1]; + t4 = a[2]; + b[-1] = t1; + b[0] = t2; + b[1] = t3; + b[2] = t4; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/rs6000-power2-2.c b/gcc/testsuite/gcc.target/powerpc/rs6000-power2-2.c new file mode 100644 index 00000000000..c5c7c7b8fe3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/rs6000-power2-2.c @@ -0,0 +1,22 @@ +/* { dg-do compile { target powerpc-*-* rs6000-*-* } } */ +/* { dg-options "-O3 -mcpu=power2 -fno-schedule-insns -w -mhard-float" } */ +/* { dg-final { scan-assembler-not "lfd" } } */ +/* { dg-final { scan-assembler-not "sfd" } } */ +/* { dg-final { scan-assembler "lfq" } } */ +/* { dg-final { scan-assembler "stfq" } } */ + +register volatile double t1 __asm__("fr0"); +register volatile double t2 __asm__("fr1"); +register volatile double t3 __asm__("fr2"), t4 __asm__("fr3"); +void t(double *a, double *b) +{ + t1 = a[-1]; + t2 = a[0]; + t3 = a[1]; + t4 = a[2]; + b[-1] = t1; + b[0] = t2; + b[1] = t3; + b[2] = t4; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/spe1.c b/gcc/testsuite/gcc.target/powerpc/spe1.c new file mode 100644 index 00000000000..9ce56e08d54 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/spe1.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target powerpc-*-eabi* } } */ +/* { dg-options "-mcpu=8540 -mabi=spe -O0" } */ + +/* (Test with -O0 so we don't optimize any of them away). */ + + +typedef float __attribute__((vector_size(8))) __ev64_fs__; + +static __ev64_opaque__ Foo (void); + +void Bar () +{ + __ev64_fs__ fs = Foo (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/stabs-attrib-vect-darwin.c b/gcc/testsuite/gcc.target/powerpc/stabs-attrib-vect-darwin.c new file mode 100644 index 00000000000..d380f8e8d00 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/stabs-attrib-vect-darwin.c @@ -0,0 +1,11 @@ +/* Test Attribute Vector associated with vector type stabs. */ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-options "-gstabs -fno-eliminate-unused-debug-types -faltivec" } */ + +int main () +{ + vector int vi = { 6,7,8,9 }; + return 0; +} + +/* { dg-final { scan-assembler ".stabs.*vi\:\\(0,16\\)=\@V" } } */ |