| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Initial Grand Ridge support | Hu, Lin1 | 2022-11-07 | 1 | -0/+6 |
| * | Support Intel RAO-INT | konglin1 | 2022-11-07 | 1 | -0/+2 |
| * | Initial Granite Rapids Support | Haochen Jiang | 2022-11-07 | 1 | -0/+9 |
| * | Support Intel prefetchit0/t1 | Haochen Jiang | 2022-11-07 | 1 | -0/+2 |
| * | Support Intel AMX-FP16 ISA | Hongyu Wang | 2022-11-04 | 1 | -0/+5 |
| * | Initial Sierra Forest Support | Haochen Jiang | 2022-11-04 | 1 | -0/+6 |
| * | Support Intel CMPccXADD | Haochen Jiang | 2022-11-04 | 1 | -0/+2 |
| * | Support Intel AVX-NE-CONVERT | konglin1 | 2022-10-31 | 1 | -0/+2 |
| * | i386: add reset_cpu_feature | Martin Liska | 2022-10-26 | 1 | -5/+33 |
| * | Enable AMD znver4 support and add instruction reservations | Tejas Joshi | 2022-10-21 | 1 | -1/+15 |
| * | Support Intel AVX-VNNI-INT8 | Kong Lingling | 2022-10-21 | 1 | -0/+2 |
| * | Support Intel AVX-IFMA | Hongyu Wang | 2022-10-21 | 1 | -0/+2 |
| * | Initial Meteorlake Support | Hu, Lin1 | 2022-10-17 | 1 | -0/+4 |
| * | Initial Raptorlake Support | Haochen Jiang | 2022-10-17 | 1 | -0/+2 |
| * | x86: Require AVX for F16C and VAES | H.J. Lu | 2022-06-13 | 1 | -4/+4 |
| * | [x86_64]: Zhaoxin lujiazui enablement | Mayshao | 2022-05-23 | 1 | -1/+53 |
| * | i386: simplify cpu_feature handling | Martin Liska | 2022-05-11 | 1 | -22/+28 |
| * | x86: Properly check FEATURE_AESKLE | H.J. Lu | 2022-03-21 | 1 | -2/+2 |
| * | x86: Update model value for Alderlake and Rocketlake | Cui,Lili | 2022-01-04 | 1 | -0/+2 |
| * | Update copyright years. | Jakub Jelinek | 2022-01-03 | 1 | -1/+1 |
| * | i386: support micro-levels in target{,_clone} attrs [PR101696] | Martin Liska | 2021-09-13 | 1 | -0/+48 |
| * | AVX512FP16: Initial support for AVX512FP16 feature and scalar _Float16 instru... | Guo, Xuepeng | 2021-09-08 | 1 | -0/+2 |
| * | Add rocketlake to gcc. | Cui,Lili | 2021-04-12 | 1 | -2/+8 |
| * | Change march=alderlake ISA list and add m_ALDERLAKE to m_CORE_AVX2 | Cui,Lili | 2021-04-12 | 1 | -0/+1 |
| * | Update copyright years. | Jakub Jelinek | 2021-01-04 | 1 | -1/+1 |
| * | Fix feature check for HRESET/AVX_VNNI/UINTR | Hongyu | 2020-12-11 | 1 | -10/+15 |
| * | X86_64: Enable support for next generation AMD Zen3 CPU. | Venkataramanan Kumar | 2020-12-05 | 1 | -0/+17 |
| * | Support Intel AVX VNNI | liuhongt | 2020-11-11 | 1 | -0/+2 |
| * | Enable GCC to support Intel Key Locker ISA | liuhongt | 2020-10-29 | 1 | -0/+19 |
| * | Enable Intel HRESET Instruction | Hongyu Wang | 2020-10-15 | 1 | -0/+3 |
| * | Enable gcc support for UINTR | liuhongt | 2020-10-15 | 1 | -0/+2 |
| * | Enable GCC support for AMX-TILE,AMX-INT8,AMX-BF16. | liuhongt | 2020-09-28 | 1 | -0/+16 |
| * | x86: Detect Rocket Lake and Alder Lake | H.J. Lu | 2020-08-19 | 1 | -0/+10 |
| * | Initial Sapphire Rapids and Alder Lake support from ISA r40 | Cui,Lili | 2020-07-10 | 1 | -0/+8 |
| * | x86: Remove brand ID check for Intel processors | H.J. Lu | 2020-06-24 | 1 | -7/+5 |
| * | x86: Add Cooper Lake detection with AVX512BF16 | H.J. Lu | 2020-06-24 | 1 | -1/+9 |
| * | x86: Move cpuinfo.h from libgcc to common/config/i386 | H.J. Lu | 2020-06-24 | 1 | -0/+844 |
