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* Initial Grand Ridge supportHu, Lin12022-11-071-1/+1
* Support Intel RAO-INTkonglin12022-11-071-1/+2
* Initial Granite Rapids SupportHaochen Jiang2022-11-071-1/+1
* Support Intel prefetchit0/t1Haochen Jiang2022-11-071-1/+1
* Remove support for Intel MIC offloadingThomas Schwinge2022-11-041-8/+0
* Support Intel AMX-FP16 ISAHongyu Wang2022-11-041-1/+1
* Initial Sierra Forest SupportHaochen Jiang2022-11-041-1/+2
* Support Intel CMPccXADDHaochen Jiang2022-11-041-1/+2
* Support Intel AVX-NE-CONVERTkonglin12022-10-311-1/+1
* d: Remove D-specific version definitions from target headersIain Buclaw2022-10-291-4/+20
* RISC-V: Support load/store in mov<mode> pattern for RVV modes.Ju-Zhe Zhong2022-10-261-1/+1
* MIPS: add builtime option for -mcompact-branchesYunQiang Su2022-10-251-2/+11
* Enable AMD znver4 support and add instruction reservationsTejas Joshi2022-10-211-1/+9
* RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests.Ju-Zhe Zhong2022-10-211-1/+1
* RISC-V: Add RVV intrinsic basic framework.Ju-Zhe Zhong2022-10-211-0/+2
* Support Intel AVX-VNNI-INT8Kong Lingling2022-10-211-1/+1
* Support Intel AVX-IFMAHongyu Wang2022-10-211-1/+2
* gcc: Add 'mcf' thread model support from mcfgthreadLIU Hao2022-10-191-0/+3
* elf: ELF toolchain --without-{headers, newlib} should provide stdint.hArsen Arsenovic2022-10-171-0/+5
* Generic configury support for shared libs on VxWorksOlivier Hainque2022-10-111-0/+9
* MIPS: improve -march=native arch detectionYunQiang Su2022-10-091-0/+2
* RISC-V: Introduce RVV header to enable builtin typesJu-Zhe Zhong2022-10-051-0/+1
* Define GCC_DRIVER_HOST_INITIALIZATION for VxWorks targetsMarc Poulhiès2022-10-021-0/+2
* aarch64: Small config.gcc cleanupsRichard Sandiford2022-09-291-8/+0
* RISC-V: Add ABI-defined RVV types.Ju-Zhe Zhong2022-09-291-0/+1
* nvptx: Allow '--with-arch' to override the default '-misa'Thomas Schwinge2022-09-261-0/+5
* nvptx: Introduce dummy multilib option for default '-misa=sm_30'Thomas Schwinge2022-09-261-0/+1
* nvptx: Make default '-misa=sm_30' explicitThomas Schwinge2022-09-261-0/+16
* RISC-V: Support poly move manipulation and selftests.zhongjuzhe2022-09-231-1/+1
* d: Fix #error You must define PREFERRED_DEBUGGING_TYPE if DWARF is not supportedIain Buclaw2022-09-021-4/+6
* STABS: remove -gstabs and -gxcoff functionalityMartin Liska2022-09-021-116/+116
* 32-bit PA-RISC with HP-UX: remove deprecated portsMartin Liska2022-08-311-82/+3
* cr16: remove leftover in config.gccMartin Liska2022-08-311-7/+1
* m32c-rtems: remove obsoleted portMartin Liska2022-08-301-6/+0
* arm: Define with_float to hard when target name ends with hfChristophe Lyon2022-08-171-0/+7
* Remove long deprecated tilegx and tilepro portsJeff Law2022-06-251-29/+1
* amdgcn: Add gfx90a supportAndrew Stubbs2022-05-241-1/+1
* [x86_64]: Zhaoxin lujiazui enablementMayshao2022-05-231-1/+9
* AArch64: Cleanup CPU option processing codeWilco Dijkstra2022-05-201-42/+1
* IBM zSystems: Add support for z16 as CPU name.Andreas Krebbel2022-04-121-1/+1
* RISC-V: Support -misa-spec for arch-canonicalize and multilib-generator. [PR1...Kito Cheng2022-04-111-1/+2
* aarch64: PR target/105157 Increase number of cores TARGET_CPU_DEFAULT can encodeAndre Vieira2022-04-081-1/+1
* LoongArch Port: gcc buildchenglulu2022-03-291-1/+434
* [nvptx] Add nvptx-gen.h and nvptx-gen.optTom de Vries2022-03-011-0/+1
* RISC-V: Always pass -misa-spec to assembler [PR104219]Kito Cheng2022-02-051-1/+3
* rs6000: Consolidate target built-ins codeBill Schmidt2022-02-031-1/+1
* RISC-V: Change default ISA version into 20191213Jia-Wei Chen2022-01-241-4/+4
* Manual changes for .cc renaming.Martin Liska2022-01-171-1/+1
* Change references of .c files to .cc filesMartin Liska2022-01-171-20/+20
* Include elfos.h before ${tm_file}.Martin Liska2022-01-121-1/+1
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