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path: root/gcc/config/aarch64/aarch64.c
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* * config/aarch64/aarch64.c (aarch64_emit_probe_stack_range): Handlelaw2017-06-221-5/+13
* 2017-06-21 Andrew Pinski <apinski@cavium.com>pinskia2017-06-211-10/+50
* 2017-06-21 Andrew Pinski <apinski@cavium.com>pinskia2017-06-211-5/+48
* Mark symbols as constantwilco2017-06-211-0/+5
* Update prefetch tuning parameters for qdf24xx.mkuvyrkov2017-06-161-4/+4
* Enable -fprefetch-loop-arrays at given optimization level.mkuvyrkov2017-06-161-4/+17
* Add prefetch configuration to aarch64 backend.mkuvyrkov2017-06-161-25/+77
* PR target/71663naveenh2017-06-141-4/+51
* 2017-06-07 Tamar Christina <tamar.christina@arm.com>tnfchris2017-06-071-8/+6
* [PATCH][AArch64] Allow CMP+SHIFT when comparing with zerojgreenhalgh2017-06-021-1/+1
* [AArch64] Emit tighter strong atomic compare-exchange loop when comparing aga...ktkachov2017-06-021-6/+35
* [PATCH][AARCH64]Simplify call, call_value, sibcall, sibcall_value patterns.renlin2017-05-151-0/+44
* Many supported cores use the AUTOPREFETCHER_WEAK setting which trieswilco2017-05-041-1/+1
* Set jump alignment to 4 for Cortex cores as it reduces codesize by 0.4% onwilco2017-05-041-5/+5
* With -mcpu=generic the loop alignment is currently 4. All but one of thewilco2017-05-041-2/+2
* All cores which add a cpu_addrcost_table use a non-zero value forwilco2017-05-041-2/+2
* [AArch64] Accept more addressing modes for PRFMktkachov2017-05-041-0/+18
* [AArch64] Fix for gcc-7 regression PR 80530rearnsha2017-04-271-22/+29
* PR target/77728jakub2017-04-271-69/+21
* PR target/77728jakub2017-04-251-26/+75
* Error message on target attribute on aarch64 target (PR target/79889).marxin2017-04-071-2/+6
* PR target/78002ebotcazou2017-04-051-18/+15
* Recently we've put a lot of effort into improving ifcvt to use CSEL on AArch64.wilco2017-03-221-2/+2
* Many supported cores implement fusion of AES instructions. When fusionwilco2017-03-221-1/+1
* aarch64.c: tweaks to quoting in error messages (PR target/79925)dmalcolm2017-03-111-5/+5
* [AArch64] Fix bootstrap due to wide_int .elt (0) uninit warningktkachov2017-03-031-1/+1
* [Patch AArch64] Use 128-bit vectors when autovectorizing 16-bit float typesjgreenhalgh2017-02-141-0/+4
* [AArch64] PR rtl-optimization/68664 Implement TARGET_SCHED_CAN_SPECULATE_INSN...ktkachov2017-02-141-0/+32
* [AArch64] Use contains_mem_rtx_p to detect memory sub-rtxesktkachov2017-02-131-16/+1
* 2017-02-02 Naveen H.S <Naveen.Hurugalawadi@cavium.com>naveenh2017-02-031-1/+1
* 2017-02-01 Andrew Pinski <apinski@cavium.com>pinskia2017-02-011-26/+43
* 2017-01-23 Andrew Pinski <apinski@cavium.com>pinskia2017-01-241-3/+3
* 2017-01-23 Andreas Tobler <andreast@gcc.gnu.org>andreast2017-01-231-2/+8
* [AArch64][2/4] Generate dwarf information for -msign-return-addressjiwang2017-01-201-2/+10
* [AArch64][1/4] Support Return address protection on AArch64jiwang2017-01-201-0/+44
* gcc/tnfchris2017-01-191-2/+4
* SHA1H instructions may be scheduled after a SHA1C instructionwilco2017-01-181-0/+23
* This patch simplifies the handling of EH return. We force the use of thewilco2017-01-171-42/+35
* PR ada/67205ebotcazou2017-01-171-0/+4
* 2017-01-09 Andrew Pinski <apinski@cavium.com>pinskia2017-01-091-10/+10
* Introduce RTL function readerdmalcolm2017-01-051-0/+53
* Update copyright years.jakub2017-01-011-1/+1
* 2016-12-14 Andrew Pinski <apinski@cavium.com>pinskia2016-12-141-1/+1
* This patch fixes an issue in aarch64_classify_address. TImode and TFmodewilco2016-12-081-1/+4
* 2016-12-08 Naveen H.S <Naveen.Hurugalawadi@cavium.com>naveenh2016-12-081-2/+6
* 2016-12-08 Andrew Pinski <apinski@cavium.com>naveenh2016-12-081-1/+2
* Improve TI mode address offsets - these may either use LDP of 64-bit orwilco2016-12-071-13/+15
* 2016-12-07 Naveen H.S <Naveen.Hurugalawadi@cavium.com>naveenh2016-12-071-0/+39
* [AArch64] Separate shrink wrapping hooks implementationktkachov2016-12-021-24/+272
* [Patch AArch64 13/17] Enable _Float16 for AArch64jgreenhalgh2016-11-241-2/+69
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