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* [PATCH 1/2] [AARCH64,NEON] Add patterns + builtins for vld[234](q?)_lane_* in...cbaylis2014-10-241-0/+3
* PR target/63173fyang2014-10-241-0/+3
* [AArch64] Enable shrink wrapping.mshawcroft2014-09-231-0/+13
* [PATCH AArch64]: Add constraint letter for stack_protect_test patternjgreenhalgh2014-09-191-1/+1
* Fix PR63190vekumar2014-09-071-2/+2
* [PATCH][AArch64] One-liner: fix type of an add in SIMD registersalalaw012014-09-051-1/+1
* [AArch64 Obvious] Add a mode to operand 1 of sibcall_value_insnjgreenhalgh2014-09-051-1/+2
* [AArch64] Use CC_Z and CC_NZ with csinc and similar instructions.ktkachov2014-09-021-19/+15
* PR target/62262carrot2014-08-271-1/+2
* [AArch64] Restrict usage of FP/SIMD registers for TImode reload and absdi2 pa...ktkachov2014-08-071-10/+21
* [AArch64][2/2] Add constrain to address offset in storewb_pair/loadwb_pair insnsjiwang2014-08-011-4/+4
* [AArch64][1/2] Fix offset glitch in load reg pair patternjiwang2014-08-011-10/+8
* 2014-07-26 Andrew Pinski <apinski@cavium.com>pinskia2014-07-271-1/+1
* [AArch64] Simplify epilogue expansion using new helper functions.mshawcroft2014-07-231-0/+16
* [AArch64] Simplify prologue expand using new helper functions.mshawcroft2014-07-231-0/+16
* [AArch64][1/2] Remove UNSPEC_CLS and use clrsb RTL code in its' place.ktkachov2014-07-221-2/+1
* 2014-07-17 Terry Guo <terry.guo@arm.com>xguo2014-07-171-19/+19
* * aarch64.md (add_losym_<mode>): Set type to alu_imm.rearnsha2014-07-141-1/+1
* [AArch64] Fix register clobber in, aarch64_ashr_sisd_or_int_<mode>3 split.mshawcroft2014-06-301-11/+16
* Re: [AArch64] Implement ADD in vector registers for 32-bit scalar values.jgreenhalgh2014-06-231-1/+2
* [AArch64] Implement ADD in vector registers for 32-bit scalar values.jgreenhalgh2014-06-231-4/+5
* -fuse-caller-save - Enable for AArch64vries2014-06-181-2/+50
* PR target/61545rth2014-06-181-0/+1
* [AArch64] Implement CRC32 ACLE intrinsics.ktkachov2014-06-111-0/+25
* [AArch64] Fix some reg-to-reg move scheduler types.ktkachov2014-06-101-4/+4
* [AArch64] Implement movmem for the benefit of inline memcpyjgreenhalgh2014-06-061-0/+18
* [AArch64] Remove ISB after FPCR write.mshawcroft2014-06-021-1/+1
* 2014-05-27 Andrew Pinski <apinski@cavium.com>pinskia2014-05-281-5/+5
* [AARCH64] Support tail indirect function call.mshawcroft2014-05-231-9/+20
* 2014-05-23 Kugan Vivekanandarajah <kuganv@linaro.org>kugan2014-05-221-0/+35
* 2014-04-29 Zhenqiang Chen <zhenqiang.chen@linaro.org>zqchen2014-04-291-0/+19
* [AArch64] Improve vst4_lane intrinsicsjgreenhalgh2014-04-281-0/+3
* [AARCH64] Use standard patterns for stack protection.mshawcroft2014-04-231-0/+63
* [AArch64] Fully support rotate on logical operations.mshawcroft2014-04-231-1/+24
* [AArch64][2/3] Recognise rev16 operations on SImode and DImode dataktkachov2014-04-231-0/+32
* AArch64 add, sub, mul in TImoderth2014-04-221-5/+84
* [AArch64] Fix TLS for ILP32.mshawcroft2014-04-221-12/+39
* gcc/ChangeLog:vp2014-04-221-10/+14
* [AArch64] vrnd<*>_f64 patchmshawcroft2014-04-221-1/+1
* [AArch64] Logical vector shift right conformancejgreenhalgh2014-03-241-0/+1
* [PATCH][AArch64] Vector shift by 64 fixjgreenhalgh2014-01-231-0/+1
* [AArch64_BE 1/4] Big-Endian lane numbering fixktkachov2014-01-231-0/+2
* PR target/9744rearnsha2014-01-101-2/+2
* Update copyright years in gcc/rsandifo2014-01-021-1/+1
* 2013-12-06 Andrew Pinski <apinski@cavium.com>pinskia2013-12-061-0/+6
* [AArch64] Remove "mode", "mode2" attributesjgreenhalgh2013-11-201-392/+201
* [PATCH] [AArch64] Fix whitespace around aarch64_movdi_<mode>lowmshawcroft2013-11-191-3/+3
* [AArch64] Remove v8type attribute.jgreenhalgh2013-11-191-573/+208
* [AArch64] Remove simd_typejgreenhalgh2013-11-151-31/+17
* [AArch64] [-mtune cleanup 4/5] Remove "example-1", "example-2" tuning options.jgreenhalgh2013-11-141-3/+1
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