| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [AArch64] Tighten predicates on SIMD shift intrinsics | jgreenhalgh | 2014-09-25 | 1 | -2/+11 |
| * | [AArch64] Auto-generate the "BUILTIN_" macros for aarch64-builtins.c | jgreenhalgh | 2014-09-22 | 1 | -0/+3 |
| * | [AArch64] Simplify vreinterpret for float64x1_t using casts. | alalaw01 | 2014-09-11 | 1 | -3/+0 |
| * | PR target/62040 | carrot | 2014-09-04 | 1 | -0/+6 |
| * | PR/60825 Make float64x1_t in arm_neon.h a proper vector type | alalaw01 | 2014-06-23 | 1 | -2/+5 |
| * | [AArch64] Fix some saturating math NEON intrinsics types. | ktkachov | 2014-06-20 | 1 | -12/+4 |
| * | [AArch64] Implement CRC32 ACLE intrinsics. | ktkachov | 2014-06-11 | 1 | -0/+14 |
| * | Recognize shuffle patterns for REV instructions on AArch64, rewrite intrinsics. | alalaw01 | 2014-06-03 | 1 | -0/+9 |
| * | Detect EXT patterns to vec_perm_const, use for EXT intrinsics | alalaw01 | 2014-05-29 | 1 | -0/+1 |
| * | [AArch64] Improve vst4_lane intrinsics | jgreenhalgh | 2014-04-28 | 1 | -0/+26 |
| * | [AArch64] Vectorise bswap[16,32,64] | ktkachov | 2014-04-24 | 1 | -0/+6 |
| * | gcc/ChangeLog: | vp | 2014-04-22 | 1 | -2/+10 |
| * | Update copyright years in gcc/ | rsandifo | 2014-01-02 | 1 | -1/+1 |
| * | Implement support for AArch64 Crypto PMULL.64. | belagod | 2013-12-19 | 1 | -0/+2 |
| * | Implement support for AArch64 Crypto SHA256. | belagod | 2013-12-19 | 1 | -0/+8 |
| * | Implement support for AArch64 Crypto SHA1. | belagod | 2013-12-19 | 1 | -0/+11 |
| * | Implement support for AArch64 Crypto AES. | belagod | 2013-12-19 | 1 | -0/+10 |
| * | [AArch64] [3/4 Fix vtbx1]Implement bsl intrinsics using builtins | jgreenhalgh | 2013-11-26 | 1 | -1/+6 |
| * | 2013-11-22 Tejas Belagod <tejas.belagod@arm.com> | belagod | 2013-11-22 | 1 | -1/+10 |
| * | [AArch64] [Neon types 4/10] Add type attributes to all simd insns | jgreenhalgh | 2013-10-15 | 1 | -6/+16 |
| * | [AArch64] [Neon types 2/10] Update Current type attributes to new Neon Types. | jgreenhalgh | 2013-10-15 | 1 | -0/+9 |
| * | [AArch64] Improve arm_neon.h vml<as>_lane handling. | jgreenhalgh | 2013-09-16 | 1 | -0/+3 |
| * | [AArch64] Implement vmul<q>_lane<q>_<fsu><16,32,64> intrinsics in C | jgreenhalgh | 2013-09-16 | 1 | -1/+23 |
| * | [AArch64] Rewrite the vdup_lane intrinsics in C | jgreenhalgh | 2013-09-02 | 1 | -1/+15 |
| * | [AArch64] Fixup the vget_lane RTL patterns and intrinsics | jgreenhalgh | 2013-08-09 | 1 | -0/+15 |
| * | AArch64 support for NEG in vector registers for DI and SI mode (part 2) | ibolton | 2013-07-26 | 1 | -0/+6 |
| * | [AArch64, ILP32] 2/6 More backend changes and support for small absolute and | yufeng | 2013-07-23 | 1 | -1/+7 |
| * | * config/aarch64/aarch64-simd.md (aarch64_combine<mode>): convert to split. | sofiane | 2013-06-12 | 1 | -1/+2 |
| * | [AArch64] Fix vcond where comparison and result have different types. | jgreenhalgh | 2013-05-14 | 1 | -0/+3 |
| * | [AArch64] Refactor reduc_<su>plus patterns. | jgreenhalgh | 2013-05-01 | 1 | -1/+5 |
| * | [AArch64] Refactor vector max and min RTL and builtins. | jgreenhalgh | 2013-05-01 | 1 | -19/+37 |
| * | [AArch64] Add combiner patterns for FAC instructions | jgreenhalgh | 2013-05-01 | 1 | -0/+3 |
| * | [AArch64] Improve description of <F>CM instructions in RTL | jgreenhalgh | 2013-05-01 | 1 | -23/+38 |
| * | [AArch64] Add vector fix, fixuns, fix_trunc, fixuns_trunc standard patterns | jgreenhalgh | 2013-04-29 | 1 | -0/+5 |
| * | [AArch64] Add vector int to float conversions. | jgreenhalgh | 2013-04-29 | 1 | -0/+6 |
| * | [AArch64] Map fcvt intrinsics to builtin name directly. | jgreenhalgh | 2013-04-29 | 1 | -2/+3 |
| * | [AArch64] Map frint intrinsics to standard pattern names directly. | jgreenhalgh | 2013-04-29 | 1 | -3/+6 |
| * | [AArch64] Describe the 'BSL' RTL pattern more accurately. | jgreenhalgh | 2013-04-25 | 1 | -1/+0 |
| * | [AArch64] Support vrecp<esx> neon intrinsics in RTL. | jgreenhalgh | 2013-04-22 | 1 | -0/+4 |
| * | * config/aarch64/aarch64.md (*mov<mode>_aarch64): Add alternatives for | sofiane | 2013-04-02 | 1 | -0/+3 |
| * | 2013-01-25 Tejas Belagod <tejas.belagod@arm.com> | belagod | 2013-01-25 | 1 | -0/+16 |
| * | [AArch64] Fix unordered comparisons to floating-point vcond. | jgreenhalgh | 2013-01-18 | 1 | -0/+8 |
| * | 2013-01-14 Tejas Belagod <tejas.belagod@arm.com> | belagod | 2013-01-14 | 1 | -0/+3 |
| * | Update copyright years in gcc/ | rsandifo | 2013-01-10 | 1 | -1/+1 |
| * | [AARCH64] Add zip{1, 2}, uzp{1, 2}, trn{1, 2} support | jgreenhalgh | 2012-12-05 | 1 | -0/+16 |
| * | [AARCH64] Implement Vector Permute Support. | jgreenhalgh | 2012-12-05 | 1 | -1/+4 |
| * | [AARCH64] Add support for vectorizable standard math patterns. | jgreenhalgh | 2012-12-05 | 1 | -0/+25 |
| * | gcc/ | jgreenhalgh | 2012-11-20 | 1 | -1/+15 |
| * | 2012-10-30 James Greenhalgh <james.greenhalgh@arm.com> | jgreenhalgh | 2012-10-30 | 1 | -0/+1 |
| * | AArch64 [3/10] | mshawcroft | 2012-10-23 | 1 | -0/+716 |
