| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Update copyright years. | jakub | 2016-01-04 | 1 | -1/+1 |
| * | 2015-12-02 David Sherwood <david.sherwood@arm.com> | davids | 2015-12-02 | 1 | -0/+10 |
| * | [AArch64] Add sqrdmah, sqrdmsh instructions. | mwahab | 2015-11-26 | 1 | -0/+6 |
| * | 2015-11-24 Michael Collison <michael.collison@linaro.org> | collison | 2015-11-25 | 1 | -0/+12 |
| * | [AArch64][v2] Improve comparison with complex immediates followed by branch/cset | ktkachov | 2015-11-24 | 1 | -1/+2 |
| * | [AArch64] Move iterators from atomics.md to iterators.md | mwahab | 2015-11-10 | 1 | -0/+33 |
| * | [AArch64][2/3] Implement negcc, notcc optabs | ktkachov | 2015-11-10 | 1 | -0/+6 |
| * | [AARCH64][PATCH 1/3] Implementing the variants of the vmulx_ NEON intrinsic | jgreenhalgh | 2015-11-03 | 1 | -0/+1 |
| * | [AArch64_be] Fix vtbl[34] and vtbx4 | clyon | 2015-10-12 | 1 | -0/+1 |
| * | gcc/ChangeLog: | kugan | 2015-10-06 | 1 | -0/+1 |
| * | [AArch64 array_mode 7/8] Combine the expanders using VSTRUCT:nregs | alalaw01 | 2015-09-15 | 1 | -0/+3 |
| * | [AArch64 array_mode 6/8] Remove V_TWO_ELEM, again using BLKmode + set_mem_size. | alalaw01 | 2015-09-15 | 1 | -10/+0 |
| * | [AArch64 array_mode 5/8] Remove V_FOUR_ELEM, again using BLKmode + set_mem_size. | alalaw01 | 2015-09-15 | 1 | -10/+0 |
| * | [AArch64 array_mode 3/8] Stop using EImode in aarch64-simd.md and iterators.md | alalaw01 | 2015-09-15 | 1 | -9/+0 |
| * | [AArch64 array_mode 2/8] Remove VSTRUCT_DREG, use BLKmode for d-reg aarch64_s... | alalaw01 | 2015-09-15 | 1 | -2/+0 |
| * | [AArch64] Handle literal pools for functions > 1 MiB in size. | ramana | 2015-09-14 | 1 | -0/+3 |
| * | Remove separate movtf pattern - Use an iterator for all FP modes. | ramana | 2015-09-11 | 1 | -2/+2 |
| * | [AArch64] Add vcvt(_high)?_f32_f16 intrinsics, with BE RTL fix | alalaw01 | 2015-09-08 | 1 | -5/+13 |
| * | [AArch64] Improve code generation for float16 vector code | alalaw01 | 2015-09-08 | 1 | -1/+6 |
| * | [AArch64] Implement vcvt_{,high_}f16_f32 | alalaw01 | 2015-09-08 | 1 | -1/+9 |
| * | [AArch64] vld{2,3,4}{,_lane,_dup}, vcombine, vcreate | alalaw01 | 2015-09-08 | 1 | -6/+12 |
| * | [AArch64] Add support for float16x{4,8}_t vectors/builtins | alalaw01 | 2015-09-08 | 1 | -8/+28 |
| * | 2015-08-27 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | thopre01 | 2015-08-27 | 1 | -0/+6 |
| * | gcc/ | mwahab | 2015-08-14 | 1 | -3/+10 |
| * | [AArch64] Removed unused VRL2/3/4 iterator values | alalaw01 | 2015-07-30 | 1 | -12/+3 |
| * | [AArch64] Add basic FP16 support | alalaw01 | 2015-07-29 | 1 | -0/+3 |
| * | [AArch64][2/2] Implement -fpic for -mcmodel=small | jiwang | 2015-06-26 | 1 | -0/+4 |
| * | [PATCH][AARCH64]Define vec_shr as an unspec, use shl for big-endian. | renlin | 2015-04-30 | 1 | -0/+1 |
| * | [Patch AArch64] Make integer vabs intrinsics UNSPECs | jgreenhalgh | 2015-01-28 | 1 | -0/+1 |
| * | [AArch64] Improve bit-test-branch pattern to avoid unnecessary register clobber | jiwang | 2015-01-27 | 1 | -0/+3 |
| * | gcc/ | rsandifo | 2015-01-21 | 1 | -0/+3 |
| * | Update copyright years. | jakub | 2015-01-05 | 1 | -1/+1 |
| * | [AArch64 3/3] Fix XOR_one_cmpl pattern; add SIMD-reg variants for BIC,ORN,EON | alalaw01 | 2014-12-19 | 1 | -0/+3 |
| * | [AArch64 2/3] Add SIMD-reg variants of logical operators and/ior/xor/not | alalaw01 | 2014-12-19 | 1 | -1/+2 |
| * | * config/aarch64/arm_neon.h (vrecpe_u32, vrecpeq_u32): Rewrite using | fyang | 2014-12-08 | 1 | -0/+3 |
| * | [AArch64] Remove/merge redundant iterators | alalaw01 | 2014-12-03 | 1 | -26/+1 |
| * | [AArch64] Add vector pattern for __builtin_ctz | jiwang | 2014-11-21 | 1 | -0/+6 |
| * | gcc/: | alalaw01 | 2014-11-17 | 1 | -3/+0 |
| * | [AArch64] Fix predicate and constraint mismatch in logical atomic operations | clyon | 2014-11-04 | 1 | -0/+3 |
| * | [AArch64] Use new reduc_plus_scal optabs, inc. for __builtins | alalaw01 | 2014-10-27 | 1 | -5/+1 |
| * | [AArch64] Tighten predicates on SIMD shift intrinsics | jgreenhalgh | 2014-09-25 | 1 | -2/+11 |
| * | [AArch64] Auto-generate the "BUILTIN_" macros for aarch64-builtins.c | jgreenhalgh | 2014-09-22 | 1 | -0/+3 |
| * | [AArch64] Simplify vreinterpret for float64x1_t using casts. | alalaw01 | 2014-09-11 | 1 | -3/+0 |
| * | PR target/62040 | carrot | 2014-09-04 | 1 | -0/+6 |
| * | PR/60825 Make float64x1_t in arm_neon.h a proper vector type | alalaw01 | 2014-06-23 | 1 | -2/+5 |
| * | [AArch64] Fix some saturating math NEON intrinsics types. | ktkachov | 2014-06-20 | 1 | -12/+4 |
| * | [AArch64] Implement CRC32 ACLE intrinsics. | ktkachov | 2014-06-11 | 1 | -0/+14 |
| * | Recognize shuffle patterns for REV instructions on AArch64, rewrite intrinsics. | alalaw01 | 2014-06-03 | 1 | -0/+9 |
| * | Detect EXT patterns to vec_perm_const, use for EXT intrinsics | alalaw01 | 2014-05-29 | 1 | -0/+1 |
| * | [AArch64] Improve vst4_lane intrinsics | jgreenhalgh | 2014-04-28 | 1 | -0/+26 |
