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* Update copyright years.jakub2016-01-041-1/+1
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@232055 138bc75d-0d04-0410-961f-82ee72b054a4
* 2015-12-02 David Sherwood <david.sherwood@arm.com>davids2015-12-021-0/+10
| | | | | | | | | | | | | gcc/ * config/aarch64/aarch64.md: New pattern. * config/aarch64/aarch64-simd.md: Likewise. * config/aarch64/iterators.md: New unspecs, iterators. gcc/testsuite * gcc.target/aarch64/fmaxmin.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@231187 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64] Add sqrdmah, sqrdmsh instructions.mwahab2015-11-261-0/+6
| | | | | | | | | | | | | | | | * config/aarch64/aarch64-simd.md (aarch64_sqmovun<mode>): Fix some white-space. (aarch64_<sur>qmovun<mode>): Likewise. (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h<mode>): New. (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): New. (aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): New. * config/aarch64/iterators.md (UNSPEC_SQRDMLAH): New. (UNSPEC_SQRDMLSH): New. (SQRDMLH_AS): New. (rdma_as): New. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@230959 138bc75d-0d04-0410-961f-82ee72b054a4
* 2015-11-24 Michael Collison <michael.collison@linaro.org>collison2015-11-251-0/+12
| | | | | | | | | | | | | | | | | | * config/aarch64/aarch64-simd.md (widen_ssum, widen_usum) (aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>_internal): New patterns * config/aarch64/iterators.md (Vhalf, VDBLW): New mode attributes. * gcc.target/aarch64/saddw-1.c: New test. * gcc.target/aarch64/saddw-2.c: New test. * gcc.target/aarch64/uaddw-1.c: New test. * gcc.target/aarch64/uaddw-2.c: New test. * gcc.target/aarch64/uaddw-3.c: New test. * lib/target-support.exp (check_effective_target_vect_widen_sum_hi_to_si_pattern): Add aarch64 to list of support targets. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@230853 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64][v2] Improve comparison with complex immediates followed by branch/csetktkachov2015-11-241-1/+2
| | | | | | | | | | | | | | | | | * config/aarch64/aarch64.md (*condjump): Rename to... (condjump): ... This. (*compare_condjump<mode>): New define_insn_and_split. (*compare_cstore<mode>_insn): Likewise. (*cstore<mode>_insn): Rename to... (cstore<mode>_insn): ... This. * config/aarch64/iterators.md (CMP): Handle ne code. * config/aarch64/predicates.md (aarch64_imm24): New predicate. * gcc.target/aarch64/cmpimm_branch_1.c: New test. * gcc.target/aarch64/cmpimm_cset_1.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@230805 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64] Move iterators from atomics.md to iterators.mdmwahab2015-11-101-0/+33
| | | | | | | | | | | | | * config/aarch64/atomics.md (unspecv): Move to iterators.md. (ATOMIC_LDOP): Likewise. (atomic_ldop): Likewise. * config/aarch64/iterators.md (unspecv): Moved from atomics.md. (ATOMIC_LDOP): Likewise. (atomic_ldop): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@230114 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64][2/3] Implement negcc, notcc optabsktkachov2015-11-101-0/+6
| | | | | | | | | | | | * config/aarch64/aarch64.md (<neg_not_op><mode>cc): New define_expand. * config/aarch64/iterators.md (NEG_NOT): New code iterator. (neg_not_op): New code attribute. * gcc.target/aarch64/cond_op_imm_1.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@230090 138bc75d-0d04-0410-961f-82ee72b054a4
* [AARCH64][PATCH 1/3] Implementing the variants of the vmulx_ NEON intrinsicjgreenhalgh2015-11-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc/ * config/aarch64/aarch64-simd-builtins.def (fmulx): New. * config/aarch64/aarch64-simd.md (aarch64_fmulx<mode>): New. * config/aarch64/arm_neon.h (vmulx_f32): Rewrite to call fmulx builtin. (vmulxq_f32): Likewise. (vmulx_f64): New. (vmulxq_f64): Rewrite to call fmulx builtin. (vmulxs_f32): Likewise. (vmulxd_f64): Likewise. (vmulx_lane_f32): Remove. * config/aarch64/iterators.md (UNSPEC): Add fmulx. gcc/testsuite/ * gcc/testsuite/gcc.target/aarch64/simd/vmulx_f32_1.c: New. * gcc/testsuite/gcc.target/aarch64/simd/vmulx_f64_1.c: New. * gcc/testsuite/gcc.target/aarch64/simd/vmulxq_f32_1.c: New. * gcc/testsuite/gcc.target/aarch64/simd/vmulxq_f64_1.c: New. * gcc/testsuite/gcc.target/aarch64/simd/vmulxs_f32_1.c: New. * gcc/testsuite/gcc.target/aarch64/simd/vmulxd_f64_1.c: New. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@229702 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64_be] Fix vtbl[34] and vtbx4clyon2015-10-121-0/+1
| | | | | | | | | | | | | | | | | 2015-10-12 Christophe Lyon <christophe.lyon@linaro.org> * config/aarch64/aarch64-simd-builtins.def: Update builtins tables: add tbl3 and tbx4. * config/aarch64/aarch64-simd.md (aarch64_tbl3v8qi): New. (aarch64_tbx4v8qi): New. * config/aarch64/arm_neon.h (vtbl3_s8, vtbl3_u8, vtbl3_p8) (vtbl4_s8, vtbl4_u8, vtbl4_p8, vtbx4_s8, vtbx4_u8, vtbx4_p8): Rewrite using builtin functions. * config/aarch64/iterators.md (UNSPEC_TBX): New. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228716 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/ChangeLog:kugan2015-10-061-0/+1
| | | | | | | | | | | | | | | | | 2015-10-07 Kugan Vivekanandarajah <kuganv@linaro.org> * config/aarch64/iterators.md (vwcore): Add missing cases for V4HF/V8HF modes. gcc/testsuite/ChangeLog: 2015-10-07 Kugan Vivekanandarajah <kuganv@linaro.org> * gcc.target/aarch64/get_lane_f16_1.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228547 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64 array_mode 7/8] Combine the expanders using VSTRUCT:nregsalalaw012015-09-151-0/+3
| | | | | | | | | | | | | | | | * config/aarch64/aarch64-simd.md (aarch64_ld2r<mode>, aarch64_ld3r<mode>, aarch64_ld4r<mode>): Combine together, making... (aarch64_simd_ld<VSTRUCT:nregs>r<VALLDIF:mode>): ...this. (aarch64_ld2_lane<mode>, aarch64_ld3_lane<mode>, aarch64_ld4_lane<mode>): Combine together, making... (aarch64_ld<VSTRUCT:nregs>_lane<VALLDIF:mode>): ...this. (aarch64_st2_lane<mode>, aarch64_st3_lane<mode>, aarch64_st4_lane<mode>): Combine together, making... (aarch64_st<VSTRUCT:nregs>_lane<VALLDIF:mode>): ...this. * config/aarch64/iterators.md (nregs): Add comment. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@227793 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64 array_mode 6/8] Remove V_TWO_ELEM, again using BLKmode + set_mem_size.alalaw012015-09-151-10/+0
| | | | | | | | | | | | | | * config/aarch64/aarch64-simd.md (aarch64_simd_ld2r<mode>): Change operand mode from <V_TWO_ELEM> to BLK. (aarch64_vec_load_lanesoi_lane<mode>): Likewise. (aarch64_vec_store_lanesoi_lane<mode): Likewise (aarch64_ld2r<mode>): Generate MEM rtx with BLKmode, call set_mem_size. (aarch64_ld2_lane<mode>): Likewise. (aarch64_st2_lane<VQ:mode>): Likewise. * config/aarch64/iterators.md (V_TWO_ELEM): Remove. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@227790 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64 array_mode 5/8] Remove V_FOUR_ELEM, again using BLKmode + set_mem_size.alalaw012015-09-151-10/+0
| | | | | | | | | | | | | | * config/aarch64/aarch64-simd.md (aarch64_simd_ld4r<mode>): Change operand mode from <V_FOUR_ELEM> to BLK. (aarch64_vec_load_lanesxi_lane<mode>): Likewise. (aarch64_vec_store_lanesxi_lane<mode): Likewise. (aarch64_ld4r<mode>): Generate MEM rtx with BLKmode, call set_mem_size. (aarch64_ld4_lane<mode>): Likewise. (aarch64_st4_lane<mode>): Likewise. * config/aarch64/iterators.md (V_FOUR_ELEM): Remove. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@227789 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64 array_mode 3/8] Stop using EImode in aarch64-simd.md and iterators.mdalalaw012015-09-151-9/+0
| | | | | | | | | | | | | | * config/aarch64/aarch64-simd.md (aarch64_simd_ld3r<mode>): Change operand mode from <V_THREE_ELEM> to BLK. (aarch64_vec_load_lanesci_lane<mode>): Likewise. (aarch64_vec_store_lanesci_lane<mode>): Likewise. (aarch64_ld3r<mode>): Generate MEM rtx with BLKmode, call set_mem_size. (aarch64_ld3_lane<mode>): Likewise. (aarch64_st3_lane<mode>): Likewise. * config/aarch64/iterators.md (V_THREE_ELEM): Remove. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@227783 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64 array_mode 2/8] Remove VSTRUCT_DREG, use BLKmode for d-reg ↵alalaw012015-09-151-2/+0
| | | | | | | | | | | | | | | | | | | | | aarch64_st/ld expands * config/aarch64/aarch64-simd.md (aarch64_ld2<mode>_dreg VD & DX, aarch64_st2<mode>_dreg VD & DX ): Change all TImode operands to BLKmode. (aarch64_ld3<mode>_dreg VD & DX, aarch64_st3<mode>_dreg VD & DX): Change all EImode operands to BLKmode. (aarch64_ld4<mode>_dreg VD & DX, aarch64_st4<mode>_dreg VD & DX): Change all OImode operands to BLKmode. (aarch64_ld<VSTRUCT:nregs><VDC:mode>): Generate MEM rtx with BLKmode and call set_mem_size. (aarch64_st<VSTRUCT:nregs><VDC:mode>): Likewise * config/aarch64/iterators.md (VSTRUCT_DREG): Remove. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@227782 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64] Handle literal pools for functions > 1 MiB in size.ramana2015-09-141-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the issue in PR63304 where we have functions that are > 1MiB. The idea is to use adrp / ldr or adrp / add instructions to address the literal pools under the use of a command line option. I would like to turn this on by default on trunk but keep this disabled by default for the release branches in order to get some serious testing for this feature while it bakes on trunk. As a follow-up I would like to try and see if estimate_num_insns or something else can give us a heuristic to turn this on for "large" functions. After all the number of incidences of this are quite low in real life, so may be we should look to restrict this use as much as possible on the grounds that this code generation implies an extra integer register for addressing for every floating point and vector constant and I don't think that's great in code that already may have high register pressure. Tested on aarch64-none-elf with no regressions. A previous version was bootstrapped and regression tested. Applied to trunk. regards Ramana 2015-09-14 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> PR target/63304 * config/aarch64/aarch64.c (aarch64_expand_mov_immediate): Handle nopcrelative_literal_loads. (aarch64_classify_address): Likewise. (aarch64_constant_pool_reload_icode): Define. (aarch64_secondary_reload): Handle secondary reloads for literal pools. (aarch64_override_options): Handle nopcrelative_literal_loads. (aarch64_classify_symbol): Handle nopcrelative_literal_loads. * config/aarch64/aarch64.md (aarch64_reload_movcp<GPF_TF:mode><P:mode>): Define. (aarch64_reload_movcp<VALL:mode><P:mode>): Likewise. * config/aarch64/aarch64.opt (mpc-relative-literal-loads): New option. * config/aarch64/predicates.md (aarch64_constant_pool_symref): New predicate. * doc/invoke.texi (mpc-relative-literal-loads): Document. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@227748 138bc75d-0d04-0410-961f-82ee72b054a4
* Remove separate movtf pattern - Use an iterator for all FP modes.ramana2015-09-111-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | movtf is unnecessary as a separate expander. Move this to be with the standard scalar floating point expanders. Achieved by adding a new iterator and then using the same. Tested cross aarch64-none-elf and no regressions. Rebased version from https://gcc.gnu.org/ml/gcc-patches/2015-09/msg00767.html 2015-09-10 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> PR target/63304 * config/aarch64/aarch.md (mov<mode>:GPF_F16): Use GPF_TF_F16. (movtf): Delete. * config/aarch64/iterators.md (GPF_TF_F16): New. (GPF_F16): Delete. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@227679 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64] Add vcvt(_high)?_f32_f16 intrinsics, with BE RTL fixalalaw012015-09-081-5/+13
| | | | | | | | | | | | | | | | | | | | | | gcc/: * config/aarch64/aarch64-simd.md (aarch64_simd_vec_unpacks_lo_<mode>, aarch64_simd_vec_unpacks_hi_<mode>): New insn. (vec_unpacks_lo_v4sf, vec_unpacks_hi_v4sf): Delete insn. (vec_unpacks_lo_<mode>, vec_unpacks_hi_<mode>): New expand. (aarch64_float_extend_lo_v2df): Rename to... (aarch64_float_extend_lo_<Vwide>): this, using VDF and so adding V4SF. * config/aarch64/aarch64-simd-builtins.def (vec_unpacks_hi): Add v8hf. (float_extend_lo): Add v4sf. * config/aarch64/arm_neon.h (vcvt_f32_f16, vcvt_high_f32_f16): New. * config/aarch64/iterators.md (VQ_HSF): New iterator. (VWIDE, Vwtype, Vhalftype): Add V8HF, V4SF. (Vwide): New mode_attr. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@227551 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64] Improve code generation for float16 vector codealalaw012015-09-081-1/+6
| | | | | | | | | | | | | | | | | | gcc/: * config/aarch64/aarch64-simd.md (aarch64_simd_dup<mode>, aarch64_dup_lane<mode>, aarch64_dup_lane_<vswap_width_name><mode>, aarch64_simd_vec_set<mode>, vec_set<mode>, vec_perm_const<mode>, vec_init<mode>, *aarch64_simd_ld1r<mode>, vec_extract<mode>): Add V4HF and V8HF variants to iterator. * config/aarch64/aarch64.c (aarch64_evpc_dup): Add V4HF and V8HF cases. * config/aarch64/iterators.md (VDQF_F16): New. (VSWAP_WIDTH, vswap_width_name): Add V4HF and V8HF cases. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@227550 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64] Implement vcvt_{,high_}f16_f32alalaw012015-09-081-1/+9
| | | | | | | | | | | | | | | | | | | | * config/aarch64/aarch64-simd.md (aarch64_float_truncate_lo_v2sf): Reparameterize to... (aarch64_float_truncate_lo_<mode>): ...this, for both V2SF and V4HF. (aarch64_float_truncate_hi_v4sf): Reparameterize to... (aarch64_float_truncate_hi_<Vdbl>): ...this, for both V4SF and V8HF. * config/aarch64/aarch64-simd-builtins.def (float_truncate_hi_): Add v8hf variant. (float_truncate_lo_): Use BUILTIN_VDF iterator. * config/aarch64/arm_neon.h (vcvt_f16_f32, vcvt_high_f16_f32): New. * config/aarch64/iterators.md (VDF, Vdtype): New. (VWIDE, Vmwtype): Add cases for V4HF and V2SF. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@227545 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64] vld{2,3,4}{,_lane,_dup}, vcombine, vcreatealalaw012015-09-081-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc/: * config/aarch64/aarch64.c (aarch64_split_simd_combine): Add V4HFmode. * config/aarch64/aarch64-builtins.c (VAR13, VAR14): New. (aarch64_scalar_builtin_types, aarch64_init_simd_builtin_scalar_types): Add __builtin_aarch64_simd_hf. * config/aarch64/arm_neon.h (float16x4x2_t, float16x8x2_t, float16x4x3_t, float16x8x3_t, float16x4x4_t, float16x8x4_t, vcombine_f16, vst2_lane_f16, vst2q_lane_f16, vst3_lane_f16, vst3q_lane_f16, vst4_lane_f16, vst4q_lane_f16, vld2_f16, vld2q_f16, vld3_f16, vld3q_f16, vld4_f16, vld4q_f16, vld2_dup_f16, vld2q_dup_f16, vld3_dup_f16, vld3q_dup_f16, vld4_dup_f16, vld4q_dup_f16, vld2_lane_f16, vld2q_lane_f16, vld3_lane_f16, vld3q_lane_f16, vld4_lane_f16, vld4q_lane_f16, vst2_f16, vst2q_f16, vst3_f16, vst3q_f16, vst4_f16, vst4q_f16, vcreate_f16): New. * config/aarch64/iterators.md (VALLDIF, Vtype, Vetype, Vbtype, V_cmp_result, v_cmp_result): Add cases for V4HF and V8HF. (VDC, Vdbl): Add V4HF. gcc/testsuite/: * gcc.target/aarch64/vldN_1.c: Add float16x4_t and float16x8_t cases. * gcc.target/aarch64/vldN_dup_1.c: Likewise. * gcc.target/aarch64/vldN_lane_1.c: Likewise. (main): update orig_data to avoid float16 NaN on bigendian. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@227543 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64] Add support for float16x{4,8}_t vectors/builtinsalalaw012015-09-081-8/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc/: * config/aarch64/aarch64.c (aarch64_vector_mode_supported_p): Support V4HFmode and V8HFmode. (aarch64_split_simd_move): Add case for V8HFmode. * config/aarch64/aarch64-builtins.c (v4hf_UP, v8hf_UP): Define. (aarch64_simd_builtin_std_type): Handle HFmode. (aarch64_init_simd_builtin_types): Include Float16x4_t and Float16x8_t. * config/aarch64/aarch64-simd.md (mov<mode>, aarch64_get_lane<mode>, aarch64_ld1<VALL:mode>, aarch64_st1<VALL:mode): Use VALL_F16 iterator. (aarch64_be_ld1<mode>, aarch64_be_st1<mode>): Use VALLDI_F16 iterator. * config/aarch64/aarch64-simd-builtin-types.def: Add Float16x4_t, Float16x8_t. * config/aarch64/aarch64-simd-builtins.def (ld1, st1): Use VALL_F16. * config/aarch64/arm_neon.h (float16x4_t, float16x8_t, float16_t): New typedefs. (vget_lane_f16, vgetq_lane_f16, vset_lane_f16, vsetq_lane_f16, vld1_f16, vld1q_f16, vst1_f16, vst1q_f16, vst1_lane_f16, vst1q_lane_f16): New. * config/aarch64/iterators.md (VD, VQ, VQ_NO2E): Add vectors of HFmode. (VALLDI_F16, VALL_F16): New. (Vmtype, VEL, VCONQ, VHALF, V_TWO_ELEM, V_THREE_ELEM, V_FOUR_ELEM, q): Add cases for V4HF and V8HF. (VDBL, VRL2, VRL3, VRL4): Add V4HF case. gcc/testsuite/: * g++.dg/abi/mangle-neon-aarch64.C: Add cases for float16x4_t and float16x8_t. * gcc.target/aarch64/vset_lane_1.c: Likewise. * gcc.target/aarch64/vld1-vst1_1.c: Likewise. * gcc.target/aarch64/vld1_lane.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@227542 138bc75d-0d04-0410-961f-82ee72b054a4
* 2015-08-27 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>thopre012015-08-271-0/+6
| | | | | | | | | | | | | | | | | | | Andre Vieira <andre.simoesdiasvieira@arm.com> gcc/ * config/aarch64/aarch64.md (*condjump): Handle functions > 1 MiB. (*cb<optab><mode>1): Likewise. (*tb<optab><mode>1): Likewise. (*cb<optab><mode>1): Likewise. * config/aarch64/iterators.md (inv_cb): New code attribute. (inv_tb): Likewise. * config/aarch64/aarch64.c (aarch64_gen_far_branch): New. * config/aarch64/aarch64-protos.h (aarch64_gen_far_branch): New. gcc/testsuite/ * gcc.target/aarch64/long_branch_1.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@227253 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/mwahab2015-08-141-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | 2015-08-14 Matthew Wahab <matthew.wahab@arm.com> PR target/67143 * config/aarch64/atomics.md (atomic_<optab><mode>): Replace 'lconst_atomic' with 'const_atomic'. (atomic_fetch_<optab><mode>): Likewise. (atomic_<optab>_fetch<mode>): Likewise. * config/aarch64/iterators.md (lconst-atomic): Move below 'const_atomic'. (const_atomic): New. gcc/testsuite/ 2015-08-14 Matthew Wahab <matthew.wahab@arm.com> Matthias Klose <doko@debian.org> PR target/67143 * gcc.c-torture/compile/pr67143.c: New * gcc.target/aarch64/atomic-op-imm.c (atomic_fetch_add_negative_RELAXED): New. (atomic_fetch_sub_negative_ACQUIRE): New. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@226895 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64] Removed unused VRL2/3/4 iterator valuesalalaw012015-07-301-12/+3
| | | | | | | | * config/aarch64/iterators.md (VRL2, VRL3, VRL4): Remove values for 128-bit vector modes. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@226408 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64] Add basic FP16 supportalalaw012015-07-291-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc/: * config/aarch64/aarch64-builtins.c (aarch64_fp16_type_node): New. (aarch64_init_builtins): Make aarch64_fp16_type_node, use for __fp16. * config/aarch64/aarch64-modes.def: Add HFmode. * config/aarch64/aarch64.h (TARGET_CPU_CPP_BUILTINS): Define __ARM_FP16_FORMAT_IEEE and __ARM_FP16_ARGS. Set bit 1 of __ARM_FP. * config/aarch64/aarch64.c (aarch64_init_libfuncs, aarch64_promoted_type): New. (aarch64_float_const_representable_p): Disable HFmode. (aarch64_mangle_type): Mangle half-precision floats to "Dh". (TARGET_PROMOTED_TYPE): Define to aarch64_promoted_type. (TARGET_INIT_LIBFUNCS): Define to aarch64_init_libfuncs. * config/aarch64/aarch64.md (mov<mode>): Include HFmode using GPF_F16. (movhf_aarch64, extendhfsf2, extendhfdf2, truncsfhf2, truncdfhf2): New. * config/aarch64/iterators.md (GPF_F16): New. gcc/testsuite/: * gcc.target/aarch64/f16_movs_1.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@226346 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64][2/2] Implement -fpic for -mcmodel=smalljiwang2015-06-261-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2015-06-26 Jiong Wang <jiong.wang@arm.com> gcc/ * config/aarch64/aarch64-protos.h (aarch64_symbol_type): New type SYMBOL_SMALL_GOT_28K. * config/aarch64/aarch64.md: (ldr_got_small_<mode>): Support new GOT relocation modifiers. (unspec): New enum "UNSPEC_GOTMALLPIC28K. (ldr_got_small_28k_<mode>): New. (ldr_got_small_28k_sidi): New. * config/aarch64/iterators.md (got_modifier): New mode iterator. * config/aarch64/aarch64-otps.h (aarch64_code_model): New model. * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Support SYMBOL_SMALL_GOT_28K. (aarch64_rtx_costs): Add costs for new instruction sequences. (initialize_aarch64_code_model): Initialize new model. (aarch64_classify_symbol): Recognize new model and new symbol classification. (aarch64_asm_preferred_eh_data_format): Support new model. (aarch64_load_symref_appropriately): Generate new instruction sequences for -fpic. (TARGET_USE_PSEUDO_PIC_REG): New definition. (aarch64_use_pseudo_pic_reg): New function. gcc/testsuite/ * gcc.target/aarch64/pic-small.c: New testcase. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@225017 138bc75d-0d04-0410-961f-82ee72b054a4
* [PATCH][AARCH64]Define vec_shr as an unspec, use shl for big-endian.renlin2015-04-301-0/+1
| | | | | | | | | | | | | | | | | | | | gcc/ 2015-04-30 Renlin Li <renlin.li@arm.com> * config/aarch64/aarch64-simd.md (vec_shr): Defined as an unspec. * config/aarch64/iterators.md (unspec): Add UNSPEC_VEC_SHR. gcc/testsuite/ 2015-04-30 Renlin Li <renlin.li@arm.com> Alan Lawrence <alan.lawrence@arm.com> * gcc.target/aarch64/vect-reduc-or_1.c: New. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@222635 138bc75d-0d04-0410-961f-82ee72b054a4
* [Patch AArch64] Make integer vabs intrinsics UNSPECsjgreenhalgh2015-01-281-0/+1
| | | | | | | | | | | | | | | | | gcc/ * config/aarch64/aarch64-simd.md (aarch64_abs<mode>): New. * config/aarch64/aarch64-simd-builtins.def (abs): Split by integer and floating point variants. * config/aarch64/iterators.md (unspec): Add UNSPEC_ABS. gcc/testsuite/ * gcc.target/aarch64/abs_2.c: New. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@220202 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64] Improve bit-test-branch pattern to avoid unnecessary register clobberjiwang2015-01-271-0/+3
| | | | | | | | | | | | | | | | | | 2015-01-27 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> Jiong Wang <jiong.wang@arm.com> gcc/ * config/aarch64/aarch64.md (tb<optab><mode>1): Clobber CC reg instead of scratch reg. (cb<optab><mode>1): Likewise. * config/aarch64/iterators.md (bcond): New define_code_attr. gcc/testsuite/ * gcc.dg/long_branch.c: New testcase. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@220170 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/rsandifo2015-01-211-0/+3
| | | | | | | | | | | | | | | | | | | | | 2015-01-21 David Sherwood <david.sherwood@arm.com> Tejas Belagod <Tejas.Belagod@arm.com> * config/aarch64/aarch64-protos.h (aarch64_simd_attr_length_rglist) (aarch64_reverse_mask): New decls. * config/aarch64/iterators.md (UNSPEC_REV_REGLIST): New enum. (insn_count): New mode_attr. * config/aarch64/aarch64-simd.md (vec_store_lanesoi, vec_store_lanesci) (vec_store_lanesxi, vec_load_lanesoi, vec_load_lanesci) (vec_load_lanesxi): Made ABI compliant for Big Endian targets. (aarch64_rev_reglist, aarch64_simd_ld2, aarch64_simd_ld3) (aarch64_simd_ld4, aarch64_simd_st2, aarch64_simd_st3) (aarch64_simd_st4): New patterns. * config/aarch64/aarch64.c (aarch64_simd_attr_length_rglist) (aarch64_reverse_mask): New functions. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@219959 138bc75d-0d04-0410-961f-82ee72b054a4
* Update copyright years.jakub2015-01-051-1/+1
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@219188 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64 3/3] Fix XOR_one_cmpl pattern; add SIMD-reg variants for BIC,ORN,EONalalaw012014-12-191-0/+3
| | | | | | | | | | | | | | | | | | | gcc/: * config/aarch64/aarch64.c (<LOGICAL:optab>_one_cmpl<mode>3): Reparameterize to... (<NLOGICAL:optab>_one_cmpl<mode>3): with extra SIMD-register variant. (xor_one_cmpl<mode>3): New define_insn_and_split. * config/aarch64/iterators.md (NLOGICAL): New define_code_iterator. gcc/testsuite/: * gcc.target/aarch64/eon_1.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218961 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64 2/3] Add SIMD-reg variants of logical operators and/ior/xor/notalalaw012014-12-191-1/+2
| | | | | | | | | * config/aarch64/aarch64.md (<optab><mode>3, one_cmpl<mode>2): Add SIMD-register variant. * config/aarch64/iterators.md (Vbtype): Add value for SI. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218960 138bc75d-0d04-0410-961f-82ee72b054a4
* * config/aarch64/arm_neon.h (vrecpe_u32, vrecpeq_u32): Rewrite usingfyang2014-12-081-0/+3
| | | | | | | | | | | | | | | | | | | | | | builtin functions. (vfma_f32, vfmaq_f32, vfmaq_f64, vfma_n_f32, vfmaq_n_f32, vfmaq_n_f64, vfms_f32, vfmsq_f32, vfmsq_f64): Likewise. (vhsub_s8, vhsub_u8, vhsub_s16, vhsub_u16, vhsub_s32, vhsub_u32, vhsubq_s8, vhsubq_u8, vhsubq_s16, vhsubq_u16, vhsubq_s32, vhsubq_u32, vsubhn_s16, vsubhn_u16, vsubhn_s32, vsubhn_u32, vsubhn_s64, vsubhn_u66, vrsubhn_s16, vrsubhn_u16, vrsubhn_s32, vrsubhn_u32, vrsubhn_s64, vrsubhn_u64, vsubhn_high_s16, vsubhn_high_u16, vsubhn_high_s32, vsubhn_high_u32, vsubhn_high_s64, vsubhn_high_u64, vrsubhn_high_s16, vrsubhn_high_u16, vrsubhn_high_s32, vrsubhn_high_u32, vrsubhn_high_s64, vrsubhn_high_u64): Likewise. * config/aarch64/iterators.md (VDQ_SI): New mode iterator. * config/aarch64/aarch64.md (define_c_enum "unspec"): Add UNSPEC_URECPE. * config/aarch64/aarch64-simd.md (aarch64_urecpe<mode>): New pattern. * config/aarch64/aarch64-simd-builtins.def (shsub, uhsub, subhn, rsubhn, subhn2, rsubhn2, urecpe): New builtins. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218484 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64] Remove/merge redundant iteratorsalalaw012014-12-031-26/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * config/aarch64/aarch64-simd.md (aarch64_simd_dup<mode>, orn<mode>3, bic<mode>3, add<mode>3, sub<mode>3, neg<mode>2, abs<mode>2, and<mode>3, ior<mode>3, xor<mode>3, one_cmpl<mode>2, aarch64_simd_lshr<mode> ,arch64_simd_ashr<mode>, aarch64_simd_imm_shl<mode>, aarch64_simd_reg_sshl<mode>, aarch64_simd_reg_shl<mode>_unsigned, aarch64_simd_reg_shr<mode>_signed, ashl<mode>3, lshr<mode>3, ashr<mode>3, vashl<mode>3, reduc_plus_scal_<mode>, aarch64_vcond_internal<mode><mode>, vcondu<mode><mode>, aarch64_cm<optab><mode>, aarch64_cmtst<mode>): Change VDQ to VDQ_I. (mul<mode>3): Change VDQM to VDQ_BHSI. (aarch64_simd_vec_set<mode>,vashr<mode>3, vlshr<mode>3, vec_set<mode>, aarch64_mla<mode>, aarch64_mls<mode>, <su><maxmin><mode>3, aarch64_<sur>h<addsub><mode>): Change VQ_S to VDQ_BHSI. (*aarch64_<su>mlal<mode>, *aarch64_<su>mlsl<mode>, aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>, aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>, aarch64_<sur>shll_n<mode>): Change VDW to VD_BHSI. (*aarch64_combinez<mode>, *aarch64_combinez_be<mode>): Change VDIC to VD_BHSI. * config/aarch64/aarch64-simd-builtins.def (saddl, uaddl, ssubl, usubl, saddw, uaddw, ssubw, usubw, shadd, uhadd, srhadd, urhadd, sshll_n, ushll_n): Change BUILTIN_VDW to BUILTIN_VD_BHSI. * config/aarch64/iterators.md (SDQ_I, VDQ, VQ_S, VSDQ_I_BHSI, VDQM, VDW, VDIC, VDQQHS): Remove. (Vwtype): Update comment (changing VDW to VD_BHSI). git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218310 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64] Add vector pattern for __builtin_ctzjiwang2014-11-211-0/+6
| | | | | | | | | | | | | | | | | | gcc/ * config/aarch64/iterators.md (VS): New mode iterator. (vsi2qi): New mode attribute. (VSI2QI): Likewise. * config/aarch64/aarch64-simd-builtins.def: New entry for ctz. * config/aarch64/aarch64-simd.md (ctz<mode>2): New pattern for ctz. * config/aarch64/aarch64-builtins.c (aarch64_builtin_vectorized_function): Support BUILT_IN_CTZ. gcc/testsuite/ * gcc.target/aarch64/vect_ctz_1.c: New testcase. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@217938 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/:alalaw012014-11-171-3/+0
| | | | | | | | | | | | | | | | | * config/aarch64/aarch64-builtins.c (TYPES_CREATE): Remove. * config/aarch64/aarch64-simd-builtins.def (create): Remove. * config/aarch64/aarch64-simd.md (aarch64_create<mode>): Remove. * config/aarch64/arm_neon.h (vcreate_f64, vreinterpret_f64_s64, vreinterpret_f64_u64): Replace __builtin_aarch64_createv1df with C casts. * config/aarch64/iterators.md (VD1): Remove. gcc/testsuite/: * gcc.target/aarch64/simd/vfma_f64.c: Add asm volatile memory. * gcc.target/aarch64/simd/vfms_f64.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@217662 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64] Fix predicate and constraint mismatch in logical atomic operationsclyon2014-11-041-0/+3
| | | | | | | | | | | | | | | | | | 2014-11-04 Michael Collison <michael.collison@linaro.org> * config/aarch64/iterators.md (lconst_atomic): New mode attribute to support constraints for CONST_INT in atomic operations. * config/aarch64/atomics.md (atomic_<atomic_optab><mode>): Use lconst_atomic constraint. (atomic_nand<mode>): Likewise. (atomic_fetch_<atomic_optab><mode>): Likewise. (atomic_fetch_nand<mode>): Likewise. (atomic_<atomic_optab>_fetch<mode>): Likewise. (atomic_nand_fetch<mode>): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@217076 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64] Use new reduc_plus_scal optabs, inc. for __builtinsalalaw012014-10-271-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * config/aarch64/aarch64-simd-builtins.def (reduc_splus_<mode>/VDQF, reduc_uplus_<mode>/VDQF, reduc_splus_v4sf): Remove. (reduc_plus_scal_<mode>, reduc_plus_scal_v4sf): New. * config/aarch64/aarch64-simd.md (reduc_<sur>plus_mode): Remove. (reduc_splus_<mode>, reduc_uplus_<mode>, reduc_plus_scal_<mode>): New. (reduc_<sur>plus_mode): Change SUADDV -> UNSPEC_ADDV, rename to... (aarch64_reduc_plus_internal<mode>): ...this. (reduc_<sur>plus_v2si): Change SUADDV -> UNSPEC_ADDV, rename to... (aarch64_reduc_plus_internalv2si): ...this. (reduc_splus_<mode>/V2F): Rename to... (aarch64_reduc_plus_internal<mode>): ...this. * config/aarch64/iterators.md (UNSPEC_SADDV, UNSPEC_UADDV, SUADDV): Remove. (UNSPEC_ADDV): New. (sur): Remove elements for UNSPEC_SADDV and UNSPEC_UADDV. * config/aarch64/arm_neon.h (vaddv_s8, vaddv_s16, vaddv_s32, vaddv_u8, vaddv_u16, vaddv_u32, vaddvq_s8, vaddvq_s16, vaddvq_s32, vaddvq_s64, vaddvq_u8, vaddvq_u16, vaddvq_u32, vaddvq_u64, vaddv_f32, vaddvq_f32, vaddvq_f64): Change __builtin_aarch64_reduc_[us]plus_... to __builtin_aarch64_reduc_plus_scal, remove vget_lane wrapper. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@216738 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64] Tighten predicates on SIMD shift intrinsicsjgreenhalgh2014-09-251-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc/ * config/aarch64/aarch64-protos.h (aarch64_simd_const_bounds): Delete. * config/aarch64/aarch64-simd.md (aarch64_<sur>q<r>shl<mode>): Use new predicates. (aarch64_<sur>shll2_n<mode>): Likewise. (aarch64_<sur>shr_n<mode>): Likewise. (aarch64_<sur>sra_n<mode>: Likewise. (aarch64_<sur>s<lr>i_n<mode>): Likewise. (aarch64_<sur>qshl<u>_n<mode>): Likewise. * config/aarch64/aarch64.c (aarch64_simd_const_bounds): Delete. * config/aarch64/iterators.md (ve_mode): New. (offsetlr): Remap to infix text for use in new predicates. * config/aarch64/predicates.md (aarch64_simd_shift_imm_qi): New. (aarch64_simd_shift_imm_hi): Likewise. (aarch64_simd_shift_imm_si): Likewise. (aarch64_simd_shift_imm_di): Likewise. (aarch64_simd_shift_imm_offset_qi): Likewise. (aarch64_simd_shift_imm_offset_hi): Likewise. (aarch64_simd_shift_imm_offset_si): Likewise. (aarch64_simd_shift_imm_offset_di): Likewise. (aarch64_simd_shift_imm_bitsize_qi): Likewise. (aarch64_simd_shift_imm_bitsize_hi): Likewise. (aarch64_simd_shift_imm_bitsize_si): Likewise. (aarch64_simd_shift_imm_bitsize_di): Likewise. gcc/testsuite/ * gcc.target/aarch64/simd/vqshlb_1.c: New. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215612 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64] Auto-generate the "BUILTIN_" macros for aarch64-builtins.cjgreenhalgh2014-09-221-0/+3
| | | | | | | | | | | | | gcc/ * config/aarch64/geniterators.sh: New. * config/aarch64/iterators.md (VDQF_DF): New. * config/aarch64/t-aarch64: Generate aarch64-builtin-iterators.h. * config/aarch64/aarch64-builtins.c (BUILTIN_*) Remove. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215471 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64] Simplify vreinterpret for float64x1_t using casts.alalaw012014-09-111-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * config/aarch64/aarch64-builtins.c (aarch64_types_unop_su_qualifiers, TYPES_REINTERP_SU, aarch64_types_unop_sp_qualifiers, TYPE_REINTERP_SP, aarch64_types_unop_us_qualifiers, TYPES_REINTERP_US, aarch64_types_unop_ps_qualifiers, TYPES_REINTERP_PS, BUILTIN_VD): Delete. (aarch64_fold_builtin): Remove all reinterpret cases. * config/aarch64/aarch64-protos.h (aarch64_simd_reinterpret): Delete. * config/aarch64/aarch64-simd-builtins.def (reinterpret*) : Delete. * config/aarch64/aarch64-simd.md (aarch64_reinterpretv8qi<mode>, aarch64_reinterpretv4hi<mode>, aarch64_reinterpretv2si<mode>, aarch64_reinterpretv2sf<mode>, aarch64_reinterpretdi<mode>, aarch64_reinterpretv1df<mode>, aarch64_reinterpretv16qi<mode>, aarch64_reinterpretv8hi<mode>, aarch64_reinterpretv4si<mode>, aarch64_reinterpretv4sf<mode>, aarch64_reinterpretv2di<mode>, aarch64_reinterpretv2df<mode>): Delete. * config/aarch64/aarch64.c (aarch64_simd_reinterpret): Delete. * config/aarch64/arm_neon.h (vreinterpret_p8_f64, vreinterpret_p16_f64, vreinterpret_f32_f64, vreinterpret_f64_f32, vreinterpret_f64_p8, vreinterpret_f64_p16, vreinterpret_f64_s8, vreinterpret_f64_s16, vreinterpret_f64_s32, vreinterpret_f64_u8, vreinterpret_f64_u16, vreinterpret_f64_u32, vreinterpret_s64_f64, vreinterpret_u64_f64, vreinterpret_s8_f64, vreinterpret_s16_f64, vreinterpret_s32_f64, vreinterpret_u8_f64, vreinterpret_u16_f64, vreinterpret_u32_f64): Use cast. * config/aarch64/iterators.md (VD_RE): Delete. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215180 138bc75d-0d04-0410-961f-82ee72b054a4
* PR target/62040carrot2014-09-041-0/+6
| | | | | | | | | | | | | * config/aarch64/iterators.md (VQ_NO2E, VQ_2E): New iterators. * config/aarch64/aarch64-simd.md (move_lo_quad_internal_<mode>): Split it into two patterns. (move_lo_quad_internal_be_<mode>): Likewise. * gcc.target/aarch64/pr62040.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@214905 138bc75d-0d04-0410-961f-82ee72b054a4
* PR/60825 Make float64x1_t in arm_neon.h a proper vector typealalaw012014-06-231-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc/ChangeLog: PR target/60825 * config/aarch64/aarch64.c (aarch64_simd_mangle_map): Add entry for V1DFmode. * config/aarch64/aarch64-builtins.c (aarch64_simd_builtin_type_mode): add V1DFmode (BUILTIN_VD1): New. (BUILTIN_VD_RE): Remove. (aarch64_init_simd_builtins): Add V1DF to modes/modenames. (aarch64_fold_builtin): Update reinterpret patterns, df becomes v1df. * config/aarch64/aarch64-simd-builtins.def (create): Make a v1df variant but not df. (vreinterpretv1df*, vreinterpret*v1df): New. (vreinterpretdf*, vreinterpret*df): Remove. * config/aarch64/aarch64-simd.md (aarch64_create, aarch64_reinterpret*): Generate V1DFmode pattern not DFmode. * config/aarch64/iterators.md (VD_RE): Include V1DF, remove DF. (VD1): New. * config/aarch64/arm_neon.h (float64x1_t): typedef with gcc extensions. (vcreate_f64): Remove cast, use v1df builtin. (vcombine_f64): Remove cast, get elements with gcc vector extensions. (vget_low_f64, vabs_f64, vceq_f64, vceqz_f64, vcge_f64, vgfez_f64, vcgt_f64, vcgtz_f64, vcle_f64, vclez_f64, vclt_f64, vcltz_f64, vdup_n_f64, vdupq_lane_f64, vld1_f64, vld2_f64, vld3_f64, vld4_f64, vmov_n_f64, vst1_f64): Use gcc vector extensions. (vget_lane_f64, vdupd_lane_f64, vmulq_lane_f64, ): Use gcc extensions, add range check using __builtin_aarch64_im_lane_boundsi. (vfma_lane_f64, vfmad_lane_f64, vfma_laneq_f64, vfmaq_lane_f64, vfms_lane_f64, vfmsd_lane_f64, vfms_laneq_f64, vfmsq_lane_f64): Fix type signature, use gcc vector extensions. (vreinterpret_p8_f64, vreinterpret_p16_f64, vreinterpret_f32_f64, vreinterpret_f64_f32, vreinterpret_f64_p8, vreinterpret_f64_p16, vreinterpret_f64_s8, vreinterpret_f64_s16, vreinterpret_f64_s32, vreinterpret_f64_s64, vreinterpret_f64_u8, vreinterpret_f64_u16, vreinterpret_f64_u32, vreinterpret_f64_u64, vreinterpret_s8_f64, vreinterpret_s16_f64, vreinterpret_s32_f64, vreinterpret_s64_f64, vreinterpret_u8_f64, vreinterpret_u16_f64, vreinterpret_u32_f64, vreinterpret_u64_f64): Use v1df builtin not df. gcc/testsuite/ChangeLog: * g++.dg/abi/mangle-neon-aarch64.C: Also test mangling of float64x1_t. * gcc.target/aarch64/aapcs/test_64x1_1.c: New test. * gcc.target/aarch64/aapcs/func-ret-64x1_1.c: New test. * gcc.target/aarch64/simd/ext_f64_1.c (main): Compare vector elements. * gcc.target/aarch64/vadd_f64.c: Rewrite with macro to use vector types. * gcc.target/aarch64/vsub_f64.c: Likewise. * gcc.target/aarch64/vdiv_f.c (INDEX*, RUN_TEST): Remove indexing scheme as now the same for all variants. * gcc.target/aarch64/vrnd_f64_1.c (compare_f64): Return float64_t not float64x1_t. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211892 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64] Fix some saturating math NEON intrinsics types.ktkachov2014-06-201-12/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [gcc/] * config/aarch64/iterators.md (VCOND): Handle SI and HI modes. Update comments. (VCONQ): Make comment more helpful. (VCON): Delete. * config/aarch64/aarch64-simd.md (aarch64_sqdmulh_lane<mode>): Use VCOND for operands 2. Update lane checking and flipping logic. (aarch64_sqrdmulh_lane<mode>): Likewise. (aarch64_sq<r>dmulh_lane<mode>_internal): Likewise. (aarch64_sqdmull2<mode>): Remove VCON, use VQ_HSI mode iterator. (aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal, VD_HSI): Change mode attribute of operand 3 to VCOND. (aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal, SD_HSI): Likewise. (aarch64_sqdml<SBINQOPS:as>l2_lane<mode>_internal): Likewise. (aarch64_sqdmull_lane<mode>_internal, VD_HSI): Likewise. (aarch64_sqdmull_lane<mode>_internal, SD_HSI): Likewise. (aarch64_sqdmull2_lane<mode>_internal): Likewise. (aarch64_sqdml<SBINQOPS:as>l_laneq<mode>_internal, VD_HSI: New define_insn. (aarch64_sqdml<SBINQOPS:as>l_laneq<mode>_internal, SD_HSI): Likewise. (aarch64_sqdml<SBINQOPS:as>l2_laneq<mode>_internal): Likewise. (aarch64_sqdmull_laneq<mode>_internal, VD_HSI): Likewise. (aarch64_sqdmull_laneq<mode>_internal, SD_HSI): Likewise. (aarch64_sqdmull2_laneq<mode>_internal): Likewise. (aarch64_sqdmlal_lane<mode>): Change mode attribute of penultimate operand to VCOND. Update lane flipping and bounds checking logic. (aarch64_sqdmlal2_lane<mode>): Likewise. (aarch64_sqdmlsl_lane<mode>): Likewise. (aarch64_sqdmull_lane<mode>): Likewise. (aarch64_sqdmull2_lane<mode>): Likewise. (aarch64_sqdmlal_laneq<mode>): Replace VCON usage with VCONQ. Emit aarch64_sqdmlal_laneq<mode>_internal insn. (aarch64_sqdmlal2_laneq<mode>): Emit aarch64_sqdmlal2_laneq<mode>_internal insn. Replace VCON with VCONQ. (aarch64_sqdmlsl2_lane<mode>): Replace VCON with VCONQ. (aarch64_sqdmlsl2_laneq<mode>): Likewise. (aarch64_sqdmull_laneq<mode>): Emit aarch64_sqdmull_laneq<mode>_internal insn. Replace VCON with VCONQ. (aarch64_sqdmull2_laneq<mode>): Emit aarch64_sqdmull2_laneq<mode>_internal insn. (aarch64_sqdmlsl_laneq<mode>): Replace VCON usage with VCONQ. * config/aarch64/arm_neon.h (vqdmlal_high_lane_s16): Change type of 3rd argument to int16x4_t. (vqdmlalh_lane_s16): Likewise. (vqdmlslh_lane_s16): Likewise. (vqdmull_high_lane_s16): Likewise. (vqdmullh_lane_s16): Change type of 2nd argument to int16x4_t. (vqdmlal_lane_s16): Don't create temporary int16x8_t value. (vqdmlsl_lane_s16): Likewise. (vqdmull_lane_s16): Don't create temporary int16x8_t value. (vqdmlal_high_lane_s32): Change type 3rd argument to int32x2_t. (vqdmlals_lane_s32): Likewise. (vqdmlsls_lane_s32): Likewise. (vqdmull_high_lane_s32): Change type 2nd argument to int32x2_t. (vqdmulls_lane_s32): Likewise. (vqdmlal_lane_s32): Don't create temporary int32x4_t value. (vqdmlsl_lane_s32): Likewise. (vqdmull_lane_s32): Don't create temporary int32x4_t value. (vqdmulhh_lane_s16): Change type of second argument to int16x4_t. (vqrdmulhh_lane_s16): Likewise. (vqdmlsl_high_lane_s16): Likewise. (vqdmulhs_lane_s32): Change type of second argument to int32x2_t. (vqdmlsl_high_lane_s32): Likewise. (vqrdmulhs_lane_s32): Likewise. [gcc/testsuite] * gcc.target/aarch64/simd/vqdmulhh_lane_s16.c: New test. * gcc.target/aarch64/simd/vqdmulhs_lane_s32.c: Likewise. * gcc.target/aarch64/simd/vqrdmulhh_lane_s16.c: Likewise. * gcc.target/aarch64/simd/vqrdmulhs_lane_s32.c: Likewise. * gcc.target/aarch64/simd/vqdmlal_high_lane_s16.c: New test. * gcc.target/aarch64/simd/vqdmlal_high_lane_s32.c: Likewise. * gcc.target/aarch64/simd/vqdmlal_high_laneq_s16.c: Likewise. * gcc.target/aarch64/simd/vqdmlal_high_laneq_s32.c: Likewise. * gcc.target/aarch64/simd/vqdmlal_lane_s16.c: Likewise. * gcc.target/aarch64/simd/vqdmlal_lane_s32.c: Likewise. * gcc.target/aarch64/simd/vqdmlal_laneq_s16.c: Likewise. * gcc.target/aarch64/simd/vqdmlal_laneq_s32.c: Likewise. * gcc.target/aarch64/simd/vqdmlalh_lane_s16.c: Likewise. * gcc.target/aarch64/simd/vqdmlals_lane_s32.c: Likewise. * gcc.target/aarch64/simd/vqdmlsl_high_lane_s16.c: Likewise. * gcc.target/aarch64/simd/vqdmlsl_high_lane_s32.c: Likewise. * gcc.target/aarch64/simd/vqdmlsl_high_laneq_s16.c: Likewise. * gcc.target/aarch64/simd/vqdmlsl_high_laneq_s32.c: Likewise. * gcc.target/aarch64/simd/vqdmlsl_lane_s16.c: Likewise. * gcc.target/aarch64/simd/vqdmlsl_lane_s32.c: Likewise. * gcc.target/aarch64/simd/vqdmlsl_laneq_s32.c: Likewise. * gcc.target/aarch64/simd/vqdmlslh_lane_s16.c: Likewise. * gcc.target/aarch64/simd/vqdmlsls_lane_s32.c: Likewise. * gcc.target/aarch64/simd/vqdmulh_laneq_s16.c: Likewise. * gcc.target/aarch64/simd/vqdmulh_laneq_s32.c: Likewise. * gcc.target/aarch64/simd/vqdmulhq_laneq_s16.c: Likewise. * gcc.target/aarch64/simd/vqdmulhq_laneq_s32.c: Likewise. * gcc.target/aarch64/simd/vqdmull_high_lane_s16.c: Likewise. * gcc.target/aarch64/simd/vqdmull_high_lane_s32.c: Likewise. * gcc.target/aarch64/simd/vqdmull_high_laneq_s16.c: Likewise. * gcc.target/aarch64/simd/vqdmull_high_laneq_s32.c: Likewise. * gcc.target/aarch64/simd/vqdmull_lane_s16.c: Likewise. * gcc.target/aarch64/simd/vqdmull_lane_s32.c: Likewise. * gcc.target/aarch64/simd/vqdmull_laneq_s16.c: Likewise. * gcc.target/aarch64/simd/vqdmull_laneq_s32.c: Likewise. * gcc.target/aarch64/simd/vqdmullh_lane_s16.c: Likewise. * gcc.target/aarch64/simd/vqdmulls_lane_s32.c: Likewise. * gcc.target/aarch64/simd/vqrdmulh_laneq_s16.c: Likewise. * gcc.target/aarch64/simd/vqrdmulh_laneq_s32.c: Likewise. * gcc.target/aarch64/simd/vqrdmulhq_laneq_s16.c: Likewise. * gcc.target/aarch64/simd/vqrdmulhq_laneq_s32.c: Likewise. * gcc.target/aarch64/vector_intrinsics.c: Simplify arm_neon.h include. (test_vqdmlal_high_lane_s16): Fix parameter type. (test_vqdmlal_high_lane_s32): Likewise. (test_vqdmull_high_lane_s16): Likewise. (test_vqdmull_high_lane_s32): Likewise. (test_vqdmlsl_high_lane_s32): Likewise. (test_vqdmlsl_high_lane_s16): Likewise. * gcc.target/aarch64/scalar_intrinsics.c (test_vqdmlalh_lane_s16): Fix argument type. (test_vqdmlals_lane_s32): Likewise. (test_vqdmlslh_lane_s16): Likewise. (test_vqdmlsls_lane_s32): Likewise. (test_vqdmulhh_lane_s16): Likewise. (test_vqdmulhs_lane_s32): Likewise. (test_vqdmullh_lane_s16): Likewise. (test_vqdmulls_lane_s32): Likewise. (test_vqrdmulhh_lane_s16): Likewise. (test_vqrdmulhs_lane_s32): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211842 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64] Implement CRC32 ACLE intrinsics.ktkachov2014-06-111-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | * config.gcc (aarch64*-*-*): Add arm_acle.h to extra headers. * Makefile.in (TEXI_GCC_FILES): Add aarch64-acle-intrinsics.texi to dependencies. * config/aarch64/aarch64-builtins.c (AARCH64_CRC32_BUILTINS): Define. (aarch64_crc_builtin_datum): New struct. (aarch64_crc_builtin_data): New. (aarch64_init_crc32_builtins): New function. (aarch64_init_builtins): Initialise CRC32 builtins when appropriate. (aarch64_crc32_expand_builtin): New. (aarch64_expand_builtin): Add CRC32 builtin expansion case. * config/aarch64/aarch64.h (TARGET_CPU_CPP_BUILTINS): Define __ARM_FEATURE_CRC32 when appropriate. (TARGET_CRC32): Define. * config/aarch64/aarch64.md (UNSPEC_CRC32B, UNSPEC_CRC32H, UNSPEC_CRC32W, UNSPEC_CRC32X, UNSPEC_CRC32CB, UNSPEC_CRC32CH, UNSPEC_CRC32CW, UNSPEC_CRC32CX): New unspec values. (aarch64_<crc_variant>): New pattern. * config/aarch64/arm_acle.h: New file. * config/aarch64/iterators.md (CRC): New int iterator. (crc_variant, crc_mode): New int attributes. * doc/aarch64-acle-intrinsics.texi: New file. * doc/extend.texi (aarch64): Document aarch64 ACLE intrinsics. Include aarch64-acle-intrinsics.texi. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211440 138bc75d-0d04-0410-961f-82ee72b054a4
* Recognize shuffle patterns for REV instructions on AArch64, rewrite intrinsics.alalaw012014-06-031-0/+9
| | | | | | | | | | | | | | | | | | | | | * config/aarch64/aarch64-simd.md (aarch64_rev<REVERSE:rev-op><mode>): New pattern. * config/aarch64/aarch64.c (aarch64_evpc_rev): New function. (aarch64_expand_vec_perm_const_1): Add call to aarch64_evpc_rev. * config/aarch64/iterators.md (REVERSE): New iterator. (UNSPEC_REV64, UNSPEC_REV32, UNSPEC_REV16): New enum elements. (rev_op): New int_attribute. * config/aarch64/arm_neon.h (vrev16_p8, vrev16_s8, vrev16_u8, vrev16q_p8, vrev16q_s8, vrev16q_u8, vrev32_p8, vrev32_p16, vrev32_s8, vrev32_s16, vrev32_u8, vrev32_u16, vrev32q_p8, vrev32q_p16, vrev32q_s8, vrev32q_s16, vrev32q_u8, vrev32q_u16, vrev64_f32, vrev64_p8, vrev64_p16, vrev64_s8, vrev64_s16, vrev64_s32, vrev64_u8, vrev64_u16, vrev64_u32, vrev64q_f32, vrev64q_p8, vrev64q_p16, vrev64q_s8, vrev64q_s16, vrev64q_s32, vrev64q_u8, vrev64q_u16, vrev64q_u32): Replace temporary __asm__ with __builtin_shuffle. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211174 138bc75d-0d04-0410-961f-82ee72b054a4
* Detect EXT patterns to vec_perm_const, use for EXT intrinsicsalalaw012014-05-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | * config/aarch64/aarch64-builtins.c (aarch64_types_binopv_qualifiers, TYPES_BINOPV): New static data. * config/aarch64/aarch64-simd-builtins.def (im_lane_bound): New builtin. * config/aarch64/aarch64-simd.md (aarch64_ext, aarch64_im_lane_boundsi): New patterns. * config/aarch64/aarch64.c (aarch64_expand_vec_perm_const_1): Match patterns for EXT. (aarch64_evpc_ext): New function. * config/aarch64/iterators.md (UNSPEC_EXT): New enum element. * config/aarch64/arm_neon.h (vext_f32, vext_f64, vext_p8, vext_p16, vext_s8, vext_s16, vext_s32, vext_s64, vext_u8, vext_u16, vext_u32, vext_u64, vextq_f32, vextq_f64, vextq_p8, vextq_p16, vextq_s8, vextq_s16, vextq_s32, vextq_s64, vextq_u8, vextq_u16, vextq_u32, vextq_u64): Replace __asm with __builtin_shuffle and im_lane_boundsi. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211058 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64] Improve vst4_lane intrinsicsjgreenhalgh2014-04-281-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc/ * config/aarch64/aarch64-builtins.c (aarch64_types_storestruct_lane_qualifiers): New. (TYPES_STORESTRUCT_LANE): Likewise. * config/aarch64/aarch64-simd-builtins.def (st2_lane): New. (st3_lane): Likewise. (st4_lane): Likewise. * config/aarch64/aarch64-simd.md (vec_store_lanesoi_lane<mode>): New. (vec_store_lanesci_lane<mode>): Likewise. (vec_store_lanesxi_lane<mode>): Likewise. (aarch64_st2_lane<VQ:mode>): Likewise. (aarch64_st3_lane<VQ:mode>): Likewise. (aarch64_st4_lane<VQ:mode>): Likewise. * config/aarch64/aarch64.md (unspec): Add UNSPEC_ST{2,3,4}_LANE. * config/aarch64/arm_neon.h (__ST2_LANE_FUNC): Rewrite using builtins, update use points to use new macro arguments. (__ST3_LANE_FUNC): Likewise. (__ST4_LANE_FUNC): Likewise. * config/aarch64/iterators.md (V_TWO_ELEM): New. (V_THREE_ELEM): Likewise. (V_FOUR_ELEM): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@209880 138bc75d-0d04-0410-961f-82ee72b054a4
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