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* gcc/rsandifo2014-11-081-17/+12
* [AArch64] Add ACLE arch-related predefined macrosjiwang2014-11-062-5/+20
* [AArch64] Restructure arm_neon.h vector types.belagod2014-11-056-336/+382
* [AArch64] fix unsafe access to deallocated stackjiwang2014-11-041-0/+12
* [AArch64] Fix predicate and constraint mismatch in logical atomic operationsclyon2014-11-042-6/+9
* 2014-11-01 Andrew MacLeod <amacleod@redhat,com>amacleod2014-11-011-0/+1
* [Patch 6/7 AArch64] Deprecate *_BY_PIECES_P, move to hookized versionjgreenhalgh2014-11-012-6/+20
* [AArch64] Restore recog state after finding pre-madd instructionktkachov2014-10-291-0/+4
* [AArch64] Fix/revert fallout from machine_mode changektkachov2014-10-291-1/+1
* gcc/ada/rsandifo2014-10-296-212/+212
* [AArch64] Restore gimple_folding of reduction intrinsicsalalaw012014-10-272-23/+11
* [AArch64] Use new reduc_[us](min|max)_scal optabs, inc. for builtinsalalaw012014-10-273-90/+82
* [AArch64] Use new reduc_plus_scal optabs, inc. for __builtinsalalaw012014-10-274-53/+60
* 2014-10-27 Andrew MacLeod <amacleod@redhat.com>amacleod2014-10-272-1/+23
* [AArch64] Temporarily remove aarch64_gimple_fold_builtin code for reduction o...alalaw012014-10-272-2/+6
* [PATCH 2/2] [AARCH64,NEON] Convert arm_neon.h to use new builtins for vld[234...cbaylis2014-10-241-125/+281
* [PATCH 1/2] [AARCH64,NEON] Add patterns + builtins for vld[234](q?)_lane_* in...cbaylis2014-10-244-0/+107
* [AArch64] LINK_SPEC changes for Cortex-A53 erratum 835769 workaround ktkachov2014-10-242-2/+20
* [AArch64] Cleanup logic around aarch64_final_prescanktkachov2014-10-242-20/+33
* PR target/63173fyang2014-10-244-120/+942
* 2014-10-21 Andrew Pinski <apinski@cavium.com>pinskia2014-10-214-2/+152
* 2014-10-16 Andrew MacLeod <amacleod@redhat.com>amacleod2014-10-161-1/+5
* * config/aarch64/aarch64.c (aarch64_legitimize_address): New function.rearnsha2014-10-161-0/+44
* [AARCH64] Add ACLE 2.0 predefined macrosjiwang2014-10-151-2/+16
* [AArch64] Remove unused variable and marcojiwang2014-10-151-4/+0
* [AArch64] Add --enable-fix-cortex-a53-835769 configure-time optionktkachov2014-10-102-1/+10
* [AArch64] Implement workaround for ARM Cortex-A53 erratum 835769ktkachov2014-10-104-0/+137
* [AArch64] Wire up vqdmullh_laneq_s16 and vqdmullh_laneq_s32jgreenhalgh2014-09-303-4/+16
* 2014-09-26 Christophe Lyon <christophe.lyon@linaro.org>clyon2014-09-262-0/+17
* [AArch64] Tighten predicates on SIMD shift intrinsicsjgreenhalgh2014-09-255-42/+81
* [AArch64] Improve regmove_costs for 128-bit types.jiwang2014-09-241-8/+21
* [AArch64] Use __aarch64_vget_lane* macros for getting the lane in some lane m...ktkachov2014-09-241-4/+4
* [AArch64] Enable shrink wrapping.mshawcroft2014-09-233-0/+34
* [AArch64] Auto-generate the "BUILTIN_" macros for aarch64-builtins.cjgreenhalgh2014-09-224-120/+57
* [PATCH AArch64]: Add constraint letter for stack_protect_test patternjgreenhalgh2014-09-191-1/+1
* [AArch64] Add regmove_costs for Cortex-A57 and A53jiwang2014-09-121-2/+22
* [AArch64] Fix cost for Q register movesjiwang2014-09-121-5/+2
* [AArch64] Add cost handling of CALLER_SAVE_REGS and POINTER_REGSjiwang2014-09-121-0/+7
* [AArch64] Simplify vreinterpret for float64x1_t using casts.alalaw012014-09-117-203/+20
* [AArch64] Replace temporary inline assembler for vset_lanealalaw012014-09-111-312/+168
* [AArch64] Cheap fix for argument types of vmull_high_lane_{us}{16,32}jgreenhalgh2014-09-111-4/+4
* recog_memoized works on an rtx_insn *dmalcolm2014-09-092-2/+2
* Add crtfastmath for AArch64.ramana2014-09-092-1/+11
* [AArch64] PR 61749: Do not ICE in lane intrinsics when passed non-constant la...ktkachov2014-09-092-15/+19
* [Obvious] Remove unused aarch64_types_cmtst_qualifiers, was breaking bootstrap.alalaw012014-09-081-5/+0
* Fix PR63190vekumar2014-09-071-2/+2
* [PATCH AArch64] Rename [u]int32x1_t to [u]int32_t (resp 16x1, 8x1) in arm_neon.halalaw012014-09-051-223/+217
* [PATCH AArch64 2/2] Replace temporary inline assembler for vget_highalalaw012014-09-051-132/+79
* [PATCH AArch64 2/2] Remove vector compare/tst __builtinsalalaw012014-09-053-306/+160
* [PATCH AArch64 1/2] Improve codegen of vector compares inc. tst instructionalalaw012014-09-056-60/+114
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