| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | gcc/ | rsandifo | 2014-11-08 | 1 | -17/+12 |
| * | [AArch64] Add ACLE arch-related predefined macros | jiwang | 2014-11-06 | 2 | -5/+20 |
| * | [AArch64] Restructure arm_neon.h vector types. | belagod | 2014-11-05 | 6 | -336/+382 |
| * | [AArch64] fix unsafe access to deallocated stack | jiwang | 2014-11-04 | 1 | -0/+12 |
| * | [AArch64] Fix predicate and constraint mismatch in logical atomic operations | clyon | 2014-11-04 | 2 | -6/+9 |
| * | 2014-11-01 Andrew MacLeod <amacleod@redhat,com> | amacleod | 2014-11-01 | 1 | -0/+1 |
| * | [Patch 6/7 AArch64] Deprecate *_BY_PIECES_P, move to hookized version | jgreenhalgh | 2014-11-01 | 2 | -6/+20 |
| * | [AArch64] Restore recog state after finding pre-madd instruction | ktkachov | 2014-10-29 | 1 | -0/+4 |
| * | [AArch64] Fix/revert fallout from machine_mode change | ktkachov | 2014-10-29 | 1 | -1/+1 |
| * | gcc/ada/ | rsandifo | 2014-10-29 | 6 | -212/+212 |
| * | [AArch64] Restore gimple_folding of reduction intrinsics | alalaw01 | 2014-10-27 | 2 | -23/+11 |
| * | [AArch64] Use new reduc_[us](min|max)_scal optabs, inc. for builtins | alalaw01 | 2014-10-27 | 3 | -90/+82 |
| * | [AArch64] Use new reduc_plus_scal optabs, inc. for __builtins | alalaw01 | 2014-10-27 | 4 | -53/+60 |
| * | 2014-10-27 Andrew MacLeod <amacleod@redhat.com> | amacleod | 2014-10-27 | 2 | -1/+23 |
| * | [AArch64] Temporarily remove aarch64_gimple_fold_builtin code for reduction o... | alalaw01 | 2014-10-27 | 2 | -2/+6 |
| * | [PATCH 2/2] [AARCH64,NEON] Convert arm_neon.h to use new builtins for vld[234... | cbaylis | 2014-10-24 | 1 | -125/+281 |
| * | [PATCH 1/2] [AARCH64,NEON] Add patterns + builtins for vld[234](q?)_lane_* in... | cbaylis | 2014-10-24 | 4 | -0/+107 |
| * | [AArch64] LINK_SPEC changes for Cortex-A53 erratum 835769 workaround | ktkachov | 2014-10-24 | 2 | -2/+20 |
| * | [AArch64] Cleanup logic around aarch64_final_prescan | ktkachov | 2014-10-24 | 2 | -20/+33 |
| * | PR target/63173 | fyang | 2014-10-24 | 4 | -120/+942 |
| * | 2014-10-21 Andrew Pinski <apinski@cavium.com> | pinskia | 2014-10-21 | 4 | -2/+152 |
| * | 2014-10-16 Andrew MacLeod <amacleod@redhat.com> | amacleod | 2014-10-16 | 1 | -1/+5 |
| * | * config/aarch64/aarch64.c (aarch64_legitimize_address): New function. | rearnsha | 2014-10-16 | 1 | -0/+44 |
| * | [AARCH64] Add ACLE 2.0 predefined macros | jiwang | 2014-10-15 | 1 | -2/+16 |
| * | [AArch64] Remove unused variable and marco | jiwang | 2014-10-15 | 1 | -4/+0 |
| * | [AArch64] Add --enable-fix-cortex-a53-835769 configure-time option | ktkachov | 2014-10-10 | 2 | -1/+10 |
| * | [AArch64] Implement workaround for ARM Cortex-A53 erratum 835769 | ktkachov | 2014-10-10 | 4 | -0/+137 |
| * | [AArch64] Wire up vqdmullh_laneq_s16 and vqdmullh_laneq_s32 | jgreenhalgh | 2014-09-30 | 3 | -4/+16 |
| * | 2014-09-26 Christophe Lyon <christophe.lyon@linaro.org> | clyon | 2014-09-26 | 2 | -0/+17 |
| * | [AArch64] Tighten predicates on SIMD shift intrinsics | jgreenhalgh | 2014-09-25 | 5 | -42/+81 |
| * | [AArch64] Improve regmove_costs for 128-bit types. | jiwang | 2014-09-24 | 1 | -8/+21 |
| * | [AArch64] Use __aarch64_vget_lane* macros for getting the lane in some lane m... | ktkachov | 2014-09-24 | 1 | -4/+4 |
| * | [AArch64] Enable shrink wrapping. | mshawcroft | 2014-09-23 | 3 | -0/+34 |
| * | [AArch64] Auto-generate the "BUILTIN_" macros for aarch64-builtins.c | jgreenhalgh | 2014-09-22 | 4 | -120/+57 |
| * | [PATCH AArch64]: Add constraint letter for stack_protect_test pattern | jgreenhalgh | 2014-09-19 | 1 | -1/+1 |
| * | [AArch64] Add regmove_costs for Cortex-A57 and A53 | jiwang | 2014-09-12 | 1 | -2/+22 |
| * | [AArch64] Fix cost for Q register moves | jiwang | 2014-09-12 | 1 | -5/+2 |
| * | [AArch64] Add cost handling of CALLER_SAVE_REGS and POINTER_REGS | jiwang | 2014-09-12 | 1 | -0/+7 |
| * | [AArch64] Simplify vreinterpret for float64x1_t using casts. | alalaw01 | 2014-09-11 | 7 | -203/+20 |
| * | [AArch64] Replace temporary inline assembler for vset_lane | alalaw01 | 2014-09-11 | 1 | -312/+168 |
| * | [AArch64] Cheap fix for argument types of vmull_high_lane_{us}{16,32} | jgreenhalgh | 2014-09-11 | 1 | -4/+4 |
| * | recog_memoized works on an rtx_insn * | dmalcolm | 2014-09-09 | 2 | -2/+2 |
| * | Add crtfastmath for AArch64. | ramana | 2014-09-09 | 2 | -1/+11 |
| * | [AArch64] PR 61749: Do not ICE in lane intrinsics when passed non-constant la... | ktkachov | 2014-09-09 | 2 | -15/+19 |
| * | [Obvious] Remove unused aarch64_types_cmtst_qualifiers, was breaking bootstrap. | alalaw01 | 2014-09-08 | 1 | -5/+0 |
| * | Fix PR63190 | vekumar | 2014-09-07 | 1 | -2/+2 |
| * | [PATCH AArch64] Rename [u]int32x1_t to [u]int32_t (resp 16x1, 8x1) in arm_neon.h | alalaw01 | 2014-09-05 | 1 | -223/+217 |
| * | [PATCH AArch64 2/2] Replace temporary inline assembler for vget_high | alalaw01 | 2014-09-05 | 1 | -132/+79 |
| * | [PATCH AArch64 2/2] Remove vector compare/tst __builtins | alalaw01 | 2014-09-05 | 3 | -306/+160 |
| * | [PATCH AArch64 1/2] Improve codegen of vector compares inc. tst instruction | alalaw01 | 2014-09-05 | 6 | -60/+114 |
