| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [AArch64] Tie operand 1 to operand 0 in AESMC pattern when AES/AESMC fusion i... | ktkachov | 2016-05-27 | 3 | -3/+24 |
| * | [AArch64] PR target/63596, honor tree-stdarg analysis result to improve VAARG... | jiwang | 2016-05-27 | 1 | -14/+23 |
| * | [AArch64] Enable tree-stdarg pass for AArch64 by defining counter fields | jiwang | 2016-05-27 | 1 | -0/+7 |
| * | Remove aarch64_cannot_change_mode_class as the underlying issue | wilco | 2016-05-27 | 3 | -24/+0 |
| * | [AArch64] Simplify ashl<mode>3 expander for SHORT modes | ktkachov | 2016-05-27 | 1 | -12/+6 |
| * | [AArch64] Delete obsolete CC_ZESWP and CC_SESWP CC modes | ktkachov | 2016-05-27 | 2 | -16/+0 |
| * | GCC expands switch statements in a very simplistic way and tries to use a table | wilco | 2016-05-26 | 1 | -2/+7 |
| * | SIMD operations like combine prefer to have their operands in FP registers, | wilco | 2016-05-26 | 1 | -2/+2 |
| * | [Patch AArch64] Simplify reduc_plus_scal_v2[sd]f sequence | jgreenhalgh | 2016-05-18 | 1 | -16/+3 |
| * | gcc/ChangeLog: | kugan | 2016-05-18 | 1 | -10/+0 |
| * | [AArch64, 4/4] Reimplement vmvn* intrinscis, remove inline assembly | jiwang | 2016-05-17 | 1 | -155/+86 |
| * | [AArch64, 3/4] Reimplement multiply by element to get rid of inline assembly | jiwang | 2016-05-17 | 1 | -121/+68 |
| * | [AArch64, 2/4] Extend vector mutiply by element to all supported modes | jiwang | 2016-05-17 | 1 | -8/+8 |
| * | [AArch64, 1/4] Add the missing support of vfms_n_f32, vfmsq_n_f32, vfmsq_n_f64 | jiwang | 2016-05-17 | 2 | -20/+49 |
| * | [AArch64] PR target/70809: Delete aarch64_vmls<mode> pattern | ktkachov | 2016-05-17 | 1 | -10/+0 |
| * | [Patch AArch64] Delete ASM_OUTPUT_DEF and fallback to default .set directive | jgreenhalgh | 2016-05-17 | 1 | -9/+0 |
| * | [Patch obvious AArch64] Wrap SHIFT_COUNT_TRUNCATED in brackets | jgreenhalgh | 2016-05-17 | 1 | -1/+1 |
| * | [AArch64 trivial] Don't define a macro when a variable will do | jgreenhalgh | 2016-05-17 | 1 | -2/+1 |
| * | Some patterns are using '%w2' for immediate operands, which means that a zero | wilco | 2016-05-16 | 1 | -8/+16 |
| * | This patch fixes the attributes of integer immediate shifts which were | wilco | 2016-05-16 | 1 | -29/+36 |
| * | [AArch64] Remove an unused reload hook. | mwahab | 2016-05-16 | 3 | -130/+0 |
| * | Set TARGET_OMIT_STRUCT_RETURN_REG to true | ramana | 2016-05-13 | 1 | -0/+3 |
| * | [AArch64] Define WORD_REGISTER_OPERATIONS to zero and comment why | ktkachov | 2016-04-28 | 1 | -1/+6 |
| * | [AArch64] Replace insn to zero up SIMD registers | evandro | 2016-04-27 | 1 | -14/+17 |
| * | [PATCH 2/2] (header usage fix) include c++ headers in system.h | nsz | 2016-04-22 | 1 | -2/+1 |
| * | [AArch64] Work around PR target/64971 | ktkachov | 2016-04-20 | 1 | -0/+15 |
| * | [Patch AArch64 3/3] Fix up for pr70133 | jgreenhalgh | 2016-04-11 | 1 | -77/+110 |
| * | [Patch AArch64 2/3] Rework the code to print extension strings (pr70133) | jgreenhalgh | 2016-04-11 | 4 | -98/+55 |
| * | [Patch AArch64 1/3] Enable CRC by default for armv8.1-a | jgreenhalgh | 2016-04-11 | 1 | -1/+1 |
| * | [AArch64] Fix SIMD predicate | evandro | 2016-04-01 | 1 | -1/+1 |
| * | 2016-03-25 Richard Henderson <rth@redhat.com> | law | 2016-03-25 | 3 | -0/+18 |
| * | Tweak the pipeline model for Exynos M1 | evandro | 2016-03-17 | 1 | -1/+1 |
| * | PR target/70048 | rth | 2016-03-16 | 1 | -70/+46 |
| * | [AArch64] PR target/70002: Make aarch64_set_current_function play nice with p... | ktkachov | 2016-03-11 | 3 | -48/+38 |
| * | PR target/7044 | nickc | 2016-03-10 | 1 | -1/+16 |
| * | 2016-03-10 Christophe Lyon <christophe.lyon@linaro.org> | clyon | 2016-03-10 | 5 | -6/+37 |
| * | 2016-03-10 Christophe Lyon <christophe.lyon@linaro.org> | clyon | 2016-03-10 | 1 | -1/+3 |
| * | Rename the tuning option and related functions to enable the Newton series fo... | evandro | 2016-02-26 | 5 | -19/+17 |
| * | 2016-02-26 Joel Sherrill <joel@rtems.org> | joel | 2016-02-26 | 1 | -0/+28 |
| * | [AArch64] Set TREE_TARGET_GLOBALS in aarch64_set_current_function when new tr... | ktkachov | 2016-02-26 | 1 | -1/+1 |
| * | [AArch64] PR target/69613: Return zero TARGET_SHIFT_TRUNCATION_MASK when SHIF... | ktkachov | 2016-02-26 | 1 | -1/+2 |
| * | Tweak the pipeline model for Exynos M1 | evandro | 2016-02-23 | 1 | -1/+1 |
| * | * gcc/config/aarch64/aarch64.c (exynosm1_tunings): Enable the Newton | evandro | 2016-02-23 | 1 | -1/+1 |
| * | PR target/69894 | jakub | 2016-02-22 | 1 | -1/+2 |
| * | [AArch64] PR target/69161: Don't use special predicate for CCmode comparisons... | ktkachov | 2016-02-17 | 2 | -8/+17 |
| * | As part of the final cleanup of aarch64_internal_mov_immediate a return was | wilco | 2016-02-17 | 1 | -0/+1 |
| * | [AArch64] Remove AARCH64_EXTRA_TUNE_RECIP_SQRT from Cortex-A57 tuning | jgreenhalgh | 2016-02-16 | 1 | -2/+1 |
| * | [Patch AArch64] Use software sqrt expansion always for -mlow-precision-recip-... | jgreenhalgh | 2016-02-16 | 1 | -2/+3 |
| * | [Patch AArch64] GCC 6 regression in vector performance. - Fix vector initiali... | jgreenhalgh | 2016-02-16 | 1 | -28/+28 |
| * | [Patch AArch64] Restrict 16-bit sqrdml{sa}h instructions to FP_LO_REGS | jgreenhalgh | 2016-02-16 | 1 | -4/+4 |
