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* [ARM] PR target/69161: Don't ignore mode when matching comparison operator ↵ktkachov2016-02-171-2/+2
| | | | | | | | | | | | | | | | | | | | in cstore-like patterns PR target/69161 * config/arm/predicates.md (arm_comparison_operator_mode): New predicate. * config/arm/arm.md (*mov_scc): Use arm_comparison_operator_mode instead of arm_comparison_operator. (*mov_negscc): Likewise. (*mov_notscc): Likewise. * config/arm/thumb2.md (*thumb2_mov_scc): Likewise. (*thumb2_mov_negscc): Likewise. (*thumb2_mov_negscc_strict_it): Likewise. (*thumb2_mov_notscc): Likewise. (*thumb2_mov_notscc_strict_it): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@233495 138bc75d-0d04-0410-961f-82ee72b054a4
* Update copyright years.jakub2016-01-041-1/+1
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@232055 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM] PR target/68648: Fold NOT of CONST_INT in andsi_iorsi3_notsi splitterktkachov2015-12-161-2/+16
| | | | | | | | | | | | PR target/68648 * config/arm/arm.md (*andsi_iorsi3_notsi): Try to simplify the complement of operands[3] during splitting. * gcc.c-torture/execute/pr68648.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@231675 138bc75d-0d04-0410-961f-82ee72b054a4
* Add scheduling model for Exynos M1evandro2015-12-071-1/+2
| | | | | | | | | | gcc/ * config/aarch64/aarch64-cores.def: Use the Exynos M1 sched model. * config/aarch64/aarch64.md: Include "exynos-m1.md". * config/arm/arm.md: Likewise. * config/arm/exynos-m1.md: New file. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@231378 138bc75d-0d04-0410-961f-82ee72b054a4
* PR middle-end/65958ebotcazou2015-12-041-1/+1
| | | | | | | | | | | | * config/arm/unspecs.md (unspec): Remove UNSPEC_PROBE_STACK_RANGE. (unspecv): Add VUNSPEC_PROBE_STACK_RANGE. * config/arm/arm.md (probe_stack_range): Adjust. * config/aarch64/aarch64.md (unspec): Remove UNSPEC_PROBE_STACK_RANGE. (unspecv): Add UNSPECV_PROBE_STACK_RANGE. (probe_stack_range_<PTR:mode>): Adjust. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@231295 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM] PR target/68214: Delete IP-reg-clobbering call-through-mem patternsktkachov2015-12-041-34/+0
| | | | | | | | | | | | PR target/68214 * config/arm/arm.md (*call_mem): Delete pattern. (*call_value_mem): Likewise. * config/arm/arm.c (output_call_mem): Delete. * config/arm/arm-protos.h (output_call_mem): Delete prototype. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@231252 138bc75d-0d04-0410-961f-82ee72b054a4
* [AArch64] Add attribute for compatibility with ARM pipeline modelsjgreenhalgh2015-11-201-0/+3
| | | | | | | | | | | | gcc/ * config/aarch64/aarch64.md (predicated): Copy attribute from "arm.md". * config/arm/arm.md (predicated): Added description. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@230666 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM] Do not expand movmisalign pattern if not in 32-bit modektkachov2015-11-201-5/+5
| | | | | | | | | | | | | | | | | * config/arm/arm.c (arm_option_override): Require TARGET_32BIT for unaligned_access. * config/arm/arm.md (unaligned_loadsi): Remove redundant TARGET_32BIT from matching condition. (unaligned_loadhis): Likewise. (unaligned_loadhiu): Likewise. (unaligned_storesi): Likewise. (unaligned_storehi): Likewise. * gcc.target/arm/armv6-unaligned-load-ice.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@230664 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM] PR 68149 Fix ICE in unaligned_loaddi splitktkachov2015-11-201-53/+0
| | | | | | | | | | | | PR target/68149 * config/arm/arm.md (unaligned_loaddi): Delete. (unaligned_storedi): Likewise. * config/arm/arm.c (gen_movmem_ldrd_strd): Don't generate unaligned DImode memory ops. Instead perform two back-to-back unaligned SImode ops. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@230663 138bc75d-0d04-0410-961f-82ee72b054a4
* [PATCH][ARM]Fix addsi3_compare_op2 pattern.renlin2015-11-121-2/+2
| | | | | | | | | | | | gcc/ 2015-11-12 Renlin Li <renlin.li@arm.com> * config/arm/arm.md (addsi3_compare_op2): Make the order of assembly pattern consistent with constraint order. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@230222 138bc75d-0d04-0410-961f-82ee72b054a4
* 2015-11-06 Michael Collison <michael.collison@linaro.orgcollison2015-11-061-38/+0
| | | | | | | | | | | | | | | | | | | | | | | Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> Revert: 2015-08-01 Michael Collison <michael.collison@linaro.org Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> * config/arm/arm.md (*arm_smin_cmp): New pattern. (*arm_umin_cmp): Likewise. 2015-11-06 Michael Collison <michael.collison@linaro.org Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> Revert: 2015-08-01 Michael Collison <michael.collison@linaro.org Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> * gcc.target/arm/mincmp.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@229895 138bc75d-0d04-0410-961f-82ee72b054a4
* [Patch ARM] Unified assembler in ARM state.ramana2015-11-061-85/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc/ChangeLog: 2015-11-06 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * config/arm/arm-ldmstm.ml: Rewrite to generate unified asm templates. * config/arm/arm.c (arm_asm_trampoline_template): Make unified asm safe. (arm_output_multireg_pop): Likewise. (output_move_double): Likewise. (output_move_quad): Likewise. (output_return_instruction): Likewise. (arm_print_operand): Remove support for %( and %. print modifiers. (arm_output_shift): Make unified asm. (arm_declare_function_name): Likewise. * config/arm/arm.h (TARGET_UNIFIED_ASM): Delete. (ASM_APP_OFF): Adjust. (ASM_OUTPUT_REG_PUSH): Undo special casing for TARGET_ARM. (ASM_OUTPUT_REG_POP): Likewise. * config/arm/arm.md: Adjust uses of %., %(, %) * config/arm/sync.md: Likewise. * config/arm/thumb2.md: Likewise. * config/arm/ldmstm.md: Regenerate. * config/arm/arm.opt (masm-unified-syntax): Do not special case Thumb. * doc/invoke.texi (masm-unified-syntax): Update documentation. gcc/testsuite/ChangeLog: 2015-11-06 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * gcc.target/arm/combine-movs.c: * gcc.target/arm/interrupt-1.c: * gcc.target/arm/interrupt-2.c: * gcc.target/arm/unaligned-memcpy-4.c: git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@229875 138bc75d-0d04-0410-961f-82ee72b054a4
* [Patch PR target/67366 1/2] [ARM] - Add movmisalignhi / si patternsramana2015-10-091-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds movmisalignhi and movmisalignsi expanders when unaligned access is allowed by the architecture. This allows the mid-end to expand to misaligned loads and stored. Compared code generated for the Linux kernel and it changes code generation for a handful of files all for the better basically by reducing the stack usage. Tested by : 1. armhf bootstrap and regression test - no regressions. 2.. arm-none-eabi cross build and regression test for {-marm/-march=armv7-a/-mfpu=vfpv3-d16/-mfloat-abi=softfp} {-mthumb/-march=armv8-a/-mfpu=crypto-neon-fp-armv8/-mfloat-abi=hard} {-marm/-mcpu=arm7tdmi/-mfloat-abi=soft} {-mthumb/-mcpu=arm7tdmi/-mfloat-abi=soft} Will apply to trunk once 2/2 is approved. regards Ramana 2015-10-09 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> PR target/67366 * config/arm/arm.md (movmisalign<mode>): New. * config/arm/iterators.md (HSI): New. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228643 138bc75d-0d04-0410-961f-82ee72b054a4
* * config/arm/arm.c (arm_emit_probe_stack_range): Adjust comment.ebotcazou2015-10-061-3/+1
| | | | | | | | | (output_probe_stack_range): Rotate the loop and simplify. (thumb1_expand_prologue): Tweak sorry message. * config/arm/arm.md (probe_stack): Use bare string. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228534 138bc75d-0d04-0410-961f-82ee72b054a4
* Remove REAL_VALUE_FROM_CONST_DOUBLErsandifo2015-10-051-23/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To maintain symmetry after the previous removal of CONST_DOUBLE_FROM_REAL_VALUE, this patch also gets rid of REAL_VALUE_FROM_CONST_DOUBLE. All the macro did was copy the contents of CONST_DOUBLE_REAL_VALUE into a temporary real_value structure. In many cases there was no need for this temporary and we could simply use the CONST_DOUBLE_REAL_VALUE directly. For that reason this patch is less automatic than the others. Bootstrapped & regression-tested on x86_64-linux-gnu. Also tested by building one target per CPU directory and checking that there were no new warnings and no changes in testsuite output at -O2. gcc/ * real.h (REAL_VALUE_FROM_CONST_DOUBLE): Delete. * config/aarch64/aarch64.c (aarch64_float_const_zero_rtx_p) (aarch64_print_operand, aarch64_float_const_representable_p) (aarch64_output_simd_mov_immediate): Use CONST_DOUBLE_REAL_VALUE instead of REAL_VALUE_FROM_CONST_DOUBLE. * config/arc/arc.c (arc_print_operand): Likewise. * config/arm/arm.c (arm_const_double_rtx, vfp3_const_double_index) (neon_valid_immediate, arm_print_operand, arm_emit_fp16_const) (vfp3_const_double_for_fract_bits, vfp3_const_double_for_bits): Likewise. * config/arm/arm.md (*arm32_movhf, consttable_4, consttable_8) (consttable_16): Likewise. * config/arm/vfp.md (*movhf_vfp_neon, *movhf_vfp): Likewise. * config/avr/avr.c (avr_print_operand): Likewise. * config/bfin/bfin.md: Likewise (in a define_split). * config/c6x/c6x.md: Likewise (in a define_split). * config/cr16/cr16.c (cr16_const_double_ok): Likewise. (cr16_print_operand): Likewise. * config/cris/cris.c (cris_print_operand): Likewise. * config/epiphany/epiphany.c (epiphany_print_operand): Likewise. * config/fr30/fr30.c (fr30_print_operand): Likewise. (fr30_const_double_is_zero): Likewise. * config/frv/frv.c (frv_print_operand, output_move_single): Likewise. * config/frv/frv.md: Likewise (in a define_split). * config/frv/predicates.md (int_2word_operand): Likewise. * config/h8300/h8300.c (h8300_print_operand): Likewise. * config/i386/i386.c (standard_80387_constant_p): Likewise. (ix86_print_operand, ix86_split_to_parts): Likewise. * config/i386/i386.md: Likewise (in a define_split). * config/ia64/ia64.c (ia64_split_tmode, ia64_print_operand): Likewise. * config/iq2000/iq2000.md (movsf_lo_sum, movsf_high): Likewise. * config/m32r/m32r.c (easy_df_const, m32r_print_operand): Likewise. * config/m68k/m68k.c (handle_move_double, standard_68881_constant_p) (print_operand): Likewise. * config/m68k/m68k.md (movsf_cf_hard, movdf_cf_hard): Likewise. * config/mep/mep.md: Likewise (in define_split). * config/microblaze/microblaze.c (microblaze_const_double_ok) (print_operand): Likewise. * config/mips/mips.md (consttable_float): Likewise. * config/mmix/mmix.c (mmix_intval): Likewise. * config/mn10300/mn10300.c (mn10300_print_operand): Likewise. * config/nvptx/nvptx.c (nvptx_print_operand): Likewise. * config/pa/pa.c (pa_singlemove_string): Likewise. * config/pdp11/pdp11.c (pdp11_expand_operands): Likewise. (pdp11_asm_print_operand, legitimate_const_double_p): Likewise. * config/rs6000/rs6000.c (num_insns_constant, rs6000_emit_cmove) (output_toc): Likewise. * config/rs6000/rs6000.md: Likewise (in define_splits). * config/rx/rx.c (rx_print_operand): Likewise. * config/s390/s390.c (s390_output_pool_entry): Likewise. * config/sh/sh.c (fp_zero_operand, fp_one_operand): Likewise. * config/sh/sh.md (consttable_sf, consttable_df): Likewise (and also in define_splits). * config/sparc/sparc.c (fp_sethi_p, fp_mov_p): Likewise. (fp_high_losum_p): Likewise. * config/sparc/sparc.md (*movsf_insn, *movsf_lo_sum): Likewise. (*movsf_high): Likewise. * config/spu/spu.c (const_double_to_hwint): Likewise. * config/v850/v850.c (const_double_split): Likewise. * config/vax/vax.c (vax_float_literal): Likewise. * config/visium/visium.c (visium_expand_copysign): Likewise. * config/visium/visium.md: Likewise (in define_split). * config/xtensa/predicates.md (const_float_1_operand): Likewise. * config/xtensa/xtensa.c (print_operand): Likewise. (xtensa_output_literal): Likewise. * cprop.c (implicit_set_cond_p): Likewise. * dwarf2out.c (insert_float): Likewise. * expmed.c (expand_mult, make_tree): Likewise. * expr.c (compress_float_constant): Likewise. * rtlanal.c (split_double): Likewise. * simplify-rtx.c (avoid_constant_pool_reference): Likewise. (simplify_const_unary_operation, simplify_binary_operation_1) (simplify_const_binary_operation): Likewise. (simplify_const_relational_operation): Likewise. * varasm.c (output_constant_pool_2): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228478 138bc75d-0d04-0410-961f-82ee72b054a4
* 2015-09-17 Christian Bruel <christian.bruel@st.com>chrbr2015-09-171-1/+1
| | | | | | | | * config/arm/arm.md (*call_value_symbol): Fix operand for interworking. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@227880 138bc75d-0d04-0410-961f-82ee72b054a4
* PR middle-end/65958ebotcazou2015-09-171-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * config/arm/linux-elf.h (STACK_CHECK_STATIC_BUILTIN): Define. * config/arm/arm-protos.h (output_probe_stack_range): Declare. * config/arm/arm.c: Include common/common-target.h. (use_return_insn): Return 0 if the static chain register was saved above a non-APCS frame. (arm_compute_static_chain_stack_bytes): Adjust for stack checking. (struct scratch_reg): New. (get_scratch_register_on_entry): New function. (release_scratch_register_on_entry): Likewise. (arm_emit_probe_stack_range): Likewise. (output_probe_stack_range): Likewise. (arm_expand_prologue): Factor out code dealing with the IP register for nested function and adjust it for stack checking. Invoke arm_emit_probe_stack_range if static builtin stack checking is enabled. (thumb1_expand_prologue): Sorry out if static builtin stack checking is enabled. (arm_expand_epilogue): Add the saved static chain register, if any, to the amount of pre-pushed registers to pop. (arm_frame_pointer_required): Return true if static stack checking is enabled and we want to catch the exception with the EABI unwinder. * config/arm/unspecs.md (UNSPEC_PROBE_STACK): New constant. (UNSPEC_PROBE_STACK_RANGE): Likewise. * config/arm/arm.md (probe_stack): New insn. (probe_stack_range): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@227860 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM] PR 67439: Allow matching of *arm32_movhf when -mrestrict-it is onktkachov2015-09-101-2/+3
| | | | | | | | | | | | PR target/67439 * config/arm/arm.md (*arm32_movhf): Remove !arm_restrict_it from predicate. Set predicable_short_it attr to "no". * gcc.target/arm/pr67439_1.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@227630 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM][3/3] Expand mod by power of 2ktkachov2015-09-091-1/+70
| | | | | | | | | | | | | | | | | | * config/arm/arm.md (*subsi3_compare0): Rename to... (subsi3_compare0): ... This. (modsi3): New define_expand. * config/arm/arm.c (arm_new_rtx_costs, MOD case): Handle case when operand is power of 2. * gcc.target/aarch64/mod_2.x: New file. * gcc.target/aarch64/mod_256.x: Likewise. * gcc.target/arm/mod_2.c: New test. * gcc.target/arm/mod_256.c: Likewise. * gcc.target/aarch64/mod_2.c: Likewise. * gcc.target/aarch64/mod_256.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@227586 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/rsandifo2015-08-241-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * genflags.c (gen_macro): Delete. (gen_proto): Don't create GEN.*CALL.* macros. * gensupport.h (get_file_location): Declare. * gensupport.c (rtx_locs): New variable. (read_md_rtx): Record rtx locations. (get_file_location): New function. * target-insns.def (call, call_pop, call_value, call_value_pop) (sibcall, sibcall_value): New patterns. * gentarget-def.c (parse_argument): New function. (def_target_insn): Use it. Handle optional operands. Raise an error if an .md pattern has the wrong number of operands for the pattern name. Remove the names of unused operands from the prototype. * builtins.c (expand_builtin_apply): Use targetm functions instead of HAVE_call_value and GEN_CALL_VALUE. * calls.c (emit_call_1): Likewise. Remove support for sibcall_pop and sibcall_value_pop. * config/aarch64/aarch64.md (untyped_call): Use gen_call instead of GEN_CALL. * config/alpha/alpha.md (untyped_call): Likewise. * config/iq2000/iq2000.md (untyped_call): Likewise. * config/m68k/m68k.md (untyped_call): Likewise. * config/mips/mips.md (untyped_call): Likewise. * config/pa/pa.md (untyped_call): Likewise. * config/rs6000/rs6000.md (untyped_call): Likewise. * config/sparc/sparc.md (untyped_call): Likewise. * config/tilegx/tilegx.md (untyped_call): Likewise. * config/tilepro/tilepro.md (untyped_call): Likewise. * config/visium/visium.md (untyped_call): Likewise. * config/alpha/alpha.c (alpha_emit_xfloating_libcall): Use gen_call_value instead of GEN_CALL_VALUE. * config/arm/arm.md (untyped_call): Likewise. * config/cr16/cr16.c (cr16_function_arg): Remove reference to GEN_CALL. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@227143 138bc75d-0d04-0410-961f-82ee72b054a4
* [PATCH][ARM]Tighten the conditions for arm_movw, arm_movt.renlin2015-08-241-1/+1
| | | | | | | | | | | | | | | gcc/ 2015-08-24 Renlin Li <renlin.li@arm.com> * config/arm/arm-protos.h (arm_valid_symbolic_address_p): Declare. * config/arm/arm.c (arm_valid_symbolic_address_p): Define. * config/arm/arm.md (arm_movt): Use arm_valid_symbolic_address_p. * config/arm/constraints.md ("j"): Add check for high code. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@227129 138bc75d-0d04-0410-961f-82ee72b054a4
* 2015-08-12 Yvan Roux <yvan.roux@linaro.org>yroux2015-08-121-2/+2
| | | | | | | | | | PR target/67127 * config/arm/arm.md (movdi): Restrict illegitimate ldrd/strd checking to ARM core registers. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@226811 138bc75d-0d04-0410-961f-82ee72b054a4
* 2015-08-01 Michael Collison <michael.collison@linaro.orgcollison2015-08-021-0/+38
| | | | | | | | | | | | | Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> * gcc/config/arm/arm.md (*arm_smin_cmp): New pattern. (*arm_umin_cmp): Likewise. * gcc.target/arm/mincmp.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@226476 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM][2/3] Make if_neg_move and if_move_neg into insn_and_splitktkachov2015-07-311-22/+38
| | | | | | | | | * config/arm/arm.md (*if_neg_move): Convert to insn_and_split. Enable for TARGET_32BIT. (*if_move_neg): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@226447 138bc75d-0d04-0410-961f-82ee72b054a4
* Fix double word typos.aldyh2015-07-131-1/+1
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@225726 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM] fix movdi expander to avoid illegal ldrd/strdalalaw012015-07-061-0/+36
| | | | | | | * config/arm/arm.md (movdi): Avoid odd-number ldrd/strd in ARM state. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@225461 138bc75d-0d04-0410-961f-82ee72b054a4
* Add ARM/thumb attribute targetchrbr2015-06-101-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PR target/52144 * config/arm/arm.opt (THUMB, arm_restrict_it, inline_asm_unified): Save. * config/arm/arm-protos.h (arm_valid_target_attribute_tree): Declare. (arm_reset_previous_fndecl, arm_change_mode_p): Likewise. * config/arm/arm.h (SWITCHABLE_TARGET): Define. * config/arm/arm.c (arm_reset_previous_fndecl): New functions. (arm_valid_target_attribute_tree, arm_change_mode_p): Likewise. (arm_valid_target_attribute_p): Likewise. (arm_set_current_function, arm_can_inline_p): Likewise. (arm_valid_target_attribute_rec): Likewise. (arm_previous_fndecl): New variable. (TARGET_SET_CURRENT_FUNCTION, TARGET_OPTION_VALID_ATTRIBUTE_P): Define. (TARGET_CAN_INLINE_P): Define. (arm_asm_trampoline_template): Emit mode. (arm_file_start): Don't set unified syntax. (arm_declare_function_name): Set unified syntax and mode. (arm_option_override): Init target_option_default_node. and target_option_current_node. * config/arm/arm.md (*call_value_symbol): Set mode when possible. (*call_symbol): Likewise. * doc/extend.texi: Document ARM/Thumb target attribute. * doc/invoke.texi: Likewise. * gcc.target/arm/attr_arm.c: New test * gcc.target/arm/attr_arm-err.c: New test * gcc.target/arm/attr_thumb.c: New test * gcc.target/arm/attr_thumb-static.c: New test git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@224314 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/configavelenko2015-05-181-0/+49
| | | | | | | | | | | | | | | | | | | | 2015-05-18 Alex Velenko <Alex.Velenko@arm.com> * arm/arm.md (andsi_not_shiftsi_si_scc): New pattern. (andsi_not_shiftsi_si_scc_no_reuse): New pattern. gcc/testsuite 2015-05-18 Alex Velenko <Alex.Velenko@arm.com> * gcc.target/arm/bics_1.c : New testcase. * gcc.target/arm/bics_2.c : New testcase. * gcc.target/arm/bics_3.c : New testcase. * gcc.target/arm/bics_4.c : New testcase. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@223295 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/ChangeLog:kugan2015-05-161-21/+52
| | | | | | | | | | | | | | | | | | | | | | 2015-05-16 Kugan Vivekanandarajah <kuganv@linaro.org> Zhenqiang Chen <zhenqiang.chen@linaro.org> PR target/65768 * config/arm/arm.h (DONT_EARLY_SPLIT_CONSTANT): New macro. * config/arm/arm.md (subsi3, andsi3, iorsi3, xorsi3, movsi): Keep some large constants in register instead of splitting them. gcc/testsuite/ChangeLog: 2015-05-16 Kugan Vivekanandarajah <kuganv@linaro.org> Zhenqiang Chen <zhenqiang.chen@linaro.org> PR target/65768 * gcc.target/arm/maskdata.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@223235 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM] Fix PR 65955: Do not take REGNO on non-REG operand in movcond_addsiktkachov2015-05-121-1/+1
| | | | | | | | | PR target/65955 * config/arm/arm.md (movcond_addsi): Check that operands[2] is a REG before taking its REGNO. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@223049 138bc75d-0d04-0410-961f-82ee72b054a4
* 2014-09-23 Christian Bruel <christian.bruel@st.com>chrbr2015-05-111-2/+6
| | | | | | | | | | | | | | | | * config/arm/arm.c (arm_option_override): Reoganized and split into : (arm_option_params_internal); New function. (arm_option_check_internal): New function. (arm_option_override_internal): New function. (thumb_code, thumb1_code): Remove. * config/arm/arm.h (TREE_TARGET_THUMB, TREE_TARGET_THUMB1): New macros. (TREE_TARGET_THUM2, TREE_TARGET_ARM): Likewise. (thumb_code, thumb1_code): Remove. * config/arm/arm.md (is_thumb, is_thumb1): Check TARGET flag. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@222995 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/rsandifo2015-05-071-48/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * rtl.h (always_void_p): New function. * gengenrtl.c (always_void_p): Likewise. (genmacro): Don't add a mode parameter to gen_rtx_foo if rtxes with code foo are always VOIDmode. * genemit.c (gen_exp): Update gen_rtx_foo calls accordingly. * builtins.c, caller-save.c, calls.c, cfgexpand.c, combine.c, compare-elim.c, config/aarch64/aarch64.c, config/aarch64/aarch64.md, config/alpha/alpha.c, config/alpha/alpha.md, config/arc/arc.c, config/arc/arc.md, config/arm/arm-fixed.md, config/arm/arm.c, config/arm/arm.md, config/arm/ldrdstrd.md, config/arm/thumb2.md, config/arm/vfp.md, config/avr/avr.c, config/bfin/bfin.c, config/c6x/c6x.c, config/c6x/c6x.md, config/cr16/cr16.c, config/cris/cris.c, config/cris/cris.md, config/darwin.c, config/epiphany/epiphany.c, config/epiphany/epiphany.md, config/fr30/fr30.c, config/frv/frv.c, config/frv/frv.md, config/h8300/h8300.c, config/i386/i386.c, config/i386/i386.md, config/i386/sse.md, config/ia64/ia64.c, config/ia64/vect.md, config/iq2000/iq2000.c, config/iq2000/iq2000.md, config/lm32/lm32.c, config/lm32/lm32.md, config/m32c/m32c.c, config/m32r/m32r.c, config/m68k/m68k.c, config/m68k/m68k.md, config/mcore/mcore.c, config/mcore/mcore.md, config/mep/mep.c, config/microblaze/microblaze.c, config/mips/mips.c, config/mips/mips.md, config/mmix/mmix.c, config/mn10300/mn10300.c, config/msp430/msp430.c, config/nds32/nds32-memory-manipulation.c, config/nds32/nds32.c, config/nds32/nds32.md, config/nios2/nios2.c, config/nvptx/nvptx.c, config/pa/pa.c, config/pa/pa.md, config/rl78/rl78.c, config/rs6000/altivec.md, config/rs6000/rs6000.c, config/rs6000/rs6000.md, config/rs6000/vector.md, config/rs6000/vsx.md, config/rx/rx.c, config/rx/rx.md, config/s390/s390.c, config/s390/s390.md, config/sh/sh.c, config/sh/sh.md, config/sh/sh_treg_combine.cc, config/sparc/sparc.c, config/sparc/sparc.md, config/spu/spu.c, config/spu/spu.md, config/stormy16/stormy16.c, config/tilegx/tilegx.c, config/tilegx/tilegx.md, config/tilepro/tilepro.c, config/tilepro/tilepro.md, config/v850/v850.c, config/v850/v850.md, config/vax/vax.c, config/visium/visium.c, config/xtensa/xtensa.c, cprop.c, dse.c, expr.c, gcse.c, ifcvt.c, ira.c, jump.c, lower-subreg.c, lra-constraints.c, lra-eliminations.c, lra.c, postreload.c, ree.c, reg-stack.c, reload.c, reload1.c, reorg.c, sel-sched.c, var-tracking.c: Update calls accordingly. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@222883 138bc75d-0d04-0410-961f-82ee72b054a4
* 2015-04-28 Yvan Roux <yvan.roux@linaro.org>yroux2015-04-281-16/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | * config/arm/arm.md (*arm_movt): Fix type attribute. (*cmpsi_shiftsi): Likewise. (*cmpsi_shiftsi_swp): Likewise. (*movsicc_insn): Likewise. (*cond_move): Likewise. (*if_plus_move): Likewise. (*if_move_plus): Likewise. (*if_arith_move): Likewise. (*if_move_arith): Likewise. (*if_shift_move): Likewise. (*if_move_shift): Likewise. (*arm_movtas_ze): Likewise. * config/arm/thumb2.md (*thumb2_movsicc_insn): Fix alternative redundancy and type attribute. (*thumb2_movsi_insn): Fix type attribute. (*thumb2_addsi_short): Likewise. (thumb2_addsi3_compare0): Likewise. (*thumb2_addsi3_compare0_scratch): Merge alternatives and fix attributes accordingly. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@222528 138bc75d-0d04-0410-961f-82ee72b054a4
* 2015-04-27 Yvan Roux <yvan.roux@linaro.org>yroux2015-04-271-3/+3
| | | | | | | | | * config/arm/arm.md (*arm_subsi3_insn): Fixed redundant alternatives. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@222453 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM][trivial] Use uppercase for code iterator namesktkachov2015-04-241-7/+7
| | | | | | | | | | | | | | | | | | | | * config/arm/iterators.md (shiftable_ops): Rename to... (SHIFTABLE_OPS): ... This. Update use in comments. (ior_xor): Rename to... (IOR_XOR): ... This. (vqh_ops): Rename to... (VQH_OPS): ... This. (vqhs_ops): Rename to... (VQHS_OPS): ... This. (rshifts): Rename to... (RSHIFTS): ... This. (returns): Rename to... (RETURNS): ... This. * config/arm/arm.md: Update uses of the above. * config/arm/neon.md: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@222416 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM] Restrict {load,store}_multiple expanders to MAX_LD_STM_OPS regsktkachov2015-04-231-2/+2
| | | | | | | | | | * config/arm/arm.md (load_multiple): Reject operand 2 greater than MAX_LDM_STM_OPS. (store_multiple): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@222357 138bc75d-0d04-0410-961f-82ee72b054a4
* gcc/xguo2015-02-261-1/+2
| | | | | | | | | | | | | | | | | * config/arm/arm-cores.def (cortex-m7): Add flag FL_NO_VOLATILE_CE. * config/arm/arm-protos.h (FL_NO_VOLATILE_CE): New flag. (arm_arch_no_volatile_ce): Declare new global variable. * config/arm/arm.c (arm_arch_no_volatile_ce): New global variable. (arm_option_override): Assign value to arm_arch_no_volatile_ce. * config/arm/arm.h (arm_arch_no_volatile_ce): Declare it. (TARGET_NO_VOLATILE_CE): New macro. * config/arm/arm.md (arm_comparison_operator): Disabled if not allow volatile memory access in IT block gcc/testsuite/ * gcc.target/arm/no-volatile-in-it.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@220999 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM] Wire up the new scheduler description for the ARM Cortex-A57 processorjgreenhalgh2015-01-261-2/+3
| | | | | | | | | | | | * config/arm/arm-cores.def (cortex-a57): Use the new Cortex-A57 pipeline model. config/arm/arm.md: Include the new Cortex-A57 model. (generic_sched): Don't use generic_sched when tuning for Cortex-A57. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@220103 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM] Move comment about splitting Thumb1 patterns to thumb1.mdktkachov2015-01-161-19/+0
| | | | | | | | * config/arm/arm.md: Move comment about splitting Thumb1 patterns to... * config/arm/thumb1.md: ... Here. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@219755 138bc75d-0d04-0410-961f-82ee72b054a4
* 2015-01-15 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>ptomsich2015-01-151-2/+9
| | | | | | | | | | | | | | * config/arm/arm.md (generic_sched): Specify xgene1 in 'no' list. Include xgene1.md. * config/arm/arm.c (arm_issue_rate): Specify 4 for xgene1. * config/arm/arm-cores.def (xgene1): New entry. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Regenerate. * config/arm/bpabi.h (BE8_LINK_SPEC): Specify mcpu=xgene1. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@219661 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM] Fix PR target/64460: Set 'shift' attr properly on some patterns.ktkachov2015-01-141-2/+2
| | | | | | | | | | | | PR target/64460 * config/arm/arm.md (*<arith_shift_insn>_multsi): Set 'shift' to 2. (*<arith_shift_insn>_shiftsi): Set 'shift' attr to 3. * gcc.target/arm/pr64460_1.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@219583 138bc75d-0d04-0410-961f-82ee72b054a4
* Update copyright years.jakub2015-01-051-1/+1
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@219188 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM] Optimize copysign/copysignf for soft-float using BFIjiwang2014-11-281-0/+41
| | | | | | | | | | | | | | gcc/ * config/arm/arm.md (copysignsf3): New pattern. (copysigndf3): Likewise. gcc/testsuite/ * gcc.target/arm/copysign_softfloat_1.c: New copysign/copysignf testcase for soft-float. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218159 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM] Add Cortex-A17 supportktkachov2014-11-281-2/+3
| | | | | | | | | | | | | | | | | * config/arm/arm.md (generic_sched): Specify cortexa17 in 'no' list. Include cortex-a17.md. * config/arm/arm.c (arm_issue_rate): Specify 2 for cortexa17. * config/arm/arm-cores.def (cortex-a17): New entry. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Regenerate. * config/arm/bpabi.h (BE8_LINK_SPEC): Specify mcpu=cortex-a17. * config/arm/cortex-a17.md: New file. * config/arm/cortex-a17-neon.md: New file. * config/arm/driver-arm.c (arm_cpu_table): Add entry for cortex-a17. * config/arm/t-aprofile: Add cortex-a17 entries to MULTILIB_MATCHES. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218145 138bc75d-0d04-0410-961f-82ee72b054a4
* 2014-11-27 Thomas Preud'homme <thomas.preudhomme@arm.com>thopre012014-11-271-9/+42
| | | | | | | | | | | | | | | | | | | | gcc/ PR target/59593 * config/arm/arm.c (dump_minipool): dispatch to consttable pattern based on mode size. * config/arm/arm.md (consttable_1): Move from config/arm/thumb1.md and make it TARGET_EITHER. (consttable_2): Move from config/arm/thumb1.md, make it TARGET_EITHER and move HFmode handling from consttable_4 to it. (consttable_4): Move HFmode handling to consttable_2 pattern. * config/arm/thumb1.md (consttable_1): Move to config/arm/arm.md. (consttable_2): Ditto. gcc/testsuite/ PR target/59593 * gcc.target/arm/constant-pool.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218118 138bc75d-0d04-0410-961f-82ee72b054a4
* Fix missing output formatter.ramana2014-11-201-1/+1
| | | | | | | | | | | | 2014-11-20 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> PR target/59593 * config/arm/arm.md (*movhi_insn): Use right formatting for immediate. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@217826 138bc75d-0d04-0410-961f-82ee72b054a4
* PR target/59593fyang2014-11-191-7/+15
| | | | | | | | | * config/arm/arm.md (define_attr "arch"): Add v6t2. (define_attr "arch_enabled"): Add test for the above. (*movhi_insn_arch4): Add new alternative. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@217772 138bc75d-0d04-0410-961f-82ee72b054a4
* [ARM] Use std::swap instead of manually swappingktkachov2014-11-181-12/+4
| | | | | | | | | | | | | | | | | * config/arm/arm.md (unaligned_loaddi): Use std::swap instead of manual swapping implementation. (movcond_addsi): Likewise. * config/arm/arm.c (arm_canonicalize_comparison): Likewise. (arm_select_dominance_cc_mode): Likewise. (arm_reload_out_hi): Likewise. (gen_operands_ldrd_strd): Likewise. (output_move_double): Likewise. (arm_print_operand_address): Likewise. (thumb_output_move_mem_multiple): Likewise. (SWAP_RTX): Delete. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@217701 138bc75d-0d04-0410-961f-82ee72b054a4
* 2014-11-17 Terry Guo <terry.guo@arm.com>xguo2014-11-181-2/+9
| | | | | | | | | * config/arm/arm.c (arm_issue_rate): Return 2 for cortex-m7. * config/arm/arm.md (generic_sched): Exclude cortex-m7. (generic_vfp): Likewise. * config/arm/cortex-m7.md: Pipeline description for cortex-m7. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@217687 138bc75d-0d04-0410-961f-82ee72b054a4
* Fix typo in *<arith_shift_insn>_shiftsiramana2014-11-121-1/+1
| | | | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@217430 138bc75d-0d04-0410-961f-82ee72b054a4
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