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* arm: Fix ICEs with compare-and-swap and -march=armv8-m.base [PR99977]Alex Coplan2021-04-271-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PR shows two ICEs with __sync_bool_compare_and_swap and -mcpu=cortex-m23 (equivalently, -march=armv8-m.base): one in LRA and one later on, after the CAS insn is split. The LRA ICE occurs because the @atomic_compare_and_swap<CCSI:arch><SIDI:mode>_1 pattern attempts to tie two output operands together (operands 0 and 1 in the third alternative). LRA can't handle this, since it doesn't make sense for an insn to assign to the same operand twice. The later (post-splitting) ICE occurs because the expansion of the cbranchsi4_scratch insn doesn't quite go according to plan. As it stands, arm_split_compare_and_swap calls gen_cbranchsi4_scratch, attempting to pass a register (neg_bval) to use as a scratch register. However, since the RTL template has a match_scratch here, gen_cbranchsi4_scratch ignores this argument and produces a scratch rtx. Since this is all happening after RA, this is doomed to fail (and we get an ICE about the insn not matching its constraints). It seems that the motivation for the choice of constraints in the atomic_compare_and_swap pattern comes from an attempt to satisfy the constraints of the cbranchsi4_scratch insn. This insn requires the scratch register to be the same as the input register in the case that we use a larger negative immediate (one that satisfies J, but not L). Of course, as noted above, LRA refuses to assign two output operands to the same register, so this was never going to work. The solution I'm proposing here is to collapse the alternatives to the CAS insn (allowing the two output register operands to be matched to different registers) and to ensure that the constraints for cbranchsi4_scratch are met in arm_split_compare_and_swap. We do this by inserting a move to ensure the source and destination registers match if necessary (i.e. in the case of large negative immediates). Another notable change here is that we only do: emit_move_insn (neg_bval, const1_rtx); for non-negative immediates. This is because the ADDS instruction used in the negative case suffices to leave a suitable value in neg_bval: if the operands compare equal, we don't take the branch (so neg_bval will be set by the load exclusive). Otherwise, the ADDS will leave a nonzero value in neg_bval, which will correctly signal that the CAS has failed when it is later negated. gcc/ChangeLog: PR target/99977 * config/arm/arm.c (arm_split_compare_and_swap): Fix up codegen with negative immediates: ensure we expand cbranchsi4_scratch correctly and ensure we satisfy its constraints. * config/arm/sync.md (@atomic_compare_and_swap<CCSI:arch><NARROW:mode>_1): Don't attempt to tie two output operands together with constraints; collapse two alternatives. (@atomic_compare_and_swap<CCSI:arch><SIDI:mode>_1): Likewise. * config/arm/thumb1.md (cbranchsi4_neg_late): New. gcc/testsuite/ChangeLog: PR target/99977 * gcc.target/arm/pr99977.c: New test.
* Update copyright years.Jakub Jelinek2021-01-041-1/+1
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* Update copyright years.Jakub Jelinek2020-01-011-1/+1
| | | | From-SVN: r279813
* [arm] Fix ambiguous .md attribute usesRichard Sandiford2019-07-061-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is part of a series that fixes ambiguous attribute uses in .md files, i.e. cases in which attributes didn't use <ITER:ATTR> to specify an iterator, and in which <ATTR> could have different values depending on the iterator chosen. I think this is a genuine bugfix for Thumb-1, since previously the LDREX width was taken from the SImode success result rather than the memory mode: -#define HAVE_atomic_compare_and_swapt1qi_1 ((TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER) && (TARGET_THUMB1)) -#define HAVE_atomic_compare_and_swapt1hi_1 ((TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER) && (TARGET_THUMB1)) -#define HAVE_atomic_compare_and_swapt1di_1 ((TARGET_HAVE_LDREX && TARGET_HAVE_MEMORY_BARRIER) && (TARGET_THUMB1)) +#define HAVE_atomic_compare_and_swapt1qi_1 ((TARGET_HAVE_LDREXBH && TARGET_HAVE_MEMORY_BARRIER) && (TARGET_THUMB1)) +#define HAVE_atomic_compare_and_swapt1hi_1 ((TARGET_HAVE_LDREXBH && TARGET_HAVE_MEMORY_BARRIER) && (TARGET_THUMB1)) +#define HAVE_atomic_compare_and_swapt1di_1 ((TARGET_HAVE_LDREXD && ARM_DOUBLEWORD_ALIGN \ + && TARGET_HAVE_MEMORY_BARRIER) && (TARGET_THUMB1)) The same goes for the predicate and constraints in @atomic_compare_and_swapt1di_1, which previously used the SI values from the success result. 2019-07-06 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/arm/sync.md (@atomic_compare_and_swap<CCSI:arch><NARROW:mode>_1): Use <NARROW:sync_predtab> instead of (implicitly) <CCSI:sync_predtab>. (@atomic_compare_and_swap<CCSI:arch><SIDI:mode>_1): Likewise <SIDI:sync_predtab>. Use <SIDI:cas_cmp_operand> and <SIDI:cas_cmp_str>. From-SVN: r273158
* [Arm] Remove constraint strings from define_expand constructs in the back endDennis Zhang2019-06-281-5/+5
| | | | | | | | | | | | | | | | | | | | | | | A number of Arm define_expand patterns have specified constraints for their operands. But the constraint strings are ignored at expand time and are therefore redundant/useless. We now avoid specifying constraints in new define_expands, but we should clean up the existing define_expand definitions. 2019-06-28 Dennis Zhang <dennis.zhang@arm.com> * config/arm/arm.md: Remove redundant constraints from define_expand but leave reload_inm and reload_outm patterns untouched since they need special constraints to work. * config/arm/arm-fixed.md: Remove redundant constraints from define_expand. * config/arm/iwmmxt.md: Likewise. * config/arm/neon.md: Likewise. * config/arm/sync.md: Likewise. * config/arm/thumb1.md: Likewise. * config/arm/vec-common.md: Likewise. From-SVN: r272779
* Update copyright years.Jakub Jelinek2019-01-011-1/+1
| | | | From-SVN: r267494
* [PATCH, ARM] Clean up arm backend using the @ construct for MD patternsMihail Ionescu2018-11-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes some of the machine mode checks from the arm backend when emitting instructions by using the '@' construct (Parameterized Names[2]). It is based on the previous AArch64 patch[1]. [1] https://gcc.gnu.org/ml/gcc-patches/2018-07/msg00673.html [2] https://gcc.gnu.org/onlinedocs/gccint/Parameterized-Names.html#Parameterized-Names 2018-23-11 Mihail Ionescu <mihail.ionescu@arm.com> * config/arm/arm.c (arm_expand_compare_and_swap): Simplify and call gen_atomic_compare_swap_1. (arm_evpc_neon_vuzp): Likewise gen_neon_vuzp_internal. (arm_evpc_neon_vtrn): Likewise gen_neon_vtrn_internal. (arm_evpc_neon_vext): Likewise gen_neon_vext_internal. (arm_evpc_neon_vzip): Likewise gen_neon_vzip_internal. (arm_evpc_neon_vrev): Replace the function pointer and simplify the mode checks. * config/arm/arm.md (neon_vext<mode>), (neon_vrev64<mode>, neon_vrev32<mode>), (neon_vrev16<mode>, neon_vtrn<mode>_internal), (neon_vzip<mode>_internal, neon_vuzp<mode>_internal): Add an '@'character before the pattern name. * config/arm/sync.md: (atomic_compare_and_swap<CCSI:arch><NARROW:mode>_1), (atomic_compare_and_swap<CCSI:arch><SIDI:mode>_1): Likewise. From-SVN: r266404
* A few places in the arm and aarch64 backends check whether an atomic ↵Matthew Malcomson2018-09-261-12/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | operation needs acquire or release semantics. A few places in the arm and aarch64 backends check whether an atomic operation needs acquire or release semantics. This is generally done with a check like (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_release (model)) In this patch we introduce two helper functions to make things a little tidier. There are a few places in the arm/ backend that check whether an operation needs memory model semantics with an idiom that can now be replaced with the new aarch_mm_needs_* functions, so we make that replacement. There is also some backslash removal to make things a little tidier. Full bootstrap and regression test plus cross-compilation regression tests done on arm-none-linux-gnueabihf. Ok for trunk? gcc/ChangeLog: 2018-09-20 Matthew Malcomson <matthew.malcomson@arm.com> * config/arm/arm.c (arm_split_compare_and_swap, arm_split_atomic_op): Use new helper functions. * config/arm/sync.md (atomic_load<mode>, atomic_store<mode>): Use new helper functions. * config/arm/aarch-common-protos.h (aarch_mm_needs_acquire, aarch_mm_needs_release): New declarations. * config/arm/aarch-common.c (aarch_mm_needs_acquire, aarch_mm_needs_release): New. From-SVN: r264598
* Update copyright years.Jakub Jelinek2018-01-031-1/+1
| | | | From-SVN: r256169
* [Arm] Cleanup IT attributesWilco Dijkstra2017-11-061-24/+12
| | | | | | | | | | | | | | | | | | | | A recent change to remove the movdi_vfp_cortexa8 meant that ldrd was used in ITs block even when arm_restrict_it was enabled. Rather than just fixing this latent issue, change the default of predicable_short_it to "no" so that only 16-bit instructions need to be marked with it. As a result there are far fewer patterns that need the attribute, and omitting predicable_short_it is no longer causing issues. * config/arm/arm.md (predicable_short_it): Change default to "no", improve documentation, remove uses that are identical to the default. (enabled_for_depr_it): Rename to enabled_for_short_it. * gcc/config/arm/arm-fixed.md (predicable_short_it): Remove default uses. * gcc/config/arm/ldmstm.md (predicable_short_it): Likewise. * gcc/config/arm/sync.md (predicable_short_it): Likewise. * gcc/config/arm/thumb2.md (predicable_short_it): Likewise. * gcc/config/arm/vfp.md (predicable_short_it): Likewise. From-SVN: r254463
* [ARM] Set mode for success result of atomic compare and swapThomas Preud'homme2017-05-031-6/+6
| | | | | | | | | | | | | | | | 2017-05-03 Thomas Preud'homme <thomas.preudhomme@arm.com> gcc/ * config/arm/iterators.md (CCSI): New mode iterator. (arch): New mode attribute. * config/arm/sync.md (atomic_compare_and_swap<mode>_1): Rename into ... (atomic_compare_and_swap<CCSI:arch><NARROW:mode>_1): This and ... (atomic_compare_and_swap<CCSI:arch><SIDI:mode>_1): This. Use CCSI code iterator for success result mode. * config/arm/arm.c (arm_expand_compare_and_swap): Adapt code to use the corresponding new insn generators. From-SVN: r247542
* Update copyright years.Jakub Jelinek2017-01-011-1/+1
| | | | From-SVN: r243994
* Adapt other atomic operations to ARMv8-M BaselineThomas Preud'homme2016-10-271-37/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2016-10-27 Thomas Preud'homme <thomas.preudhomme@arm.com> gcc/ * config/arm/arm.c (arm_split_atomic_op): Add function comment. Add logic to to decide whether to copy over old value to register for new value. * config/arm/sync.md: Add comments explaning why mode and code attribute are not defined in iterators.md (thumb1_atomic_op_str): New code attribute. (thumb1_atomic_newop_str): Likewise. (thumb1_atomic_fetch_op_str): Likewise. (thumb1_atomic_fetch_newop_str): Likewise. (thumb1_atomic_fetch_oldop_str): Likewise. (atomic_exchange<mode>): Add new ARMv8-M Baseline only alternatives to mirror the more restrictive constraints of the Thumb-1 insns after split compared to Thumb-2 counterpart insns. (atomic_<sync_optab><mode>): Likewise. Add comment to keep constraints in sync with non atomic version. (atomic_nand<mode>): Likewise. (atomic_fetch_<sync_optab><mode>): Likewise. (atomic_fetch_nand<mode>): Likewise. (atomic_<sync_optab>_fetch<mode>): Likewise. (atomic_nand_fetch<mode>): Likewise. * config/arm/thumb1.md (thumb1_addsi3): Add comment to keep contraint in sync with atomic version. (thumb1_subsi3_insn): Likewise. (thumb1_andsi3_insn): Likewise. (thumb1_iorsi3_insn): Likewise. (thumb1_xorsi3_insn): Likewise. From-SVN: r241614
* Adapt atomic compare and swap to ARMv8-M BaselineThomas Preud'homme2016-10-261-14/+20
| | | | | | | | | | | | | | | | | 2016-10-26 Thomas Preud'homme <thomas.preudhomme@arm.com> gcc/ * config/arm/sync.md (atomic_compare_and_swap<mode>_1): Add new ARMv8-M Baseline only alternatives to (i) hold store atomic success value in a return register rather than a scratch register, (ii) use a low register for it and to (iii) ensure the cbranchsi insn generated by the split respect the constraints of Thumb-1 cbranchsi4_insn and cbranchsi4_scratch. * config/arm/thumb1.md (cbranchsi4_insn): Add comment to indicate constraints must match those in atomic_compare_and_swap. (cbranchsi4_scratch): Likewise. From-SVN: r241578
* Refactor atomic compare_and_swap to make it fit for ARMv8-M BaselineThomas Preud'homme2016-10-261-20/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | 2016-10-26 Thomas Preud'homme <thomas.preudhomme@arm.com> gcc/ * config/arm/arm.c (arm_expand_compare_and_swap): Add new bdst local variable. Add the new parameter to the insn generator. Set that parameter to be CC flag for 32-bit targets, bval otherwise. Set the return value from the negation of that parameter for Thumb-1, keeping the logic unchanged otherwise except for using bdst as the destination register of the compare_and_swap insn. (arm_split_compare_and_swap): Add explanation about how is the value returned to the function comment. Rename scratch variable to neg_bval. Adapt initialization of variables holding operands to the new operand numbers. Use return register to hold result of store exclusive for Thumb-1, scratch register otherwise. Construct the appropriate cbranch for Thumb-1 targets, keeping the logic unchanged for 32-bit targets. Guard Z flag setting to restrict to 32bit targets. Use gen_cbranchsi4 rather than hand-written conditional branch to loop for strongly ordered compare_and_swap. * config/arm/predicates.md (cc_register_operand): New predicate. * config/arm/sync.md (atomic_compare_and_swap<mode>_1): Use a match_operand with the new predicate to accept either the CC flag or a destination register for the boolean return value, restricting it to CC flag only via constraint. Adapt operand numbers accordingly. From-SVN: r241577
* constraints.md (Q constraint): Document its use for Thumb-1.Thomas Preud'homme2016-10-251-34/+74
| | | | | | | | | | | | | | | | | | | | | | | | | 2016-10-25 Thomas Preud'homme <thomas.preudhomme@arm.com> gcc/ * config/arm/constraints.md (Q constraint): Document its use for Thumb-1. (Pf constraint): New constraint for relaxed, consume or relaxed memory models. * config/arm/sync.md (atomic_load<mode>): Add new ARMv8-M Baseline only alternatives to allow any register when memory model matches Pf and thus lda is used, but only low registers otherwise. Use unpredicated output template for Thumb-1 targets. (atomic_store<mode>): Likewise for stl. (arm_load_exclusive<mode>): Add new ARMv8-M Baseline only alternative whose output template does not have predication. (arm_load_acquire_exclusive<mode>): Likewise. (arm_load_exclusivesi): Likewise. (arm_load_acquire_exclusivesi): Likewise. (arm_store_release_exclusive<mode>): Likewise. (arm_store_exclusive<mode>): Use unpredicated output template for Thumb-1 targets. From-SVN: r241507
* arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M Mainline.Thomas Preud'homme2016-07-141-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2016-07-14 Thomas Preud'homme <thomas.preudhomme@arm.com> gcc/ * config/arm/arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M Mainline. (TARGET_HAVE_LDACQD): New macro. * config/arm/sync.md (atomic_loaddi): Use TARGET_HAVE_LDACQD rather than TARGET_HAVE_LDACQ. (arm_load_acquire_exclusivedi): Likewise. (arm_store_release_exclusivedi): Likewise. libgcc/ * gcc.target/arm/atomic-comp-swap-release-acquire.c: Rename into ... * gcc.target/arm/atomic-comp-swap-release-acquire-1.c: This. * gcc.target/arm/atomic-op-acq_rel.c: Rename into ... * gcc.target/arm/atomic-op-acq_rel-1.c: This. * gcc.target/arm/atomic-op-acquire.c: Rename into ... * gcc.target/arm/atomic-op-acquire-1.c: This. * gcc.target/arm/atomic-op-char.c: Rename into ... * gcc.target/arm/atomic-op-char-1.c: This. * gcc.target/arm/atomic-op-consume.c: Rename into ... * gcc.target/arm/atomic-op-consume-1.c: This. * gcc.target/arm/atomic-op-int.c: Rename into ... * gcc.target/arm/atomic-op-int-1.c: This. * gcc.target/arm/atomic-op-relaxed.c: Rename into ... * gcc.target/arm/atomic-op-relaxed-1.c: This. * gcc.target/arm/atomic-op-release.c: Rename into ... * gcc.target/arm/atomic-op-release-1.c: This. * gcc.target/arm/atomic-op-seq_cst.c: Rename into ... * gcc.target/arm/atomic-op-seq_cst-1.c: This. * gcc.target/arm/atomic-op-short.c: Rename into ... * gcc.target/arm/atomic-op-short-1.c: This. * gcc.target/arm/atomic-comp-swap-release-acquire-2.c: New test. * gcc.target/arm/atomic-op-acq_rel-2.c: Likewise. * gcc.target/arm/atomic-op-acquire-2.c: Likewise. * gcc.target/arm/atomic-op-char-2.c: Likewise. * gcc.target/arm/atomic-op-consume-2.c: Likewise. * gcc.target/arm/atomic-op-int-2.c: Likewise. * gcc.target/arm/atomic-op-relaxed-2.c: Likewise. * gcc.target/arm/atomic-op-release-2.c: Likewise. * gcc.target/arm/atomic-op-seq_cst-2.c: Likewise. * gcc.target/arm/atomic-op-short-2.c: Likewise. From-SVN: r238348
* [ARM] Use proper output modifier for DImode register in store exclusive patternsKyrylo Tkachov2016-06-011-9/+6
| | | | | | | | | * config/arm/sync.md (arm_store_exclusive<mode>): Use 'H' output modifier on operands[2] rather than creating a new entry in out-of-bounds memory of the operands array. (arm_store_release_exclusivedi): Likewise. From-SVN: r236984
* [ARM] PR target/69875 Fix atomic_loaddi expansionKyrylo Tkachov2016-02-241-17/+47
| | | | | | | | | | | | | | | | | | | | | | | | PR target/69875 * config/arm/arm.h (TARGET_HAVE_LPAE): Define. * config/arm/unspecs.md (VUNSPEC_LDRD_ATOMIC): New value. * config/arm/sync.md (arm_atomic_loaddi2_ldrd): New pattern. (atomic_loaddi_1): Delete. (atomic_loaddi): Rewrite expander using the above changes. * gcc.target/arm/atomic_loaddi_acquire.x: New file. * gcc.target/arm/atomic_loaddi_relaxed.x: Likewise. * gcc.target/arm/atomic_loaddi_seq_cst.x: Likewise. * gcc.target/arm/atomic_loaddi_1.c: New test. * gcc.target/arm/atomic_loaddi_2.c: Likewise. * gcc.target/arm/atomic_loaddi_3.c: Likewise. * gcc.target/arm/atomic_loaddi_4.c: Likewise. * gcc.target/arm/atomic_loaddi_5.c: Likewise. * gcc.target/arm/atomic_loaddi_6.c: Likewise. * gcc.target/arm/atomic_loaddi_7.c: Likewise. * gcc.target/arm/atomic_loaddi_8.c: Likewise. * gcc.target/arm/atomic_loaddi_9.c: Likewise. From-SVN: r233658
* Update copyright years.Jakub Jelinek2016-01-041-1/+1
| | | | From-SVN: r232055
* [Patch ARM] Unified assembler in ARM state.Ramana Radhakrishnan2015-11-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc/ChangeLog: 2015-11-06 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * config/arm/arm-ldmstm.ml: Rewrite to generate unified asm templates. * config/arm/arm.c (arm_asm_trampoline_template): Make unified asm safe. (arm_output_multireg_pop): Likewise. (output_move_double): Likewise. (output_move_quad): Likewise. (output_return_instruction): Likewise. (arm_print_operand): Remove support for %( and %. print modifiers. (arm_output_shift): Make unified asm. (arm_declare_function_name): Likewise. * config/arm/arm.h (TARGET_UNIFIED_ASM): Delete. (ASM_APP_OFF): Adjust. (ASM_OUTPUT_REG_PUSH): Undo special casing for TARGET_ARM. (ASM_OUTPUT_REG_POP): Likewise. * config/arm/arm.md: Adjust uses of %., %(, %) * config/arm/sync.md: Likewise. * config/arm/thumb2.md: Likewise. * config/arm/ldmstm.md: Regenerate. * config/arm/arm.opt (masm-unified-syntax): Do not special case Thumb. * doc/invoke.texi (masm-unified-syntax): Update documentation. gcc/testsuite/ChangeLog: 2015-11-06 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * gcc.target/arm/combine-movs.c: * gcc.target/arm/interrupt-1.c: * gcc.target/arm/interrupt-2.c: * gcc.target/arm/unaligned-memcpy-4.c: From-SVN: r229875
* Use dmb ish instead of dmb sy for ARM.Ramana Radhakrishnan2015-06-101-5/+2
| | | | | | | | | 2015-06-10 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * config/arm/sync.md (*memory_barrier): Use dmb ish instead of dmb sy. Adjust tabs. From-SVN: r224317
* [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing ↵Shiva Chen2015-06-091-6/+8
| | | | | | | | | | | | | | | | | conditional code On behalf of Shiva Chen 2015-06-09 Shiva Chen <shiva0217@gmail.com> * sync.md (atomic_load<mode>): Add conditional code for lda/ldr (atomic_store<mode>): Likewise. 2015-06-09 Shiva Chen <shiva0217@gmail.com> * gcc.target/arm/stl-cond.c: New test. From-SVN: r224269
* re PR target/65697 (__atomic memory barriers not strong enough for __sync ↵Andrew MacLeod2015-05-121-10/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | builtins) 2015-05-12 Andrew MacLeod <amacleod@redhat.com> PR target/65697 * coretypes.h (MEMMODEL_SYNC, MEMMODEL_BASE_MASK): New macros. (enum memmodel): Add SYNC_{ACQUIRE,RELEASE,SEQ_CST}. * tree.h (memmodel_from_int, memmodel_base, is_mm_relaxed, is_mm_consume,is_mm_acquire, is_mm_release, is_mm_acq_rel, is_mm_seq_cst, is_mm_sync): New accessor functions. * builtins.c (expand_builtin_sync_operation, expand_builtin_compare_and_swap): Use MEMMODEL_SYNC_SEQ_CST. (expand_builtin_sync_lock_release): Use MEMMODEL_SYNC_RELEASE. (get_memmodel, expand_builtin_atomic_compare_exchange, expand_builtin_atomic_load, expand_builtin_atomic_store, expand_builtin_atomic_clear): Use new accessor routines. (expand_builtin_sync_synchronize): Use MEMMODEL_SYNC_SEQ_CST. * optabs.c (expand_compare_and_swap_loop): Use MEMMODEL_SYNC_SEQ_CST. (maybe_emit_sync_lock_test_and_set): Use new accessors and MEMMODEL_SYNC_ACQUIRE. (expand_sync_lock_test_and_set): Use MEMMODEL_SYNC_ACQUIRE. (expand_mem_thread_fence, expand_mem_signal_fence, expand_atomic_load, expand_atomic_store): Use new accessors. * emit-rtl.c (need_atomic_barrier_p): Add additional enum cases. * tsan.c (instrument_builtin_call): Update check for memory model beyond final enum to use MEMMODEL_LAST. * c-family/c-common.c: Use new accessor for memmodel_base. * config/aarch64/aarch64.c (aarch64_expand_compare_and_swap): Use new accessors. * config/aarch64/atomics.md (atomic_load<mode>,atomic_store<mode>, arch64_load_exclusive<mode>, aarch64_store_exclusive<mode>, mem_thread_fence, *dmb): Likewise. * config/alpha/alpha.c (alpha_split_compare_and_swap, alpha_split_compare_and_swap_12): Likewise. * config/arm/arm.c (arm_expand_compare_and_swap, arm_split_compare_and_swap, arm_split_atomic_op): Likewise. * config/arm/sync.md (atomic_load<mode>, atomic_store<mode>, atomic_loaddi): Likewise. * config/i386/i386.c (ix86_destroy_cost_data, ix86_memmodel_check): Likewise. * config/i386/sync.md (mem_thread_fence, atomic_store<mode>): Likewise. * config/ia64/ia64.c (ia64_expand_atomic_op): Add new memmodel cases and use new accessors. * config/ia64/sync.md (mem_thread_fence, atomic_load<mode>, atomic_store<mode>, atomic_compare_and_swap<mode>, atomic_exchange<mode>): Use new accessors. * config/mips/mips.c (mips_process_sync_loop): Likewise. * config/pa/pa.md (atomic_loaddi, atomic_storedi): Likewise. * config/rs6000/rs6000.c (rs6000_pre_atomic_barrier, rs6000_post_atomic_barrier): Add new cases. (rs6000_expand_atomic_compare_and_swap): Use new accessors. * config/rs6000/sync.md (mem_thread_fence): Add new cases. (atomic_load<mode>): Add new cases and use new accessors. (store_quadpti): Add new cases. * config/s390/s390.md (mem_thread_fence, atomic_store<mode>): Use new accessors. * config/sparc/sparc.c (sparc_emit_membar_for_model): Use new accessors. * doc/extend.texi: Update docs to indicate 16 bits are used for memory model, not 8. From-SVN: r223096
* Update copyright years.Jakub Jelinek2015-01-051-1/+1
| | | | From-SVN: r219188
* Update copyright years in gcc/Richard Sandiford2014-01-021-1/+1
| | | | From-SVN: r206289
* sync.md (atomic_loaddi_1): Disable predication for arm_restrict_it.Kyrylo Tkachov2013-06-061-10/+20
| | | | | | | | | | | | | | | | | | | 2013-06-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/arm/sync.md (atomic_loaddi_1): Disable predication for arm_restrict_it. (arm_load_exclusive<mode>): Likewise. (arm_load_exclusivesi): Likewise. (arm_load_exclusivedi): Likewise. (arm_load_acquire_exclusive<mode>): Likewise. (arm_load_acquire_exclusivesi): Likewise. (arm_load_acquire_exclusivedi): Likewise. (arm_store_exclusive<mode>): Likewise. (arm_store_exclusive<mode>): Likewise. (arm_store_release_exclusivedi): Likewise. (arm_store_release_exclusive<mode>): Likewise. From-SVN: r199733
* arm.c (arm_emit_load_exclusive): Add acq parameter.Kyrylo Tkachov2013-03-251-0/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | 2013-03-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/arm/arm.c (arm_emit_load_exclusive): Add acq parameter. Emit load-acquire versions when acq is true. (arm_emit_store_exclusive): Add rel parameter. Emit store-release versions when rel is true. (arm_split_compare_and_swap): Use acquire-release instructions instead. of barriers when appropriate. (arm_split_atomic_op): Likewise. * config/arm/arm.h (TARGET_HAVE_LDACQ): New macro. * config/arm/unspecs.md (VUNSPEC_LAX): New unspec. (VUNSPEC_SLX): Likewise. (VUNSPEC_LDA): Likewise. (VUNSPEC_STL): Likewise. * config/arm/sync.md (atomic_load<mode>): New pattern. (atomic_store<mode>): Likewise. (arm_load_acquire_exclusive<mode>): Likewise. (arm_load_acquire_exclusivesi): Likewise. (arm_load_acquire_exclusivedi): Likewise. (arm_store_release_exclusive<mode>): Likewise. From-SVN: r197046
* Update copyright years in gcc/Richard Sandiford2013-01-101-1/+1
| | | | From-SVN: r195098
* Update Copyright years for files modified in 2011 and/or 2012.Jakub Jelinek2013-01-041-1/+1
| | | | From-SVN: r194903
* arm.md (UNSPEC_LL): New.Richard Henderson2012-04-301-10/+26
| | | | | | | | * config/arm/arm.md (UNSPEC_LL): New. * config/arm/sync.md (atomic_loaddi, atomic_loaddi_1): New. (arm_load_exclusivedi): Use %H0. From-SVN: r186990
* sync.md (sync_optab): Change ior attribute to "or".Ramana Radhakrishnan2012-04-191-1/+1
| | | | | | | | 2012-04-19 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> * config/arm/sync.md (sync_optab): Change ior attribute to "or". From-SVN: r186587
* arm: Convert to atomic optabs.Richard Henderson2012-01-091-406/+264
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * config/arm/arm.c (arm_gen_compare_reg): Add scratch argument; use it if reload_completed. (arm_legitimize_sync_memory, arm_emit, arm_insn_count, arm_count, arm_output_asm_insn, arm_process_output_memory_barrier, arm_output_memory_barrier, arm_ldrex_suffix, arm_output_ldrex, arm_output_strex, arm_output_it, arm_output_op2, arm_output_op3, arm_output_sync_loop, arm_get_sync_operand, FETCH_SYNC_OPERAND, arm_process_output_sync_insn, arm_output_sync_insn, arm_sync_loop_insns, arm_call_generator, arm_expand_sync): Remove. (arm_pre_atomic_barrier, arm_post_atomic_barrier): New. (arm_emit_load_exclusive, arm_emit_store_exclusive): New. (emit_unlikely_jump): New. (arm_expand_compare_and_swap, arm_split_compare_and_swap): New. (arm_split_atomic_op): New. * config/arm/arm-protos.h: Update. * config/arm/arm.h (enum arm_sync_generator_tag): Remove. (struct arm_sync_generator): Remove. * config/arm/arm.md (VUNSPEC_SYNC_COMPARE_AND_SWAP, VUNSPEC_SYNC_LOCK, VUNSPEC_SYNC_OP, VUNSPEC_SYNC_NEW_OP, VUNSPEC_SYNC_OLD_OP): Remove. (VUNSPEC_ATOMIC_CAS, VUNSPEC_ATOMIC_XCHG, VUNSPEC_ATOMIC_OP): New. (VUNSPEC_LL, VUNSPEC_SC): New. (sync_result, sync_memory, sync_required_value, sync_new_value, sync_t1, sync_t2, sync_release_barrier, sync_op): Remove. (attr length): Don't use arm_sync_loop_insns. (cbranch_cc, cstore_cc): Update call to arm_gen_compare_reg. (movsfcc, movdfcc): Likewise. * config/arm/constraints.md (Ua): New. * config/arm/prediates.md (mem_noofs_operand): New. (sync_compare_and_swap<QHSD>, sync_lock_test_and_set<QHSD>): Remove. (sync_clobber, sync_t2_reqd): Remove. (sync_<syncop><QHSD>, sync_nand<QHSD>): Remove. (sync_new_<syncop><QHSD>, sync_new_nand<QHSD>): Remove. (sync_old_<syncop><QHSD>, sync_old_nand<QHSD>): Remove. (arm_sync_compare_and_swap<SIDI>): Remove. (arm_sync_compare_and_swap<NARROW>): Remove. (arm_sync_lock_test_and_set<SIDI>): Remove. (arm_sync_lock_test_and_set<NARROW>): Remove. (arm_sync_new_<syncop><SIDI>): Remove. (arm_sync_new_<syncop><NARROW>): Remove. (arm_sync_new_nand<SIDI>): Remove. (arm_sync_new_nand<NARROW>): Remove. (arm_sync_old_<syncop><SIDI>): Remove. (arm_sync_old_<syncop><NARROW>): Remove. (arm_sync_old_nand<SIDI>): Remove. (arm_sync_old_nand<NARROW>): Remove. (*memory_barrier): Merge arm_output_memory_barrier. (atomic_compare_and_swap<QHSD>): New. (atomic_compare_and_swap<NARROW>_1): New. (atomic_compare_and_swap<SIDI>_1): New. (atomic_exchange<QHSD>): New. (cas_cmp_operand, cas_cmp_str): New. (atomic_op_operand, atomic_op_str): New. (atomic_<syncop><QHSD>, atomic_nand<QHSD>): New. (atomic_fetch_<syncop><QHSD>, atomic_fetch_nand<QHSD>): New. (atomic_<syncop>_fetch<QHSD>, atomic_nand_fetch<QHSD>): New. (arm_load_exclusive<NARROW>): New. (arm_load_exclusivesi, arm_load_exclusivedi): New. (arm_store_exclusive<QHSD>): New. From-SVN: r183050
* arm.c (arm_output_ldrex): Support ldrexd.David Alan Gilbert2011-10-141-265/+159
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc/ 2011-10-14 David Alan Gilbert <david.gilbert@linaro.org> * config/arm/arm.c (arm_output_ldrex): Support ldrexd. (arm_output_strex): Support strexd. (arm_output_it): New helper to output it in Thumb2 mode only. (arm_output_sync_loop): Support DI mode. Change comment to not support const_int. (arm_expand_sync): Support DI mode. * config/arm/arm.h (TARGET_HAVE_LDREXBHD): Split into LDREXBH and LDREXD. * config/arm/iterators.md (NARROW): move from sync.md. (QHSD): New iterator for all current ARM integer modes. (SIDI): New iterator for SI and DI modes only. * config/arm/sync.md (sync_predtab): New mode_attr. (sync_compare_and_swapsi): Fold into sync_compare_and_swap<mode>. (sync_lock_test_and_setsi): Fold into sync_lock_test_and_setsi<mode>. (sync_<sync_optab>si): Fold into sync_<sync_optab><mode>. (sync_nandsi): Fold into sync_nand<mode>. (sync_new_<sync_optab>si): Fold into sync_new_<sync_optab><mode>. (sync_new_nandsi): Fold into sync_new_nand<mode>. (sync_old_<sync_optab>si): Fold into sync_old_<sync_optab><mode>. (sync_old_nandsi): Fold into sync_old_nand<mode>. (sync_compare_and_swap<mode>): Support SI & DI. (sync_lock_test_and_set<mode>): Likewise. (sync_<sync_optab><mode>): Likewise. (sync_nand<mode>): Likewise. (sync_new_<sync_optab><mode>): Likewise. (sync_new_nand<mode>): Likewise. (sync_old_<sync_optab><mode>): Likewise. (sync_old_nand<mode>): Likewise. (arm_sync_compare_and_swapsi): Turn into iterator on SI & DI. (arm_sync_lock_test_and_setsi): Likewise. (arm_sync_new_<sync_optab>si): Likewise. (arm_sync_new_nandsi): Likewise. (arm_sync_old_<sync_optab>si): Likewise. (arm_sync_old_nandsi): Likewise. (arm_sync_compare_and_swap<mode> NARROW): use sync_predtab, fix indent. (arm_sync_lock_test_and_setsi<mode> NARROW): Likewise. (arm_sync_new_<sync_optab><mode> NARROW): Likewise. (arm_sync_new_nand<mode> NARROW): Likewise. (arm_sync_old_<sync_optab><mode> NARROW): Likewise. (arm_sync_old_nand<mode> NARROW): Likewise. From-SVN: r179981
* sync.md (sync_clobber, [...]): New code attribute.Ken Werner2010-12-311-8/+16
| | | | | | | | | | | | | gcc/ 2010-12-15 Ken Werner <ken.werner@de.ibm.com> * config/arm/sync.md (sync_clobber, sync_t2_reqd): New code attribute. (arm_sync_old_<sync_optab>si, arm_sync_old_<sync_optab><mode>): Use the sync_clobber and sync_t2_reqd code attributes. * config/arm/arm.c (arm_output_sync_loop): Reverse the operation if the t2 argument is NULL. From-SVN: r168375
* arm.md: (define_attr "conds"): Update comment.Marcus Shawcroft2010-09-131-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | 2010-09-13 Marcus Shawcroft <marcus.shawcroft@arm.com> * config/arm/arm.md: (define_attr "conds"): Update comment. * config/arm/sync.md (arm_sync_compare_and_swapsi): Change conds attribute to clob. (arm_sync_compare_and_swapsi): Likewise. (arm_sync_compare_and_swap<mode>): Likewise. (arm_sync_lock_test_and_setsi): Likewise. (arm_sync_lock_test_and_set<mode>): Likewise. (arm_sync_new_<sync_optab>si): Likewise. (arm_sync_new_nandsi): Likewise. (arm_sync_new_<sync_optab><mode>): Likewise. (arm_sync_new_nand<mode>): Likewise. (arm_sync_old_<sync_optab>si): Likewise. (arm_sync_old_nandsi): Likewise. (arm_sync_old_<sync_optab><mode>): Likewise. (arm_sync_old_nand<mode>): Likewise. 2010-09-13 Marcus Shawcroft <marcus.shawcroft@arm.com> * gcc.target/arm/sync-1.c: New. From-SVN: r164247
* predicates.md (arm_sync_memory_operand): New.Marcus Shawcroft2010-09-021-12/+12
| | | | | | | | | | | | | | | | | | | | | | 2010-09-02 Marcus Shawcroft <marcus.shawcroft@arm.com> * config/arm/predicates.md (arm_sync_memory_operand): New. * config/arm/sync.md (arm_sync_compare_and_swapsi): Change predicate to arm_sync_memory_operand and constraint to Q. (arm_sync_compare_and_swap<mode>): Likewise. (arm_sync_compare_and_swap<mode>): Likewise. (arm_sync_lock_test_and_setsi): Likewise. (arm_sync_lock_test_and_set<mode>): Likewise. (arm_sync_new_<sync_optab>si): Likewise. (arm_sync_new_nandsi): Likewise. (arm_sync_new_<sync_optab><mode>): Likewise. (arm_sync_new_nand<mode>): Likewise. (arm_sync_old_<sync_optab>si): Likewise. (arm_sync_old_nandsi): Likewise. (arm_sync_old_<sync_optab><mode>): Likewise. (arm_sync_old_nand<mode>): Likewise. From-SVN: r163765
* For Marcus - Implement sync primitives inline for ARM.Marcus Shawcroft2010-08-181-0/+594
2010-08-18 Marcus Shawcroft <marcus.shawcroft@arm.com> * config/arm/arm-protos.h (arm_expand_sync): New. (arm_output_memory_barrier, arm_output_sync_insn): New. (arm_sync_loop_insns): New. * config/arm/arm.c (FL_ARCH7): New. (FL_FOR_ARCH7): Include FL_ARCH7. (arm_arch7): New. (arm_print_operand): Support %C markup. (arm_legitimize_sync_memory): New. (arm_emit, arm_insn_count, arm_count, arm_output_asm_insn): New. (arm_process_output_memory_barrier, arm_output_memory_barrier): New. (arm_ldrex_suffix, arm_output_ldrex, arm_output_strex): New. (arm_output_op2, arm_output_op3, arm_output_sync_loop): New. (arm_get_sync_operand, FETCH_SYNC_OPERAND): New. (arm_process_output_sync_insn, arm_output_sync_insn): New. (arm_sync_loop_insns,arm_call_generator, arm_expand_sync): New. * config/arm/arm.h (struct arm_sync_generator): New. (TARGET_HAVE_DMB, TARGET_HAVE_DMB_MCR): New. (TARGET_HAVE_MEMORY_BARRIER): New. (TARGET_HAVE_LDREX, TARGET_HAVE_LDREXBHD): New. * config/arm/arm.md: Include sync.md. (UNSPEC_MEMORY_BARRIER): New. (VUNSPEC_SYNC_COMPARE_AND_SWAP, VUNSPEC_SYNC_LOCK): New. (VUNSPEC_SYNC_OP):New. (VUNSPEC_SYNC_NEW_OP, VUNSPEC_SYNC_OLD_OP): New. (sync_result, sync_memory, sync_required_value): New attributes. (sync_new_value, sync_t1, sync_t2): Likewise. (sync_release_barrier, sync_op): Likewise. (length): Add logic to length attribute defintion to call arm_sync_loop_insns when appropriate. * config/arm/sync.md: New file. From-SVN: r163327
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