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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@232055 138bc75d-0d04-0410-961f-82ee72b054a4
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AMD znver1 enablement.
* config.gcc (i[34567]86-*-linux* | ...): Add znver1.
(case ${target}): Add znver1.
* config/i386/cpuid.h(bit_CLZERO): Define.
* config/i386/driver-i386.c: (host_detect_local_cpu): Let
-march=native recognize znver1 processors.
* config/i386/i386-c.c (ix86_target_macros_internal): Add
znver1, clzero def_and_undef.
* config/i386/i386.c (struct processor_costs znver1_cost): New.
(m_znver1): New definition.
(m_AMD_MULTIPLE): Includes m_znver1.
(processor_target_table): Add znver1 entry.
(ix86_target_string) : Add clzero entry.
(static const char *const cpu_names): Add znver1 entry.
(ix86_option_override_internal): Add znver1 instruction sets.
(PTA_CLZERO) : New definition.
(ix86_option_override_internal): Handle new clzerooption.
(ix86_issue_rate): Add znver1.
(ix86_adjust_cost): Add znver1.
(ia32_multipass_dfa_lookahead): Add znver1.
(has_dispatch): Add znver1.
* config/i386/i386.h (TARGET_znver1): New definition.
(TARGET_CLZERO): Define.
(TARGET_CLZERO_P): Define.
(struct ix86_size_cost): Add TARGET_ZNVER1.
(enum processor_type): Add PROCESSOR_znver1.
* config/i386/i386.md (define_attr "cpu"): Add znver1.
(set_attr znver1_decode): New definitions for znver1.
* config/i386/i386.opt (flag_dispatch_scheduler): Add znver1.
(mclzero): New.
* config/i386/mmx.md (set_attr znver1_decode): New definitions
for znver1.
* config/i386/sse.md (set_attr znver1_decode): Likewise.
* config/i386/x86-tune.def: Add znver1 tunings.
* config/i386/znver1.md: Introduce znver1 cpu and include new md file.
* gcc/doc/invoke.texi: Add details about znver1
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228520 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@219188 138bc75d-0d04-0410-961f-82ee72b054a4
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Emit movshdup for SSE3 and shufps otherwise.
(*vec_extractv2si_1): Do not emit punpckhdq and unpckhps.
Emit pshufd for SSE2 and shufps otherwise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@219074 138bc75d-0d04-0410-961f-82ee72b054a4
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* expr.c (emit_move_resolve_push): Export; be bit more selective
on when to clear alias set.
* expr.h (emit_move_resolve_push): Declare.
* function.h (struct function): Add tail_call_marked.
* tree-tailcall.c (optimize_tail_call): Set tail_call_marked.
* config/i386/i386-protos.h (ix86_expand_push): Remove.
* config/i386/i386.md (TImode move expander): De not call
ix86_expand_push.
(FP push expanders): Preserve memory attributes.
* config/i386/sse.md (push<mode>1): Remove.
* config/i386/i386.c (ix86_expand_vector_move): Handle push
operation.
(ix86_expand_push): Remove.
* config/i386/mmx.md (push<mode>1): Remove.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@207587 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@206289 138bc75d-0d04-0410-961f-82ee72b054a4
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* configure: Regenerate.
* config/i386/i386.md (*movdi_internal): Change
HAVE_AS_IX86_INTERUNIT_MOVQ to runtime check.
(*movdf_internal): Ditto.
* config/i386/mmx.md (*mov<mode>_internal): Ditto.
* config/i386/sse.md (vec_concatv2di): Output interunit movq
for HAVE_AS_IX86_INTERUNIT_MOVQ targets.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@204289 138bc75d-0d04-0410-961f-82ee72b054a4
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* gcc/config/i386/i386.md (*movti_internal): Use
predicate to determine if EVEX is needed.
(*movsi_internal): Ditto.
(*movdf_internal): Ditto.
(*movsf_internal): Ditto.
* gcc/config/i386/mmx.md (*mov<mode>_internal): Ditto.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@201936 138bc75d-0d04-0410-961f-82ee72b054a4
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(OPTION_MASK_ISA_AVX512CD_SET): Ditto.
(OPTION_MASK_ISA_AVX512PF_SET): Ditto.
(OPTION_MASK_ISA_AVX512ER_SET): Ditto.
(OPTION_MASK_ISA_AVX2_UNSET): Update.
(OPTION_MASK_ISA_AVX512F_UNSET): New.
(OPTION_MASK_ISA_AVX512CD_UNSET): Ditto.
(OPTION_MASK_ISA_AVX512PF_UNSET): Ditto.
(OPTION_MASK_ISA_AVX512ER_UNSET): Ditto.
(ix86_handle_option): Handle OPT_mavx512f, OPT_mavx512cd,
OPT_mavx512pf, OPT_mavx512er cases.
* config/i386/constraints.md (v): New constraint.
(Yi, Yj): Replace SSE_REGS with ALL_SSE_REGS.
* config/i386/cpuid.h (bit_AVX512F, bit_AVX512PF, bit_AVX512ER)
(bit_AVX512CD): New.
* config/i386/driver-i386.c (host_detect_local_cpu): Detect
AVX512F, AVX512ER, AVX512PF, AVX512CD features.
* config/i386/i386-c.c (ix86_target_macros_internal):
Conditionally define __AVX512F__, __AVX512ER__, __AVX512CD__,
__AVX512PF__.
* config/i386/i386-modes.def (VECTOR_MODES (INT, 128))
(VECTOR_MODES (FLOAT, 128), INT_MODE (XI, 64)): New modes.
* config/i386/i386.c (regclass_map, dbx_register_map)
(dbx64_register_map, svr4_dbx_register_map): Add new SSE registers.
(gate_insert_vzeroupper): Disable vzeroupper for TARGET_AVX512F.
(ix86_target_string): Define -mavx512f, -mavx512er, -mavx512cd,
-mavx512pf options.
(ix86_option_override_internal): Define PTA_AVX512F, PTA_AVX512ER,
PTA_AVX512PF, PTA_AVX512CD. Handle -mavx512f, -mavx512er, -mavx512cd,
-mavx512pf options. Fix formatting.
(ix86_conditional_register_usage): Squash EXT_REX_SSE_REGs for 32-bit
targets. Squash EVEX_SSE_REGS if AVX512F is disabled.
(ix86_valid_target_attribute_inner_p): Handle -mavx512f, -mavx512er,
-mavx512cd, -mavx512pf options.
(standard_sse_constant_opcode): Add vpternlogd for 512-bit modes.
(print_reg, ix86_print_operand): Handle 'g' to output 512-bit operands.
(ix86_preferred_output_reload_class): Replace SSE_REGS with
ALL_SSE_REGS.
(ix86_hard_regno_mode_ok): Support 512-bit registers.
(ix86_set_reg_reg_cost): Ditto.
(x86_order_regs_for_local_alloc): Ditto.
(MAX_VECT_LEN): Extend to 64-byte.
(ix86_spill_class): Replace SSE_REGS with ALL_SSE_REGS.
* config/i386/i386.h (TARGET_AVX512F, TARGET_AVX512PF)
(TARGET_AVX512ER, TARGET_AVX512CD): New.
(BIGGEST_ALIGNMENT): Extend to 512-bits.
(FIRST_PSEUDO_REGISTER, FIXED_REGISTERS): Add new registers.
(CALL_USED_REGISTERS, REG_ALLOC_ORDER): Likewise.
(VALID_AVX512F_SCALAR_MODE, VALID_AVX512F_REG_MODE): New.
(SSE_REG_MODE_P): Support new modes.
(FIRST_MMX_REG, FIRST_REX_INT_REG, FIRST_REX_SSE_REG): Add comments.
(FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG): New.
(reg_class, REG_CLASS_NAMES): Add EVEX_SSE_REGS, ALL_SSE_REGS.
(SSE_CLASS_P, MAYBE_SSE_CLASS_P): Replace SSE_REGS with ALL_SSE_REGS.
(REG_CLASS_CONTENTS): Add new registers.
(SSE_REGNO_P, SSE_REGNO, HARD_REGNO_RENAME_OK): Support new registers.
(EXT_REX_SSE_REGNO_P): New.
(HI_REGISTER_NAMES): Add new registers.
* config/i386/i386.md: Define constants for new registers.
(mode): Add new 512-bit modes.
(prefix): Support evex prefix.
(isa): Support avx512f, noavx512f, fma_avx512f.
(ssemodesuffix): Add new 512-bit modes.
(movxi): New.
(*movxi_internal_avx512f): Ditto.
(*movdi_internal): Replace constraint "x" with the new constraint "v".
Support MODE_XI.
(*movsi_internal): Likewise.
(*movdf_internal): Likewise.
(*movsf_internal): Likewise.
(*fop_<mode>_comm_sse): Replace constraint "x" with new constraint "v".
(<code><mode>3): Likewise.
* config/i386/i386.opt (mavx512f, mavx512pf, mavx512er, mavx512cd): New.
* config/i386/mmx.md (*mov<mode>_internal): Replace constraint "x"
with the new constraint "v".
* config/i386/sse.md (*mov<mode>_internal): Support new registers and
modes.
(<sse>_loadu<ssemodesuffix><avxsizesuffix>): Replace constraint "x"
with the new constraint "v".
(<sse2>_loaddqu<avxsizesuffix>): Likewise.
(<sse2>_storedqu<avxsizesuffix>): Likewise.
(*<plusminus_insn><mode>3): Likewise.
(<sse>_vm<plusminus_insn><mode>3): Likewise.
(*mul<mode>3): Likewise.
(<sse>_vmmul<mode>3): Likewise.
(<sse>_div<mode>3): Likewise.
(<sse>_vmdiv<mode>3): Likewise.
(<sse>_sqrt<mode>2): Likewise.
(<sse>_vmsqrt<mode>2): Likewise.
(*<code><mode>3_finite): Likewise.
(*<code><mode>3) <smaxmin>: Likewise.
(<sse>_vm<code><mode>3): Likewise.
(*<code><mode>3) <any_logic>: Likewise.
(*fma_fmadd_<mode>): Likewise.
(*fma_fmsub_<mode>): Likewise.
(*fma_fnmadd_<mode>): Likewise.
(*fma_fnmsub_<mode>): Likewise.
(*fma_fmaddsub_<mode>): Likewise.
(*fma_fmsubadd_<mode>): Likewise.
(*fmai_fmadd_<mode>): Likewise.
(*fmai_fmsub_<mode>): Likewise.
(*fmai_fnmadd_<mode>): Likewise.
(*fmai_fnmsub_<mode>): Likewise.
(sse_cvtsi2ss): Likewise.
(sse_cvtsi2ssq): Likewise.
(sse_cvtss2si): Likewise.
(sse_cvtss2si_2): Likewise.
(sse_cvtss2siq): Likewise.
(sse_cvtss2siq_2): Likewise.
(sse_cvttss2si): Likewise.
(sse_cvtss2siq_2): Likewise.
(float<sseintvecmodelower><mode>2): Likewise.
(sse2_cvtsd2si_2): Likewise.
(sse2_cvtsd2siq_2): Likewise.
(*<plusminus_insn><mode>3): Likewise.
(*<sse2_avx2>_<plusminus_insn><mode>3): Likewise.
(*<sse4_1_avx2>_mul<mode>3): Likewise.
(ashr<mode>3): Likewise.
(<shift_insn><mode>3): Likewise.
(avx2_<code><mode>3): Likewise.
(*avx2_<code><mode>3): Likewise.
(*andnot<mode>3): Likewise.
(*<code><mode>3) <any_logic>: Likewise.
(abs<mode>2): Likewise.
(avx2_permvar<mode>): Likewise.
(avx2_perm<mode>_1): Likewise.
(*avx_vpermilp<mode>): Likewise.
(avx_vpermilvar<mode>3): Likewise.
(avx2_ashrv<mode>): Likewise.
(avx2_<shift_insn>v<mode>): Likewise.
* doc/invoke.texi: Document -mavx512f, -mavx512pf, -mavx512er,
-mavx512cd.
* doc/rtl.texi: Document XImode.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@201915 138bc75d-0d04-0410-961f-82ee72b054a4
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* config/i386/sse.md (sse_movlhps): Change alternative 3
of operand 2 to "m".
2013-07-06 Uros Bizjak <ubizjak@gmail.com>
PR target/57807
* config/i386/sse.md (iptr): New mode attribute.
(sse2_movq128): Add pointer size overrides for Intel asm dialect.
(<sse>_vm<plusminus_insn><mode>3): Ditto.
(<sse>_vmmul<mode>3): Ditto.
(<sse>_vmdiv<mode>3): Ditto.
(sse_vmrcpv4sf2): Ditto.
(<sse>_vmsqrt<mode>2): Ditto.
(sse_vmrsqrtv4sf2): Ditto.
(<sse>_vm<code><mode>3): Ditto.
(avx_vmcmp<mode>3): Ditto.
(<sse>_vmmaskcmp<mode>3): Ditto.
(<sse>_comi): Ditto.
(<sse>_ucomi): Ditto.
(*xop_vmfrcz_<mode>): Ditto.
(*fmai_fmadd_<mode>): Ditto.
(*fmai_fmsub_<mode>): Ditto.
(*fmai_fnmadd_<mode>): Ditto.
(*fmai_fnmsub_<mode>): Ditto.
(*fma4i_vmfmadd_<mode>): Ditto.
(*fma4i_vmfmsub_<mode>): Ditto.
(*fma4i_vmfnmadd_<mode>): Ditto.
(*fma4i_vmfnmsub_<mode>): Ditto.
(*xop_vmfrcz_<mode>): Ditto.
(sse_cvtps2pi): Ditto.
(sse_cvttps2pi): Ditto.
(sse_cvtss2si): Ditto.
(sse_cvtss2si_2): Ditto.
(sse_cvtss2siq_2): Ditto.
(sse_cvttss2si): Ditto.
(sse_cvttss2siq): Ditto.
(sse_cvtsd2si): Ditto.
(sse_cvtsd2si_2): Ditto.
(sse_cvtsd2siq_2): Ditto.
(sse_cvttsd2si): Ditto.
(sse_cvttsd2siq): Ditto.
(sse_cvtsd2ss): Ditto.
(sse_cvtss2sd): Ditto.
(avx2_pbroadcast<mode>): Ditto.
(avx2_pbroadcast<mode>_1): Ditto.
(*avx_vperm_broadcast_v4sf): Ditto.
(sse_movhlps): Ditto for movlp[sd]/movhp[sd] alternatives.
(sse_movlhps): Ditto.
(sse_storehps): Ditto.
(sse_loadhps): Ditto.
(sse_storelps): Ditto.
(sse_loadlps): Ditto.
(*vec_concatv4sf): Ditto.
(*vec_interleave_highv2df): Ditto.
(*vec_interleave_lowv2df): Ditto.
(*vec_extractv2df_1_sse): Ditto.
(*vec_extractv2df_0_sse): Ditto.
(sse2_storelpd): Ditto.
(sse2_loadlpd): Ditto.
(sse2_movsd): Ditto.
(*vec_concatv4si): Ditto.
(vec_concatv2di): Ditto.
* config/i386/mmx.md (mmx_punpcklbw): Add pointer size overrides
for Intel asm dialect.
(mmx_punpcklwd): Ditto.
(mmx_punpckldq): Ditto.
* config/i386/i386.c (ix86_print_operand) ['H']: Output 'qword ptr'
for intel assembler dialect.
testsuite/ChangeLog:
2013-07-06 Uros Bizjak <ubizjak@gmail.com>
PR target/57807
* gcc.target/i386/pr57807.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@200737 138bc75d-0d04-0410-961f-82ee72b054a4
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(*vec_extractv4si_zext_mem): Ditto.
(*vec_extractv2di): Add 0->x and x->x alternatives.
* config/i386/mmx.md (*vec_extractv2si_zext_mem): New pattern.
* config/i386/i386.md (*zero_extendsidi2): Add *Yj->?r alternative.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@198752 138bc75d-0d04-0410-961f-82ee72b054a4
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splitter preparation statements.
* config/i386/sse.md (*vec_extract* splitters): Ditto.
(*avx_vperm_broadcast_<mode>): Use adjust_address instead of
adjust_address_nv.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@198718 138bc75d-0d04-0410-961f-82ee72b054a4
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* config/i386/i386.h (enum ix86_tune_indices)
<X86_TUNE_INTER_UNIT_MOVES_TO_VEC, X86_TUNE_INTER_UNIT_MOVES_FROM_VEC>:
New, split from X86_TUNE_INTER_UNIT_MOVES.
<X86_TUNE_INTER_UNIT_MOVES>: Remove.
(TARGET_INTER_UNIT_MOVES_TO_VEC): New define.
(TARGET_INTER_UNIT_MOVES_FROM_VEC): Ditto.
(TARGET_INTER_UNIT_MOVES): Remove.
* config/i386/i386.c (initial_ix86_tune_features): Update.
Disable X86_TUNE_INTER_UNIT_MOVES_FROM_VEC for m_ATHLON_K8 only.
(ix86_expand_convert_uns_didf_sse): Use
TARGET_INTER_UNIT_MOVES_TO_VEC instead of TARGET_INTER_UNIT_MOVES.
(ix86_expand_vector_init_one_nonzero): Ditto.
(ix86_expand_vector_init_interleave): Ditto.
(inline_secondary_memory_needed): Return true for moves from SSE class
registers for !TARGET_INTER_UNIT_MOVES_FROM_VEC targets and for moves
to SSE class registers for !TARGET_INTER_UNIT_MOVES_TO_VEC targets.
* config/i386/constraints.md (Yi, Ym): Depend on
TARGET_INTER_UNIT_MOVES_TO_VEC.
(Yj, Yn): New constraints.
* config/i386/i386.md (*movdi_internal): Change constraints of
operand 1 from Yi to Yj and from Ym to Yn.
(*movsi_internal): Ditto.
(*movdf_internal): Ditto.
(*movsf_internal): Ditto.
(*float<SWI48x:mode><X87MODEF:mode>2_1): Use
TARGET_INTER_UNIT_MOVES_TO_VEC instead of TARGET_INTER_UNIT_MOVES.
(*float<SWI48x:mode><X87MODEF:mode>2_1 splitters): Ditto.
(floatdi<X87MODEF:mode>2_i387_with_xmm): Ditto.
(floatdi<X87MODEF:mode>2_i387_with_xmm splitters): Ditto.
* config/i386/sse.md (movdi_to_sse): Ditto.
(sse2_stored): Change constraint of operand 1 from Yi to Yj.
Use TARGET_INTER_UNIT_MOVES_FROM_VEC instead of
TARGET_INTER_UNIT_MOVES.
(sse_storeq_rex64): Change constraint of operand 1 from Yi to Yj.
(sse_storeq_rex64 splitter): Use TARGET_INTER_UNIT_MOVES_FROM_VEC
instead of TARGET_INTER_UNIT_MOVES.
* config/i386/mmx.md (*mov<mode>_internal): Change constraint of
operand 1 from Yi to Yj and from Ym to Yn.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@198401 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@197024 138bc75d-0d04-0410-961f-82ee72b054a4
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using MMXMODE mode iterator.
(*move<mode>_internal): Merge with *movv2sf_internal and
*movv2sf_internal_rex64 using MMXMODE mode iterator.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@197021 138bc75d-0d04-0410-961f-82ee72b054a4
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*mov<mode>_internal_rex64. Use x64 and nox64 isa attributes.
Emit insn template depending on type attribute. Use
HAVE_AS_IX86_INTERUNIT_MOVQ to handle broken assemblers that require
movd instead of movq mnemonic for interunit moves. Rewrite mode
attribute calculation. Remove unit attribute calculation.
Set prefix attribute to maybe_vex for sselog1 and ssemov types.
Set prefix_data16 attribute for DImode ssemov types.
Use Ym instead of y for SSE-MMX conversion alternatives.
Reorder operand constraints.
testsuite/ChangeLog:
* gcc.target/i386/pr22152.c (dg-options): Add -mtune=core2.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@196981 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@195098 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@194903 138bc75d-0d04-0410-961f-82ee72b054a4
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* config/i386/sync.md: Ditto.
* config/i386/sse.md: Ditto.
* config/i386/mmx.md: Ditto.
* config/i386/pentium.md: Ditto.
* config/i386/athlon.md: Ditto.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@185505 138bc75d-0d04-0410-961f-82ee72b054a4
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UNSPEC_PFRCPIT1, UNSPEC_PFRCPIT2, UNSPEC_PFRSQRT, UNSPEC_PFRSQIT1>:
Move from config/i386/i386.md
(unspecv) <UNSPECV_EMMS, UNSPECV_FEMMS>: Ditto.
* config/i386/sse.md (unspec) <UNSPEC_MOVNT,UNSPEC_MOVU, UNSPEC_LDDQU,
UNSPEC_PSHUFB, UNSPEC_PSIGN, UNSPEC_PALIGNR, UNSPEC_EXTRQI,
UNSPEC_EXTRQ, UNSPEC_INSERTQI, UNSPEC_INSERTQ, UNSPEC_BLENDV,
UNSPEC_INSERTPS, UNSPEC_DP, UNSPEC_MOVNTDQA, UNSPEC_MPSADBW,
UNSPEC_PHMINPOSUW, UNSPEC_PTEST, UNSPEC_PCMPESTR, UNSPEC_PCMPISTR,
UNSPEC_FMADDSUB, UNSPEC_XOP_UNSIGNED_CMP, UNSPEC_XOP_TRUEFALSE,
UNSPEC_XOP_PERMUTE, UNSPEC_FRCZ, UNSPEC_AESENC, UNSPEC_AESENCLAST,
UNSPEC_AESDEC, UNSPEC_AESDECLAST, UNSPEC_AESIMC,
UNSPEC_AESKEYGENASSIST, UNSPEC_PCLMUL, UNSPEC_PCMP, UNSPEC_VPERMIL,
UNSPEC_VPERMIL2, UNSPEC_VPERMIL2F128, UNSPEC_CAST, UNSPEC_VTESTP,
UNSPEC_VCVTPH2PS, UNSPEC_VCVTPS2PH, UNSPEC_VPERMSI, UNSPEC_VPERMDF,
UNSPEC_VPERMSF, UNSPEC_VPERMTI, UNSPEC_GATHER, UNSPEC_VSIBADDR>: Ditto.
(unspecv) <UNSPECV_LDMXCSR, UNSPECV_STMXCSR, UNSPECV_CLFLUSH,
UNSPECV_MONITOR, UNSPECV_MWAIT, UNSPECV_VZEROALL, UNSPECV_VZEROUPPER>:
Ditto.
* config/i386/sync.md (unspec) <UNSPEC_LFENCE, UNSPEC_SFENCE,
UNSPEC_MFENCE, UNSPEC_MOVA>: Ditto.
(unspecv) <UNSPECV_CMPXCHG_1, UNSPECV_CMPXCHG_2, UNSPECV_CMPXCHG_3,
UNSPECV_CMPXCHG_4, UNSPECV_XCHG, UNSPECV_LOCK>: Ditto.
(sse2_lfence): Move from config/i386/sse.md.
(*sse2_lfence): Ditto.
(sse_sfence): Ditto.
(*sse_sfence): Ditto.
(sse2_mfence): Ditto.
(mfence_sse2): Ditto. Rename from *sse2_mfence. Enable also
for TARGET_64BIT.
(mem_thread_fence): Use mfence_sse2.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@181590 138bc75d-0d04-0410-961f-82ee72b054a4
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(UNSPEC_MOVNTQ): New unspec.
* config/i386/mmx.md (sse_movntq): Rename from sse_movntdi.
Use UNSPEC_MOVNTQ instead of UNSPEC_MOVNT.
* config/i386/sse.md (sse2_movnti<mode>): Use UNSPEC_MOVNT instead of
UNSPEC_MOVNTI.
(STORENT_MODE): Add DI and V4DI modes.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@181531 138bc75d-0d04-0410-961f-82ee72b054a4
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shiftrt_insn. Also handle ashift RTX.
(shift): Rename code attribute from shiftrt. Also handle ashift RTX.
(vshift): New code attribute.
(<shift_insn>*): Rename from <shiftrt_insn>*. Update asm templates.
(any_lshift): Move and rename code iterator from ...
* config/i386/sse.md (lshift): ... here.
(lshift_insn): Remove code attribute.
(lshift): Remove code attribute.
(vlshr<mode>3): Use lshiftrt RTX.
(vashr<mode>3, ashrv16qi3, ashrv2di3): Use ashiftrt RTX.
(vashl<mode>3, ashlv16qi3): Use ashift RTX.
(avx2_<lshift>v<mode>): Rename from avx2_<shift_insn>v<mode>. Use
any_lshift code iterator. Update asm template.
(<shift_insn><mode>3): Macroize insn from lshr<mode>3 and ashl<mode>3
usign any_lshift code iterator.
* config/i386/mmx.md (mmx_<shift_insn><mode>3): Macroize insn from
mmx_lshr<mode>3 and mmx_ashl<mode>3 usign any_lshift code iterator.
* config/i386/i386.c (bdesc_args) <__builtin_ia32_psll>: Update.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@180624 138bc75d-0d04-0410-961f-82ee72b054a4
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2011-10-25 H.J. Lu <hongjiu.lu@intel.com>
* config/i386/mmx.md (*mmx_maskmovq): Replace :SI with :P and
remove "&& !TARGET_64BIT"
(*mmx_maskmovq_rex): Removed.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@180458 138bc75d-0d04-0410-961f-82ee72b054a4
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to calculate unit, prefix_rep and prefix_data16 attributes.
(*mov<mode>_internal): Ditto for unit attribute.
(*movv2sf_internal_rex64): Ditto for unit and prefix_rep attributes.
(*movv2sf_internal): Ditto.
* config/i386/sse.md (VI1248_256): Remove mode iterator.
(avx2_eq<mode>3): Use VI_256 instead of VI1248_256.
(*avx2_eq<mode>3): Ditto.
(avx2_gt<mode>3): Ditto.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@178982 138bc75d-0d04-0410-961f-82ee72b054a4
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* config/i386/i386.md: Use (match_test ...) for attribute tests.
* config/i386/mmx.md: Likewise.
* config/i386/sse.md: Likewise.
* config/i386/predicates.md (call_insn_operand): Use
(not (match_test "...")) instead of (match_test "!...")
* config/i386/constraints.md (w): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@178389 138bc75d-0d04-0410-961f-82ee72b054a4
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sse4 and sse4_noavx.
(enabled): Handle sse2, sse2_noavx, sse3, sse4 and sse4_noavx.
(*pushdf_rex64): Change Y2 register constraint to x.
(*movdf_internal_rex64): Ditto.
(*zero_extendsidi2_rex64): Ditto.
(*movdi_internal): Change Y2 register constraint to x
and update "isa" attribute.
(*pushdf): Ditto.
(*movdf internal): Ditto.
(zero_extendsidi2_1): Ditto.
(*truncdfdf_mixed): Ditto.
(*truncxfdf2_mixed): Ditto.
* config/i386/mmx.md (*mov<mode>_internal_rex64): Change Y2
register constraint to x.
(*movv2sf_internal_rex64): Ditto.
(*mov<mode>_internal): Change Y2 register constraint to x
and add "isa" attribute.
(*movv2sf_internal): Ditto.
(*vec_extractv2si_1): Ditto.
* config/i386/sse.md ("vec_set<mode>_0): Change Y2 and Y4 register
constraints to x and update "isa" attribute.
(*vec_interleave_highv2df): Change Y3 registerconstraint
to x and update "isa" attribute.
(*vec_interleave_lowv2df): Ditto.
(*vec_concatv2df): Change Y2 register constraint to x and
update "isa" attribute.
(sse2_loadld): Ditto.
(*vec_extractv2di_1): Ditto.
(*vec_dupv4si): Ditto.
(*vec_dupv2di): Ditto.
(*vec_concatv4si): Ditto.
(vec_concatv2di): Ditto.
* config/i386/constraints.md (Y2): Remove.
(Y3): Ditto.
(Y4): Ditto.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@178073 138bc75d-0d04-0410-961f-82ee72b054a4
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* config/i386/sse.md: Ditto.
* config/i386/mmx.md: Ditto.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@174945 138bc75d-0d04-0410-961f-82ee72b054a4
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* config/i386/predicates.md (const_pow2_1_to_2_operand): Remove.
(const_pow2_1_to_8_operand): Ditto.
(const_pow2_1_to_128_operand): Ditto.
(const_pow2_1_to_32768_operand): Ditto.
* config/i386/mmx.md (*mmx_pinsrw): Use const_int_operand instead of
const_pow2_1_to_8_operand for operand 3 predicate. Use exact_log2
in insn constraint to check integer value of operand 3.
* config/i386/sse.md (*vec_setv4sf_sse4_1): Ditto.
(PINSR_MODE): New mode iterator.
(sse2p4_1): New mode attribute.
(<sse2p4_1>_pinsr<ssemodesuffix>): Merge insn from sse4_1_pinsrb,
sse2_pinsrw, sse4_1_pinsrd and sse4_1_pinsrq using PINSR_MODE mode
iterator. Use const_int_operand instead of
const_pow2_1_to_{2,8,128,32768}_operand for operand 3 predicate. Use
exact_log2 in insn constraint to check integer value of operand 3.
2011-05-09 Uros Bizjak <ubizjak@gmail.com>
* config/i386/sse.md (blendbits): Remove mode attribute.
(<sse4_1>_blend<ssemodesuffix><avxsizesuffix>): Use const_int_operand
instead of const_0_to_<blendbits>_operand for operand 3 predicate.
Check integer value of operand 3 in insn constraint.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@173580 138bc75d-0d04-0410-961f-82ee72b054a4
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* config/i386/i386.md (*movdi_internal_rex64) Use %vmovd
for reg<->xmm moves.
* config/i386/sse.md (*vec_concatv2di_rex64_sse4_1): Ditto.
(vec_concatv2di_rex64_sse): Ditto.
(*sse2_storeq_rex64): Do not emit %v prefix for mov{q} mnemonic.
(*vec_extractv2di_1_rex64): Ditto.
Revert:
2011-05-02 Uros Bizjak <ubizjak@gmail.com>
* config/i386/mmx.md (*mov<mode>_internal_rex64): Use %vmovq for
reg<->xmm moves.
(*movv2sf_internal_rex64): Use %vmovq for reg<->xmm moves.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@173361 138bc75d-0d04-0410-961f-82ee72b054a4
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(*movv2sf_internal): Ditto.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@173267 138bc75d-0d04-0410-961f-82ee72b054a4
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reg<->xmm moves.
(*mov<mode>_internal): Merge with *mov<mode>_internal_avx.
(*movv2sf_internal_rex64): Use %vmovq for reg<->xmm moves. Merge
with *movv2sf_internal_rex64_avx.
(*movv2sf_internal): Merge with *movv2sf_internal_avx.
* config/i386/i386.md (*movdi_internal_rex64) <TYPE_SSEMOV>:
Use %v prefix in insn mnemonic to handle TARGET_AVX.
(*movdi_internal): Add "isa" attribute. Use "maybe_vex" instead of
"vex" in "prefix" attribute calculation.
(*movdf_internal): Output AVX mnemonics. Add "prefix" attribute.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@173265 138bc75d-0d04-0410-961f-82ee72b054a4
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@168438 138bc75d-0d04-0410-961f-82ee72b054a4
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gcc/config.gcc (with_cpu): Default i[34567]86-*-darwin* and
x86_64-*-darwin* to with_cpu:-core2.
gcc/config/i386/mmx.md (*mov<mode>_internal_rex64): Replace movq
with movd for darwin assembler.
gcc/config/i386/sse.md (*vec_concatv2di_rex64_sse4_1): Ditto.
(*vec_concatv2di_rex64_sse): Ditto.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@167611 138bc75d-0d04-0410-961f-82ee72b054a4
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preparation statements from expanders.
* config/i386/mmx.md: Ditto.
* config/i386/sse.md: Ditto.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@164329 138bc75d-0d04-0410-961f-82ee72b054a4
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* config/i386/mmx.md (*mov<mode>_internal_rex64,
*mov<mode>_internal_avx, *mov<mode>_internal,
*movv2sf_internal_rex64_avx, *movv2sf_internal_rex64,
*movv2sf_internal_avx, *movv2sf_internal): Split out !y-!y alternative.
[
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@163926 138bc75d-0d04-0410-961f-82ee72b054a4
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maxminiprefix and update all users.
(maxmin_float): Ditto from maxminfprefix.
(logic): Ditto from logicprefix.
(absneg_mnemonic): Ditto from absnegprefix.
* config/i386/mmx.md: Update all users of maxminiprefix,
maxminfprefix and loficprefix for rename.
* config/i386/sse.md: Ditto.
* config/i386/sync.md (sync_<code><mode>): Update for
logicprefix rename.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@158350 138bc75d-0d04-0410-961f-82ee72b054a4
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* config/i386/mmx.md ("*mmx_subv2sf3): Fix insn operand number for
alternative 1.
testsuite/ChangeLog:
PR target/42549
* gcc.target/i386/mmx-3dnow-check.h: New file.
* gcc.target/i386/pr42549.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@155519 138bc75d-0d04-0410-961f-82ee72b054a4
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(any_logic): Rename from plogic code iterator.
(logicprefix): Rename from plogicprefix code attribute.
(<code><mode>3): Macroize expander from {ior,xor}<mode>3 using
any_or code iterator.
(*<code><mode>_1): Macroize insn from *{ior,xor}<mode>_1 using
any_or code iterator.
(*<code><mode>_2): Ditto from *{ior,xor}<mode>_2.
(*<code><mode>_3): Ditto from *{ior,xor}<mode>_3.
(ior and xor splitters): Ditto.
* config/i386/mmx.md: Updated for rename.
* config/i386/sse.md: Ditto.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@155037 138bc75d-0d04-0410-961f-82ee72b054a4
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* config/i386/i386.c (print_operand): For 32-byte memory use
YMMWORD in -masm=intel mode. Use TBYTE instead of XWORD.
* config/i386/i386.md (crc32modesuffix): Expand to nothing
in -masm=intel mode.
(sse4_2_crc32di): Print just crc32 instead of crc32q in
-masm=intel mode.
* config/i386/mmx.md (*mmx_pinsrw): Print correct size of
memory operand in -masm=intel mode.
* config/i386/sse.md (*avx_pinsr<ssevecsize>, *sse4_1_pinsrb,
*sse2_pinsrw): Likewise.
(sse_cvtss2siq, sse_cvtss2siq_2, sse_cvttss2siq): Don't print
q suffix in -masm=intel mode.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@154652 138bc75d-0d04-0410-961f-82ee72b054a4
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(vzeroupper_operation): Ditto.
(vzeroall_operation): Improve pattern recognition.
* config/i386/sse.md (avx_vzeroupper_rex64): Remove insn pattern.
(avx_vzeroupper): Change insn pattern to expander.
(*avx_vzeroupper): New insn pattern. Use vzeroupper_operation
predicate.
(*avx_vzeroall): Remove operands 1 and 2.
* config/i386/mmx.md (mmx_emms): Change insn pattern to expander.
(mmx_femms): Ditto.
(*mmx_emms): New insn pattern. Use emms_operation predicate.
(*mmx_femms): Ditto.
* config/i386/i386.c (enum ix86_builtins)
<IX86_BUILTIN_VZEROUPPER_REX64>: Remove.
(struct builtin_description) <CODE_FOR_avx_vzeroupper_rex64>:
Remove initailization.
<CODE_FOR_avx_vzeroupper>: Unconditionally initialize here.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@154649 138bc75d-0d04-0410-961f-82ee72b054a4
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TYPE_SSE{MULADD,4ARG,IADD1,CVT1} by default.
(prefix_rex): For UNIT_MMX don't imply the prefix by default
if MODE_DI.
(prefix_extra): Default to 2 for TYPE_SSE{MULADD,4ARG} and
to 1 for TYPE_SSE{IADD1,CVT1}.
(prefix_vex_imm8): Removed.
(length_vex): Only pass 1 as second argument to
ix86_attr_length_vex_default if prefix_extra is 0.
(modrm): For TYPE_INCDEC only set to 0 if not TARGET_64BIT.
(length): For prefix vex computation use length_immediate
attribute instead of prefix_vex_imm8.
(cmpqi_ext_3_insn, cmpqi_ext_3_insn_rex64,
addqi_ext_1, addqi_ext_1_rex64, *testqi_ext_0, andqi_ext_0,
*andqi_ext_0_cc, *iorqi_ext_0, *xorqi_ext_0, *xorqi_cc_ext_1,
*xorqi_cc_ext_1_rex64): Override modrm attribute to 1.
(extendsidi2_rex64, extendhidi2, extendqidi2, extendhisi2,
*extendhisi2_zext, extendqihi2, extendqisi2, *extendqisi2_zext): Emit
a space in between the operands.
(*anddi_1_rex64, *andsi_1): Likewise. Override prefix_rex to 1
if one operand is 0xff and the other one si, di, bp or sp.
(*andhi_1): Override prefix_rex to 1 if one operand is 0xff and the
other one si, di, bp or sp.
(*btsq, *btrq, *btcq, *btdi_rex64, *btsi): Add mode attribute.
(*ffssi_1, *ffsdi_1, ctzsi2, ctzdi2): Add
type and mode attributes.
(*bsr, *bsr_rex64, *bsrhi): Add type attribute.
(*cmpfp_i_mixed, *cmpfp_iu_mixed): For TYPE_SSECOMI, clear
prefix_rep attribute and set prefix_data16 attribute iff MODE_DF.
(*cmpfp_i_sse, *cmpfp_iu_sse): Clear prefix_rep attribute and set
prefix_data16 attribute iff MODE_DF.
(*movsi_1): For TYPE_SSEMOV MODE_SI set prefix_data16 attribute.
(fix_trunc<mode>di_sse): Set prefix_rex attribute.
(*adddi_4_rex64, *addsi_4): Use const128_operand instead of
constm128_operand in length_immediate computation.
(*addhi_4): Likewise. Fix mode attribute to MODE_HI.
(anddi_1_rex64): Use movzbl/movzwl instead of movzbq/movzwq.
(*avx_ashlti3, sse2_ashlti3, *avx_lshrti3, sse2_lshrti3): Set
length_immediate attribute to 1.
(x86_fnstsw_1, x86_fnstcw_1, x86_fldcw_1): Fix length attribute.
(*movdi_1_rex64): Override prefix_rex or prefix_data16 attributes
for certain alternatives.
(*movdf_nointeger, *movdf_integer_rex64, *movdf_integer): Override
prefix_data16 attribute if MODE_V1DF.
(*avx_setcc<mode>, *sse_setcc<mode>, *sse5_setcc<mode>): Set
length_immediate to 1.
(set_got_rex64, set_rip_rex64): Remove length attribute, set
length_address to 4, set mode attribute to MODE_DI.
(set_got_offset_rex64): Likewise. Set length_immediate to 0.
(fxam<mode>2_i387): Set length attribute to 4.
(*prefetch_sse, *prefetch_sse_rex, *prefetch_3dnow,
*prefetch_3dnow_rex): Override length_address attribute.
(sse4_2_crc32<mode>): Override prefix_data16 and prefix_rex
attributes.
* config/i386/predicates.md (ext_QIreg_nomode_operand): New predicate.
(constm128_operand): Removed.
* config/i386/i386.c (memory_address_length): For
disp && !index && !base in 64-bit mode account for SIB byte if
print_operand_address can't optimize disp32 into disp32(%rip)
and UNSPEC doesn't imply (%rip) addressing. Add 1 to length
for fs: or gs: segment.
(ix86_attr_length_immediate_default): When checking if shortform
is possible, truncate immediate to the length of the non-shortened
immediate.
(ix86_attr_length_address_default): Ignore MEM_P operands
with X constraint.
(ix86_attr_length_vex_default): Only check for DImode on
GENERAL_REG_P operands.
* config/i386/sse.md (<sse>_comi, <sse>_ucomi): Clear
prefix_rep attribute, set prefix_data16 attribute iff MODE_DF.
(sse_cvttps2pi): Clear prefix_rep attribute.
(sse2_cvttps2dq, *sse2_cvtpd2dq, sse2_cvtps2pd): Clear prefix_data16
attribute.
(*sse2_cvttpd2dq): Don't clear prefix_rep attribute.
(*avx_ashr<mode>3, ashr<mode>3, *avx_lshr<mode>3, lshr<mode>3,
*avx_ashl<mode>3, ashl<mode>3): Set length_immediate attribute to 1
iff operand 2 is const_int_operand.
(*vec_dupv4si, avx_shufpd256_1, *avx_shufpd_<mode>,
sse2_shufpd_<mode>): Set length_immediate attribute to 1.
(sse2_pshufd_1): Likewise. Set prefix attribute to maybe_vex
instead of vex.
(sse2_pshuflw_1, sse2_pshufhw_1): Set length_immediate to 1 and clear
prefix_data16.
(sse2_unpckhpd, sse2_unpcklpd, sse2_storehpd, *vec_concatv2df): Set
prefix_data16 attribute for movlpd and movhpd instructions.
(sse2_loadhpd, sse2_loadlpd, sse2_movsd): Likewise. Override
length_immediate for shufpd instruction.
(sse2_movntsi, sse3_lddqu): Clear prefix_data16 attribute.
(avx_cmpp<avxmodesuffixf2c><mode>3,
avx_cmps<ssemodesuffixf2c><mode>3, *avx_maskcmp<mode>3,
<sse>_maskcmp<mode>3, <sse>_vmmaskcmp<mode>3,
avx_shufps256_1, *avx_shufps_<mode>, sse_shufps_<mode>,
*vec_dupv4sf_avx, *vec_dupv4sf): Set
length_immediate attribute to 1.
(*avx_cvtsi2ssq, *avx_cvtsi2sdq): Set length_vex attribute to 4.
(sse_cvtsi2ssq, sse2_cvtsi2sdq): Set prefix_rex attribute to 1.
(sse2_cvtpi2pd, sse_loadlps, sse2_storelpd): Override
prefix_data16 attribute for the first alternative to 1.
(*avx_loadlps): Override length_immediate for the first alternative.
(*vec_concatv2sf_avx): Override length_immediate and prefix_extra
attributes for second alternative.
(*vec_concatv2sf_sse4_1): Override length_immediate and
prefix_data16 attributes for second alternative.
(*vec_setv4sf_avx, *avx_insertps, vec_extract_lo_<mode>,
vec_extract_hi_<mode>, vec_extract_lo_v16hi,
vec_extract_hi_v16hi, vec_extract_lo_v32qi,
vec_extract_hi_v32qi): Set prefix_extra and length_immediate to 1.
(*vec_setv4sf_sse4_1, sse4_1_insertps, *sse4_1_extractps): Set
prefix_data16 and length_immediate to 1.
(*avx_mulv2siv2di3, *avx_mulv4si3, sse4_2_gtv2di3): Set prefix_extra
to 1.
(*avx_<code><mode>3, *avx_eq<mode>3, *avx_gt<mode>3): Set
prefix_extra attribute for variants that don't have 0f prefix
alone.
(*avx_pinsr<ssevecsize>): Likewise. Set length_immediate to 1.
(*sse4_1_pinsrb, *sse2_pinsrw, *sse4_1_pinsrd, *sse4_1_pextrb,
*sse4_1_pextrb_memory, *sse2_pextrw, *sse4_1_pextrw_memory,
*sse4_1_pextrd): Set length_immediate to 1.
(*sse4_1_pinsrd): Likewise. Set prefix_extra to 1.
(*sse4_1_pinsrq, *sse4_1_pextrq): Set prefix_rex and length_immediate
to 1.
(*vec_extractv2di_1_rex64_avx, *vec_extractv2di_1_rex64,
*vec_extractv2di_1_avx, *vec_extractv2di_1_sse2): Override
length_immediate to 1 for second alternative.
(*vec_concatv2si_avx, *vec_concatv2di_rex64_avx): Override
prefix_extra and length_immediate attributes for the first
alternative.
(vec_concatv2si_sse4_1): Override length_immediate to 1 for the
first alternative.
(*vec_concatv2di_rex64_sse4_1): Likewise. Override prefix_rex
to 1 for the first and third alternative.
(*vec_concatv2di_rex64_sse): Override prefix_rex to 1 for the second
alternative.
(*sse2_maskmovdqu, *sse2_maskmovdqu_rex64): Override length_vex
attribute.
(*sse_sfence, sse2_mfence, sse2_lfence): Override length_address
attribute to 0.
(*avx_phaddwv8hi3, *avx_phadddv4si3, *avx_phaddswv8hi3,
*avx_phsubwv8hi3, *avx_phsubdv4si3, *avx_phsubswv8hi,
*avx_pmaddubsw128, *avx_pmulhrswv8hi3, *avx_pshufbv16qi3,
*avx_psign<mode>3): Set prefix_extra attribute to 1.
(ssse3_phaddwv4hi3, ssse3_phadddv2si3, ssse3_phaddswv4hi3,
ssse3_phsubwv4hi3, ssse3_phsubdv2si3, ssse3_phsubswv4hi3,
ssse3_pmaddubsw, *ssse3_pmulhrswv4hi, ssse3_pshufbv8qi3,
ssse3_psign<mode>3): Override prefix_rex attribute.
(*avx_palignrti): Override prefix_extra and length_immediate
to 1.
(ssse3_palignrti): Override length_immediate to 1.
(ssse3_palignrdi): Override length_immediate to 1, override
prefix_rex attribute.
(abs<mode>2): Override prefix_rep to 0, override prefix_rex
attribute.
(sse4a_extrqi): Override length_immediate to 2.
(sse4a_insertqi): Likewise. Override prefix_data16 to 0.
(sse4a_insertq): Override prefix_data16 to 0.
(avx_blendp<avxmodesuffixf2c><avxmodesuffix>,
avx_blendvp<avxmodesuffixf2c><avxmodesuffix>,
avx_dpp<avxmodesuffixf2c><avxmodesuffix>, *avx_mpsadbw,
*avx_pblendvb, *avx_pblendw, avx_roundp<avxmodesuffixf2c>256,
avx_rounds<avxmodesuffixf2c>256): Override prefix_extra
and length_immediate to 1.
(sse4_1_blendp<ssemodesuffixf2c>, sse4_1_dpp<ssemodesuffixf2c>,
sse4_2_pcmpestr, sse4_2_pcmpestri, sse4_2_pcmpestrm,
sse4_2_pcmpestr_cconly, sse4_2_pcmpistr, sse4_2_pcmpistri,
sse4_2_pcmpistrm, sse4_2_pcmpistr_cconly): Override prefix_data16
and length_immediate to 1.
(sse4_1_blendvp<ssemodesuffixf2c>): Override prefix_data16 to 1.
(sse4_1_mpsadbw, sse4_1_pblendw): Override length_immediate to 1.
(*avx_packusdw, avx_vtestp<avxmodesuffixf2c><avxmodesuffix>,
avx_ptest256): Override prefix_extra to 1.
(sse4_1_roundp<ssemodesuffixf2c>, sse4_1_rounds<ssemodesuffixf2c>):
Override prefix_data16 and length_immediate to 1.
(sse5_pperm_zero_v16qi_v8hi, sse5_pperm_sign_v16qi_v8hi,
sse5_pperm_zero_v8hi_v4si, sse5_pperm_sign_v8hi_v4si,
sse5_pperm_zero_v4si_v2di, sse5_pperm_sign_v4si_v2di,
sse5_vrotl<mode>3, sse5_ashl<mode>3, sse5_lshl<mode>3): Override
prefix_data16 to 0 and prefix_extra to 2.
(sse5_rotl<mode>3, sse5_rotr<mode>3): Override length_immediate to 1.
(sse5_frcz<mode>2, sse5_vmfrcz<mode>2): Don't override prefix_extra
attribute.
(*sse5_vmmaskcmp<mode>3, sse5_com_tf<mode>3,
sse5_maskcmp<mode>3, sse5_maskcmp<mode>3, sse5_maskcmp_uns<mode>3):
Override prefix_data16 and prefix_rep to 0, length_immediate to 1
and prefix_extra to 2.
(sse5_maskcmp_uns2<mode>3, sse5_pcom_tf<mode>3): Override
prefix_data16 to 0, length_immediate to 1 and prefix_extra to 2.
(*avx_aesenc, *avx_aesenclast, *avx_aesdec, *avx_aesdeclast,
avx_vpermilvar<mode>3,
avx_vbroadcasts<avxmodesuffixf2c><avxmodesuffix>,
avx_vbroadcastss256, avx_vbroadcastf128_p<avxmodesuffixf2c>256,
avx_maskloadp<avxmodesuffixf2c><avxmodesuffix>,
avx_maskstorep<avxmodesuffixf2c><avxmodesuffix>):
Override prefix_extra to 1.
(aeskeygenassist, pclmulqdq): Override length_immediate to 1.
(*vpclmulqdq, avx_vpermil<mode>, avx_vperm2f128<mode>3,
vec_set_lo_<mode>, vec_set_hi_<mode>, vec_set_lo_v16hi,
vec_set_hi_v16hi, vec_set_lo_v32qi, vec_set_hi_v32qi): Override
prefix_extra and length_immediate to 1.
(*avx_vzeroall, avx_vzeroupper, avx_vzeroupper_rex64): Override
modrm to 0.
(*vec_concat<mode>_avx): Override prefix_extra and length_immediate
to 1 for the first alternative.
* config/i386/mmx.md (*mov<mode>_internal_rex64): Override
prefix_rep, prefix_data16 and/or prefix_rex attributes in certain
cases.
(*mov<mode>_internal_avx, *movv2sf_internal_rex64,
*movv2sf_internal_avx, *movv2sf_internal): Override
prefix_rep attribute for certain alternatives.
(*mov<mode>_internal): Override prefix_rep or prefix_data16
attributes for certain alternatives.
(*movv2sf_internal_rex64_avx): Override prefix_rep and length_vex
attributes for certain alternatives.
(*mmx_addv2sf3, *mmx_subv2sf3, *mmx_mulv2sf3,
*mmx_<code>v2sf3_finite, *mmx_<code>v2sf3, mmx_rcpv2sf2,
mmx_rcpit1v2sf3, mmx_rcpit2v2sf3, mmx_rsqrtv2sf2, mmx_rsqit1v2sf3,
mmx_haddv2sf3, mmx_hsubv2sf3, mmx_addsubv2sf3,
*mmx_eqv2sf3, mmx_gtv2sf3, mmx_gev2sf3, mmx_pf2id, mmx_pf2iw,
mmx_pi2fw, mmx_floatv2si2, mmx_pswapdv2sf2, *mmx_pmulhrwv4hi3,
mmx_pswapdv2si2): Set prefix_extra attribute to 1.
(mmx_ashr<mode>3, mmx_lshr<mode>3, mmx_ashl<mode>3): Set
length_immediate to 1 if operand 2 is const_int_operand.
(*mmx_pinsrw, mmx_pextrw, mmx_pshufw_1, *vec_dupv4hi,
*vec_extractv2si_1): Set length_immediate
attribute to 1.
(*mmx_uavgv8qi3): Override prefix_extra attribute to 1 if
using old 3DNOW insn rather than SSE/3DNOW_A.
(mmx_emms, mmx_femms): Clear modrm attribute.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@147981 138bc75d-0d04-0410-961f-82ee72b054a4
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(*call_1_rex64_ms_sysv): Use named constants instead of magic
numbers to describe clobbbered registers.
(*call_value_0_rex64_ms_sysv): Ditto.
* config/i386/mmx.md (emms): Ditto.
(femms): Ditto.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@144554 138bc75d-0d04-0410-961f-82ee72b054a4
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* config/i386/sse.md (avx_nand<mode>3): Rename to avx_andnot<mode>3.
(<sse>_nand<mode>3): Rename to <sse>_andnot<mode>3.
(sse2_nand<mode>3): Rename to sse2_andnot<mode>3.
(*sse_nand<mode>3): Rename to *sse_andnot<mode>3.
(*avx_nand<mode>3): Rename to *avx_andnot<mode>3.
(*nand<mode>3): Rename to *andnot<mode>3.
(*nandtf3): rename to *andnottf3.
* config/i386/i386.c (bdesc_args) [IX86_BUILTIN_PANDN]:
Use CODE_FOR_mmx_andnotv2si3.
[IX86_BUILTIN_ANDNPS]: Use CODE_FOR_sse_andnotv4sf3.
[IX86_BUILTIN_ANDNPD]: Use CODE_FOR_sse2_andnotv2df3.
[IX86_BUILTIN_PANDN128]: Use CODE_FOR_sse2_andnotv2di3.
[IX86_BUILTIN_ANDNPS256]: Use CODE_FOR_avx_andnotv8sf3.
[IX86_BUILTIN_ANDNPD256]: Use CODE_FOR_avx_andnotv4df3.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@142083 138bc75d-0d04-0410-961f-82ee72b054a4
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Joey Ye <joey.ye@intel.com>
Xuepeng Guo <xuepeng.guo@intel.com>
* config.gcc (extra_headers): Add gmmintrin.h for x86 and x86-64.
* config/i386/cpuid.h (bit_FMA): New.
(bit_XSAVE): Likewise.
(bit_OSXSAVE): Likewise.
(bit_AVX): Likewise.
* config/i386/gas.h (ASM_OUTPUT_OPCODE): Undefine before
define. Use ASM_OUTPUT_AVX_PREFIX.
* config/i386/gmmintrin.h: New.
* config/i386/i386.c (x86_64_reg_class): Add X86_64_AVX_CLASS.
(OPTION_MASK_ISA_AVX_SET): New.
(OPTION_MASK_ISA_FMA_SET): Likewise.
(OPTION_MASK_ISA_AVX_UNSET): Likewise.
(OPTION_MASK_ISA_FMA_SET): Likewise.
(OPTION_MASK_ISA_SSE4_2_UNSET): Updated.
(ix86_handle_option): Handle OPT_mavx and OPT_mfma.
(pta_flags): Add PTA_AVX and PTA_FMA.
(override_options): Handle PTA_AVX and PTA_FMA.
(init_cumulative_args): Handle warn_avx.
(classify_argument): Return 0 for COImode and OImode. Return
1 and X86_64_AVX_CLASS for 256bit vector types.
(examine_argument): Handle X86_64_AVX_CLASS.
(construct_container): Likewise.
(function_arg_advance_32): Pass OImode and 256bit vector types
in AVX register.
(function_arg_advance_64): Take a new argument to indicate if a
parameter is named. Handle 256bit vector types. Return
immediately for unnamed 256bit vector mode parameters.
(function_arg_advance): Updated.
(function_arg_32): Add comments for TImode. Handle OImode
and 256bit vector types.
(function_arg_64): Take a new argument to indicate if a
parameter is named. Handle 256bit vector types. Return NULL
for unnamed 256bit vector mode parameters.
(function_arg): Updated.
(setup_incoming_varargs_64): Support
AVX encoding for *sse_prologue_save_insn.
(ix86_gimplify_va_arg): Handle 256bit vector mode parameters.
(standard_sse_constant_p): Return -2 for all 1s if SSE2 isn't
enabled. For all 1s in 256bit vector modes, return 3 if AVX is
enabled, otherwise return -3.
(standard_sse_constant_opcode): Handle AVX and 256bit vector
modes.
(print_reg): Support AVX registers. Handle 'x' and 't'.
Handle 'd' to duplicate the operand.
(print_operand): Likewise. Also support AVX vector compare
instructions.
(output_387_binary_op): Support AVX.
(output_fp_compare): Likewise.
(ix86_expand_vector_move_misalign): Likewise.
(ix86_attr_length_vex_default): New.
(ix86_builtins): Add IX86_BUILTIN_ADDPD256,
IX86_BUILTIN_ADDPS256, IX86_BUILTIN_ADDSUBPD256,
IX86_BUILTIN_ADDSUBPS256, IX86_BUILTIN_ANDPD256,
IX86_BUILTIN_ANDPS256, IX86_BUILTIN_ANDNPD256,
IX86_BUILTIN_ANDNPS256, IX86_BUILTIN_BLENDPD256,
IX86_BUILTIN_BLENDPS256, IX86_BUILTIN_BLENDVPD256,
IX86_BUILTIN_BLENDVPS256, IX86_BUILTIN_DIVPD256,
IX86_BUILTIN_DIVPS256, IX86_BUILTIN_DPPS256,
IX86_BUILTIN_HADDPD256, IX86_BUILTIN_HADDPS256,
IX86_BUILTIN_HSUBPD256, IX86_BUILTIN_HSUBPS256,
IX86_BUILTIN_MAXPD256, IX86_BUILTIN_MAXPS256,
IX86_BUILTIN_MINPD256, IX86_BUILTIN_MINPS256,
IX86_BUILTIN_MULPD256, IX86_BUILTIN_MULPS256,
IX86_BUILTIN_ORPD256, IX86_BUILTIN_ORPS256,
IX86_BUILTIN_SHUFPD256, IX86_BUILTIN_SHUFPS256,
IX86_BUILTIN_SUBPD256, IX86_BUILTIN_SUBPS256,
IX86_BUILTIN_XORPD256, IX86_BUILTIN_XORPS256,
IX86_BUILTIN_CMPSD, IX86_BUILTIN_CMPSS, IX86_BUILTIN_CMPPD,
IX86_BUILTIN_CMPPS, IX86_BUILTIN_CMPPD256,
IX86_BUILTIN_CMPPS256, IX86_BUILTIN_CVTDQ2PD256,
IX86_BUILTIN_CVTDQ2PS256, IX86_BUILTIN_CVTPD2PS256,
IX86_BUILTIN_CVTPS2DQ256, IX86_BUILTIN_CVTPS2PD256,
IX86_BUILTIN_CVTTPD2DQ256, IX86_BUILTIN_CVTPD2DQ256,
IX86_BUILTIN_CVTTPS2DQ256, IX86_BUILTIN_EXTRACTF128PD256,
IX86_BUILTIN_EXTRACTF128PS256, IX86_BUILTIN_EXTRACTF128SI256,
IX86_BUILTIN_VZEROALL, IX86_BUILTIN_VZEROUPPER,
IX86_BUILTIN_VZEROUPPER_REX64, IX86_BUILTIN_VPERMILVARPD,
IX86_BUILTIN_VPERMILVARPS, IX86_BUILTIN_VPERMILVARPD256,
IX86_BUILTIN_VPERMILVARPS256, IX86_BUILTIN_VPERMILPD,
IX86_BUILTIN_VPERMILPS, IX86_BUILTIN_VPERMILPD256,
IX86_BUILTIN_VPERMILPS256, IX86_BUILTIN_VPERMIL2PD,
IX86_BUILTIN_VPERMIL2PS, IX86_BUILTIN_VPERMIL2PD256,
IX86_BUILTIN_VPERMIL2PS256, IX86_BUILTIN_VPERM2F128PD256,
IX86_BUILTIN_VPERM2F128PS256, IX86_BUILTIN_VPERM2F128SI256,
IX86_BUILTIN_VBROADCASTSS, IX86_BUILTIN_VBROADCASTSD256,
IX86_BUILTIN_VBROADCASTSS256, IX86_BUILTIN_VBROADCASTPD256,
IX86_BUILTIN_VBROADCASTPS256, IX86_BUILTIN_VINSERTF128PD256,
IX86_BUILTIN_VINSERTF128PS256, IX86_BUILTIN_VINSERTF128SI256,
IX86_BUILTIN_LOADUPD256, IX86_BUILTIN_LOADUPS256,
IX86_BUILTIN_STOREUPD256, IX86_BUILTIN_STOREUPS256,
IX86_BUILTIN_LDDQU256, IX86_BUILTIN_LOADDQU256,
IX86_BUILTIN_STOREDQU256, IX86_BUILTIN_MASKLOADPD,
IX86_BUILTIN_MASKLOADPS, IX86_BUILTIN_MASKSTOREPD,
IX86_BUILTIN_MASKSTOREPS, IX86_BUILTIN_MASKLOADPD256,
IX86_BUILTIN_MASKLOADPS256, IX86_BUILTIN_MASKSTOREPD256,
IX86_BUILTIN_MASKSTOREPS256, IX86_BUILTIN_MOVSHDUP256,
IX86_BUILTIN_MOVSLDUP256, IX86_BUILTIN_MOVDDUP256,
IX86_BUILTIN_SQRTPD256, IX86_BUILTIN_SQRTPS256,
IX86_BUILTIN_SQRTPS_NR256, IX86_BUILTIN_RSQRTPS256,
IX86_BUILTIN_RSQRTPS_NR256, IX86_BUILTIN_RCPPS256,
IX86_BUILTIN_ROUNDPD256, IX86_BUILTIN_ROUNDPS256,
IX86_BUILTIN_UNPCKHPD256, IX86_BUILTIN_UNPCKLPD256,
IX86_BUILTIN_UNPCKHPS256, IX86_BUILTIN_UNPCKLPS256,
IX86_BUILTIN_SI256_SI, IX86_BUILTIN_PS256_PS,
IX86_BUILTIN_PD256_PD, IX86_BUILTIN_SI_SI256,
IX86_BUILTIN_PS_PS256, IX86_BUILTIN_PD_PD256,
IX86_BUILTIN_VTESTZPD, IX86_BUILTIN_VTESTCPD,
IX86_BUILTIN_VTESTNZCPD, IX86_BUILTIN_VTESTZPS,
IX86_BUILTIN_VTESTCPS, IX86_BUILTIN_VTESTNZCPS,
IX86_BUILTIN_VTESTZPD256, IX86_BUILTIN_VTESTCPD256,
IX86_BUILTIN_VTESTNZCPD256, IX86_BUILTIN_VTESTZPS256,
IX86_BUILTIN_VTESTCPS256, IX86_BUILTIN_VTESTNZCPS256,
IX86_BUILTIN_PTESTZ256, IX86_BUILTIN_PTESTC256,
IX86_BUILTIN_PTESTNZC256, IX86_BUILTIN_MOVMSKPD256
and IX86_BUILTIN_MOVMSKPS256,
(ix86_special_builtin_type): Add V32QI_FTYPE_PCCHAR,
V8SF_FTYPE_PCV4SF, V8SF_FTYPE_PCFLOAT, V4DF_FTYPE_PCV2DF,
V4DF_FTYPE_PCDOUBLE, V8SF_FTYPE_PCV8SF_V8SF,
V4DF_FTYPE_PCV4DF_V4DF, V4SF_FTYPE_PCV4SF_V4SF,
V2DF_FTYPE_PCV2DF_V2DF, VOID_FTYPE_PCHAR_V32QI,
VOID_FTYPE_PFLOAT_V8SF, VOID_FTYPE_PDOUBLE_V4DF,
VOID_FTYPE_PV8SF_V8SF_V8SF, VOID_FTYPE_PV4DF_V4DF_V4DF,
VOID_FTYPE_PV4SF_V4SF_V4SF and VOID_FTYPE_PV2DF_V2DF_V2DF,
(ix86_builtin_type): Add INT_FTYPE_V8SF_V8SF_PTEST,
INT_FTYPE_V4DI_V4DI_PTEST, INT_FTYPE_V4DF_V4DF_PTEST,
INT_FTYPE_V4SF_V4SF_PTEST, INT_FTYPE_V2DF_V2DF_PTEST,
INT_FTYPE_V8SF, INT_FTYPE_V4DF, V8SI_FTYPE_V8SF, V8SI_FTYPE_V4SI,
V8SF_FTYPE_V8SF, V8SF_FTYPE_V8SI, V8SF_FTYPE_V4SF,
V4SI_FTYPE_V8SI, V4SI_FTYPE_V4DF, V4DF_FTYPE_V4DF,
V4DF_FTYPE_V4SI, V4DF_FTYPE_V4SF, V4DF_FTYPE_V2DF,
V4SF_FTYPE_V4DF, V4SF_FTYPE_V8SF, V2DF_FTYPE_V4DF,
V8SF_FTYPE_V8SF_V8SF, V8SF_FTYPE_V8SF_V8SI,
V4DF_FTYPE_V4DF_V4DF, V4DF_FTYPE_V4DF_V4DI,
V4SF_FTYPE_V4SF_V4SI, V2DF_FTYPE_V2DF_V2DI,
V8SF_FTYPE_V8SF_INT, V4SI_FTYPE_V8SI_INT, V4SF_FTYPE_V8SF_INT,
V2DF_FTYPE_V4DF_INT, V4DF_FTYPE_V4DF_INT,
V8SF_FTYPE_V8SF_V8SF_V8SF, V4DF_FTYPE_V4DF_V4DF_V4DF,
V8SI_FTYPE_V8SI_V8SI_INT, V8SF_FTYPE_V8SF_V8SF_INT,
V4DF_FTYPE_V4DF_V4DF_INT, V4DF_FTYPE_V4DF_V2DF_INT,
V8SF_FTYPE_V8SF_V8SF_V8SI_INT, V4DF_FTYPE_V4DF_V4DF_V4DI_INT,
V4SF_FTYPE_V4SF_V4SF_V4SI_INT and V2DF_FTYPE_V2DF_V2DF_V2DI_INT.
(bdesc_special_args): Add IX86_BUILTIN_VZEROALL,
IX86_BUILTIN_VZEROUPPER. IX86_BUILTIN_VZEROUPPER_REX64,
IX86_BUILTIN_VBROADCASTSS, IX86_BUILTIN_VBROADCASTSD256,
IX86_BUILTIN_VBROADCASTSS256, IX86_BUILTIN_VBROADCASTPD256,
IX86_BUILTIN_VBROADCASTPS256, IX86_BUILTIN_LOADUPD256,
IX86_BUILTIN_LOADUPS256, IX86_BUILTIN_STOREUPD256,
IX86_BUILTIN_STOREUPS256, IX86_BUILTIN_LOADDQU256,
IX86_BUILTIN_STOREDQU256, IX86_BUILTIN_LDDQU256,
IX86_BUILTIN_MASKLOADPD, IX86_BUILTIN_MASKLOADPS,
IX86_BUILTIN_MASKLOADPD256, IX86_BUILTIN_MASKLOADPS256,
IX86_BUILTIN_MASKSTOREPD, IX86_BUILTIN_MASKSTOREPS,
IX86_BUILTIN_MASKSTOREPD256 and IX86_BUILTIN_MASKSTOREPS256.
(ix86_builtins): Add IX86_BUILTIN_ADDPD256,
IX86_BUILTIN_ADDPS256, IX86_BUILTIN_ADDSUBPD256,
IX86_BUILTIN_ADDSUBPS256, IX86_BUILTIN_ANDPD256,
IX86_BUILTIN_ANDPS256, IX86_BUILTIN_ANDNPD256,
IX86_BUILTIN_ANDNPS256, IX86_BUILTIN_DIVPD256,
IX86_BUILTIN_DIVPS256, IX86_BUILTIN_HADDPD256,
IX86_BUILTIN_HSUBPS256, IX86_BUILTIN_HSUBPD256,
IX86_BUILTIN_HADDPS256, IX86_BUILTIN_MAXPD256,
IX86_BUILTIN_MAXPS256, IX86_BUILTIN_MINPD256,
IX86_BUILTIN_MINPS256, IX86_BUILTIN_MULPD256,
IX86_BUILTIN_MULPS256, IX86_BUILTIN_ORPD256,
IX86_BUILTIN_ORPS256, IX86_BUILTIN_SUBPD256,
IX86_BUILTIN_SUBPS256, IX86_BUILTIN_XORPD256,
IX86_BUILTIN_XORPS256, IX86_BUILTIN_VPERMILVARPD,
IX86_BUILTIN_VPERMILVARPS, IX86_BUILTIN_VPERMILVARPD256,
IX86_BUILTIN_VPERMILVARPS256, IX86_BUILTIN_BLENDPD256,
IX86_BUILTIN_BLENDPS256, IX86_BUILTIN_BLENDVPD256,
IX86_BUILTIN_BLENDVPS256, IX86_BUILTIN_DPPS256,
IX86_BUILTIN_SHUFPD256, IX86_BUILTIN_SHUFPS256,
IX86_BUILTIN_CMPSD, IX86_BUILTIN_CMPSS, IX86_BUILTIN_CMPPD,
IX86_BUILTIN_CMPPS,
IX86_BUILTIN_CMPPD256,IX86_BUILTIN_CMPPS256,
IX86_BUILTIN_EXTRACTF128PD256, IX86_BUILTIN_EXTRACTF128PS256,
IX86_BUILTIN_EXTRACTF128SI256, IX86_BUILTIN_CVTDQ2PD256,
IX86_BUILTIN_CVTDQ2PS256, IX86_BUILTIN_CVTPD2PS256,
IX86_BUILTIN_CVTPS2DQ256, IX86_BUILTIN_CVTPS2PD256,
IX86_BUILTIN_CVTTPD2DQ256, IX86_BUILTIN_CVTPD2DQ256,
IX86_BUILTIN_CVTTPS2DQ256, IX86_BUILTIN_VPERM2F128PD256,
IX86_BUILTIN_VPERM2F128PS256, IX86_BUILTIN_VPERM2F128SI256,
IX86_BUILTIN_VPERMILPD, IX86_BUILTIN_VPERMILPS,
IX86_BUILTIN_VPERMILPD256, IX86_BUILTIN_VPERMILPS256,
IX86_BUILTIN_VPERMIL2PD, IX86_BUILTIN_VPERMILPS,
IX86_BUILTIN_VPERMILPD256, IX86_BUILTIN_VPERMILPS256,
IX86_BUILTIN_VPERMIL2PD, IX86_BUILTIN_VPERMIL2PS,
IX86_BUILTIN_VPERMIL2PD256, IX86_BUILTIN_VPERMIL2PS256,
IX86_BUILTIN_VINSERTF128PD256, IX86_BUILTIN_VINSERTF128PS256,
IX86_BUILTIN_VINSERTF128SI256, IX86_BUILTIN_MOVSHDUP256,
IX86_BUILTIN_MOVSLDUP256, IX86_BUILTIN_MOVDDUP256,
IX86_BUILTIN_SQRTPD256, IX86_BUILTIN_SQRTPS256,
IX86_BUILTIN_SQRTPS_NR256, IX86_BUILTIN_RSQRTPS256,
IX86_BUILTIN_RSQRTPS_NR256, IX86_BUILTIN_RCPPS256,
IX86_BUILTIN_ROUNDPD256, IX86_BUILTIN_ROUNDPS256,
IX86_BUILTIN_UNPCKHPD256, IX86_BUILTIN_UNPCKLPD256,
IX86_BUILTIN_UNPCKHPS256, IX86_BUILTIN_UNPCKLPS256,
IX86_BUILTIN_SI256_SI, IX86_BUILTIN_PS256_PS,
IX86_BUILTIN_PD256_PD, IX86_BUILTIN_SI_SI256,
IX86_BUILTIN_PS_PS256, IX86_BUILTIN_PD_PD256,
IX86_BUILTIN_VTESTZPD, IX86_BUILTIN_VTESTCPD,
IX86_BUILTIN_VTESTNZCPD, IX86_BUILTIN_VTESTZPS,
IX86_BUILTIN_VTESTCPS, IX86_BUILTIN_VTESTNZCPS,
IX86_BUILTIN_VTESTZPD256, IX86_BUILTIN_VTESTCPD256,
IX86_BUILTIN_VTESTNZCPD256, IX86_BUILTIN_VTESTZPS256,
IX86_BUILTIN_VTESTCPS256, IX86_BUILTIN_VTESTNZCPS256,
IX86_BUILTIN_PTESTZ256, IX86_BUILTIN_PTESTC256,
IX86_BUILTIN_PTESTNZC256, IX86_BUILTIN_MOVMSKPD256 and
IX86_BUILTIN_MOVMSKPS256.
(ix86_init_mmx_sse_builtins): Support AVX builtins.
(ix86_expand_args_builtin): Likewise.
(ix86_expand_special_args_builtin): Likewise.
(ix86_hard_regno_mode_ok): Handle AVX modes.
(ix86_expand_vector_init_duplicate): Likewise.
(ix86_expand_vector_init_one_nonzero): Likewise.
(ix86_expand_vector_init_one_var): Likewise.
(ix86_expand_vector_init_concat): Likewise.
(ix86_expand_vector_init_general): Likewise.
(ix86_expand_vector_set): Likewise.
(ix86_vector_mode_supported_p): Likewise.
(x86_extended_reg_mentioned_p): Check INSN_P before using
PATTERN.
* config/i386/i386-c.c (ix86_target_macros_internal): Handle
OPTION_MASK_ISA_AVX and OPTION_MASK_ISA_FMA.
* config/i386/i386.h (TARGET_AVX): New.
(TARGET_FMA): Likewise.
(TARGET_CPU_CPP_BUILTINS): Handle TARGET_AVX and TARGET_FMA.
(BIGGEST_ALIGNMENT): Set to 256 for TARGET_AVX.
(VALID_AVX256_REG_MODE): New.
(AVX256_VEC_FLOAT_MODE_P): Likewise.
(AVX_FLOAT_MODE_P): Likewise.
(AVX128_VEC_FLOAT_MODE_P): Likewise.
(AVX256_VEC_FLOAT_MODE_P): Likewise.
(AVX_VEC_FLOAT_MODE_P): Likewise.
(ASM_OUTPUT_AVX_PREFIX): Likewise.
(ASM_OUTPUT_OPCODE): Likewise.
(UNITS_PER_SIMD_WORD): Add a FIXME for 32byte vectorizer
support.
(SSE_REG_MODE_P): Allow 256bit vector modes.
(ix86_args): Add a warn_avx field.
* config/i386/i386.md (UNSPEC_PCMP): New.
(UNSPEC_VPERMIL): Likewise.
(UNSPEC_VPERMIL2): Likewise.
(UNSPEC_VPERMIL2F128): Likewise.
(UNSPEC_MASKLOAD): Likewise.
(UNSPEC_MASKSTORE): Likewise.
(UNSPEC_CAST): Likewise.
(UNSPEC_VTESTP): Likewise.
(UNSPECV_VZEROALL): Likewise.
(UNSPECV_VZEROUPPER): Likewise.
(XMM0_REG): Likewise.
(XMM1_REG): Likewise.
(XMM2_REG): Likewise.
(XMM3_REG): Likewise.
(XMM4_REG): Likewise.
(XMM5_REG): Likewise.
(XMM6_REG): Likewise.
(XMM8_REG): Likewise.
(XMM9_REG): Likewise.
(XMM10_REG): Likewise.
(XMM11_REG): Likewise.
(XMM12_REG): Likewise.
(XMM13_REG): Likewise.
(XMM14_REG): Likewise.
(XMM15_REG): Likewise.
(prefix): Likewise.
(prefix_vex_imm8): Likewise.
(prefix_vex_w): Likewise.
(length_vex): Likewise.
(maxmin): Likewise.
(movoi): Likewise.
(*avx_ashlti3): Likewise.
(*avx_lshrti3): Likewise.
(*avx_setcc<mode>): Likewise.
(*fop_<mode>_comm_mixed_avx): Likewise.
(*fop_<mode>_comm_avx): Likewise.
(*fop_<mode>_1_mixed_avx): Likewise.
(*fop_<mode>_1_avx): Likewise.
(*avx_<code><mode>3): Likewise.
(*avx_ieee_smin<mode>3): Likewise.
(*avx_ieee_smax<mode>3): Likewise.
(mode): Add OI, V8SF and V4DF.
(length): Support VEX prefix.
(*cmpfp_i_mixed): Set prefix attribute.
(*cmpfp_i_sse): Likewise.
(*cmpfp_iu_mixed): Likewise.
(*cmpfp_iu_sse): Likewise.
(*movsi_1): Support AVX.
(*movdi_2): Likewise.
(*movdi_1_rex64): Likewise.
(*movti_internal): Likewise.
(*movti_rex64): Likewise.
(*movsf_1): Likewise.
(*movdf_nointeger): Likewise.
(*movdf_integer_rex64): Likewise.
(*movtf_internal): Likewise.
(zero_extendsidi2_32): Likewise.
(zero_extendsidi2_rex64): Likewise.
(*extendsfdf2_mixed): Likewise.
(*extendsfdf2_sse): Likewise.
(*truncdfsf_fast_mixed): Likewise.
(*truncdfsf_fast_sse): Likewise.
(*truncdfsf_mixed): Likewise.
(fix_trunc<mode>di_sse): Likewise.
(fix_trunc<mode>si_sse): Likewise.
(*float<SSEMODEI24:mode><MODEF:mode>2_mixed_interunit): Likewise.
(*float<SSEMODEI24:mode><MODEF:mode>2_mixed_nointerunit): Likewise.
(*float<SSEMODEI24:mode><MODEF:mode>2_sse_interunit): Likewise.
(*float<SSEMODEI24:mode><MODEF:mode>2_sse_nointerunit): Likewise.
(*rcpsf2_sse): Likewise.
(*rsqrtsf2_sse): Likewise.
(*sqrt<mode>2_sse): Likewise.
(sse4_1_round<mode>2): Likewise.
(*sse_prologue_save_insn): Disallow REX prefix for AVX.
Support AVX. Set length attribute properly for AVX.
* config/i386/i386-modes.def (VECTOR_MODES (INT, 32)): New.
(VECTOR_MODES (FLOAT, 32)): Likewise.
(VECTOR_MODE (INT, DI, 8)): Likewise.
(VECTOR_MODE (INT, HI, 32)): Likewise.
(VECTOR_MODE (INT, QI, 64)): Likewise.
(VECTOR_MODE (FLOAT, DF, 8)): Likewise.
(VECTOR_MODE (FLOAT, SF, 16)): Likewise.
(VECTOR_MODE (INT, DI, 4)): Removed.
(VECTOR_MODE (INT, SI, 8)): Likewise.
(VECTOR_MODE (INT, HI, 16)): Likewise.
(VECTOR_MODE (INT, QI, 32)): Likewise.
(VECTOR_MODE (FLOAT, SF, 8)): Likewise.
(INT_MODE (OI, 32)): Likewise.
* config/i386/i386.opt (mavx): New.
(mfma): Likewise.
* config/i386/i386-protos.h (ix86_attr_length_vex_default): New.
* config/i386/mmx.md (*mov<mode>_internal_rex64): Support AVX.
(*mov<mode>_internal_avx): New.
(*movv2sf_internal_rex64_avx): Likewise.
(*movv2sf_internal_avx): Likewise.
* config/i386/predicates.md (const_4_to_5_operand): New.
(const_6_to_7_operand): Likewise.
(const_8_to_11_operand): Likewise.
(const_12_to_15_operand): Likewise.
(avx_comparison_float_operator): Likewise.
* config/i386/sse.md (AVX256MODEI): New.
(AVX256MODE): Likewise.
(AVXMODEQI): Likewise.
(AVXMODE): Likewise.
(AVX256MODEF2P): Likewise.
(AVX256MODE2P): Likewise.
(AVX256MODE4P): Likewise.
(AVX256MODE8P): Likewise.
(AVXMODEF2P): Likewise.
(AVXMODEF4P): Likewise.
(AVXMODEDCVTDQ2PS): Likewise.
(AVXMODEDCVTPS2DQ): Likewise.
(avxvecmode): Likewise.
(avxvecpsmode): Likewise.
(avxhalfvecmode): Likewise.
(avxscalarmode): Likewise.
(avxcvtvecmode): Likewise.
(avxpermvecmode): Likewise.
(avxmodesuffixf2c): Likewise.
(avxmodesuffixp): Likewise.
(avxmodesuffixs): Likewise.
(avxmodesuffix): Likewise.
(vpermilbits): Likewise.
(pinsrbits): Likewise.
(mov<mode>): Likewise.
(*mov<mode>_internal): Likewise.
(push<mode>1): Likewise.
(movmisalign<mode>): Likewise.
(avx_movup<avxmodesuffixf2c><avxmodesuffix>): Likewise.
(avx_movdqu<avxmodesuffix>): Likewise.
(avx_lddqu<avxmodesuffix>): Likewise.
(<plusminus_insn><mode>3): Likewise.
(*avx_<plusminus_insn><mode>3): Likewise.
(*avx_vm<plusminus_insn><mode>3): Likewise.
(mul<mode>3): Likewise.
(*avx_mul<mode>3): Likewise.
(*avx_vmmul<mode>3): Likewise.
(divv8sf3): Likewise.
(divv4df3): Likewise.
(avx_div<mode>3): Likewise.
(*avx_div<mode>3): Likewise.
(*avx_vmdiv<mode>3): Likewise.
(avx_rcpv8sf2): Likewise.
(*avx_vmrcpv4sf2): Likewise.
(sqrtv8sf2): Likewise.
(avx_sqrtv8sf2): Likewise.
(*avx_vmsqrt<mode>2): Likewise.
(rsqrtv8sf2): Likewise.
(avx_rsqrtv8sf2): Likewise.
(*avx_vmrsqrtv4sf2): Likewise.
(<code><mode>3): Likewise.
(*avx_<code><mode>3_finite): Likewise.
(*avx_<code><mode>3): Likewise.
(*avx_vm<code><mode>3): Likewise.
(*avx_ieee_smin<mode>3): Likewise.
(*avx_ieee_smax<mode>3): Likewise.
(avx_addsubv8sf3): Likewise.
(avx_addsubv4df3): Likewise.
(*avx_addsubv4sf3): Likewise.
(*avx_addsubv2df3): Likewise.
(avx_h<plusminus_insn>v4df3): Likewise.
(avx_h<plusminus_insn>v8sf3): Likewise.
(*avx_h<plusminus_insn>v4sf3): Likewise.
(*avx_h<plusminus_insn>v2df3): Likewise.
(avx_cmpp<avxmodesuffixf2c><mode>3): Likewise.
(avx_cmps<ssemodesuffixf2c><mode>3): Likewise.
(*avx_maskcmp<mode>3): Likewise.
(avx_nand<mode>3): Likewise.
(*avx_<code><mode>3): Likewise.
(*avx_nand<mode>3): Likewise.
(*avx_<code><mode>3): Likewise.
(*avx_cvtsi2ss): Likewise.
(*avx_cvtsi2ssq): Likewise.
(*avx_cvtsi2sd): Likewise.
(*avx_cvtsi2sdq): Likewise.
(*avx_cvtsd2ss): Likewise.
(avx_cvtss2sd): Likewise.
(avx_cvtdq2ps<avxmodesuffix>): Likewise.
(avx_cvtps2dq<avxmodesuffix>): Likewise.
(avx_cvttps2dq<avxmodesuffix>): Likewise.
(*avx_cvtsi2sd): Likewise.
(*avx_cvtsi2sdq): Likewise.
(avx_cvtdq2pd256): Likewise.
(avx_cvtpd2dq256): Likewise.
(avx_cvttpd2dq256): Likewise.
(*avx_cvtsd2ss): Likewise.
(*avx_cvtss2sd): Likewise.
(avx_cvtpd2ps256): Likewise.
(avx_cvtps2pd256): Likewise.
(*avx_movhlps): Likewise.
(*avx_movlhps): Likewise.
(avx_unpckhps256): Likewise.
(*avx_unpckhps): Likewise.
(avx_unpcklps256): Likewise.
(*avx_unpcklps): Likewise.
(avx_movshdup256): Likewise.
(avx_movsldup256): Likewise.
(avx_shufps256): Likewise.
(avx_shufps256_1): Likewise.
(*avx_shufps_<mode>): Likewise.
(*avx_loadhps): Likewise.
(*avx_storelps): Likewise.
(*avx_loadlps): Likewise.
(*avx_movss): Likewise.
(*vec_dupv4sf_avx): Likewise.
(*vec_concatv2sf_avx): Likewise.
(*vec_concatv4sf_avx): Likewise.
(*vec_setv4sf_0_avx): Likewise.
(*vec_setv4sf_avx): Likewise.
(*avx_insertps): Likewise.
(avx_vextractf128<mode>): Likewise.
(vec_extract_lo_<mode>): Likewise.
(vec_extract_hi_<mode>): Likewise.
(vec_extract_lo_<mode>): Likewise.
(vec_extract_hi_<mode>): Likewise.
(vec_extract_lo_v16hi): Likewise.
(vec_extract_hi_v16hi): Likewise.
(vec_extract_lo_v32qi): Likewise.
(vec_extract_hi_v32qi): Likewise.
(avx_unpckhpd256): Likewise.
(*avx_unpckhpd): Likewise.
(avx_movddup256): Likewise.
(*avx_movddup): Likewise.
(avx_unpcklpd256): Likewise.
(*avx_unpcklpd): Likewise.
(avx_shufpd256): Likewise.
(avx_shufpd256_1): Likewise.
(*avx_punpckhqdq): Likewise.
(*avx_punpcklqdq): Likewise.
(*avx_shufpd_<mode>): Likewise.
(*avx_storehpd): Likewise.
(*avx_loadhpd): Likewise.
(*avx_loadlpd): Likewise.
(*avx_movsd): Likewise.
(*vec_concatv2df_avx): Likewise.
(*avx_<plusminus_insn><mode>3): Likewise.
(*avx_<plusminus_insn><mode>3): Likewise.
(*avx_mulv8hi3): Likewise.
(*avxv8hi3_highpart): Likewise.
(*avx_umulv8hi3_highpart): Likewise.
(*avx_umulv2siv2di3): Likewise.
(*avx_mulv2siv2di3): Likewise.
(*avx_pmaddwd): Likewise.
(*avx_mulv4si3): Likewise.
(*avx_ashr<mode>3): Likewise.
(*avx_lshr<mode>3): Likewise.
(*avx_ashl<mode>3): Likewise.
(*avx_<code><mode>3): Likewise.
(*avx_eq<mode>3): Likewise.
(*avx_gt<mode>3): Likewise.
(*avx_nand<mode>3): Likewise.
(*avx_nand<mode>3): Likewise.
(*avx_<code><mode>3): Likewise.
(*avx_<code><mode>3): Likewise.
(*avx_packsswb): Likewise.
(*avx_packssdw): Likewise.
(*avx_packuswb): Likewise.
(*avx_punpckhbw): Likewise.
(*avx_punpcklbw): Likewise.
(*avx_punpckhwd): Likewise.
(*avx_punpcklwd): Likewise.
(*avx_punpckhdq): Likewise.
(*avx_punpckldq): Likewise.
(*avx_pinsr<avxmodesuffixs>): Likewise.
(*avx_pinsrq): Likewise.
(*avx_loadld): Likewise.
(*vec_extractv2di_1_rex64_avx): Likewise.
(*vec_extractv2di_1_avx): Likewise.
(*vec_dupv2di_avx): Likewise.
(*vec_concatv2si_avx): Likewise.
(*vec_concatv4si_1_avx): Likewise.
(*vec_concatv2di_avx): Likewise.
(*vec_concatv2di_rex64_avx): Likewise.
(*avx_uavgv16qi3): Likewise.
(*avx_uavgv8hi3): Likewise.
(*avx_psadbw): Likewise.
(avx_movmskp<avxmodesuffixf2c>256): Likewise.
(*avx_phaddwv8hi3): Likewise.
(*avx_phadddv4si3): Likewise.
(*avx_phaddswv8hi3): Likewise.
(*avx_phsubwv8hi3): Likewise.
(*avx_phsubdv4si3): Likewise.
(*avx_phsubswv8hi3): Likewise.
(*avx_pmaddubsw128): Likewise.
(*avx_pmulhrswv8hi3): Likewise.
(*avx_pshufbv16qi3): Likewise.
(*avx_psign<mode>3): Likewise.
(*avx_palignrti): Likewise.
(avx_blendp<avxmodesuffixf2c><avxmodesuffix>): Likewise.
(avx_blendvp<avxmodesuffixf2c><avxmodesuffix>): Likewise.
(avx_dpp<avxmodesuffixf2c><avxmodesuffix>): Likewise.
(*avx_mpsadbw): Likewise.
(*avx_packusdw): Likewise.
(*avx_pblendvb): Likewise.
(*avx_pblendw): Likewise.
(avx_vtestp<avxmodesuffixf2c><avxmodesuffix>): Likewise.
(avx_ptest256): Likewise.
(avx_roundp<avxmodesuffixf2c>256): Likewise.
(*avx_rounds<ssemodesuffixf2c>): Likewise.
(*avx_aesenc): Likewise.
(*avx_aesenclast): Likewise.
(*avx_aesdec): Likewise.
(*avx_aesdeclast): Likewise.
(avx_vzeroupper): Likewise.
(avx_vzeroupper_rex64): Likewise.
(avx_vpermil<mode>): Likewise.
(avx_vpermilvar<mode>3): Likewise.
(avx_vpermil2<mode>3): Likewise.
(avx_vperm2f128<mode>3): Likewise.
(avx_vbroadcasts<avxmodesuffixf2c><avxmodesuffix>): Likewise.
(avx_vbroadcastss256): Likewise.
(avx_vbroadcastf128_p<avxmodesuffixf2c>256): Likewise.
(avx_vinsertf128<mode>): Likewise.
(vec_set_lo_<mode>): Likewise.
(vec_set_hi_<mode>): Likewise.
(vec_set_lo_<mode>): Likewise.
(vec_set_hi_<mode>): Likewise.
(vec_set_lo_v16hi): Likewise.
(vec_set_hi_v16hi): Likewise.
(vec_set_lo_v32qi): Likewise.
(vec_set_hi_v32qi): Likewise.
(avx_maskloadp<avxmodesuffixf2c><avxmodesuffix>): Likewise.
(avx_maskstorep<avxmodesuffixf2c><avxmodesuffix>): Likewise.
(avx_<avxmodesuffixp><avxmodesuffix>_<avxmodesuffixp>): Likewise.
(avx_<avxmodesuffixp>_<avxmodesuffixp><avxmodesuffix>): Likewise.
(vec_init<mode>): Likewise.
(*vec_concat<mode>_avx): Likewise.
(blendbits): Support V8SF and V4DF.
(sse2_movq128): Support AVX.
(<sse>_movnt<mode>): Likewise.
(sse2_movntv2di): Likewise.
(sse_rcpv4sf2): Likewise.
(sse_sqrtv4sf2): Likewise.
(sse_rsqrtv4sf2): Likewise.
(<sse>_comi): Likewise.
(<sse>_ucomi): Likewise.
(sse_cvtss2si): Likewise.
(sse_cvtss2si_2): Likewise.
(sse_cvtss2siq): Likewise.
(sse_cvtss2siq_2): Likewise.
(sse_cvttss2si): Likewise.
(sse_cvttss2siq): Likewise.
(sse2_cvtsd2si): Likewise.
(sse2_cvtsd2si_2): Likewise.
(sse2_cvtsd2siq): Likewise.
(sse2_cvtsd2siq_2): Likewise.
(sse2_cvttsd2si): Likewise.
(sse2_cvttsd2siq): Likewise.
(sse2_cvtdq2pd): Likewise.
(*sse2_cvtpd2dq): Likewise.
(*sse2_cvttpd2dq): Likewise.
(*sse2_cvtpd2ps): Likewise.
(sse2_cvtps2pd): Likewise.
(sse3_movshdup): Likewise.
(sse3_movsldup): Likewise.
(sse_storehps): Likewise.
(*sse4_1_extractps): Likewise.
(sse2_storelpd): Likewise.
(vec_dupv2df_sse3): Likewise.
(*vec_concatv2df_sse3): Likewise.
(*sse4_1_pextrb): Likewise.
(*sse4_1_pextrb_memory): Likewise.
(*sse2_pextrw): Likewise.
(*sse4_1_pextrw_memory): Likewise.
(*sse4_1_pextrd): Likewise.
(*sse4_1_pextrq): Likewise.
(sse2_pshufd_1): Likewise.
(sse2_pshuflw_1): Likewise.
(sse2_pshufhw_1): Likewise.
(*sse2_storeq_rex64): Likewise.
(*vec_dupv4si): Likewise.
(<sse>_movmskp<ssemodesuffixf2c>): Likewise.
(sse2_pmovmskb): Likewise.
(*sse2_maskmovdqu): Likewise.
(*sse2_maskmovdqu_rex64): Likewise.
(sse_ldmxcsr): Likewise.
(sse_stmxcsr): Likewise.
(abs<mode>2): Likewise.
(sse4_1_movntdqa): Likewise.
(sse4_1_phminposuw): Likewise.
(sse4_1_extendv8qiv8hi2): Likewise.
(*sse4_1_extendv8qiv8hi2): Likewise.
(sse4_1_extendv4qiv4si2): Likewise.
(*sse4_1_extendv4qiv4si2): Likewise.
(sse4_1_extendv2qiv2di2): Likewise.
(*sse4_1_extendv2qiv2di2): Likewise.
(sse4_1_extendv4hiv4si2): Likewise.
(*sse4_1_extendv4hiv4si2): Likewise.
(sse4_1_extendv2hiv2di2): Likewise.
(*sse4_1_extendv2hiv2di2): Likewise.
(sse4_1_extendv2siv2di2): Likewise.
(*sse4_1_extendv2siv2di2): Likewise.
(sse4_1_zero_extendv8qiv8hi2): Likewise.
(*sse4_1_zero_extendv8qiv8hi2): Likewise.
(sse4_1_zero_extendv4qiv4si2): Likewise.
(*sse4_1_zero_extendv4qiv4si2): Likewise.
(sse4_1_zero_extendv2qiv2di2): Likewise.
(*sse4_1_zero_extendv2qiv2di2): Likewise.
(sse4_1_zero_extendv4hiv4si2): Likewise.
(*sse4_1_zero_extendv4hiv4si2): Likewise.
(sse4_1_zero_extendv2hiv2di2): Likewise.
(*sse4_1_zero_extendv2hiv2di2): Likewise.
(sse4_1_zero_extendv2siv2di2): Likewise.
(*sse4_1_zero_extendv2siv2di2): Likewise.
(sse4_1_ptest): Likewise.
(sse4_1_roundp<ssemodesuffixf2c>): Likewise.
(sse4_2_pcmpestri): Likewise.
(sse4_2_pcmpestrm): Likewise.
(sse4_2_pcmpistri): Likewise.
(sse4_2_pcmpistrm): Likewise.
(aesimc): Likewise.
(aeskeygenassist): Likewise.
2008-08-28 Uros Bizjak <ubizjak@gmail.com>
* config/i386/predicates.md (vzeroall_operation): New.
* config/i386/sse.md (avx_vzeroall): New.
(*avx_vzeroall): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@139726 138bc75d-0d04-0410-961f-82ee72b054a4
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* config/i386/i386.c (ix86_match_ccmode): Handle CCAmode,
CCCmode, CCOmode and CCSmode destination modes.
PR target/37191
* config/i386/mmx.md (*vec_extractv2sf_0): Avoid combining registers
from different units in a single alternative.
(*vec_extractv2sf_1): Ditto.
(*vec_extractv2si_0): Ditto.
(*vec_extractv2si_1): Ditto.
* config/i386/sse.md (sse2_storehpd): Ditto.
(sse2_storelpd): Ditto.
(sse2_loadhpd): Ditto.
(sse2_loadlpd): Ditto.
PR target/37197
* config/i386/i386.md (clzsi2_abm): Fix operand 1 constraints.
(popcountsi2): Ditto.
(clzdi2_abm): Ditto.
(popcountdi2): Ditto.
(clzhi2_abm): Ditto.
(popcounthi2): Ditto.
testsuite/ChangeLog:
PR target/37184
* gcc.target/i386/pr37184.c: New test.
PR target/37191
* gcc.target/i386/pr37191.c: New test.
PR target/37197
* gcc.target/i386/pr37197.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@139471 138bc75d-0d04-0410-961f-82ee72b054a4
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to avoid inter-unit moves for !TARGET_INTER_UNIT_MOVES.
(*movv2sf_internal_rex64): Ditto.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@138566 138bc75d-0d04-0410-961f-82ee72b054a4
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* config/i386/sse.md (vec_concatv2di): Add Y2 constraint to
alternative 0 of operand 1.
(*vec_concatv2di_rex64_sse): Ditto.
(*vec_concatv2di_rex64_sse4_1): Add x constraint to alternative 0
of operand 1.
(*sse2_storeq_rex64): Penalize allocation of "r" registers.
* config/i386/mmx.md (*mov<mode>_internal_rex64): Penalize allocation
of "Y2" registers to avoid SSE <-> MMX conversions for DImode moves.
(*movv2sf_internal_rex64): Ditto.
testsuite/ChangeLog:
PR target/36992
* gcc.target/i386/pr36992-1.c: New test.
* gcc.target/i386/pr36992-2.c: Ditto.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@138564 138bc75d-0d04-0410-961f-82ee72b054a4
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* config/i386/mmx.md (mmx_subv2sf3): New expander.
(*mmx_subv2sf3): Rename from mmx_subv2sf3 insn pattern.
(*mmx_eqv2sf3): Rename from mmx_eqv2sf3 insn pattern.
(mmx_eqv2sf3): New expander. Use ix86_fixup_binary_operands_no_copy
to handle nonimmediate operands.
(*mmx_paddwd): Rename from mmx_paddwd insn pattern.
(mmx_paddwd): New expander. Use ix86_fixup_binary_operands_no_copy
to handle nonimmediate operands.
(*mmx_pmulhrwv4hi3): Rename from mmx_pmulhrwv4hi3 insn pattern.
(mmx_pmulhrwv4hi3): New expander. Use
ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
(*sse2_umulv1siv1di3): Rename from sse2_umulv1siv1di3 insn pattern.
(sse2_umulv1siv1di3): New expander. Use
ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
(*mmx_eq<mode>3): Rename from mmx_eq<mode>3 insn pattern.
(mmx_eq<mode>3): New expander. Use
ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
(*mmx_uavgv8qi3): Rename from mmx_uavgv8qi3 insn pattern.
(mmx_uavgv8qi3): New expander. Use
ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
(*mmx_uavgv4hi3): Rename from mmx_uavgv4hi3 insn pattern.
(mmx_uavgv4hi3): New expander. Use
ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
* config/i386/sse.md
(*sse_movhlps): Rename from sse_movhlps insn pattern.
(sse_movhlps): New expander. Use ix86_fixup_binary_operands
to handle nonimmediate operands.
(*sse_movlhps): Rename from sse_movlhps insn pattern.
(sse_movlhps): New expander. Use ix86_fixup_binary_operands
to handle nonimmediate operands.
(*sse_loadhps): Rename from sse_loadhps insn pattern.
(sse_loadhps): New expander. Use ix86_fixup_binary_operands
to handle nonimmediate operands.
(*sse_loadlps): Rename from sse_loadlps insn pattern.
(sse_loadlps): New expander. Use ix86_fixup_binary_operands
to handle nonimmediate operands.
(*sse2_unpckhpd): Rename from sse2_unpckhpd insn pattern.
(sse2_unpckhpd): New expander. Use
ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
(*sse2_unpcklpd): Rename from sse2_unpcklpd insn pattern.
(sse2_unpcklpd): New expander. Use
ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
(*sse_loadhpd): Rename from sse_loadhpd insn pattern.
(sse_loadhpd): New expander. Use ix86_fixup_binary_operands
to handle nonimmediate operands.
(*sse_loadlpd): Rename from sse_loadlpd insn pattern.
(sse_loadlpd): New expander. Use ix86_fixup_binary_operands
to handle nonimmediate operands.
(*sse2_<plusminus_insn><mode>3): Rename from
sse2_<plusminus_insn><mode>3 insn pattern.
(sse2_<plusminus_insn><mode>3): New expander. Use
ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
(*sse2_umulv2siv2di3): Rename from sse2_umulv2siv2di3 insn pattern.
(sse2_umulv2siv2di3): New expander. Use
ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
(*sse4_1_mulv2siv2di3): Rename from sse4_1_mulv2siv2di3 insn pattern.
(sse4_1_mulv2siv2di3): New expander. Use
ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
(*sse2_pmaddwd): Rename from sse2_pmaddwd insn pattern.
(sse2_pmaddwd): New expander. Use
ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
(*sse2_eq<mode>3): Rename from sse2_eq<mode>3 insn pattern.
(sse2_eq<mode>3): New expander. Use
ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
(*sse4_1_eqv2di3): Rename from sse4_1_eqv2di3 insn pattern.
(sse4_1_eqv2di3): New expander. Use
ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
(*sse2_uavgv16qi3): Rename from sse2_uavgv16qi3 insn pattern.
(sse2_uavgv16qi3): New expander. Use
ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
(*sse2_uavgv16qi3): Rename from sse2_uavgv16qi3 insn pattern.
(sse2_uavgv16qi3): New expander. Use
ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
(*sse2_uavgv8hi3): Rename from sse2_uavgv8hi3 insn pattern.
(sse2_uavgv8hi3): New expander. Use
ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
(*ssse3_pmulhrswv8hi3): Rename from ssse3_pmulhrswv8hi3 insn pattern.
(ssse3_pmulhrswv8hi3): New expander. Use
ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
(*ssse3_pmulhrswv4hi3): Rename from ssse3_pmulhrswv4hi3 insn pattern.
(ssse3_pmulhrswv4hi3): New expander. Use
ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
(<sse>_vm<plusminus_insn><mode>3): Do not use ix86_binary_operator_ok.
(<sse>_vmmul<mode>3): Ditto.
(divv4sf3): Do not use ix86_fixup_binary_operands_no_copy.
(divv2df3): Ditto.
(ssse3_pmaddubsw128): Use register_operand for operand 1.
(ssse3_pmaddubsw): Ditto.
* config/i386/sse.md (ix86_fixup_binary_operands): Assert that src1
and src2 must have the same mode when swapped.
(ix86_expand_binop_builtin): Do not use ix86_fixup_binary_operands
and ix86_binary_operator_ok. Do not force operands in registers
when optimizing.
testsuite/ChangeLog:
PR target/35714
* gcc.target/i386/pr35714.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@135041 138bc75d-0d04-0410-961f-82ee72b054a4
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previous commit to "*mmx_...".
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@134991 138bc75d-0d04-0410-961f-82ee72b054a4
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(*addv2sf3): Rename from mmx_addv2sf3 insn pattern.
(mmx_addv2sf3): New expander. Use ix86_fixup_binary_operands_no_copy
to handle nonimmediate operands.
(*mulv2sf3): Rename from mmx_mulv2sf3 insn pattern.
(mmx_mulv2sf3): New expander. Use ix86_fixup_binary_operands_no_copy
to handle nonimmediate operands.
(*<code>v2sf3_finite): New insn pattern.
(*<code>v2sf3): Rename from mmx_<code>v2sf3 insn pattern.
(mmx_<code>v2sf3): New expander. Use
ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
(mmx_<plusminus_insn><mode>3): New expander. Use
ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
(*<plusminus_insn><mode>3): New insn pattern.
(mmx_add<mode>3): Removed.
(mmx_ssadd<mode>3): Ditto.
(mmx_usadd<mode>3): Ditto.
(mmx_sub<mode>3): Ditto.
(mmx_sssub<mode>3): Ditto.
(mmx_ussub<mode>3): Ditto.
(*mulv4hi3): Rename from mmx_mulv4hi3 insn pattern.
(mmx_mulv4hi3): New expander. Use ix86_fixup_binary_operands_no_copy
to handle nonimmediate operands.
(*smulv4hi3_highpart): Rename from mmx_smulv4hi3_highpart
insn pattern.
(mmx_smulv4hi3_highpart): New expander. Use
ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
(*umulv4hi3_highpart): Rename from mmx_umulv4hi3_highpart
insn pattern.
(mmx_umulv4hi3_highpart): New expander. Use
ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
(*<code>v4hi3): Rename from mmx_<code>v4hi3 insn pattern.
(mmx_<code>v4hi3): New expander. Use
ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
(*<code>v8qi3): Rename from mmx_<code>v8qi3 insn pattern.
(mmx_<code>v8qi3): New expander. Use
ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
(*<code><mode>3): Rename from mmx_<code><mode>3 insn pattern.
(mmx_<code><mode>3): New expander. Use
ix86_fixup_binary_operands_no_copy to handle nonimmediate operands.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@134976 138bc75d-0d04-0410-961f-82ee72b054a4
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