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* darwin.c: Include debug.h.Andreas Tobler2007-07-251-0/+1
| | | | | | | | 2007-07-25 Andreas Tobler <a.tobler@schweiz.org> * config/darwin.c: Include debug.h. From-SVN: r126933
* ia64.h (HARD_REGNO_NREGS): Handle RFmode.Steve Ellcey2007-07-255-124/+338
| | | | | | | | | | | | | | | * config/ia64/ia64.h (HARD_REGNO_NREGS): Handle RFmode. (HARD_REGNO_MODE_OK): Ditto. (MODES_TIEABLE_P): Ditto. (HARD_REGNO_CALLER_SAVE_MODE): Ditto. (CLASS_MAX_NREGS): Ditto. * config/ia64/ia64.c (ia64_print_operand_address): Add R format. * config/ia64/ia64.md (divsf3_internal_thr): Removed. (divdf3_internal_thr): Removed. * config/ia64/div.md: New file. * config/ia64/constraints.md: Add H constraint. From-SVN: r126930
* darwin.c (darwin_override_options): Additional fix for debug info formats ↵Daniel Berlin2007-07-251-1/+2
| | | | | | | | | | | that don't support var tracking. 2007-07-25 Daniel Berlin <dberlin@dberlin.org> * config/darwin.c (darwin_override_options): Additional fix for debug info formats that don't support var tracking. From-SVN: r126927
* mips.c (machine_function): Add initialized_mips16_gp_pseudo_p.Richard Sandiford2007-07-251-2/+12
| | | | | | | | | | | | gcc/ * config/mips/mips.c (machine_function): Add initialized_mips16_gp_pseudo_p. (mips16_gp_pseudo_reg): Do not emit the initialization of mips16_gp_pseudo_rtx when being called from the gimple cost- calculation routines; emit it on the first use outside those routines. From-SVN: r126919
* alpha.c (alpha_mangle_fundamental_type): Rename to...Julian Brown2007-07-258-25/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc/ * config/alpha/alpha.c (alpha_mangle_fundamental_type): Rename to... (alpha_mangle_type): This. (TARGET_MANGLE_FUNDAMENTAL_TYPE): Don't define. (TARGET_MANGLE_TYPE): Define this instead. * config/arm/arm-protos.h (arm_mangle_type): Add prototype. * config/arm/arm.c (TARGET_MANGLE_TYPE): Define target hook. (arm_init_neon_builtins): Fix comment. (arm_mangle_map_entry): New. (arm_mangle_map): New. (arm_mangle_type): New. * config/i386/i386.c (ix86_mangle_fundamental_type): Rename to... (ix86_mangle_type): This. Use TYPE_MAIN_VARIANT and restrict mangled types to VOID_TYPE, BOOLEAN_TYPE, INTEGER_TYPE, REAL_TYPE. (TARGET_MANGLE_FUNDAMENTAL_TYPE): Don't define. (TARGET_MANGLE_TYPE): Define this instead. * config/ia64/ia64.c (ia64_mangle_fundamental_type): Rename to... (ia64_mangle_type): This. Use TYPE_MAIN_VARIANT and restrict mangled types to VOID_TYPE, BOOLEAN_TYPE, INTEGER_TYPE, REAL_TYPE. (TARGET_MANGLE_FUNDAMENTAL_TYPE): Don't define. (TARGET_MANGLE_TYPE): Define this instead. * config/rs6000/rs6000.c (rs6000_mangle_fundamental_type): Rename to... (rs6000_mangle_type): This. Use TYPE_MAIN_VARIANT. (TARGET_MANGLE_FUNDAMENTAL_TYPE): Don't define. (TARGET_MANGLE_TYPE): Define this instead. * config/s390/s390.c (s390_mangle_fundamental_type): Rename to... (s390_mangle_type): This. (TARGET_MANGLE_FUNDAMENTAL_TYPE): Don't define. (TARGET_MANGLE_TYPE): Define this instead. * config/sparc/sparc.c (sparc_mangle_fundamental_type): Rename to... (sparc_mangle_type): This. (TARGET_MANGLE_FUNDAMENTAL_TYPE): Don't define. (TARGET_MANGLE_TYPE): Define this instead. * cp/mangle.c (write_type): Call mangle_type target hook on all types before mangling. Use original type, not main variant, as argument. * target-def.h (TARGET_MANGLE_FUNDAMENTAL_TYPE): Rename hook to... (TARGET_MANGLE_TYPE): This. * target.h (gcc_target): Rename mangle_fundamental_type to mangle_type. * doc/tm.texi (TARGET_MANGLE_FUNDAMENTAL_TYPE): Rename section to... (TARGET_MANGLE_TYPE): This. Note slightly different semantics. Co-Authored-By: Mark Shinwell <shinwell@codesourcery.com> From-SVN: r126917
* Makefile.in (TEXI_GCC_FILES): Add arm-neon-intrinsics.texi.Julian Brown2007-07-2519-294/+21400
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc/ * Makefile.in (TEXI_GCC_FILES): Add arm-neon-intrinsics.texi. * config.gcc (arm*-*-*): Add arm_neon.h to extra headers. (with_fpu): Allow --with-fpu=neon. * config/arm/aof.h (ADDITIONAL_REGISTER_NAMES): Add Q0-Q15. * config/arm/aout.h (ADDITIONAL_REGISTER_NAMES): Add Q0-Q15. * config/arm/arm-modes.def (EI, OI, CI, XI): New modes. * config/arm/arm-protos.h (neon_immediate_valid_for_move) (neon_immediate_valid_for_logic, neon_output_logic_immediate) (neon_pairwise_reduce, neon_expand_vector_init, neon_reinterpret) (neon_emit_pair_result_insn, neon_disambiguate_copy) (neon_vector_mem_operand, neon_struct_mem_operand, output_move_quad) (output_move_neon): Add prototypes. * config/arm/arm.c (FL_NEON): New flag for NEON processor capability. (all_fpus): Add FPUTYPE_NEON. (fp_model_for_fpu): Add NEON field. (arm_return_in_memory): Return vectors <= 16 bytes in ARM registers. (arm_arg_partial_bytes): Allow NEON vectors to be passed partially in registers. (arm_legitimate_address_p): Don't support fancy addressing for NEON structure moves. (thumb2_legitimate_address_p): Likewise. (neon_valid_immediate): Recognize and prepare constants suitable for NEON instructions. (neon_immediate_valid_for_move): New function. Recognize and prepare immediates for NEON move instructions. (neon_immediate_valid_for_logic): New function. Recognize and prepare immediates for NEON logic instructions. (neon_output_logic_immediate): New function. Create asm string suitable for outputting immediate logic instructions. (neon_pairwise_reduce): New function. Implement reduction using pairwise operations. (neon_expand_vector_init): New function. Expand a (possibly non-constant) vector initialization. (neon_vector_mem_operand): New function. Memory operands supported for quad-word loads/stores to/from ARM or NEON registers. Don't allow base+offset addressing for core regs. (neon_struct_mem_operand): New function. Valid mems for NEON structure moves. (coproc_secondary_reload_class): Enable NEON registers to be loaded from neon_vector_mem_operand addresses without a secondary register. (add_minipool_forward_ref): Handle >8-byte minipool entries. (add_minipool_backward_ref): Likewise. (dump_minipool): Likewise. (push_minipool_fix): Likewise. (output_move_quad): New function. Output quad-word moves, loads and stores using ARM registers. (output_move_vfp): Add support for vectors in VFP (NEON) D registers. (output_move_neon): Output a NEON load/store to/from a quadword register. (arm_print_operand): Implement new codes: - 'c' for unadorned integers (without a # sign). - 'J', 'K' for reg+2/reg+3, reg+3/reg+2 in little/big-endian mode. - 'e', 'f' for the low and high D parts of a NEON Q register. - 'q' outputs a NEON Q register. - 'h' outputs ranges of D registers for VLDM/VSTM etc. - 'T' prints NEON opcode features from a coded bitmask. - 'F' is similar to T, but signed/unsigned codes both print as 'i'. - 't' is similar to T, but 'u' is printed instead of 'p'. - 'O' prints 'r' if NEON instruction should perform rounding (as specified by bitmask), else prints nothing. - '#' is a punctuation character to stop operand numbers from running together with following digits in the assembler strings for instructions (when using mode attributes). (arm_assemble_integer): Handle extra NEON vector modes. Permute constant vectors in big-endian mode, where necessary. (arm_hard_regno_mode_ok): Allow vectors in VFP/NEON registers. Handle EI, OI, CI, XI modes. (ashlv4hi3, ashlv2si3, lshrv4hi3, lshrv2si3, ashrv4hi3) (ashrv2si3): Rename IWMMXT2_BUILTINs to... (ashlv4hi3_iwmmxt, ashlv2si3_iwmmxt, lshrv4hi3_iwmmxt) (lshrv2si3_iwmmxt, ashrv4hi3_iwmmxt, ashrv2si3_iwmmxt): New names. (neon_builtin_type_bits): Add enumeration, one bit for each vector type. (v8qi_UP, v4hi_UP, v2si_UP, v2sf_UP, di_UP, v16qi_UP, v8hi_UP) (v4si_UP, v4sf_UP, v2di_UP, ti_UP, ei_UP, oi_UP, UP): Define macros to turn v8qi, etc. into bits defined above. (neon_itype): New enumeration. Classifications of NEON builtins. (neon_builtin_datum): Define struct. Contains information about a single builtin (with multiple modes). (CF): Define helper macro for... (VAR1...VAR10): Define builtins with a type, name and 1-10 different modes. (neon_builtin_data): New array. Define information about builtins for use during initialization/expansion. (arm_init_neon_builtins): New function. (arm_init_builtins): Call arm_init_neon_builtins if TARGET_NEON is true. (neon_builtin_compare): New function. (locate_neon_builtin_icode): New function. Find an insn code for a builtin given a function code for that builtin. Also return type of builtin (NEON_BINOP, NEON_UNOP etc.). (builtin_arg): New enumeration. Types of arguments for builtins. (arm_expand_neon_args): New function. Expand a generic NEON builtin. Takes a variable argument list of builtin_arg types, terminated by NEON_ARG_STOP. (arm_expand_neon_builtin): New function. Expand a NEON builtin. (neon_reinterpret): New function. Expand NEON reinterpret intrinsic. (neon_emit_pair_result_insn): New function. Support returning pairs of vectors via a pointer. (neon_disambiguate_copy): New function. Set up operands for a multi-word copy such that registers do not get clobbered. (arm_expand_builtin): Call arm_expand_neon_builtin if fcode >= ARM_BUILTIN_NEON_BASE. (arm_file_start): Set float-abi attribute for NEON. (arm_vector_mode_supported_p): Enable NEON vector modes. (arm_mangle_map_entry): New. (arm_mangle_map): New. (arm_mangle_vector_type): New. * config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define __ARM_NEON__ when appropriate. (TARGET_NEON): New macro. Target supports NEON. (fputype): Add FPUTYPE_NEON. (UNITS_PER_SIMD_WORD): Define. Allow quad-word registers to be used for vectorization based on command-line arg. (NEON_REGNO_OK_FOR_NREGS): Define. (VALID_NEON_DREG_MODE, VALID_NEON_QREG_MODE) (VALID_NEON_STRUCT_MODE): Define. (PRINT_OPERAND_PUNCT_VALID_P): '#' is valid punctuation. (arm_builtins): Add ARM_BUILTIN_NEON_BASE. * config/arm/arm.md (VUNSPEC_POOL_16): Insert constant for unspec. (consttable_16): Add pattern for outputting 16-byte minipool entries. (movv2si, movv4hi, movv8qi): Remove blank expanders (redefined in vec-common.md). (vec-common.md, neon.md): Include md files. * config/arm/arm.opt (mvectorize-with-neon-quad): Add option. * config/arm/constraints.md (constraint "Dn", "Dl", "DL"): Define. (memory_constraint "Ut", "Un", "Us"): Define. * config/arm/iwmmxt.md (VMMX, VSHFT): New mode macros. (MMX_char): New mode attribute. (addv8qi3, addv4hi3, addv2si3): Remove. Replace with... (*add<mode>3_iwmmxt): New insn pattern. (subv8qi3, subv4hi3, subv2si3): Remove. Replace with... (*sub<mode>3_iwmmxt): New insn pattern. (mulv4hi3): Rename to... (*mulv4hi3_iwmmxt): This. (smaxv8qi3, smaxv4hi3, smaxv2si3, umaxv8qi3, umaxv4hi3) (umaxv2si3, sminv8qi3, sminv4hi3, sminv2si3, uminv8qi3) (uminv4hi3, uminv2si3): Remove. Replace with... (*smax<mode>3_iwmmxt, *umax<mode>3_iwmmxt, *smin<mode>3_iwmmxt) (*umin<mode>3_iwmmxt): These. (ashrv4hi3, ashrv2si3, ashrdi3_iwmmxt): Replace with... (ashr<mode>3_iwmmxt): This new pattern. (lshrv4hi3, lshrv2si3, lshrdi3_iwmmxt): Replace with... (lshr<mode>3_iwmmxt): This new pattern. (ashlv4hi3, ashlv2si3, ashldi3_iwmmxt): Replace with... (ashl<mode>3_iwmmxt): This new pattern. * config/arm/neon-docgen.ml: New file. Generate documentation for intrinsics. * config/arm/neon-gen.ml: New file. Generate arm_neon.h header. * config/arm/arm_neon.h: New (autogenerated). * config/arm/neon-testgen.ml: New file. Generate NEON tests automatically. * config/arm/neon.md: New file. Define NEON instructions. * config/arm/neon.ml: New file. Abstract description of NEON instructions, used to generate arm_neon.h header, documentation and tests. * config/arm/t-arm (MD_INCLUDES): Add vec-common.md, neon.md. * vec-common.md: New file. Shared parts for iWMMXt and NEON vector support. * doc/extend.texi (ARM Built-in Functions): Rename and remove extraneous comma. (ARM NEON Intrinsics): New subsection. * doc/arm-neon-intrinsics.texi: New (autogenerated). gcc/testsuite/ * gcc.dg/vect/vect.exp: Check is-effective-target arm_neon_hw. * gcc.dg/vect/tree-vect.h: Check for NEON SIMD support. * lib/gcc-dg.exp (cleanup-saved-temps): Fix comment. * lib/target-supports.exp (check_effective_target_arm_neon_ok) (check_effective_target_arm_neon_hw): New. * gcc.target/arm/neon/neon.exp: New file. * gcc.target/arm/neon/polytypes.c: New file. * gcc.target/arm/neon/v*.c (1870 files): New (autogenerated). Co-Authored-By: Joseph Myers <joseph@codesourcery.com> Co-Authored-By: Mark Shinwell <shinwell@codesourcery.com> Co-Authored-By: Paul Brook <paul@codesourcery.com> From-SVN: r126911
* * config/i386/i386-protos.h (i386_pe_asm_file_end): Remove prototype.Danny Smith2007-07-251-1/+0
| | | | From-SVN: r126905
* darwin.c (darwin_override_options): Don't force on flag_var_tracking_uninit ↵Daniel Berlin2007-07-251-1/+2
| | | | | | | | | | | when no debug info is requested. 2007-07-24 Daniel Berlin <dberlin@dberlin.org> * config/darwin.c (darwin_override_options): Don't force on flag_var_tracking_uninit when no debug info is requested. From-SVN: r126900
* 2007-07-24 Dorit Nuzman <dorit@il.ibm.com>Dorit Nuzman2007-07-241-0/+18
| | | | | | | | | | | | | * lib/target-support.exp (check_effective_target_natural_alignment): (check_effective_target_vector_alignment_reachable): New. * config/spu/spu.c (spu_vector_alignment_reachable): New. (TARGET_VECTOR_ALIGNMENT_REACHABLE): Define. * * gcc.dg/vect/pr25413a.c: Use vector_alignment_reachable target check. * gcc.dg/vect/pr25413.c: Likewise. * gcc.dg/vect/pr31699.c: Likewise. From-SVN: r126872
* i386.c (ix86_secondary_memory_needed): Break out to...Jan Hubicka2007-07-231-97/+151
| | | | | | | | | | | * i386.c (ix86_secondary_memory_needed): Break out to... (inline_secondary_memory_needed): ... here. (ix86_memory_move_cost): Break out to ... (inline_memory_move_cost): ... here; add support for IN value of 2 for maximum of input and output; fix handling of Q_REGS on 64bit. (ix86_secondary_memory_needed): Microoptimize. From-SVN: r126861
* mips.c (override_options): Use mips_costs to derive the default branch cost.Richard Sandiford2007-07-233-1/+10
| | | | | | | | | | | | | | | | gcc/ * config/mips/mips.c (override_options): Use mips_costs to derive the default branch cost. * config/mips/mips.h (BRANCH_COST): Use mips_branch_cost rather than mips_costs. * config/mips/mips.opt (mbranch-cost=): New option. * doc/invoke.texi (-mbrach-cost): Document new MIPS option. gcc/testsuite/ * gcc.target/mips/branch-cost-1.c: New test. * gcc.target/mips/branch-cost-2.c: Likewise. From-SVN: r126846
* mips.h (GR_REG_CLASS_P, [...]): Delete.Richard Sandiford2007-07-232-38/+9
| | | | | | | | | | gcc/ * config/mips/mips.h (GR_REG_CLASS_P, COP_REG_CLASS_P): Delete. (SECONDARY_MEMORY_NEEDED): Delete commented-out definition. * config/mips/mips.c (mips_init_libfuncs): Use reg_class_subset_p instead of GR_REG_CLASS_P and COP_REG_CLASS_P. From-SVN: r126844
* constraints.md (ks): New constraint.Richard Sandiford2007-07-232-33/+19
| | | | | | | | | gcc/ * config/mips/constraints.md (ks): New constraint. * config/mips/mips.md (*add<mode>3_sp1, *add<mode>3_sp2): Fold into... (*add<mode>3_mips16): ...here and fix their length calculations. From-SVN: r126842
* optabs.h (enum optab_index): Add new OTI_signbit.Uros Bizjak2007-07-211-2/+15
| | | | | | | | | | | | | | | | | | | * optabs.h (enum optab_index): Add new OTI_signbit. (signbit_optab): Define corresponding macro. (enum insn_code signbit_optab[]): Remove array. * optabs.c (init_optabs): Initialize signbit_optab using init_optab. (expand_copysign_absneg): If back end provides signbit insn, use it instead of bit operations on floating point argument. * builtins.c (enum insn_code signbit_optab[]): Remove array. (expand_builtin_signbit): Check signbit_optab->handlers[].insn_code for availability of signbit insn. * config/i386/i386.md (signbit<mode>2): New insn pattern to implement signbitf, signbit and signbitl built-ins as inline x87 intrinsics when SSE mode is not active. (isinf<mode>2): Disable for mfpmath=sse,387. From-SVN: r126813
* mips.h (mips_dwarf_regno): Declare.Nigel Stephens2007-07-204-50/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc/ 2007-07-20 Nigel Stephens <nigel@mips.com> Richard Sandiford <richard@codesourcery.com> * config/mips/mips.h (mips_dwarf_regno): Declare. (DBX_REGISTER_NUMBER): Remove redundant brackets. (HI_REGNUM, LO_REGNUM): Define in an endian-dependent way. (AC1HI_REGNUM, AC1LO_REGNUM, AC2HI_REGNUM, AC2LO_REGNUM) (AC3HI_REGNUM, AC3LO_REGNUM, ACC_HI_REG_P): Delete. (reg_class): Rename HI_REG to MD0_REG and LO_REG to MD1_REG. (REG_CLASS_NAMES): Update accordingly. * config/mips/mips.c (mips_dwarf_regno): New array. (mips_regno_to_class): Rename HI_REG to MD0_REG and LO_REG to MD1_REG. (mips_subword): Remove special handling for accumulator registers. (override_options): Initiailize mips_dwarf_regno. Remove use of ACC_HI_REG_P. (mips_swap_registers): New function. (mips_conditional_register_usage): Swap accumulator registers around if TARGET_LITTLE_ENDIAN. (mips_cannot_change_mode_class): Remove special treatment of ACC_REGS. * config/mips/constraints.md (h, l): Use the endianness to choose between MD0_REG and MD1_REG. * config/mips/mips.md (*mfhilo_<mode>_macc): Use a fixed-string, alternative-dependent template. Co-Authored-By: Richard Sandiford <richard@codesourcery.com> From-SVN: r126801
* arm.md (movsi): Use can_create_pseudo_p instead of no_new_pseudos.Richard Sandiford2007-07-201-1/+1
| | | | | | | | gcc/ * config/arm/arm.md (movsi): Use can_create_pseudo_p instead of no_new_pseudos. From-SVN: r126798
* Makefile.in (D32PBIT_FUNCS): Add _sd_to_tf and _tf_to_sd.H.J. Lu2007-07-181-0/+9
| | | | | | | | | | | | 2007-07-18 H.J. Lu <hongjiu.lu@intel.com> * Makefile.in (D32PBIT_FUNCS): Add _sd_to_tf and _tf_to_sd. (D64PBIT_FUNCS): Add _dd_to_tf and _tf_to_dd. (D128PBIT_FUNCS): Add _td_to_tf and _tf_to_td. * config/dfp-bit.c: Empty for TFmode conversions. From-SVN: r126735
* xtensa-config.h (XCHAL_HAVE_THREADPTR): New.Bob Wilson2007-07-184-0/+390
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | include/ * xtensa-config.h (XCHAL_HAVE_THREADPTR): New. (XCHAL_HAVE_RELEASE_SYNC, XCHAL_HAVE_S32C1I): New. gcc/ * config/xtensa/xtensa.c (xtensa_expand_mask_and_shift): New. (struct alignment_context, init_alignment_context): New. (xtensa_expand_compare_and_swap, xtensa_expand_atomic): New. * config/xtensa/xtensa.h (XCHAL_HAVE_RELEASE_SYNC): Add default. (XCHAL_HAVE_S32C1I): Likewise. (TARGET_RELEASE_SYNC, TARGET_S32C1I): New. * config/xtensa/xtensa.md (UNSPECV_MEMW): New constant. (UNSPECV_S32RI, UNSPECV_S32C1I): Likewise. (ATOMIC, HQI): New macros. (memory_barrier, *memory_barrier): New. (sync_lock_releasesi): New. (sync_compare_and_swapsi, sync_compare_and_swap<mode>): New. (sync_lock_test_and_set<mode>): New. (sync_<atomic><mode>): New. (sync_old_<atomic><mode>, sync_new_<atomic><mode>): New. * config/xtensa/xtensa-protos.h (xtensa_expand_compare_and_swap): New. (xtensa_expand_atomic): New. gcc/testsuite/ * lib/target-supports.exp (check_effective_target_sync_int_long): Enable for xtensa. (check_effective_target_sync_char_short): Likewise. From-SVN: r126728
* re PR target/32808 (cris: ICE: RTL check: expected elt 0 type 'e' or 'u', ↵Rask Ingemann Lambertsen2007-07-181-3/+3
| | | | | | | | | | have 'w' (rtx const_int) in cris_print_index, at config/cris/cris.c:499) PR target/32808 * config/cris/cris.c (cris_print_index): Don't use XEXP before checking that the operand is an expression. From-SVN: r126720
* PR/other 30335Christoph von Wittich2007-07-181-13/+30
| | | | | | | | | | | | | | | 2007-07-19 Christoph von Wittich <Christoph_vW@reactos.org> Danny Smith <dannysmith@users.sourceforge.net> PR/other 30335 * config/i386/host-mingw32.c (mingw32_gt_pch_use_address): Put file mapping object in local namespace if Windows version later than NT4 Co-Authored-By: Danny Smith <dannysmith@users.sourceforge.net> From-SVN: r126719
* arm-protos.h (arm_cannot_force_const_mem): Declare.Richard Sandiford2007-07-185-2/+47
| | | | | | | | | | | | | | | | gcc/ * config/arm/arm-protos.h (arm_cannot_force_const_mem): Declare. * config/arm/arm.c (TARGET_CANNOT_FORCE_CONST_MEM): Redefine to arm_cannot_force_const_mem. (arm_cannot_force_const_mem): New function. * config/arm/arm.h (ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P): New macro. (LEGITIMATE_CONSTANT_P): Test arm_cannot_force_const_mem instead of arm_tls_referenced_p. * config/arm/arm.md (movsi): Split out-of-section constants when ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P. * config/arm/vxworks.h (ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P): Define. From-SVN: r126718
* mips.md (clear_cache): Treat the size argument as Pmode.Richard Sandiford2007-07-181-2/+1
| | | | | | | gcc/ * config/mips/mips.md (clear_cache): Treat the size argument as Pmode. From-SVN: r126717
* mips.md (*extendqihi2): Convert the destination to SImode.Richard Sandiford2007-07-181-0/+1
| | | | | | | | gcc/ * config/mips/mips.md (*extendqihi2): Convert the destination to SImode. From-SVN: r126716
* fptr.c: Update license header.John David Anglin2007-07-172-21/+49
| | | | | | | * config/pa/fptr.c: Update license header. * config/pa/milli64.S: Likewise. From-SVN: r126705
* mips.h (TUNE_24K): Define.Sandra Loosemore2007-07-164-8/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | 2007-07-16 Sandra Loosemore <sandra@codesourcery.com> David Ung <davidu@mips.com> gcc/ * config/mips/mips.h (TUNE_24K): Define. (TUNE_MACC_CHAINS): Add TUNE_24K. * config/mips/mips.md: (*mul_acc_si, *mul_sub_si): Change type to imadd. * config/mips/74k.md (r74k_int_mult): Split madd/msub to .. (r74k_int_madd): .. this new reservation. (define_bypass): Fixed bypasses for r74k_int_madd to use mips_linked_madd_p. * config/mips/24k.md (define_bypass): Define new r24k_int_mul3->r24k_int_madd bypass using mips_linked_madd_p. gcc/testsuite/ * gcc.target/mips/mips-sched-madd.c: New test case. Co-Authored-By: David Ung <davidu@mips.com> From-SVN: r126688
* mips.md: Include 20kc.md.Sandra Loosemore2007-07-164-2/+285
| | | | | | | | | | | | | | | | | | 2007-07-16 Sandra Loosemore <sandra@codesourcery.com> Nigel Stephens <nigel@mips.com> gcc/ * config/mips/mips.md: Include 20kc.md. * config/mips/20kc.md: New file. * config/mips/mips.c (mips_rtx_cost_data): Fill in 20Kc costs. (mips_adjust_cost): Tweak for 20Kc. (mips_issue_rate): Likewise. * config/mips/mips.h (TUNE_20KC): Define. Co-Authored-By: Nigel Stephens <nigel@mips.com> From-SVN: r126687
* rs6000.c (struct processor cost): Add cache_line_size, l1_cache_lines, and ↵David Edelsohn2007-07-161-0/+75
| | | | | | | | | | | | simultaneous_prefetches fields. * config/rs6000/rs6000.c (struct processor cost): Add cache_line_size, l1_cache_lines, and simultaneous_prefetches fields. (*_cost): Add cache information. (rs6000_override_options): Set cache parameters. From-SVN: r126686
* re PR target/32753 (building a crosscompiler for arm-elf fails because of an ↵Paul Brook2007-07-161-25/+0
| | | | | | | | | | | | | error in cirrus.md) 2007-07-16 Paul Brook <paul@codesourcery.com> PR target/32753 gcc/ * config/arm/cirrus.md (cirrus_arm_movsi_insn): Remove dead insn. (cirrus_thumb2_movsi_insn): Ditto. From-SVN: r126681
* re PR target/32753 (building a crosscompiler for arm-elf fails because of an ↵Paul Brook2007-07-161-22/+0
| | | | | | | | | | | | error in cirrus.md) 2007-07-16 Paul Brook <paul@codesourcery.com> PR target/32753 gcc/ * config/arm/cirrus.md (cirrus_arm_movsi_insn): Remove dead insn. From-SVN: r126679
* darwin-fallback.c (interpret_libc): Change CR2_REGNO to R_CR2.Geoffrey Keating2007-07-151-1/+1
| | | | | | | * config/rs6000/darwin-fallback.c (interpret_libc): Change CR2_REGNO to R_CR2. From-SVN: r126661
* re PR middle-end/32398 (checking for suffix of object files... configure: ↵John David Anglin2007-07-153-10/+49
| | | | | | | | | | | | | | | | | | error: cannot compute suffix of f object files: cannot compile) PR middle-end/32398 PR middle-end/32769 * pa-protos.h (pa_eh_return_handler_rtx): Declare. * pa.c (pa_extra_live_on_entry, rp_saved): Declare. (TARGET_EXTRA_LIVE_ON_ENTRY): Define. (pa_output_function_prologue): Use rp_saved and current_function_is_leaf to generate .CALLINFO statement. (hppa_expand_prologue): Set rp_saved. (hppa_expand_epilogue): Use rp_saved. (pa_extra_live_on_entry, pa_eh_return_handler_rtx): New functions. * pa.h (EH_RETURN_HANDLER_RTX): Use pa_eh_return_handler_rtx. From-SVN: r126657
* sh.h (DO_GLOBAL_CTORS_BODY): Add void to prototype.Kaz Kojima2007-07-141-2/+2
| | | | | | | * config/sh/sh.h (DO_GLOBAL_CTORS_BODY): Add void to prototype. (DO_GLOBAL_DTORS_BODY): Likewise. From-SVN: r126645
* mips.c (mips_classify_symbol): Don't return SYMBOL_SMALL_DATA for constant ↵Sandra Loosemore2007-07-141-1/+2
| | | | | | | | | | | | | | | | pool addresses if... 2007-07-14 Sandra Loosemore <sandra@codesourcery.com> Nigel Stephens <nigel@mips.com> gcc/ * config/mips/mips.c (mips_classify_symbol): Don't return SYMBOL_SMALL_DATA for constant pool addresses if TARGET_EMBEDDED_DATA is true. Co-Authored-By: Nigel Stephens <nigel@mips.com> From-SVN: r126643
* * config/i386/i386.c: Fix fallout from my previous commit.Uros Bizjak2007-07-141-1/+1
| | | | From-SVN: r126640
* i386.c (init_mmx_sse_builtins): Define all builtins except ↵Uros Bizjak2007-07-141-122/+122
| | | | | | | | | | | | | | | | | | | | | __builtin_ia32_emms... * config/i386/i386.c (init_mmx_sse_builtins): Define all builtins except __builtin_ia32_emms, __builtin_ia32_ldmxcsr, __builtin_ia32_stmxcsr, __builtin_ia32_maskmovq, __builtin_ia32_loadups, __builtin_ia32_storeups, __builtin_ia32_loadhps, __builtin_ia32_loadlps, __builtin_ia32_storehps, __builtin_ia32_storelps, __builtin_ia32_movntps, __builtin_ia32_movntq, __builtin_ia32_sfence, __builtin_ia32_femms, __builtin_ia32_maskmovdqu, __builtin_ia32_loadupd, __builtin_ia32_storeupd, __builtin_ia32_loadhpd, __builtin_ia32_loadlpd, __builtin_ia32_movnti, __builtin_ia32_movntpd, __builtin_ia32_movntdq, __builtin_ia32_clflush, __builtin_ia32_lfence, __builtin_ia32_mfence, __builtin_ia32_loaddqu, __builtin_ia32_storedqu, __builtin_ia32_monitor, __builtin_ia32_mwait, __builtin_ia32_lddqu, __builtin_ia32_movntdqa, __builtin_ia32_movntsd and __builtin_ia32_movntss as const builtins using def_builtin_const. From-SVN: r126639
* spe.md (SPE_ACC_REGNO): Delete definition.David Edelsohn2007-07-138-138/+160
| | | | | | | | | | | | | | | | | | | | * config/rs6000/spe.md (SPE_ACC_REGNO): Delete definition. (SPEFSCR_REGNO): Delete definition. * config/rs6000/rs6000.c: LINK_REGISTER_REGNUM -> LR_REGNO. COUNT_REGISTER_REGNUM -> CTR_REGNO. * config/rs6000/rs6000.h: Do not define *_REGNO. LINK_REGISTER_REGNUM -> LR_REGNO. COUNT_REGISTER_REGNUM -> CTR_REGNO. * config/rs6000/predicates.md: LINK_REGISTER_REGNUM -> LR_REGNO. COUNT_REGISTER_REGNUM -> CTR_REGNO. * config/rs6000/linux-unwind.h: Define R_LR, R_CR2, R_VR0, R_VRSAVE, R_VSCR. Use them. * config/rs6000/darwin-fallback.c: Define R_LR, R_CTR, R_CR2, R_XER, R_VR0, R_VRSAVE, R_VSCR, R_SPEFSCR. Use them. * config/rs6000/rs6000.md: Define REGNO constants. Use them. * config/rs6000/aix.h: Define R_LR. Use it. From-SVN: r126631
* Add ability to track uninitialized variables, and mark uninitialized ↵Caroline Tice2007-07-131-0/+3
| | | | | | | | | | variables in the Dwarf debug info. Add ability to track uninitialized variables, and mark uninitialized variables in the Dwarf debug info. Controlled by compile option -fvar-tracking-uninit From-SVN: r126630
* config.gcc: Add options for arch and tune on SPU.Sa Liu2007-07-1310-61/+996
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2007-07-13 Sa Liu <saliu@de.ibm.com> * config.gcc: Add options for arch and tune on SPU. * config/spu/predicates.md: Add constant operands 0 and 1. * config/spu/spu-builtins.def: Add builtins for double precision floating point comparison: si_dfceq, si_dfcmeq, si_dfcgt, si_dfcmgt, si_dftsv, spu_cmpeq_13, spu_cmpabseq_1, spu_cmpgt_13, spu_cmpabsgt_1, spu_testsv. * config/spu/spu-c.c: Define __SPU_EDP__ when builtins invoked with a CELLEDP target. * config/spu/spu-protos.h: Add new function prototypes. * config/spu/spu.c (spu_override_options): Check options -march and -mtune. (spu_comp_icode): Add comparison code for DFmode and vector mode. (spu_emit_branch_or_set): Use the new code for DFmode and vector mode comparison. (spu_const_from_int): New. Create a vector constant from 4 ints. (get_vec_cmp_insn): New. Get insn index of vector compare instruction. (spu_emit_vector_compare): New. Emit vector compare. (spu_emit_vector_cond_expr): New. Emit vector conditional expression. * config/spu/spu.h: Add options -march and -mtune. Define processor types PROCESSOR_CELL and PROCESSOR_CELLEDP. Define macro CANONICALIZE_COMPARISON. * config/spu/spu.md: Add new insns for double precision compare and double precision vector compare. Add vcond and smax/smin patterns to enable DFmode vector conditional expression. * config/spu/spu.opt: Add options -march and -mtune. * config/spu/spu_internals.h: Add builtins for CELLEDP target: si_dfceq, si_dfcmeq, si_dfcgt, si_dfcmgt, si_dftsv. Add builtin for both CELL and CELLEDP targets: spu_testsv. * config/spu/spu_intrinsics.h: Add flag mnemonics for test special values. testsuite/ * gcc.dg/vect/fast-math-vect-reduc-7.c: Switch on test for V2DFmode vector conditional expression. * gcc.target/spu/dfcmeq.c: New. Test combination of abs and dfceq patterns. * gcc.target/spu/dfcmgt.c: New. Test combination of abs and dfcgt patterns. * gcc.target/spu/intrinsics-2.c: New. Test intrinsics for V2DFmode comparison and test special values. * lib/target-supports.exp: Switch on test for V2DFmode vector conditional expression. From-SVN: r126626
* linux-unwind.h (sh_fallback_frame_state): Use correct index when setting ↵Kaz Kojima2007-07-131-3/+3
| | | | | | | | | | register save state for xd registers. * config/sh/linux-unwind.h (sh_fallback_frame_state): Use correct index when setting register save state for xd registers. From-SVN: r126612
* sh.c (mark_use): Remove.Kaz Kojima2007-07-131-81/+0
| | | | | | * config/sh/sh.c (mark_use): Remove. From-SVN: r126611
* arm.c (thumb1_compute_save_reg_mask): Make sure scratch reg does not overlap ↵Paul Brook2007-07-121-0/+4
| | | | | | | | | | | | return value. 2007-07-12 Paul Brook <paul@codesourcery.com> gcc/ * config/arm/arm.c (thumb1_compute_save_reg_mask): Make sure scratch reg does not overlap return value. From-SVN: r126604
* sse.md (storentdf, storentsf): New.Zdenek Dvorak2007-07-121-0/+14
| | | | | | * config/i386/sse.md (storentdf, storentsf): New. From-SVN: r126594
* re PR target/25413 (wrong alignment or incorrect address computation in ↵Dorit Nuzman2007-07-121-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | vectorized code on Pentium 4 SSE) 2007-07-12 Dorit Nuzman <dorit@il.ibm.com> Devang Patel <dpatel@apple.com> PR tree-optimization/25413 * targhooks.c (default_builtin_vector_alignment_reachable): New. * targhooks.h (default_builtin_vector_alignment_reachable): New. * tree.h (contains_packed_reference): New. * expr.c (contains_packed_reference): New. * tree-vect-analyze.c (vector_alignment_reachable_p): New. (vect_enhance_data_refs_alignment): Call vector_alignment_reachable_p. * target.h (vector_alignment_reachable): New builtin. * target-def.h (TARGET_VECTOR_ALIGNMENT_REACHABLE): New. * config/rs6000/rs6000.c (rs6000_vector_alignment_reachable): New. (TARGET_VECTOR_ALIGNMENT_REACHABLE): Define. Co-Authored-By: Devang Patel <dpatel@apple.com> From-SVN: r126591
* target.h (builtin_vectorization_cost): Add new target builtin.Dorit Nuzman2007-07-122-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2007-07-12 Dorit Nuzman <dorit@il.ibm.com> * target.h (builtin_vectorization_cost): Add new target builtin. * target-def.h (TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST): New. * tree-vectorizer.h (TARG_SCALAR_STMT_COST): New. (TARG_SCALAR_LOAD_COST, TARG_SCALAR_STORE_COST): New. * tree-vect-analyze.c (vect_analyze_slp_instance): Initisliaze uninitialized variables. * tree-vect-transform.c (cost_for_stmt): New function. (vect_estimate_min_profitable_iters): Call cost_for_stmt instead of using cost 1 for all scalar stmts. Be less conservative when estimating the number of prologue/epulogue iterations. Call targetm.vectorize.builtin_vectorization_cost. Return min_profitable_iters-1. (vect_model_reduction_cost): Use TARG_SCALAR_TO_VEC_COST for initialization cost instead of TARG_VEC_STMT_COST. Use TARG_VEC_TO_SCALAR_COST instead of TARG_VEC_STMT_COST for reduction epilogue code. Fix epilogue cost computation. * config/spu/spu.c (spu_builtin_vectorization_cost): New. (TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST): Implement. * config/spu/spu.h (TARG_COND_BRANCH_COST, TARG_SCALAR_STMT_COST): (TARG_SCALAR_LOAD_COST, TARG_SCALAR_STORE_COST, TARG_VEC_STMT_COST): (TARG_VEC_TO_SCALAR_COST, TARG_SCALAR_TO_VEC, TARG_VEC_LOAD_COST): (TARG_VEC_UNALIGNED_LOAD_COST, TARG_VEC_STORE_COST): Define. 2007-07-12 Dorit Nuzman <dorit@il.ibm.com> * gcc.dg/vect/costmodel/ppc/costmodel-vect-reduc-1char.c: Loops now get vectorized. * gcc.dg/vect/costmodel/i386/costmodel-vect-reduc-1char.c: Loops now get vectorized. * gcc.dg/vect/costmodel/spu/spu-costmodel-vect.exp: New. * gcc.dg/vect/costmodel/spu/costmodel-fast-math-vect-pr29925.c: New. * gcc.dg/vect/costmodel/spu/costmodel-vect-31a.c: New. * gcc.dg/vect/costmodel/spu/costmodel-vect-31b.c: New. * gcc.dg/vect/costmodel/spu/costmodel-vect-31c.c: New. * gcc.dg/vect/costmodel/spu/costmodel-vect-31d.c: New. * gcc.dg/vect/costmodel/spu/costmodel-vect-iv-9.c: New. * gcc.dg/vect/costmodel/spu/costmodel-vect-33.c: New. * gcc.dg/vect/costmodel/spu/costmodel-vect-76a.c: New. * gcc.dg/vect/costmodel/spu/costmodel-vect-76b.c: New. * gcc.dg/vect/costmodel/spu/costmodel-vect-76c.c: New. * gcc.dg/vect/costmodel/spu/costmodel-vect-68a.c: New. * gcc.dg/vect/costmodel/spu/costmodel-vect-68b.c: New. * gcc.dg/vect/costmodel/spu/costmodel-vect-68c.c: New. * gcc.dg/vect/costmodel/spu/costmodel-vect-68d.c: New. * lib/target-supports.exp (check_effective_target_vect_int_mul): Add spu. From-SVN: r126584
* sh.md (symGOTOFF2reg): Add missing parenthesis.Kaz Kojima2007-07-121-2/+2
| | | | | | | * config/sh/sh.md (symGOTOFF2reg): Add missing parenthesis. (symDTPOFF2reg): Likewise. From-SVN: r126571
* re PR target/32661 (__builtin_ia32_vec_ext suboptimal for pointer/ref args)Uros Bizjak2007-07-111-5/+26
| | | | | | | | | | | | | | PR target/32661 * config/i386/sse.md (*sse2_storeq_rex64): Handle 64bit mem->reg moves. (*vec_extractv2di_1_sse2): Disable for TARGET_64BIT. (*vec_extractv2di_1_rex64): New insn pattern. testsuite/ChangeLog: PR target/32661 * gcc.target/i386/pr32661-1.c: New test. From-SVN: r126557
* linux-unwind.h (mips_fallback_frame_state): Rewrite return address calculation.David Daney2007-07-112-13/+15
| | | | | | | | | | | * config/mips/linux-unwind.h (mips_fallback_frame_state): Rewrite return address calculation. Substitute DWARF_ALT_FRAME_RETURN_COLUMN for SIGNAL_UNWIND_RETURN_COLUMN. * config/mips/mips.h (SIGNAL_UNWIND_RETURN_COLUMN): Remove. (DWARF_FRAME_REGNUM): Rewrite. (DWARF_ALT_FRAME_RETURN_COLUMN) Define. From-SVN: r126555
* * config/m32r/m32r.h (INITIALIZE_TRAMPOLINE): Revert previous delta and use ↵Nick Clifton2007-07-111-44/+12
| | | | | | gen_int_mode in place of GET_INT instead. From-SVN: r126552
* spu.c (spu_optimization_options): Remove setting of parameter ↵Ulrich Weigand2007-07-111-5/+6
| | | | | | | | | | PARAM_MAX_COMPLETELY_PEEL_TIMES. * config/spu/spu.c (spu_optimization_options): Remove setting of parameter PARAM_MAX_COMPLETELY_PEEL_TIMES. (spu_override_options): Move it here. From-SVN: r126549
* mips.h (MIPS_ISA_LEVEL_SPEC): Handle -m4ksc and -m4ksd.Richard Sandiford2007-07-112-3/+4
| | | | | | | | | | gcc/ * config/mips/mips.h (MIPS_ISA_LEVEL_SPEC): Handle -m4ksc and -m4ksd. * config/mips/mips.c (mips_cpu_info_table): Mention MIPS_ISA_LEVEL_SPEC in the comment. From-SVN: r126548
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