From 30405ccc143bb4b63476a329800244826a88faf3 Mon Sep 17 00:00:00 2001
From: Roger Sayle <roger@nextmovesoftware.com>
Date: Wed, 18 May 2022 16:13:17 +0100
Subject: Avoid andn and generate shorter not;and with -Oz on x86.

The x86 instruction encoding for SImode andn is longer than the
equivalent notl/andl sequence when the source for the not operand
is the same register as the destination.  This patch adds post_reload
splitters to i386.md to avoid "-mbmi" (which enables andn) increasing
code size with "-Oz".

One minor subtlety with this patch is that the splitter for
*andn_si_ccno swaps the order of operands (match_dup 2 and match_dup 3)
as memory operands need to appear first in *test<mode>_1 patterns.

2022-05-18  Roger Sayle  <roger@nextmovesoftware.com>

gcc/ChangeLog
	* config/i386/i386.md (define_split):  Split *andsi_1
	and *andn_si_ccno after reload with -Oz.

gcc/testsuite/ChangeLog
	* gcc.target/i386/bmi-andn-3.c: New test case.
---
 gcc/config/i386/i386.md                    | 34 ++++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/i386/bmi-andn-3.c | 15 +++++++++++++
 2 files changed, 49 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/i386/bmi-andn-3.c

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 80fc6c903eb..792bae15f58 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -10417,6 +10417,40 @@
   [(set_attr "type" "bitmanip")
    (set_attr "btver2_decode" "direct, double")
    (set_attr "mode" "<MODE>")])
+
+;; Split *andnsi_1 after reload with -Oz when not;and is shorter.
+(define_split
+  [(set (match_operand:SI 0 "register_operand")
+	(and:SI (not:SI (match_operand:SI 1 "register_operand"))
+		(match_operand:SI 2 "nonimmediate_operand")))
+   (clobber (reg:CC FLAGS_REG))]
+  "reload_completed
+   && optimize_insn_for_size_p () && optimize_size > 1
+   && REGNO (operands[0]) == REGNO (operands[1])
+   && LEGACY_INT_REG_P (operands[0])
+   && !REX_INT_REG_P (operands[2])
+   && !reg_overlap_mentioned_p (operands[0], operands[2])"
+  [(set (match_dup 0) (not:SI (match_dup 1)))
+   (parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 2)))
+	      (clobber (reg:CC FLAGS_REG))])])
+
+;; Split *andn_si_ccno with -Oz when not;test is shorter.
+(define_split
+  [(set (match_operand 0 "flags_reg_operand")
+	(match_operator 1 "compare_operator"
+	  [(and:SI (not:SI (match_operand:SI 2 "general_reg_operand"))
+		   (match_operand:SI 3 "nonimmediate_operand"))
+	   (const_int 0)]))
+   (clobber (match_dup 2))]
+  "reload_completed
+   && optimize_insn_for_size_p () && optimize_size > 1
+   && LEGACY_INT_REG_P (operands[2])
+   && !REX_INT_REG_P (operands[3])
+   && !reg_overlap_mentioned_p (operands[2], operands[3])"
+  [(set (match_dup 2) (not:SI (match_dup 2)))
+   (set (match_dup 0) (match_op_dup 1
+                        [(and:SI (match_dup 3) (match_dup 2))
+			 (const_int 0)]))])
 
 ;; Logical inclusive and exclusive OR instructions
 
diff --git a/gcc/testsuite/gcc.target/i386/bmi-andn-3.c b/gcc/testsuite/gcc.target/i386/bmi-andn-3.c
new file mode 100644
index 00000000000..16993a3037a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/bmi-andn-3.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-Oz -mbmi" } */
+int m;
+
+int foo(int x, int y)
+{
+  return (x & ~y) != 0;
+}
+
+int bar(int x)
+{
+  return (~x & m) != 0;
+}
+/* { dg-final { scan-assembler-not "andn\[ \\t\]+" } } */
+
-- 
cgit v1.2.1