From 03248b193e6bac947221d44cc4dff913183cb5ae Mon Sep 17 00:00:00 2001
From: bstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Thu, 20 Nov 2008 08:41:32 +0000
Subject: 2008-11-20  Basile Starynkevitch  <basile@starynkevitch.net> 	MELT
 branch merged with trunk r142033

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/melt-branch@142036 138bc75d-0d04-0410-961f-82ee72b054a4
---
 gcc/config/mips/loongson.md | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

(limited to 'gcc/config/mips/loongson.md')

diff --git a/gcc/config/mips/loongson.md b/gcc/config/mips/loongson.md
index 98b5113fbb5..8cdb5f466e9 100644
--- a/gcc/config/mips/loongson.md
+++ b/gcc/config/mips/loongson.md
@@ -473,3 +473,23 @@
   "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
   "punpckl<V_stretch_half_suffix>\t%0,%1,%2"
   [(set_attr "type" "fdiv")])
+
+;; Integer division and modulus.
+
+(define_insn "<u>div<mode>3"
+  [(set (match_operand:GPR 0 "register_operand" "=&d")
+	(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
+		     (match_operand:GPR 2 "register_operand" "d")))]
+  "TARGET_LOONGSON_2EF"
+  { return mips_output_division ("<d>div<u>.g\t%0,%1,%2", operands); }
+  [(set_attr "type" "idiv3")
+   (set_attr "mode" "<MODE>")])
+
+(define_insn "<u>mod<mode>3"
+  [(set (match_operand:GPR 0 "register_operand" "=&d")
+	(any_mod:GPR (match_operand:GPR 1 "register_operand" "d")
+		     (match_operand:GPR 2 "register_operand" "d")))]
+  "TARGET_LOONGSON_2EF"
+  { return mips_output_division ("<d>mod<u>.g\t%0,%1,%2", operands); }
+  [(set_attr "type" "idiv3")
+   (set_attr "mode" "<MODE>")])
-- 
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