From dc48ad1b698c6dba25276c4b030f1d94c28a5154 Mon Sep 17 00:00:00 2001 From: iverbin Date: Mon, 24 Nov 2014 12:00:54 +0000 Subject: 2014-11-24 Petr Murzin gcc/ * simplify-rtx.c (simplify_ternary_operation): Simplify vec_merge (vec_duplicate (vec_select)). gcc/testsuite/ * gcc.target/i386/extract-insert-combining.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218015 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/simplify-rtx.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'gcc/simplify-rtx.c') diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c index 98d4cebf94f..055ba787ac6 100644 --- a/gcc/simplify-rtx.c +++ b/gcc/simplify-rtx.c @@ -5233,6 +5233,22 @@ simplify_ternary_operation (enum rtx_code code, machine_mode mode, op0, XEXP (op1, 0), op2); } } + + /* Replace (vec_merge (vec_duplicate (vec_select a parallel (i))) a 1 << i) + with a. */ + if (GET_CODE (op0) == VEC_DUPLICATE + && GET_CODE (XEXP (op0, 0)) == VEC_SELECT + && GET_CODE (XEXP (XEXP (op0, 0), 1)) == PARALLEL + && mode_nunits[GET_MODE (XEXP (op0, 0))] == 1) + { + tem = XVECEXP ((XEXP (XEXP (op0, 0), 1)), 0, 0); + if (CONST_INT_P (tem) && CONST_INT_P (op2)) + { + if (XEXP (XEXP (op0, 0), 0) == op1 + && UINTVAL (op2) == HOST_WIDE_INT_1U << UINTVAL (tem)) + return op1; + } + } } if (rtx_equal_p (op0, op1) -- cgit v1.2.1