summaryrefslogtreecommitdiff
path: root/gcc/config/mips/sr71k.md
blob: e669276557a894bbfea2ac67ee2846408ed8cd95 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
;; Copyright (C) 2002-2014 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.
;;
;; .........................
;;
;; DFA-based pipeline description for Sandcraft SR3 (MIPS64 based)
;;
;; The SR3 is described as:
;;     - nine-stage pipeline, insn buffering with out-of-order issue to
;;       multiple function units, with an average dispatch rate of 2
;;       insn.s per cycle (max 6 insns: 2 fpu, 4 cpu).
;;
;;  The details on this are scant except for a diagram in
;;  Chap. 6 of Rev. 1.0 SR3 Spec.
;;
;;  The model employed below is designed to closely approximate the
;;  published latencies. Emulation of out-of-order issue and the insn
;;  buffering is done via a VLIW dispatch style (with a packing of 6 insns);
;;  the function unit reservations restrictions (define_*_set) are
;;  contrived to support published timings.
;;
;; Reference:
;;   "SR3 Microprocessor Specification, System development information,"
;;   Revision 1.0, 13 December 2000.
;;
;;
;; Reservation model is based on:
;;   1) Figure 6-1, from the 1.0 specification.
;;   2) Chapter 19, from the 1.0 specification.
;;   3) following questions(Red Hat)/answers(Sandcraft):
;;     RH> From Section 19.1
;;     RH>      1) In terms of figure 6-1, are all the instructions in
;;     RH>         table 19-1 restricted
;;     RH>         to ALUx? When ALUx is not in use for an instruction in table;;     RH>          19-1 is
;;     RH>         it fully compatible with all insns that issue to ALUy?
;;
;;     Yes, all the instructions in Table 19-1 only go to ALUX, and all the
;;     instructions that can be issued to ALUY can also be issued to ALUX.
;;
;;
;;     RH> From Section 19.2
;;     RH>      2) Explain conditional moves execution path (in terms of
;;     RH>      figure 6-1)
;;
;;     Conditional move of integer registers (based on floating point condition
;;     codes or integer register value) go to ALUX or ALUY.
;;
;;     RH>      3) Explain floating point store execution path (in terms of
;;     RH>      figure 6-1)
;;
;;     Floating point stores go to Ld/St and go to MOV in the floating point
;;     pipeline.
;;
;;     Floating point loads go to Ld/St and go to LOAD in the floating point
;;     pipeline.
;;
;;     RH>      4) Explain branch on floating condition (in terms of figure 6-1);;
;;     Branch on floating condition go to BRU.
;;
;;     RH>      5) Is the column for single RECIP instruction latency correct?
;;     RH>      What about for RSQRT single and double?
;;
;;     The latency/repeat for RECIP and RSQRT are correct.
;;

;;
;; Use four automata to isolate long latency operations, and to
;; reduce the complexity of cpu+fpu, reducing space.
;;
(define_automaton "sr71_cpu, sr71_cpu1, sr71_cp1, sr71_cp2, sr71_fextra, sr71_imacc")

;;  feeders for CPU function units and feeders for fpu (CP1 interface)
(define_cpu_unit "sr_iss0,sr_iss1,sr_iss2,sr_iss3,sr_iss4,sr_iss5" "sr71_cpu")

;; CPU function units
(define_cpu_unit "ipu_bru"       "sr71_cpu1")
(define_cpu_unit "ipu_alux"      "sr71_cpu1")
(define_cpu_unit "ipu_aluy"      "sr71_cpu1")
(define_cpu_unit "ipu_ldst"      "sr71_cpu1")
(define_cpu_unit "ipu_macc_iter" "sr71_imacc")


;; Floating-point unit (Co-processor interface 1).
(define_cpu_unit "fpu_mov"          "sr71_cp1")
(define_cpu_unit "fpu_load"         "sr71_cp1")
(define_cpu_unit "fpu_fpu"          "sr71_cp2")

;; fictitous unit to track long float insns with separate automaton
(define_cpu_unit "fpu_iter"         "sr71_fextra")


;;
;; Define common execution path (reservation) combinations
;;

;;
(define_reservation "cpu_iss"         "sr_iss0|sr_iss1|sr_iss2|sr_iss3")

;; two cycles are used for instruction using the fpu as it runs
;; at half the clock speed of the cpu. By adding an extra cycle
;; to the issue units, the default/minimum "repeat" dispatch delay is
;; accounted for all insn.s
(define_reservation "cp1_iss"         "(sr_iss4*2)|(sr_iss5*2)")

(define_reservation "serial_dispatch" "sr_iss0+sr_iss1+sr_iss2+sr_iss3+sr_iss4+sr_iss5")

;; Simulate a 6 insn VLIW dispatch, 1 cycle in dispatch followed by
;; reservation of function unit.
(define_reservation "ri_insns"         "cpu_iss,(ipu_alux|ipu_aluy)")
(define_reservation "ri_mem"           "cpu_iss,ipu_ldst")
(define_reservation "ri_alux"          "cpu_iss,ipu_alux")
(define_reservation "ri_branch"        "cpu_iss,ipu_bru")

(define_reservation "rf_insn"          "cp1_iss,fpu_fpu")
(define_reservation "rf_ldmem"         "cp1_iss,fpu_load")

; simultaneous reservation of pseudo-unit keeps cp1 fpu tied
; up until long cycle insn is finished...
(define_reservation "rf_multi1"        "rf_insn+fpu_iter")

;;
;; The ordering of the instruction-execution-path/resource-usage
;; descriptions (also known as reservation RTL) is roughly ordered
;; based on the define attribute RTL for the "type" classification.
;; When modifying, remember that the first test that matches is the
;; reservation used!
;;


(define_insn_reservation "ir_sr70_unknown" 1
  (and (eq_attr "cpu" "sr71000")
       (eq_attr "type" "unknown,atomic,syncloop"))
  "serial_dispatch")


;; Assume prediction fails.
(define_insn_reservation "ir_sr70_branch" 6
  (and (eq_attr "cpu" "sr71000")
       (eq_attr "type" "branch,jump,call"))
  "ri_branch")

(define_insn_reservation "ir_sr70_load" 2
  (and (eq_attr "cpu" "sr71000")
       (eq_attr "type" "load"))
  "ri_mem")

(define_insn_reservation "ir_sr70_store" 1
  (and (eq_attr "cpu" "sr71000")
       (eq_attr "type" "store"))
  "ri_mem")


;;
;; float loads/stores flow through both cpu and cp1...
;;
(define_insn_reservation "ir_sr70_fload" 9
  (and (eq_attr "cpu" "sr71000")
       (eq_attr "type" "fpload,fpidxload"))
  "(cpu_iss+cp1_iss),(ri_mem+rf_ldmem)")

(define_insn_reservation "ir_sr70_fstore" 1
  (and (eq_attr "cpu" "sr71000")
       (eq_attr "type" "fpstore,fpidxstore"))
  "(cpu_iss+cp1_iss),(fpu_mov+ri_mem)")


;; This reservation is for conditional move based on integer
;; or floating point CC.
(define_insn_reservation "ir_sr70_condmove" 4
  (and (eq_attr "cpu" "sr71000")
       (eq_attr "type" "condmove"))
  "ri_insns")

;; Try to discriminate move-from-cp1 versus move-to-cp1 as latencies
;; are different. Like float load/store, these insns use multiple
;; resources simultaneously
(define_insn_reservation "ir_sr70_xfer_from" 6
  (and (eq_attr "cpu" "sr71000")
       (eq_attr "type" "mfc"))
  "(cpu_iss+cp1_iss),(fpu_mov+ri_mem)")

(define_insn_reservation "ir_sr70_xfer_to" 9
  (and (eq_attr "cpu" "sr71000")
       (eq_attr "type" "mtc"))
  "(cpu_iss+cp1_iss),(ri_mem+rf_ldmem)")

(define_insn_reservation "ir_sr70_hilo" 1
  (and (eq_attr "cpu" "sr71000")
       (eq_attr "type" "mthi,mtlo,mfhi,mflo"))
  "ri_insns")

(define_insn_reservation "ir_sr70_arith" 1
  (and (eq_attr "cpu" "sr71000")
       (eq_attr "type" "arith,shift,signext,slt,clz,const,logical,move,trap"))
  "ri_insns")

;; emulate repeat (dispatch stall) by spending extra cycle(s) in
;; in iter unit
(define_insn_reservation "ir_sr70_imul_si" 4
  (and (eq_attr "cpu" "sr71000")
       (and (eq_attr "type" "imul,imul3,imadd")
	    (eq_attr "mode" "SI")))
  "ri_alux,ipu_alux,ipu_macc_iter")

(define_insn_reservation "ir_sr70_imul_di" 6
  (and (eq_attr "cpu" "sr71000")
       (and (eq_attr "type" "imul,imul3,imadd")
	    (eq_attr "mode" "DI")))
  "ri_alux,ipu_alux,(ipu_macc_iter*3)")

;; Divide algorithm is early out with best latency of 7 pcycles.
;; Use worst case for scheduling purposes.
(define_insn_reservation "ir_sr70_idiv_si" 41
  (and (eq_attr "cpu" "sr71000")
       (and (eq_attr "type" "idiv")
	    (eq_attr "mode" "SI")))
  "ri_alux,ipu_alux,(ipu_macc_iter*38)")

(define_insn_reservation "ir_sr70_idiv_di" 73
  (and (eq_attr "cpu" "sr71000")
       (and (eq_attr "type" "idiv")
	    (eq_attr "mode" "DI")))
  "ri_alux,ipu_alux,(ipu_macc_iter*70)")

;; extra reservations of fpu_fpu are for repeat latency
(define_insn_reservation "ir_sr70_fadd_sf" 8
  (and (eq_attr "cpu" "sr71000")
       (and (eq_attr "type" "fadd")
	    (eq_attr "mode" "SF")))
  "rf_insn,fpu_fpu")

(define_insn_reservation "ir_sr70_fadd_df" 10
  (and (eq_attr "cpu" "sr71000")
       (and (eq_attr "type" "fadd")
	    (eq_attr "mode" "DF")))
  "rf_insn,fpu_fpu")

;; Latencies for MADD,MSUB, NMADD, NMSUB assume the Multiply is fused
;; with the sub or add.
(define_insn_reservation "ir_sr70_fmul_sf" 8
  (and (eq_attr "cpu" "sr71000")
       (and (eq_attr "type" "fmul,fmadd")
	    (eq_attr "mode" "SF")))
  "rf_insn,fpu_fpu")

;; tie up the fpu unit to emulate the balance for the "repeat
;; rate" of 8 (2 are spent in the iss unit)
(define_insn_reservation "ir_sr70_fmul_df" 16
  (and (eq_attr "cpu" "sr71000")
       (and (eq_attr "type" "fmul,fmadd")
	    (eq_attr "mode" "DF")))
  "rf_insn,fpu_fpu*6")


;; RECIP insn uses same type attr as div, and for SR3, has same
;; timings for double. However, single RECIP has a latency of
;; 28 -- only way to fix this is to introduce new insn attrs.
;; cycles spent in iter unit are designed to satisfy balance
;; of "repeat" latency after insn uses up rf_multi1 reservation
(define_insn_reservation "ir_sr70_fdiv_sf" 60
  (and (eq_attr "cpu" "sr71000")
       (and (eq_attr "type" "fdiv,frdiv")
	    (eq_attr "mode" "SF")))
  "rf_multi1+(fpu_iter*51)")

(define_insn_reservation "ir_sr70_fdiv_df" 120
  (and (eq_attr "cpu" "sr71000")
       (and (eq_attr "type" "fdiv,frdiv")
	    (eq_attr "mode" "DF")))
  "rf_multi1+(fpu_iter*109)")

(define_insn_reservation "ir_sr70_fabs" 4
  (and (eq_attr "cpu" "sr71000")
       (eq_attr "type" "fabs,fneg,fmove"))
  "rf_insn,fpu_fpu")

(define_insn_reservation "ir_sr70_fcmp" 10
  (and (eq_attr "cpu" "sr71000")
       (eq_attr "type" "fcmp"))
  "rf_insn,fpu_fpu")

;; "fcvt" type attribute covers a number of diff insns, most have the same
;; latency descriptions, a few vary. We use the
;; most common timing (which is also worst case).
(define_insn_reservation "ir_sr70_fcvt" 12
  (and (eq_attr "cpu" "sr71000")
       (eq_attr "type" "fcvt"))
  "rf_insn,fpu_fpu*4")

(define_insn_reservation "ir_sr70_fsqrt_sf" 62
  (and (eq_attr "cpu" "sr71000")
       (and (eq_attr "type" "fsqrt")
	    (eq_attr "mode" "SF")))
  "rf_multi1+(fpu_iter*53)")

(define_insn_reservation "ir_sr70_fsqrt_df" 122
  (and (eq_attr "cpu" "sr71000")
       (and (eq_attr "type" "fsqrt")
	    (eq_attr "mode" "DF")))
  "rf_multi1+(fpu_iter*111)")

(define_insn_reservation "ir_sr70_frsqrt_sf" 48
  (and (eq_attr "cpu" "sr71000")
       (and (eq_attr "type" "frsqrt")
	    (eq_attr "mode" "SF")))
  "rf_multi1+(fpu_iter*39)")

(define_insn_reservation "ir_sr70_frsqrt_df" 240
  (and (eq_attr "cpu" "sr71000")
       (and (eq_attr "type" "frsqrt")
	    (eq_attr "mode" "DF")))
  "rf_multi1+(fpu_iter*229)")

(define_insn_reservation "ir_sr70_multi" 1
  (and (eq_attr "cpu" "sr71000")
       (eq_attr "type" "multi"))
  "serial_dispatch")

(define_insn_reservation "ir_sr70_nop" 1
  (and (eq_attr "cpu" "sr71000")
       (eq_attr "type" "nop"))
  "ri_insns")