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authorJason Molenda <jsm@bugshack.cygnus.com>1999-09-28 21:55:18 +0000
committerJason Molenda <jsm@bugshack.cygnus.com>1999-09-28 21:55:18 +0000
commit54c5b1a688796c108929df7f8115538243f84dbc (patch)
tree74c283750edf46d391c88e14f6e0323e021e29aa
parent4d23a063c8059a5141da8d829b77a277b77827da (diff)
downloadgdb-54c5b1a688796c108929df7f8115538243f84dbc.tar.gz
import gdb-1999-09-28 snapshotgdb-1999-09-28
-rw-r--r--sim/ChangeLog5
-rw-r--r--sim/common/ChangeLog11
-rw-r--r--sim/common/cgen-ops.h88
-rw-r--r--sim/common/genmloop.sh4
-rwxr-xr-xsim/configure5
-rw-r--r--sim/configure.in5
6 files changed, 62 insertions, 56 deletions
diff --git a/sim/ChangeLog b/sim/ChangeLog
index 7c44a9b6c36..e0fb2bc0689 100644
--- a/sim/ChangeLog
+++ b/sim/ChangeLog
@@ -1,3 +1,8 @@
+1999-07-16 Ben Elliston <bje@cygnus.com>
+
+ * configure.in: Configure the testsuite directory for arm.
+ * configure: Regenerate.
+
1999-04-08 Nick Clifton <nickc@cygnus.com>
* configure.in: Add support for MCore target.
diff --git a/sim/common/ChangeLog b/sim/common/ChangeLog
index e0274569ad0..75c8cdb4b08 100644
--- a/sim/common/ChangeLog
+++ b/sim/common/ChangeLog
@@ -1,3 +1,14 @@
+1999-09-25 Doug Evans <devans@casey.cygnus.com>
+
+ * cgen-ops.h (SUBWORD*): Delete cpu arg.
+ (JOIN*): Delete cpu arg.
+
+Tue Sep 21 17:14:16 1999 Dave Brolley <brolley@cygnus.com>
+
+ * genmloop.sh (@cpu@_scache_lookup): No longer takes last_insn_p
+ parameter.
+ (SET_LAST_INSN_P): Set last_insn_p flag in the scache element.
+
Mon Sep 20 21:44:06 1999 Geoffrey Keating <geoffk@cygnus.com>
* sim-fpu.c (i2fpu): Keep the guard bits sticky when converting
diff --git a/sim/common/cgen-ops.h b/sim/common/cgen-ops.h
index 326102f6a3c..de3717b1b24 100644
--- a/sim/common/cgen-ops.h
+++ b/sim/common/cgen-ops.h
@@ -1,4 +1,3 @@
-
/* Semantics ops support for CGEN-based simulators.
Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
Contributed by Cygnus Solutions.
@@ -285,15 +284,15 @@ extern SI TRUNCDISI (DI);
#define TRUNCDISI(x) ((SI) (DI) (x))
#endif
-/* Composing/decomposing the various types. */
-
-/* ??? endianness issues undecided */
-/* ??? CURRENT_TARGET_BYTE_ORDER usage wip */
+/* Composing/decomposing the various types.
+ Word ordering is endian-independent. Words are specified most to least
+ significant and word number 0 is the most significant word.
+ ??? May also wish an endian-dependent version. Later. */
#ifdef SEMOPS_DEFINE_INLINE
SEMOPS_INLINE SF
-SUBWORDSISF (SIM_CPU *cpu, SI in)
+SUBWORDSISF (SI in)
{
union { SI in; SF out; } x;
x.in = in;
@@ -301,7 +300,7 @@ SUBWORDSISF (SIM_CPU *cpu, SI in)
}
SEMOPS_INLINE SI
-SUBWORDSFSI (SIM_CPU *cpu, SF in)
+SUBWORDSFSI (SF in)
{
union { SF in; SI out; } x;
x.in = in;
@@ -309,59 +308,44 @@ SUBWORDSFSI (SIM_CPU *cpu, SF in)
}
SEMOPS_INLINE SI
-SUBWORDDISI (SIM_CPU *cpu, DI in, int word)
+SUBWORDDISI (DI in, int word)
{
- if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
- {
- if (word == 0)
- return (UDI) in >> 32;
- else
- return in;
- }
+ if (word == 0)
+ return (UDI) in >> 32;
else
- {
- if (word == 1)
- return (UDI) in >> 32;
- else
- return in;
- }
+ return in;
}
SEMOPS_INLINE SI
-SUBWORDDFSI (SIM_CPU *cpu, DF in, int word)
+SUBWORDDFSI (DF in, int word)
{
- union { DF in; SI out[2]; } x;
- x.in = in;
- if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
- return x.out[word];
+ /* Note: typedef UDI DF; */
+ if (word == 0)
+ return (UDI) in >> 32;
else
- return x.out[!word];
+ return in;
}
SEMOPS_INLINE SI
-SUBWORDXFSI (SIM_CPU *cpu, XF in, int word)
+SUBWORDXFSI (XF in, int word)
{
+ /* Note: typedef struct { SI parts[3]; } XF; */
union { XF in; SI out[3]; } x;
x.in = in;
- if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
- return x.out[word];
- else
- return x.out[2 - word];
+ return x.out[word];
}
SEMOPS_INLINE SI
-SUBWORDTFSI (SIM_CPU *cpu, TF in, int word)
+SUBWORDTFSI (TF in, int word)
{
+ /* Note: typedef struct { SI parts[4]; } TF; */
union { TF in; SI out[4]; } x;
x.in = in;
- if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
- return x.out[word];
- else
- return x.out[3 - word];
+ return x.out[word];
}
SEMOPS_INLINE DI
-JOINSIDI (SIM_CPU *cpu, SI x0, SI x1)
+JOINSIDI (SI x0, SI x1)
{
if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
return MAKEDI (x0, x1);
@@ -370,7 +354,7 @@ JOINSIDI (SIM_CPU *cpu, SI x0, SI x1)
}
SEMOPS_INLINE DF
-JOINSIDF (SIM_CPU *cpu, SI x0, SI x1)
+JOINSIDF (SI x0, SI x1)
{
union { SI in[2]; DF out; } x;
if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
@@ -381,7 +365,7 @@ JOINSIDF (SIM_CPU *cpu, SI x0, SI x1)
}
SEMOPS_INLINE XF
-JOINSIXF (SIM_CPU *cpu, SI x0, SI x1, SI x2)
+JOINSIXF (SI x0, SI x1, SI x2)
{
union { SI in[3]; XF out; } x;
if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
@@ -392,7 +376,7 @@ JOINSIXF (SIM_CPU *cpu, SI x0, SI x1, SI x2)
}
SEMOPS_INLINE TF
-JOINSITF (SIM_CPU *cpu, SI x0, SI x1, SI x2, SI x3)
+JOINSITF (SI x0, SI x1, SI x2, SI x3)
{
union { SI in[4]; TF out; } x;
if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
@@ -404,17 +388,17 @@ JOINSITF (SIM_CPU *cpu, SI x0, SI x1, SI x2, SI x3)
#else
-SF SUBWORDSISF (SIM_CPU *, SI);
-SI SUBWORDSFSI (SIM_CPU *, SF);
-SI SUBWORDDISI (SIM_CPU *, DI, int);
-SI SUBWORDDFSI (SIM_CPU *, DF, int);
-SI SUBWORDXFSI (SIM_CPU *, XF, int);
-SI SUBWORDTFSI (SIM_CPU *, TF, int);
-
-DI JOINSIDI (SIM_CPU *, SI, SI);
-DF JOINSIDF (SIM_CPU *, SI, SI);
-XF JOINSIXF (SIM_CPU *, SI, SI, SI);
-TF JOINSITF (SIM_CPU *, SI, SI, SI, SI);
+SF SUBWORDSISF (SI);
+SI SUBWORDSFSI (SF);
+SI SUBWORDDISI (DI, int);
+SI SUBWORDDFSI (DF, int);
+SI SUBWORDXFSI (XF, int);
+SI SUBWORDTFSI (TF, int);
+
+DI JOINSIDI (SI, SI);
+DF JOINSIDF (SI, SI);
+XF JOINSIXF (SI, SI, SI);
+TF JOINSITF (SI, SI, SI, SI);
#endif /* SUBWORD,JOIN */
diff --git a/sim/common/genmloop.sh b/sim/common/genmloop.sh
index 115ae8c8864..d3e17b085df 100644
--- a/sim/common/genmloop.sh
+++ b/sim/common/genmloop.sh
@@ -651,7 +651,7 @@ if [ x$scache = xyes -a x$parallel != xno ] ; then
static INLINE SCACHE *
@cpu@_scache_lookup (SIM_CPU *current_cpu, PCADDR vpc, SCACHE *scache,
- unsigned int hash_mask, int *last_insn_p, int FAST_P)
+ unsigned int hash_mask, int FAST_P)
{
/* First step: look up current insn in hash table. */
SCACHE *sc = scache + SCACHE_HASH_PC (vpc, hash_mask);
@@ -663,7 +663,7 @@ static INLINE SCACHE *
if (! FAST_P)
PROFILE_COUNT_SCACHE_MISS (current_cpu);
-#define SET_LAST_INSN_P(last_p) do { *last_insn_p = (last_p); } while (0)
+#define SET_LAST_INSN_P(last_p) do { sc->last_insn_p = (last_p); } while (0)
/* begin extract-scache */
EOF
diff --git a/sim/configure b/sim/configure
index 82caaacf491..5326e0d486f 100755
--- a/sim/configure
+++ b/sim/configure
@@ -1397,7 +1397,10 @@ extra_subdirs=common
# convention, else the table becomes a real mess to understand and maintain.
case "${target}" in
- arm*-*-*) sim_target=arm ;;
+ arm*-*-*)
+ sim_target=arm
+ extra_subdirs="${extra_subdirs} testsuite"
+ ;;
strongarm*-*-*) sim_target=arm ;;
thumb*-*-*) sim_target=arm ;;
d10v-*-*) sim_target=d10v ;;
diff --git a/sim/configure.in b/sim/configure.in
index ccff05e7cb2..97318adcdb6 100644
--- a/sim/configure.in
+++ b/sim/configure.in
@@ -47,7 +47,10 @@ extra_subdirs=common
# convention, else the table becomes a real mess to understand and maintain.
case "${target}" in
- arm*-*-*) sim_target=arm ;;
+ arm*-*-*)
+ sim_target=arm
+ extra_subdirs="${extra_subdirs} testsuite"
+ ;;
strongarm*-*-*) sim_target=arm ;;
thumb*-*-*) sim_target=arm ;;
d10v-*-*) sim_target=d10v ;;