diff options
| author | Zack Weinberg <zackw@panix.com> | 2005-04-26 05:31:43 +0000 |
|---|---|---|
| committer | Zack Weinberg <zackw@panix.com> | 2005-04-26 05:31:43 +0000 |
| commit | dfd3d2dacc181d6c13c4689cc91b1fc82d3f56a6 (patch) | |
| tree | 14903e1a807bd66bf4a606e375cbb6aa09805b41 | |
| parent | 72b3f3792d3f096413a87ecad5008206e1b1d702 (diff) | |
| download | gdb-dfd3d2dacc181d6c13c4689cc91b1fc82d3f56a6.tar.gz | |
Thumb32 assembler.
* include/elf/arm.h: Import full set of relocation names from
latest AAELF. Make the primary name of all relocations be the one
AAELF specifies. Provide aliases under the traditional names.
Kill FIRST_INVALID_RELOC_* and LAST_INVALID_RELOC_*.
* bfd/reloc.c: Reorganize ARM relocations. Remove ARM relocations
that are never generated. Document more of the relocations. Add
relocations for Thumb32.
* bfd/libbfd.h, bfd/bfd-in2.h: Regenerate.
* bfd/elf32-arm.c: Reorganize howto tables. Implement Thumb32
relocations.
* ld/testsuite/ld-arm/mixed-app.d: Adjust expectations for
renamed relocations.
* gas/hash.c (hash_find_n): New interface.
* gas/hash.h: Prototype it.
* gas/config/tc-arm.c: Rewrite and reorganize. Implement 32-bit
Thumb instructions.
* gas/testsuite/gas/arm: Convert all "gas_test" style tests to
"run_dump_test" style tests, for more thorough testing. Make
adjustments to expectations where necessary.
* gas/testsuite/gas/arm/t16-bad.s, gas/testsuite/gas/arm/tcompat.s
* gas/testsuite/gas/arm/tcompat2.s, gas/testsuite/gas/arm/thumb32.s:
New test cases.
* opcodes/arm-dis.c: Add support for Thumb32 instructions and
16-bit V6T2 instructions.
| -rw-r--r-- | ChangeLog.csl | 35 | ||||
| -rw-r--r-- | bfd/bfd-in2.h | 101 | ||||
| -rw-r--r-- | bfd/elf32-arm.c | 942 | ||||
| -rw-r--r-- | bfd/libbfd.h | 58 | ||||
| -rw-r--r-- | bfd/reloc.c | 163 | ||||
| -rw-r--r-- | include/elf/arm.h | 242 | ||||
| -rw-r--r-- | opcodes/arm-dis.c | 1294 |
7 files changed, 2020 insertions, 815 deletions
diff --git a/ChangeLog.csl b/ChangeLog.csl index a82b8ce6a5a..dc781404803 100644 --- a/ChangeLog.csl +++ b/ChangeLog.csl @@ -1,3 +1,36 @@ +2005-04-25 Zack Weinberg <zack@codesourcery.com> + + Thumb32 assembler. + + * include/elf/arm.h: Import full set of relocation names from + latest AAELF. Make the primary name of all relocations be the one + AAELF specifies. Provide aliases under the traditional names. + Kill FIRST_INVALID_RELOC_* and LAST_INVALID_RELOC_*. + * bfd/reloc.c: Reorganize ARM relocations. Remove ARM relocations + that are never generated. Document more of the relocations. Add + relocations for Thumb32. + * bfd/libbfd.h, bfd/bfd-in2.h: Regenerate. + * bfd/elf32-arm.c: Reorganize howto tables. Implement Thumb32 + relocations. + * ld/testsuite/ld-arm/mixed-app.d: Adjust expectations for + renamed relocations. + + * gas/hash.c (hash_find_n): New interface. + * gas/hash.h: Prototype it. + + * gas/config/tc-arm.c: Rewrite and reorganize. Implement 32-bit + Thumb instructions. + * gas/testsuite/gas/arm: Convert all "gas_test" style tests to + "run_dump_test" style tests, for more thorough testing. Make + adjustments to expectations where necessary. + * gas/testsuite/gas/arm/t16-bad.s, gas/testsuite/gas/arm/tcompat.s + * gas/testsuite/gas/arm/tcompat2.s, gas/testsuite/gas/arm/thumb32.s: + New test cases. + + * opcodes/arm-dis.c: Add support for Thumb32 instructions and + 16-bit V6T2 instructions. + + 2005-04-13 Paul Brook <paul@codesourcery.com> Backport from mainline. @@ -10,7 +43,7 @@ * ld/configure.tgt (arm-wrs-linux-gnueabi*): Support both big- and little-endian. - + 2005-04-08 Paul Brook <paul@codesourcery.com> * elf32-arm.c (ARM2THUMB_GLUE_SIZE): Rename... diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index 6a80f74d00d..e92295b742e 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -2662,44 +2662,23 @@ not stored in the instruction. The 2nd lowest bit comes from a 1 bit field in the instruction. */ BFD_RELOC_THUMB_PCREL_BLX, -/* These relocs are only used within the ARM assembler. They are not -(at present) written to any object files. */ - BFD_RELOC_ARM_IMMEDIATE, - BFD_RELOC_ARM_ADRL_IMMEDIATE, +/* Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches. +The lowest bit must be zero and is not stored in the instruction. +Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an +"nn" one smaller in all cases. Note further that BRANCH23 +corresponds to R_ARM_THM_CALL. */ + BFD_RELOC_THUMB_PCREL_BRANCH7, + BFD_RELOC_THUMB_PCREL_BRANCH9, + BFD_RELOC_THUMB_PCREL_BRANCH12, + BFD_RELOC_THUMB_PCREL_BRANCH20, + BFD_RELOC_THUMB_PCREL_BRANCH23, + BFD_RELOC_THUMB_PCREL_BRANCH25, + +/* 12-bit immediate offset, used in ARM-format ldr and str instructions. */ BFD_RELOC_ARM_OFFSET_IMM, - BFD_RELOC_ARM_SHIFT_IMM, - BFD_RELOC_ARM_SMI, - BFD_RELOC_ARM_SWI, - BFD_RELOC_ARM_MULTI, - BFD_RELOC_ARM_CP_OFF_IMM, - BFD_RELOC_ARM_CP_OFF_IMM_S2, - BFD_RELOC_ARM_ADR_IMM, - BFD_RELOC_ARM_LDR_IMM, - BFD_RELOC_ARM_LITERAL, - BFD_RELOC_ARM_IN_POOL, - BFD_RELOC_ARM_OFFSET_IMM8, - BFD_RELOC_ARM_HWLITERAL, - BFD_RELOC_ARM_THUMB_ADD, - BFD_RELOC_ARM_THUMB_IMM, - BFD_RELOC_ARM_THUMB_SHIFT, + +/* 5-bit immediate offset, used in Thumb-format ldr and str instructions. */ BFD_RELOC_ARM_THUMB_OFFSET, - BFD_RELOC_ARM_GOT12, - BFD_RELOC_ARM_GOT32, - BFD_RELOC_ARM_JUMP_SLOT, - BFD_RELOC_ARM_COPY, - BFD_RELOC_ARM_GLOB_DAT, - BFD_RELOC_ARM_PLT32, - BFD_RELOC_ARM_RELATIVE, - BFD_RELOC_ARM_GOTOFF, - BFD_RELOC_ARM_GOTPC, - BFD_RELOC_ARM_TLS_GD32, - BFD_RELOC_ARM_TLS_LDO32, - BFD_RELOC_ARM_TLS_LDM32, - BFD_RELOC_ARM_TLS_DTPOFF32, - BFD_RELOC_ARM_TLS_DTPMOD32, - BFD_RELOC_ARM_TLS_TPOFF32, - BFD_RELOC_ARM_TLS_IE32, - BFD_RELOC_ARM_TLS_LE32, /* Pc-relative or absolute relocation depending on target. Used for entries in .init_array sections. */ @@ -2711,7 +2690,7 @@ entries in .init_array sections. */ /* Data segment base relative address. */ BFD_RELOC_ARM_SBREL32, -/* This reloc is used for References to RTTI dta from exception handling +/* This reloc is used for references to RTTI data from exception handling tables. The actual definition depends on the target. It may be a pc-relative or some form of GOT-indirect relocation. */ BFD_RELOC_ARM_TARGET2, @@ -2719,6 +2698,48 @@ pc-relative or some form of GOT-indirect relocation. */ /* 31-bit PC relative address. */ BFD_RELOC_ARM_PREL31, +/* Relocations for setting up GOTs and PLTs for shared libraries. */ + BFD_RELOC_ARM_JUMP_SLOT, + BFD_RELOC_ARM_GLOB_DAT, + BFD_RELOC_ARM_GOT32, + BFD_RELOC_ARM_PLT32, + BFD_RELOC_ARM_RELATIVE, + BFD_RELOC_ARM_GOTOFF, + BFD_RELOC_ARM_GOTPC, + +/* ARM thread-local storage relocations. */ + BFD_RELOC_ARM_TLS_GD32, + BFD_RELOC_ARM_TLS_LDO32, + BFD_RELOC_ARM_TLS_LDM32, + BFD_RELOC_ARM_TLS_DTPOFF32, + BFD_RELOC_ARM_TLS_DTPMOD32, + BFD_RELOC_ARM_TLS_TPOFF32, + BFD_RELOC_ARM_TLS_IE32, + BFD_RELOC_ARM_TLS_LE32, + +/* These relocs are only used within the ARM assembler. They are not +(at present) written to any object files. */ + BFD_RELOC_ARM_IMMEDIATE, + BFD_RELOC_ARM_ADRL_IMMEDIATE, + BFD_RELOC_ARM_T32_IMMEDIATE, + BFD_RELOC_ARM_SHIFT_IMM, + BFD_RELOC_ARM_SMI, + BFD_RELOC_ARM_SWI, + BFD_RELOC_ARM_MULTI, + BFD_RELOC_ARM_CP_OFF_IMM, + BFD_RELOC_ARM_CP_OFF_IMM_S2, + BFD_RELOC_ARM_ADR_IMM, + BFD_RELOC_ARM_LDR_IMM, + BFD_RELOC_ARM_LITERAL, + BFD_RELOC_ARM_IN_POOL, + BFD_RELOC_ARM_OFFSET_IMM8, + BFD_RELOC_ARM_T32_OFFSET_U8, + BFD_RELOC_ARM_T32_OFFSET_IMM, + BFD_RELOC_ARM_HWLITERAL, + BFD_RELOC_ARM_THUMB_ADD, + BFD_RELOC_ARM_THUMB_IMM, + BFD_RELOC_ARM_THUMB_SHIFT, + /* Renesas / SuperH SH relocs. Not all of these appear in object files. */ BFD_RELOC_SH_PCDISP8BY2, BFD_RELOC_SH_PCDISP12BY2, @@ -2811,12 +2832,6 @@ pc-relative or some form of GOT-indirect relocation. */ BFD_RELOC_SH_TLS_DTPOFF32, BFD_RELOC_SH_TLS_TPOFF32, -/* Thumb 23-, 12- and 9-bit pc-relative branches. The lowest bit must -be zero and is not stored in the instruction. */ - BFD_RELOC_THUMB_PCREL_BRANCH9, - BFD_RELOC_THUMB_PCREL_BRANCH12, - BFD_RELOC_THUMB_PCREL_BRANCH23, - /* ARC Cores relocs. ARC 22 bit pc-relative branch. The lowest two bits must be zero and are not stored in the instruction. The high 20 bits are installed in bits 26 diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c index acc5b180bab..c4e66e74bcc 100644 --- a/bfd/elf32-arm.c +++ b/bfd/elf32-arm.c @@ -45,7 +45,7 @@ static bfd_boolean elf32_arm_nabi_grok_psinfo R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO in that slot. */ -static reloc_howto_type elf32_arm_howto_table[] = +static reloc_howto_type elf32_arm_howto_table_1[] = { /* No relocation */ HOWTO (R_ARM_NONE, /* type */ @@ -106,7 +106,7 @@ static reloc_howto_type elf32_arm_howto_table[] = 0xffffffff, /* dst_mask */ TRUE), /* pcrel_offset */ - /* 8 bit absolute */ + /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */ HOWTO (R_ARM_PC13, /* type */ 0, /* rightshift */ 0, /* size (0 = byte, 1 = short, 2 = long) */ @@ -194,7 +194,8 @@ static reloc_howto_type elf32_arm_howto_table[] = 0xffffffff, /* dst_mask */ FALSE), /* pcrel_offset */ - HOWTO (R_ARM_THM_PC22, /* type */ + /* FIXME: Has two more bits of offset in Thumb32. */ + HOWTO (R_ARM_THM_CALL, /* type */ 1, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ 23, /* bitsize */ @@ -202,7 +203,7 @@ static reloc_howto_type elf32_arm_howto_table[] = 0, /* bitpos */ complain_overflow_signed,/* complain_on_overflow */ bfd_elf_generic_reloc, /* special_function */ - "R_ARM_THM_PC22", /* name */ + "R_ARM_THM_CALL", /* name */ FALSE, /* partial_inplace */ 0x07ff07ff, /* src_mask */ 0x07ff07ff, /* dst_mask */ @@ -222,19 +223,19 @@ static reloc_howto_type elf32_arm_howto_table[] = 0x000000ff, /* dst_mask */ TRUE), /* pcrel_offset */ - HOWTO (R_ARM_AMP_VCALL9, /* type */ + HOWTO (R_ARM_BREL_ADJ, /* type */ 1, /* rightshift */ 1, /* size (0 = byte, 1 = short, 2 = long) */ - 8, /* bitsize */ - TRUE, /* pc_relative */ + 32, /* bitsize */ + FALSE, /* pc_relative */ 0, /* bitpos */ complain_overflow_signed,/* complain_on_overflow */ bfd_elf_generic_reloc, /* special_function */ - "R_ARM_AMP_VCALL9", /* name */ + "R_ARM_BREL_ADJ", /* name */ FALSE, /* partial_inplace */ - 0x000000ff, /* src_mask */ - 0x000000ff, /* dst_mask */ - TRUE), /* pcrel_offset */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + FALSE), /* pcrel_offset */ HOWTO (R_ARM_SWI24, /* type */ 0, /* rightshift */ @@ -396,7 +397,7 @@ static reloc_howto_type elf32_arm_howto_table[] = 0xffffffff, /* dst_mask */ FALSE), /* pcrel_offset */ - HOWTO (R_ARM_GOTOFF, /* type */ + HOWTO (R_ARM_GOTOFF32, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ 32, /* bitsize */ @@ -404,7 +405,7 @@ static reloc_howto_type elf32_arm_howto_table[] = 0, /* bitpos */ complain_overflow_bitfield,/* complain_on_overflow */ bfd_elf_generic_reloc, /* special_function */ - "R_ARM_GOTOFF", /* name */ + "R_ARM_GOTOFF32", /* name */ TRUE, /* partial_inplace */ 0xffffffff, /* src_mask */ 0xffffffff, /* dst_mask */ @@ -480,32 +481,32 @@ static reloc_howto_type elf32_arm_howto_table[] = 0x00ffffff, /* dst_mask */ TRUE), /* pcrel_offset */ - HOWTO (R_ARM_NONE, /* type */ - 0, /* rightshift */ - 0, /* size (0 = byte, 1 = short, 2 = long) */ - 0, /* bitsize */ - FALSE, /* pc_relative */ + HOWTO (R_ARM_THM_JUMP24, /* type */ + 1, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 24, /* bitsize */ + TRUE, /* pc_relative */ 0, /* bitpos */ - complain_overflow_dont,/* complain_on_overflow */ + complain_overflow_signed,/* complain_on_overflow */ bfd_elf_generic_reloc, /* special_function */ - "R_ARM_unknown_30", /* name */ + "R_ARM_THM_JUMP24", /* name */ FALSE, /* partial_inplace */ - 0, /* src_mask */ - 0, /* dst_mask */ - FALSE), /* pcrel_offset */ + 0x07ff2fff, /* src_mask */ + 0x07ff2fff, /* dst_mask */ + TRUE), /* pcrel_offset */ - HOWTO (R_ARM_NONE, /* type */ + HOWTO (R_ARM_BASE_ABS, /* type */ 0, /* rightshift */ - 0, /* size (0 = byte, 1 = short, 2 = long) */ - 0, /* bitsize */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ FALSE, /* pc_relative */ 0, /* bitpos */ complain_overflow_dont,/* complain_on_overflow */ bfd_elf_generic_reloc, /* special_function */ - "R_ARM_unknown_31", /* name */ + "R_ARM_BASE_ABS", /* name */ FALSE, /* partial_inplace */ - 0, /* src_mask */ - 0, /* dst_mask */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ FALSE), /* pcrel_offset */ HOWTO (R_ARM_ALU_PCREL7_0, /* type */ @@ -661,39 +662,446 @@ static reloc_howto_type elf32_arm_howto_table[] = 0x7fffffff, /* src_mask */ 0x7fffffff, /* dst_mask */ TRUE), /* pcrel_offset */ + + HOWTO (R_ARM_MOVW_ABS_NC, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_ARM_MOVW_ABS_NC", /* name */ + FALSE, /* partial_inplace */ + 0x0000ffff, /* src_mask */ + 0x0000ffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + HOWTO (R_ARM_MOVT_ABS, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_ARM_MOVT_ABS", /* name */ + FALSE, /* partial_inplace */ + 0x0000ffff, /* src_mask */ + 0x0000ffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + HOWTO (R_ARM_MOVW_PREL_NC, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_ARM_MOVW_PREL_NC", /* name */ + FALSE, /* partial_inplace */ + 0x0000ffff, /* src_mask */ + 0x0000ffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_ARM_MOVT_PREL, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_ARM_MOVT_PREL", /* name */ + FALSE, /* partial_inplace */ + 0x0000ffff, /* src_mask */ + 0x0000ffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_ARM_THM_MOVW_ABS_NC",/* name */ + FALSE, /* partial_inplace */ + 0x040f70ff, /* src_mask */ + 0x040f70ff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + HOWTO (R_ARM_THM_MOVT_ABS, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_ARM_THM_MOVT_ABS", /* name */ + FALSE, /* partial_inplace */ + 0x040f70ff, /* src_mask */ + 0x040f70ff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_ARM_THM_MOVW_PREL_NC",/* name */ + FALSE, /* partial_inplace */ + 0x040f70ff, /* src_mask */ + 0x040f70ff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_ARM_THM_MOVT_PREL, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_ARM_THM_MOVT_PREL", /* name */ + FALSE, /* partial_inplace */ + 0x040f70ff, /* src_mask */ + 0x040f70ff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_ARM_THM_JUMP19, /* type */ + 1, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 19, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_ARM_THM_JUMP19", /* name */ + FALSE, /* partial_inplace */ + 0x043f2fff, /* src_mask */ + 0x043f2fff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_ARM_THM_JUMP6, /* type */ + 1, /* rightshift */ + 1, /* size (0 = byte, 1 = short, 2 = long) */ + 6, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_unsigned,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_ARM_THM_JUMP6", /* name */ + FALSE, /* partial_inplace */ + 0x02f8, /* src_mask */ + 0x02f8, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* These are declared as 13-bit signed relocations because we can + address -4095 .. 4095(base) by altering ADDW to SUBW or vice + versa. */ + HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 13, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_ARM_THM_ALU_PREL_11_0",/* name */ + FALSE, /* partial_inplace */ + 0x040070ff, /* src_mask */ + 0x040070ff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_ARM_THM_PC12, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 13, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_ARM_THM_PC12", /* name */ + FALSE, /* partial_inplace */ + 0x040070ff, /* src_mask */ + 0x040070ff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_ARM_ABS32_NOI, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_ARM_ABS32_NOI", /* name */ + FALSE, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + HOWTO (R_ARM_REL32_NOI, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_ARM_REL32_NOI", /* name */ + FALSE, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + FALSE), /* pcrel_offset */ }; -static reloc_howto_type elf32_arm_tls_gd32_howto = - HOWTO (R_ARM_TLS_GD32, /* type */ +/* Relocations 57 .. 83 are the "group relocations" which we do not + support. */ + +static reloc_howto_type elf32_arm_howto_table_2[] = +{ + HOWTO (R_ARM_MOVW_BREL_NC, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_ARM_MOVW_BREL_NC", /* name */ + FALSE, /* partial_inplace */ + 0x0000ffff, /* src_mask */ + 0x0000ffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + HOWTO (R_ARM_MOVT_BREL, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_ARM_MOVT_BREL", /* name */ + FALSE, /* partial_inplace */ + 0x0000ffff, /* src_mask */ + 0x0000ffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + HOWTO (R_ARM_MOVW_BREL, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_ARM_MOVW_BREL", /* name */ + FALSE, /* partial_inplace */ + 0x0000ffff, /* src_mask */ + 0x0000ffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_ARM_THM_MOVW_BREL_NC",/* name */ + FALSE, /* partial_inplace */ + 0x040f70ff, /* src_mask */ + 0x040f70ff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + HOWTO (R_ARM_THM_MOVT_BREL, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_ARM_THM_MOVT_BREL", /* name */ + FALSE, /* partial_inplace */ + 0x040f70ff, /* src_mask */ + 0x040f70ff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + HOWTO (R_ARM_THM_MOVW_BREL, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_ARM_THM_MOVW_BREL", /* name */ + FALSE, /* partial_inplace */ + 0x040f70ff, /* src_mask */ + 0x040f70ff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + EMPTY_HOWTO (90), /* unallocated */ + EMPTY_HOWTO (91), + EMPTY_HOWTO (92), + EMPTY_HOWTO (93), + + HOWTO (R_ARM_PLT32_ABS, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_ARM_PLT32_ABS", /* name */ + FALSE, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + HOWTO (R_ARM_GOT_ABS, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_ARM_GOT_ABS", /* name */ + FALSE, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + HOWTO (R_ARM_GOT_PREL, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_ARM_GOT_PREL", /* name */ + FALSE, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_ARM_GOT_BREL12, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 12, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_ARM_GOT_BREL12", /* name */ + FALSE, /* partial_inplace */ + 0x00000fff, /* src_mask */ + 0x00000fff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + HOWTO (R_ARM_GOTOFF12, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 12, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_ARM_GOTOFF12", /* name */ + FALSE, /* partial_inplace */ + 0x00000fff, /* src_mask */ + 0x00000fff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */ + + /* GNU extension to record C++ vtable member usage */ + HOWTO (R_ARM_GNU_VTENTRY, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ + 0, /* bitsize */ FALSE, /* pc_relative */ 0, /* bitpos */ - complain_overflow_bitfield,/* complain_on_overflow */ - NULL, /* special_function */ - "R_ARM_TLS_GD32", /* name */ - TRUE, /* partial_inplace */ - 0xffffffff, /* src_mask */ - 0xffffffff, /* dst_mask */ - FALSE); /* pcrel_offset */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_elf_rel_vtable_reloc_fn, /* special_function */ + "R_ARM_GNU_VTENTRY", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + FALSE), /* pcrel_offset */ -static reloc_howto_type elf32_arm_tls_ldo32_howto = - HOWTO (R_ARM_TLS_LDO32, /* type */ + /* GNU extension to record C++ vtable hierarchy */ + HOWTO (R_ARM_GNU_VTINHERIT, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 0, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + NULL, /* special_function */ + "R_ARM_GNU_VTINHERIT", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + FALSE), /* pcrel_offset */ + + HOWTO (R_ARM_THM_JUMP11, /* type */ + 1, /* rightshift */ + 1, /* size (0 = byte, 1 = short, 2 = long) */ + 11, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_ARM_THM_JUMP11", /* name */ + FALSE, /* partial_inplace */ + 0x000007ff, /* src_mask */ + 0x000007ff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_ARM_THM_JUMP8, /* type */ + 1, /* rightshift */ + 1, /* size (0 = byte, 1 = short, 2 = long) */ + 8, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_ARM_THM_JUMP8", /* name */ + FALSE, /* partial_inplace */ + 0x000000ff, /* src_mask */ + 0x000000ff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* TLS relocations */ + HOWTO (R_ARM_TLS_GD32, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ 32, /* bitsize */ FALSE, /* pc_relative */ 0, /* bitpos */ complain_overflow_bitfield,/* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_ARM_TLS_LDO32", /* name */ + NULL, /* special_function */ + "R_ARM_TLS_GD32", /* name */ TRUE, /* partial_inplace */ 0xffffffff, /* src_mask */ 0xffffffff, /* dst_mask */ - FALSE); /* pcrel_offset */ + FALSE), /* pcrel_offset */ -static reloc_howto_type elf32_arm_tls_ldm32_howto = HOWTO (R_ARM_TLS_LDM32, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ @@ -706,10 +1114,9 @@ static reloc_howto_type elf32_arm_tls_ldm32_howto = TRUE, /* partial_inplace */ 0xffffffff, /* src_mask */ 0xffffffff, /* dst_mask */ - FALSE); /* pcrel_offset */ + FALSE), /* pcrel_offset */ -static reloc_howto_type elf32_arm_tls_le32_howto = - HOWTO (R_ARM_TLS_LE32, /* type */ + HOWTO (R_ARM_TLS_LDO32, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ 32, /* bitsize */ @@ -717,13 +1124,12 @@ static reloc_howto_type elf32_arm_tls_le32_howto = 0, /* bitpos */ complain_overflow_bitfield,/* complain_on_overflow */ bfd_elf_generic_reloc, /* special_function */ - "R_ARM_TLS_LE32", /* name */ + "R_ARM_TLS_LDO32", /* name */ TRUE, /* partial_inplace */ 0xffffffff, /* src_mask */ 0xffffffff, /* dst_mask */ - FALSE); /* pcrel_offset */ + FALSE), /* pcrel_offset */ -static reloc_howto_type elf32_arm_tls_ie32_howto = HOWTO (R_ARM_TLS_IE32, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ @@ -736,90 +1142,72 @@ static reloc_howto_type elf32_arm_tls_ie32_howto = TRUE, /* partial_inplace */ 0xffffffff, /* src_mask */ 0xffffffff, /* dst_mask */ - FALSE); /* pcrel_offset */ - - /* GNU extension to record C++ vtable hierarchy */ -static reloc_howto_type elf32_arm_vtinherit_howto = - HOWTO (R_ARM_GNU_VTINHERIT, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 0, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - NULL, /* special_function */ - "R_ARM_GNU_VTINHERIT", /* name */ - FALSE, /* partial_inplace */ - 0, /* src_mask */ - 0, /* dst_mask */ - FALSE); /* pcrel_offset */ + FALSE), /* pcrel_offset */ - /* GNU extension to record C++ vtable member usage */ -static reloc_howto_type elf32_arm_vtentry_howto = - HOWTO (R_ARM_GNU_VTENTRY, /* type */ + HOWTO (R_ARM_TLS_LE32, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ - 0, /* bitsize */ + 32, /* bitsize */ FALSE, /* pc_relative */ 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - _bfd_elf_rel_vtable_reloc_fn, /* special_function */ - "R_ARM_GNU_VTENTRY", /* name */ - FALSE, /* partial_inplace */ - 0, /* src_mask */ - 0, /* dst_mask */ - FALSE); /* pcrel_offset */ + complain_overflow_bitfield,/* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_ARM_TLS_LE32", /* name */ + TRUE, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + FALSE), /* pcrel_offset */ - /* 12 bit pc relative */ -static reloc_howto_type elf32_arm_thm_pc11_howto = - HOWTO (R_ARM_THM_PC11, /* type */ - 1, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 11, /* bitsize */ - TRUE, /* pc_relative */ + HOWTO (R_ARM_TLS_LDO12, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 12, /* bitsize */ + FALSE, /* pc_relative */ 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ + complain_overflow_bitfield,/* complain_on_overflow */ bfd_elf_generic_reloc, /* special_function */ - "R_ARM_THM_PC11", /* name */ + "R_ARM_TLS_LDO12", /* name */ FALSE, /* partial_inplace */ - 0x000007ff, /* src_mask */ - 0x000007ff, /* dst_mask */ - TRUE); /* pcrel_offset */ + 0x00000fff, /* src_mask */ + 0x00000fff, /* dst_mask */ + FALSE), /* pcrel_offset */ - /* 12 bit pc relative */ -static reloc_howto_type elf32_arm_thm_pc9_howto = - HOWTO (R_ARM_THM_PC9, /* type */ - 1, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 8, /* bitsize */ - TRUE, /* pc_relative */ + HOWTO (R_ARM_TLS_LE12, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 12, /* bitsize */ + FALSE, /* pc_relative */ 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ + complain_overflow_bitfield,/* complain_on_overflow */ bfd_elf_generic_reloc, /* special_function */ - "R_ARM_THM_PC9", /* name */ + "R_ARM_TLS_LE12", /* name */ FALSE, /* partial_inplace */ - 0x000000ff, /* src_mask */ - 0x000000ff, /* dst_mask */ - TRUE); /* pcrel_offset */ + 0x00000fff, /* src_mask */ + 0x00000fff, /* dst_mask */ + FALSE), /* pcrel_offset */ -/* Place relative GOT-indirect. */ -static reloc_howto_type elf32_arm_got_prel = - HOWTO (R_ARM_GOT_PREL, /* type */ + HOWTO (R_ARM_TLS_IE12GP, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - TRUE, /* pc_relative */ + 12, /* bitsize */ + FALSE, /* pc_relative */ 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ + complain_overflow_bitfield,/* complain_on_overflow */ bfd_elf_generic_reloc, /* special_function */ - "R_ARM_GOT_PREL", /* name */ + "R_ARM_TLS_IE12GP", /* name */ FALSE, /* partial_inplace */ - 0xffffffff, /* src_mask */ - 0xffffffff, /* dst_mask */ - TRUE); /* pcrel_offset */ + 0x00000fff, /* src_mask */ + 0x00000fff, /* dst_mask */ + FALSE), /* pcrel_offset */ +}; + +/* 112-127 private relocations + 128 R_ARM_ME_TOO, obsolete + 129-255 unallocated in AAELF. -/* Currently unused relocations. */ -static reloc_howto_type elf32_arm_r_howto[4] = + 249-255 extended, currently unused, relocations: */ + +static reloc_howto_type elf32_arm_howto_table_3[4] = { HOWTO (R_ARM_RREL32, /* type */ 0, /* rightshift */ @@ -881,55 +1269,18 @@ static reloc_howto_type elf32_arm_r_howto[4] = static reloc_howto_type * elf32_arm_howto_from_type (unsigned int r_type) { - if (r_type < NUM_ELEM (elf32_arm_howto_table)) - return &elf32_arm_howto_table[r_type]; - - switch (r_type) - { - case R_ARM_GOT_PREL: - return &elf32_arm_got_prel; - - case R_ARM_GNU_VTINHERIT: - return &elf32_arm_vtinherit_howto; - - case R_ARM_GNU_VTENTRY: - return &elf32_arm_vtentry_howto; + if (r_type < NUM_ELEM (elf32_arm_howto_table_1)) + return &elf32_arm_howto_table_1[r_type]; - case R_ARM_THM_PC11: - return &elf32_arm_thm_pc11_howto; + if (r_type >= R_ARM_MOVW_BREL_NC + && r_type < R_ARM_MOVW_BREL_NC + NUM_ELEM (elf32_arm_howto_table_2)) + return &elf32_arm_howto_table_2[r_type - R_ARM_MOVW_BREL_NC]; - case R_ARM_THM_PC9: - return &elf32_arm_thm_pc9_howto; - - case R_ARM_TLS_GD32: - return &elf32_arm_tls_gd32_howto; - break; - - case R_ARM_TLS_LDO32: - return &elf32_arm_tls_ldo32_howto; - break; - - case R_ARM_TLS_LDM32: - return &elf32_arm_tls_ldm32_howto; - break; - - case R_ARM_TLS_IE32: - return &elf32_arm_tls_ie32_howto; - break; - - case R_ARM_TLS_LE32: - return &elf32_arm_tls_le32_howto; - break; + if (r_type >= R_ARM_RREL32 + && r_type < R_ARM_RREL32 + NUM_ELEM (elf32_arm_howto_table_2)) + return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32]; - case R_ARM_RREL32: - case R_ARM_RABS32: - case R_ARM_RPC24: - case R_ARM_RBASE: - return &elf32_arm_r_howto[r_type - R_ARM_RREL32]; - - default: - return NULL; - } + return NULL; } static void @@ -961,12 +1312,16 @@ static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] = {BFD_RELOC_16, R_ARM_ABS16}, {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12}, {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5}, - {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_PC22}, - {BFD_RELOC_ARM_COPY, R_ARM_COPY}, + {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24}, + {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL}, + {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11}, + {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19}, + {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8}, + {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6}, {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT}, {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT}, {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE}, - {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF}, + {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32}, {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC}, {BFD_RELOC_ARM_GOT32, R_ARM_GOT32}, {BFD_RELOC_ARM_PLT32, R_ARM_PLT32}, @@ -984,6 +1339,8 @@ static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] = {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32}, {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32}, {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32}, + {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT}, + {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY}, }; static reloc_howto_type * @@ -992,43 +1349,11 @@ elf32_arm_reloc_type_lookup (abfd, code) bfd_reloc_code_real_type code; { unsigned int i; + for (i = 0; i < NUM_ELEM (elf32_arm_reloc_map); i ++) + if (elf32_arm_reloc_map[i].bfd_reloc_val == code) + return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val); - switch (code) - { - case BFD_RELOC_VTABLE_INHERIT: - return & elf32_arm_vtinherit_howto; - - case BFD_RELOC_VTABLE_ENTRY: - return & elf32_arm_vtentry_howto; - - case BFD_RELOC_THUMB_PCREL_BRANCH12: - return & elf32_arm_thm_pc11_howto; - - case BFD_RELOC_THUMB_PCREL_BRANCH9: - return & elf32_arm_thm_pc9_howto; - - case BFD_RELOC_ARM_TLS_GD32: - return & elf32_arm_tls_gd32_howto; - - case BFD_RELOC_ARM_TLS_LDO32: - return & elf32_arm_tls_ldo32_howto; - - case BFD_RELOC_ARM_TLS_LDM32: - return & elf32_arm_tls_ldm32_howto; - - case BFD_RELOC_ARM_TLS_IE32: - return & elf32_arm_tls_ie32_howto; - - case BFD_RELOC_ARM_TLS_LE32: - return & elf32_arm_tls_le32_howto; - - default: - for (i = 0; i < NUM_ELEM (elf32_arm_reloc_map); i ++) - if (elf32_arm_reloc_map[i].bfd_reloc_val == code) - return & elf32_arm_howto_table[elf32_arm_reloc_map[i].elf_reloc_val]; - - return NULL; - } + return NULL; } /* Support for core dump NOTE sections */ @@ -2026,7 +2351,7 @@ bfd_elf32_arm_process_before_allocation (bfd *abfd, && r_type != R_ARM_CALL && r_type != R_ARM_JUMP24 #endif - && r_type != R_ARM_THM_PC22) + && r_type != R_ARM_THM_CALL) continue; /* Get the section contents if we haven't done so already. */ @@ -2079,7 +2404,7 @@ bfd_elf32_arm_process_before_allocation (bfd *abfd, record_arm_to_thumb_glue (link_info, h); break; - case R_ARM_THM_PC22: + case R_ARM_THM_CALL: /* This one is a call from thumb code. We look up the target of the call. If it is not a thumb target, we insert glue. */ @@ -2882,7 +3207,7 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto, #ifndef OLD_ARM_ABI case R_ARM_THM_XPC22: #endif - case R_ARM_THM_PC22: + case R_ARM_THM_CALL: /* Thumb BL (branch long instruction). */ { bfd_vma relocation; @@ -3001,8 +3326,153 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto, } break; - case R_ARM_THM_PC11: - case R_ARM_THM_PC9: + case R_ARM_THM_JUMP24: + /* Thumb32 unconditional branch instruction. */ + { + bfd_vma relocation; + bfd_boolean overflow = FALSE; + bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data); + bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2); + bfd_signed_vma reloc_signed_max = ((1 << (howto->bitsize - 1)) - 1) >> howto->rightshift; + bfd_signed_vma reloc_signed_min = ~ reloc_signed_max; + bfd_vma check; + bfd_signed_vma signed_check; + + /* Need to refetch the addend, reconstruct the top three bits, and glue the + two pieces together. */ + if (globals->use_rel) + { + bfd_vma S = (upper_insn & 0x0400) >> 10; + bfd_vma hi = (upper_insn & 0x03ff); + bfd_vma I1 = (lower_insn & 0x2000) >> 13; + bfd_vma I2 = (lower_insn & 0x0800) >> 11; + bfd_vma lo = (lower_insn & 0x07ff); + + I1 = !(I1 ^ S); + I2 = !(I2 ^ S); + S = !S; + + signed_addend = (S << 24) | (I1 << 23) | (I2 << 22) | (hi << 12) | (lo << 1); + signed_addend -= (1 << 24); /* Sign extend. */ + } + + /* ??? Should handle interworking? GCC might someday try to + use this for tail calls. */ + + relocation = value + signed_addend; + relocation -= (input_section->output_section->vma + + input_section->output_offset + + rel->r_offset); + + check = relocation >> howto->rightshift; + + /* If this is a signed value, the rightshift just dropped + leading 1 bits (assuming twos complement). */ + if ((bfd_signed_vma) relocation >= 0) + signed_check = check; + else + signed_check = check | ~((bfd_vma) -1 >> howto->rightshift); + + /* Assumes two's complement. */ + if (signed_check > reloc_signed_max || signed_check < reloc_signed_min) + overflow = TRUE; + + /* Put RELOCATION back into the insn. */ + { + bfd_vma S = (relocation & 0x01000000) >> 24; + bfd_vma I1 = (relocation & 0x00800000) >> 23; + bfd_vma I2 = (relocation & 0x00400000) >> 22; + bfd_vma hi = (relocation & 0x003ff000) >> 12; + bfd_vma lo = (relocation & 0x00000ffe) >> 1; + + I1 = !(I1 ^ S); + I2 = !(I2 ^ S); + + upper_insn = (upper_insn & (bfd_vma) 0xf800) | (S << 10) | hi; + lower_insn = (lower_insn & (bfd_vma) 0xd000) | (I1 << 13) | (I2 << 11) | lo; + } + + /* Put the relocated value back in the object file: */ + bfd_put_16 (input_bfd, upper_insn, hit_data); + bfd_put_16 (input_bfd, lower_insn, hit_data + 2); + + return (overflow ? bfd_reloc_overflow : bfd_reloc_ok); + } + + case R_ARM_THM_JUMP19: + /* Thumb32 conditional branch instruction. */ + { + bfd_vma relocation; + bfd_boolean overflow = FALSE; + bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data); + bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2); + bfd_signed_vma reloc_signed_max = ((1 << (howto->bitsize - 1)) - 1) >> howto->rightshift; + bfd_signed_vma reloc_signed_min = ~ reloc_signed_max; + bfd_vma check; + bfd_signed_vma signed_check; + + /* Need to refetch the addend, reconstruct the top three bits, + and squish the two 11 bit pieces together. */ + if (globals->use_rel) + { + bfd_vma S = (upper_insn & 0x0400) >> 10; + bfd_vma upper = (upper_insn & 0x001f); + bfd_vma J1 = (lower_insn & 0x2000) >> 13; + bfd_vma J2 = (lower_insn & 0x0800) >> 11; + bfd_vma lower = (lower_insn & 0x07ff); + + upper |= J2 << 6; + upper |= J1 << 7; + upper |= ~S << 8; + upper -= 0x0100; /* Sign extend. */ + + addend = (upper << 12) | (lower << 1); + signed_addend = addend; + } + + /* ??? Should handle interworking? GCC might someday try to + use this for tail calls. */ + + relocation = value + signed_addend; + relocation -= (input_section->output_section->vma + + input_section->output_offset + + rel->r_offset); + + check = relocation >> howto->rightshift; + + /* If this is a signed value, the rightshift just dropped + leading 1 bits (assuming twos complement). */ + if ((bfd_signed_vma) relocation >= 0) + signed_check = check; + else + signed_check = check | ~((bfd_vma) -1 >> howto->rightshift); + + /* Assumes two's complement. */ + if (signed_check > reloc_signed_max || signed_check < reloc_signed_min) + overflow = TRUE; + + /* Put RELOCATION back into the insn. */ + { + bfd_vma S = (relocation & 0x00100000) >> 20; + bfd_vma J2 = (relocation & 0x00080000) >> 19; + bfd_vma J1 = (relocation & 0x00040000) >> 18; + bfd_vma hi = (relocation & 0x0003f000) >> 12; + bfd_vma lo = (relocation & 0x00000ffe) >> 1; + + upper_insn = (upper_insn & 0xfb30) | (S << 10) | hi; + lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo; + } + + /* Put the relocated value back in the object file: */ + bfd_put_16 (input_bfd, upper_insn, hit_data); + bfd_put_16 (input_bfd, lower_insn, hit_data + 2); + + return (overflow ? bfd_reloc_overflow : bfd_reloc_ok); + } + + case R_ARM_THM_JUMP11: + case R_ARM_THM_JUMP8: + case R_ARM_THM_JUMP6: /* Thumb B (branch) instruction). */ { bfd_signed_vma relocation; @@ -3010,6 +3480,10 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto, bfd_signed_vma reloc_signed_min = ~ reloc_signed_max; bfd_signed_vma signed_check; + /* CZB cannot jump backward. */ + if (r_type == R_ARM_THM_JUMP6) + reloc_signed_min = 0; + if (globals->use_rel) { /* Need to refetch addend. */ @@ -3035,7 +3509,11 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto, relocation >>= howto->rightshift; signed_check = relocation; - relocation &= howto->dst_mask; + + if (r_type == R_ARM_THM_JUMP6) + relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3); + else + relocation &= howto->dst_mask; relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask)); bfd_put_16 (input_bfd, relocation, hit_data); @@ -3079,19 +3557,7 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto, case R_ARM_GNU_VTENTRY: return bfd_reloc_ok; - case R_ARM_COPY: - return bfd_reloc_notsupported; - - case R_ARM_GLOB_DAT: - return bfd_reloc_notsupported; - - case R_ARM_JUMP_SLOT: - return bfd_reloc_notsupported; - - case R_ARM_RELATIVE: - return bfd_reloc_notsupported; - - case R_ARM_GOTOFF: + case R_ARM_GOTOFF32: /* Relocation is relative to the start of the global offset table. */ @@ -3452,30 +3918,6 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto, return _bfd_final_link_relocate (howto, input_bfd, input_section, contents, rel->r_offset, value, (bfd_vma) 0); - case R_ARM_SBREL32: - return bfd_reloc_notsupported; - - case R_ARM_AMP_VCALL9: - return bfd_reloc_notsupported; - - case R_ARM_RSBREL32: - return bfd_reloc_notsupported; - - case R_ARM_THM_RPC22: - return bfd_reloc_notsupported; - - case R_ARM_RREL32: - return bfd_reloc_notsupported; - - case R_ARM_RABS32: - return bfd_reloc_notsupported; - - case R_ARM_RPC24: - return bfd_reloc_notsupported; - - case R_ARM_RBASE: - return bfd_reloc_notsupported; - case R_ARM_V4BX: if (globals->fix_v4bx) { @@ -3506,7 +3948,7 @@ arm_add_to_rel (bfd * abfd, { bfd_signed_vma addend; - if (howto->type == R_ARM_THM_PC22) + if (howto->type == R_ARM_THM_CALL) { int upper_insn, lower_insn; int upper, lower; @@ -4400,7 +4842,7 @@ elf32_arm_gc_sweep_hook (bfd * abfd, case R_ARM_JUMP24: case R_ARM_PREL31: #endif - case R_ARM_THM_PC22: + case R_ARM_THM_CALL: /* Should the interworking branches be here also? */ if (h != NULL) @@ -4414,7 +4856,7 @@ elf32_arm_gc_sweep_hook (bfd * abfd, if (h->plt.refcount > 0) { h->plt.refcount -= 1; - if (ELF32_R_TYPE (rel->r_info) == R_ARM_THM_PC22) + if (ELF32_R_TYPE (rel->r_info) == R_ARM_THM_CALL) eh->plt_thumb_refcount--; } @@ -4584,7 +5026,7 @@ elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info, htab->tls_ldm_got.refcount++; /* Fall through */ - case R_ARM_GOTOFF: + case R_ARM_GOTOFF32: case R_ARM_GOTPC: if (htab->sgot == NULL) { @@ -4604,7 +5046,7 @@ elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info, case R_ARM_JUMP24: case R_ARM_PREL31: #endif - case R_ARM_THM_PC22: + case R_ARM_THM_CALL: /* Should the interworking branches be listed here? */ if (h != NULL) { @@ -4628,14 +5070,14 @@ elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info, || r_type == R_ARM_PREL31 #endif || r_type == R_ARM_PLT32 - || r_type == R_ARM_THM_PC22) + || r_type == R_ARM_THM_CALL) h->needs_plt = 1; /* If we create a PLT entry, this relocation will reference it, even if it's an ABS32 relocation. */ h->plt.refcount += 1; - if (r_type == R_ARM_THM_PC22) + if (r_type == R_ARM_THM_CALL) eh->plt_thumb_refcount += 1; } diff --git a/bfd/libbfd.h b/bfd/libbfd.h index d86ae036868..a5099b3ac58 100644 --- a/bfd/libbfd.h +++ b/bfd/libbfd.h @@ -1145,9 +1145,37 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_ARM_PCREL_BRANCH", "BFD_RELOC_ARM_PCREL_BLX", "BFD_RELOC_THUMB_PCREL_BLX", + "BFD_RELOC_THUMB_PCREL_BRANCH7", + "BFD_RELOC_THUMB_PCREL_BRANCH9", + "BFD_RELOC_THUMB_PCREL_BRANCH12", + "BFD_RELOC_THUMB_PCREL_BRANCH20", + "BFD_RELOC_THUMB_PCREL_BRANCH23", + "BFD_RELOC_THUMB_PCREL_BRANCH25", + "BFD_RELOC_ARM_OFFSET_IMM", + "BFD_RELOC_ARM_THUMB_OFFSET", + "BFD_RELOC_ARM_TARGET1", + "BFD_RELOC_ARM_ROSEGREL32", + "BFD_RELOC_ARM_SBREL32", + "BFD_RELOC_ARM_TARGET2", + "BFD_RELOC_ARM_PREL31", + "BFD_RELOC_ARM_JUMP_SLOT", + "BFD_RELOC_ARM_GLOB_DAT", + "BFD_RELOC_ARM_GOT32", + "BFD_RELOC_ARM_PLT32", + "BFD_RELOC_ARM_RELATIVE", + "BFD_RELOC_ARM_GOTOFF", + "BFD_RELOC_ARM_GOTPC", + "BFD_RELOC_ARM_TLS_GD32", + "BFD_RELOC_ARM_TLS_LDO32", + "BFD_RELOC_ARM_TLS_LDM32", + "BFD_RELOC_ARM_TLS_DTPOFF32", + "BFD_RELOC_ARM_TLS_DTPMOD32", + "BFD_RELOC_ARM_TLS_TPOFF32", + "BFD_RELOC_ARM_TLS_IE32", + "BFD_RELOC_ARM_TLS_LE32", "BFD_RELOC_ARM_IMMEDIATE", "BFD_RELOC_ARM_ADRL_IMMEDIATE", - "BFD_RELOC_ARM_OFFSET_IMM", + "BFD_RELOC_ARM_T32_IMMEDIATE", "BFD_RELOC_ARM_SHIFT_IMM", "BFD_RELOC_ARM_SMI", "BFD_RELOC_ARM_SWI", @@ -1159,33 +1187,12 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_ARM_LITERAL", "BFD_RELOC_ARM_IN_POOL", "BFD_RELOC_ARM_OFFSET_IMM8", + "BFD_RELOC_ARM_T32_OFFSET_U8", + "BFD_RELOC_ARM_T32_OFFSET_IMM", "BFD_RELOC_ARM_HWLITERAL", "BFD_RELOC_ARM_THUMB_ADD", "BFD_RELOC_ARM_THUMB_IMM", "BFD_RELOC_ARM_THUMB_SHIFT", - "BFD_RELOC_ARM_THUMB_OFFSET", - "BFD_RELOC_ARM_GOT12", - "BFD_RELOC_ARM_GOT32", - "BFD_RELOC_ARM_JUMP_SLOT", - "BFD_RELOC_ARM_COPY", - "BFD_RELOC_ARM_GLOB_DAT", - "BFD_RELOC_ARM_PLT32", - "BFD_RELOC_ARM_RELATIVE", - "BFD_RELOC_ARM_GOTOFF", - "BFD_RELOC_ARM_GOTPC", - "BFD_RELOC_ARM_TLS_GD32", - "BFD_RELOC_ARM_TLS_LDO32", - "BFD_RELOC_ARM_TLS_LDM32", - "BFD_RELOC_ARM_TLS_DTPOFF32", - "BFD_RELOC_ARM_TLS_DTPMOD32", - "BFD_RELOC_ARM_TLS_TPOFF32", - "BFD_RELOC_ARM_TLS_IE32", - "BFD_RELOC_ARM_TLS_LE32", - "BFD_RELOC_ARM_TARGET1", - "BFD_RELOC_ARM_ROSEGREL32", - "BFD_RELOC_ARM_SBREL32", - "BFD_RELOC_ARM_TARGET2", - "BFD_RELOC_ARM_PREL31", "BFD_RELOC_SH_PCDISP8BY2", "BFD_RELOC_SH_PCDISP12BY2", "BFD_RELOC_SH_IMM3", @@ -1276,9 +1283,6 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_SH_TLS_DTPMOD32", "BFD_RELOC_SH_TLS_DTPOFF32", "BFD_RELOC_SH_TLS_TPOFF32", - "BFD_RELOC_THUMB_PCREL_BRANCH9", - "BFD_RELOC_THUMB_PCREL_BRANCH12", - "BFD_RELOC_THUMB_PCREL_BRANCH23", "BFD_RELOC_ARC_B22_PCREL", "BFD_RELOC_ARC_B26", "BFD_RELOC_D10V_10_PCREL_R", diff --git a/bfd/reloc.c b/bfd/reloc.c index 17f8a45c114..edf00b83cc3 100644 --- a/bfd/reloc.c +++ b/bfd/reloc.c @@ -2622,104 +2622,139 @@ ENUMDOC Thumb 22 bit pc-relative branch. The lowest bit must be zero and is not stored in the instruction. The 2nd lowest bit comes from a 1 bit field in the instruction. + ENUM - BFD_RELOC_ARM_IMMEDIATE + BFD_RELOC_THUMB_PCREL_BRANCH7 ENUMX - BFD_RELOC_ARM_ADRL_IMMEDIATE + BFD_RELOC_THUMB_PCREL_BRANCH9 ENUMX - BFD_RELOC_ARM_OFFSET_IMM + BFD_RELOC_THUMB_PCREL_BRANCH12 ENUMX - BFD_RELOC_ARM_SHIFT_IMM + BFD_RELOC_THUMB_PCREL_BRANCH20 ENUMX - BFD_RELOC_ARM_SMI + BFD_RELOC_THUMB_PCREL_BRANCH23 ENUMX - BFD_RELOC_ARM_SWI + BFD_RELOC_THUMB_PCREL_BRANCH25 +ENUMDOC + Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches. + The lowest bit must be zero and is not stored in the instruction. + Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an + "nn" one smaller in all cases. Note further that BRANCH23 + corresponds to R_ARM_THM_CALL. + +ENUM + BFD_RELOC_ARM_OFFSET_IMM +ENUMDOC + 12-bit immediate offset, used in ARM-format ldr and str instructions. + +ENUM + BFD_RELOC_ARM_THUMB_OFFSET +ENUMDOC + 5-bit immediate offset, used in Thumb-format ldr and str instructions. + +ENUM + BFD_RELOC_ARM_TARGET1 +ENUMDOC + Pc-relative or absolute relocation depending on target. Used for + entries in .init_array sections. +ENUM + BFD_RELOC_ARM_ROSEGREL32 +ENUMDOC + Read-only segment base relative address. +ENUM + BFD_RELOC_ARM_SBREL32 +ENUMDOC + Data segment base relative address. +ENUM + BFD_RELOC_ARM_TARGET2 +ENUMDOC + This reloc is used for references to RTTI data from exception handling + tables. The actual definition depends on the target. It may be a + pc-relative or some form of GOT-indirect relocation. +ENUM + BFD_RELOC_ARM_PREL31 +ENUMDOC + 31-bit PC relative address. + +ENUM + BFD_RELOC_ARM_JUMP_SLOT ENUMX - BFD_RELOC_ARM_MULTI + BFD_RELOC_ARM_GLOB_DAT ENUMX - BFD_RELOC_ARM_CP_OFF_IMM + BFD_RELOC_ARM_GOT32 ENUMX - BFD_RELOC_ARM_CP_OFF_IMM_S2 + BFD_RELOC_ARM_PLT32 ENUMX - BFD_RELOC_ARM_ADR_IMM + BFD_RELOC_ARM_RELATIVE ENUMX - BFD_RELOC_ARM_LDR_IMM + BFD_RELOC_ARM_GOTOFF ENUMX - BFD_RELOC_ARM_LITERAL + BFD_RELOC_ARM_GOTPC +ENUMDOC + Relocations for setting up GOTs and PLTs for shared libraries. + +ENUM + BFD_RELOC_ARM_TLS_GD32 ENUMX - BFD_RELOC_ARM_IN_POOL + BFD_RELOC_ARM_TLS_LDO32 ENUMX - BFD_RELOC_ARM_OFFSET_IMM8 + BFD_RELOC_ARM_TLS_LDM32 ENUMX - BFD_RELOC_ARM_HWLITERAL + BFD_RELOC_ARM_TLS_DTPOFF32 ENUMX - BFD_RELOC_ARM_THUMB_ADD + BFD_RELOC_ARM_TLS_DTPMOD32 ENUMX - BFD_RELOC_ARM_THUMB_IMM + BFD_RELOC_ARM_TLS_TPOFF32 ENUMX - BFD_RELOC_ARM_THUMB_SHIFT + BFD_RELOC_ARM_TLS_IE32 ENUMX - BFD_RELOC_ARM_THUMB_OFFSET + BFD_RELOC_ARM_TLS_LE32 +ENUMDOC + ARM thread-local storage relocations. + +ENUM + BFD_RELOC_ARM_IMMEDIATE ENUMX - BFD_RELOC_ARM_GOT12 + BFD_RELOC_ARM_ADRL_IMMEDIATE ENUMX - BFD_RELOC_ARM_GOT32 + BFD_RELOC_ARM_T32_IMMEDIATE ENUMX - BFD_RELOC_ARM_JUMP_SLOT + BFD_RELOC_ARM_SHIFT_IMM ENUMX - BFD_RELOC_ARM_COPY + BFD_RELOC_ARM_SMI ENUMX - BFD_RELOC_ARM_GLOB_DAT + BFD_RELOC_ARM_SWI ENUMX - BFD_RELOC_ARM_PLT32 + BFD_RELOC_ARM_MULTI ENUMX - BFD_RELOC_ARM_RELATIVE + BFD_RELOC_ARM_CP_OFF_IMM ENUMX - BFD_RELOC_ARM_GOTOFF + BFD_RELOC_ARM_CP_OFF_IMM_S2 ENUMX - BFD_RELOC_ARM_GOTPC + BFD_RELOC_ARM_ADR_IMM ENUMX - BFD_RELOC_ARM_TLS_GD32 + BFD_RELOC_ARM_LDR_IMM ENUMX - BFD_RELOC_ARM_TLS_LDO32 + BFD_RELOC_ARM_LITERAL ENUMX - BFD_RELOC_ARM_TLS_LDM32 + BFD_RELOC_ARM_IN_POOL ENUMX - BFD_RELOC_ARM_TLS_DTPOFF32 + BFD_RELOC_ARM_OFFSET_IMM8 ENUMX - BFD_RELOC_ARM_TLS_DTPMOD32 + BFD_RELOC_ARM_T32_OFFSET_U8 ENUMX - BFD_RELOC_ARM_TLS_TPOFF32 + BFD_RELOC_ARM_T32_OFFSET_IMM ENUMX - BFD_RELOC_ARM_TLS_IE32 + BFD_RELOC_ARM_HWLITERAL ENUMX - BFD_RELOC_ARM_TLS_LE32 + BFD_RELOC_ARM_THUMB_ADD +ENUMX + BFD_RELOC_ARM_THUMB_IMM +ENUMX + BFD_RELOC_ARM_THUMB_SHIFT ENUMDOC These relocs are only used within the ARM assembler. They are not (at present) written to any object files. -ENUM - BFD_RELOC_ARM_TARGET1 -ENUMDOC - Pc-relative or absolute relocation depending on target. Used for - entries in .init_array sections. -ENUM - BFD_RELOC_ARM_ROSEGREL32 -ENUMDOC - Read-only segment base relative address. -ENUM - BFD_RELOC_ARM_SBREL32 -ENUMDOC - Data segment base relative address. -ENUM - BFD_RELOC_ARM_TARGET2 -ENUMDOC - This reloc is used for References to RTTI dta from exception handling - tables. The actual definition depends on the target. It may be a - pc-relative or some form of GOT-indirect relocation. -ENUM - BFD_RELOC_ARM_PREL31 -ENUMDOC - 31-bit PC relative address. ENUM BFD_RELOC_SH_PCDISP8BY2 @@ -2905,16 +2940,6 @@ ENUMDOC Renesas / SuperH SH relocs. Not all of these appear in object files. ENUM - BFD_RELOC_THUMB_PCREL_BRANCH9 -ENUMX - BFD_RELOC_THUMB_PCREL_BRANCH12 -ENUMX - BFD_RELOC_THUMB_PCREL_BRANCH23 -ENUMDOC - Thumb 23-, 12- and 9-bit pc-relative branches. The lowest bit must - be zero and is not stored in the instruction. - -ENUM BFD_RELOC_ARC_B22_PCREL ENUMDOC ARC Cores relocs. diff --git a/include/elf/arm.h b/include/elf/arm.h index 81a8de1d701..878281ccd12 100644 --- a/include/elf/arm.h +++ b/include/elf/arm.h @@ -38,7 +38,7 @@ #define EF_ARM_MAVERICK_FLOAT 0x800 /* Frame unwind information */ -#define PT_ARM_EXIDX (PT_LOPROC + 1) +#define PT_ARM_EXIDX (PT_LOPROC + 1) /* Other constants defined in the ARM ELF spec. version B-01. */ #define EF_ARM_SYMSARESORTED 0x04 /* NB conflicts with EF_INTERWORK */ @@ -84,93 +84,159 @@ /* Relocation types. */ START_RELOC_NUMBERS (elf_arm_reloc_type) - RELOC_NUMBER (R_ARM_NONE, 0) - RELOC_NUMBER (R_ARM_PC24, 1) - RELOC_NUMBER (R_ARM_ABS32, 2) - RELOC_NUMBER (R_ARM_REL32, 3) -#ifdef OLD_ARM_ABI - RELOC_NUMBER (R_ARM_ABS8, 4) - RELOC_NUMBER (R_ARM_ABS16, 5) - RELOC_NUMBER (R_ARM_ABS12, 6) - RELOC_NUMBER (R_ARM_THM_ABS5, 7) - RELOC_NUMBER (R_ARM_THM_PC22, 8) - RELOC_NUMBER (R_ARM_SBREL32, 9) - RELOC_NUMBER (R_ARM_AMP_VCALL9, 10) - RELOC_NUMBER (R_ARM_THM_PC11, 11) /* Cygnus extension to abi: Thumb unconditional branch. */ - RELOC_NUMBER (R_ARM_THM_PC9, 12) /* Cygnus extension to abi: Thumb conditional branch. */ - RELOC_NUMBER (R_ARM_GNU_VTINHERIT, 13) - RELOC_NUMBER (R_ARM_GNU_VTENTRY, 14) -#else /* not OLD_ARM_ABI */ - RELOC_NUMBER (R_ARM_PC13, 4) - RELOC_NUMBER (R_ARM_ABS16, 5) - RELOC_NUMBER (R_ARM_ABS12, 6) - RELOC_NUMBER (R_ARM_THM_ABS5, 7) - RELOC_NUMBER (R_ARM_ABS8, 8) - RELOC_NUMBER (R_ARM_SBREL32, 9) - RELOC_NUMBER (R_ARM_THM_PC22, 10) - RELOC_NUMBER (R_ARM_THM_PC8, 11) - RELOC_NUMBER (R_ARM_AMP_VCALL9, 12) - RELOC_NUMBER (R_ARM_SWI24, 13) - RELOC_NUMBER (R_ARM_THM_SWI8, 14) - RELOC_NUMBER (R_ARM_XPC25, 15) - RELOC_NUMBER (R_ARM_THM_XPC22, 16) - RELOC_NUMBER (R_ARM_TLS_DTPMOD32, 17) - RELOC_NUMBER (R_ARM_TLS_DTPOFF32, 18) - RELOC_NUMBER (R_ARM_TLS_TPOFF32, 19) -#endif /* not OLD_ARM_ABI */ - RELOC_NUMBER (R_ARM_COPY, 20) /* Copy symbol at runtime. */ - RELOC_NUMBER (R_ARM_GLOB_DAT, 21) /* Create GOT entry. */ - RELOC_NUMBER (R_ARM_JUMP_SLOT, 22) /* Create PLT entry. */ - RELOC_NUMBER (R_ARM_RELATIVE, 23) /* Adjust by program base. */ - RELOC_NUMBER (R_ARM_GOTOFF, 24) /* 32 bit offset to GOT. */ - RELOC_NUMBER (R_ARM_GOTPC, 25) /* 32 bit PC relative offset to GOT. */ - RELOC_NUMBER (R_ARM_GOT32, 26) /* 32 bit GOT entry. */ - RELOC_NUMBER (R_ARM_PLT32, 27) /* 32 bit PLT address. */ -#ifdef OLD_ARM_ABI - FAKE_RELOC (FIRST_INVALID_RELOC, 28) - FAKE_RELOC (LAST_INVALID_RELOC, 249) -#else /* not OLD_ARM_ABI */ - RELOC_NUMBER (R_ARM_CALL, 28) - RELOC_NUMBER (R_ARM_JUMP24, 29) - FAKE_RELOC (FIRST_INVALID_RELOC1, 30) - FAKE_RELOC (LAST_INVALID_RELOC1, 31) - RELOC_NUMBER (R_ARM_ALU_PCREL7_0, 32) - RELOC_NUMBER (R_ARM_ALU_PCREL15_8, 33) - RELOC_NUMBER (R_ARM_ALU_PCREL23_15, 34) - RELOC_NUMBER (R_ARM_LDR_SBREL_11_0, 35) - RELOC_NUMBER (R_ARM_ALU_SBREL_19_12, 36) - RELOC_NUMBER (R_ARM_ALU_SBREL_27_20, 37) - RELOC_NUMBER (R_ARM_TARGET1, 38) - RELOC_NUMBER (R_ARM_ROSEGREL32, 39) - RELOC_NUMBER (R_ARM_V4BX, 40) - RELOC_NUMBER (R_ARM_TARGET2, 41) - RELOC_NUMBER (R_ARM_PREL31, 42) - FAKE_RELOC (FIRST_INVALID_RELOC2, 43) - FAKE_RELOC (LAST_INVALID_RELOC2, 94) - RELOC_NUMBER (R_ARM_GOT_ABS, 95) - RELOC_NUMBER (R_ARM_GOT_PREL, 96) - RELOC_NUMBER (R_ARM_GOT_BREL12, 97) - RELOC_NUMBER (R_ARM_GOTOFF12, 98) - RELOC_NUMBER (R_ARM_GOTRELAX, 99) - RELOC_NUMBER (R_ARM_GNU_VTENTRY, 100) - RELOC_NUMBER (R_ARM_GNU_VTINHERIT, 101) - RELOC_NUMBER (R_ARM_THM_PC11, 102) /* Cygnus extension to abi: Thumb unconditional branch. */ - RELOC_NUMBER (R_ARM_THM_PC9, 103) /* Cygnus extension to abi: Thumb conditional branch. */ - RELOC_NUMBER (R_ARM_TLS_GD32, 104) - RELOC_NUMBER (R_ARM_TLS_LDM32, 105) - RELOC_NUMBER (R_ARM_TLS_LDO32, 106) - RELOC_NUMBER (R_ARM_TLS_IE32, 107) - RELOC_NUMBER (R_ARM_TLS_LE32, 108) - FAKE_RELOC (FIRST_INVALID_RELOC3, 109) - FAKE_RELOC (LAST_INVALID_RELOC3, 248) - RELOC_NUMBER (R_ARM_RXPC25, 249) -#endif /* not OLD_ARM_ABI */ - RELOC_NUMBER (R_ARM_RSBREL32, 250) - RELOC_NUMBER (R_ARM_THM_RPC22, 251) - RELOC_NUMBER (R_ARM_RREL32, 252) - RELOC_NUMBER (R_ARM_RABS32, 253) - RELOC_NUMBER (R_ARM_RPC24, 254) - RELOC_NUMBER (R_ARM_RBASE, 255) +/* AAELF official names and numbers. */ + RELOC_NUMBER (R_ARM_NONE, 0) + RELOC_NUMBER (R_ARM_PC24, 1) /* deprecated */ + RELOC_NUMBER (R_ARM_ABS32, 2) + RELOC_NUMBER (R_ARM_REL32, 3) +#ifndef OLD_ARM_ABI + RELOC_NUMBER (R_ARM_LDR_PC_G0, 4) + RELOC_NUMBER (R_ARM_ABS16, 5) + RELOC_NUMBER (R_ARM_ABS12, 6) + RELOC_NUMBER (R_ARM_THM_ABS5, 7) + RELOC_NUMBER (R_ARM_ABS8, 8) + RELOC_NUMBER (R_ARM_SBREL32, 9) + RELOC_NUMBER (R_ARM_THM_CALL, 10) + RELOC_NUMBER (R_ARM_THM_PC8, 11) + RELOC_NUMBER (R_ARM_BREL_ADJ, 12) + RELOC_NUMBER (R_ARM_SWI24, 13) /* obsolete */ + RELOC_NUMBER (R_ARM_THM_SWI8, 14) /* obsolete */ +#else + RELOC_NUMBER (R_ARM_ABS8, 4) + RELOC_NUMBER (R_ARM_ABS16, 5) + RELOC_NUMBER (R_ARM_ABS12, 6) + RELOC_NUMBER (R_ARM_THM_ABS5, 7) + RELOC_NUMBER (R_ARM_THM_CALL, 8) + RELOC_NUMBER (R_ARM_SBREL32, 9) + RELOC_NUMBER (R_ARM_BREL_ADJ, 10) + RELOC_NUMBER (R_ARM_THM_JUMP11, 11) + RELOC_NUMBER (R_ARM_THM_JUMP8, 12) + RELOC_NUMBER (R_ARM_GNU_VTINHERIT, 13) + RELOC_NUMBER (R_ARM_GNU_VTENTRY, 14) +#endif + RELOC_NUMBER (R_ARM_XPC25, 15) /* obsolete */ + RELOC_NUMBER (R_ARM_THM_XPC22, 16) /* obsolete */ + RELOC_NUMBER (R_ARM_TLS_DTPMOD32, 17) + RELOC_NUMBER (R_ARM_TLS_DTPOFF32, 18) + RELOC_NUMBER (R_ARM_TLS_TPOFF32, 19) + RELOC_NUMBER (R_ARM_COPY, 20) /* Copy symbol at runtime. */ + RELOC_NUMBER (R_ARM_GLOB_DAT, 21) /* Create GOT entry. */ + RELOC_NUMBER (R_ARM_JUMP_SLOT, 22) /* Create PLT entry. */ + RELOC_NUMBER (R_ARM_RELATIVE, 23) /* Adjust by program base. */ + RELOC_NUMBER (R_ARM_GOTOFF32, 24) /* 32 bit offset to GOT. */ + RELOC_NUMBER (R_ARM_BASE_PREL, 25) /* 32 bit PC relative offset to GOT. */ + RELOC_NUMBER (R_ARM_GOT_BREL, 26) /* 32 bit GOT entry. */ + RELOC_NUMBER (R_ARM_PLT32, 27) /* deprecated - 32 bit PLT address. */ + RELOC_NUMBER (R_ARM_CALL, 28) + RELOC_NUMBER (R_ARM_JUMP24, 29) + RELOC_NUMBER (R_ARM_THM_JUMP24, 30) + RELOC_NUMBER (R_ARM_BASE_ABS, 31) + RELOC_NUMBER (R_ARM_ALU_PCREL7_0, 32) /* obsolete */ + RELOC_NUMBER (R_ARM_ALU_PCREL15_8, 33) /* obsolete */ + RELOC_NUMBER (R_ARM_ALU_PCREL23_15, 34) /* obsolete */ + RELOC_NUMBER (R_ARM_LDR_SBREL_11_0, 35) /* deprecated, should have _NC suffix */ + RELOC_NUMBER (R_ARM_ALU_SBREL_19_12, 36) /* deprecated, should have _NC suffix */ + RELOC_NUMBER (R_ARM_ALU_SBREL_27_20, 37) /* deprecated, should have _CK suffix */ + RELOC_NUMBER (R_ARM_TARGET1, 38) + RELOC_NUMBER (R_ARM_SBREL31, 39) /* deprecated */ + RELOC_NUMBER (R_ARM_V4BX, 40) + RELOC_NUMBER (R_ARM_TARGET2, 41) + RELOC_NUMBER (R_ARM_PREL31, 42) + RELOC_NUMBER (R_ARM_MOVW_ABS_NC, 43) + RELOC_NUMBER (R_ARM_MOVT_ABS, 44) + RELOC_NUMBER (R_ARM_MOVW_PREL_NC, 45) + RELOC_NUMBER (R_ARM_MOVT_PREL, 46) + RELOC_NUMBER (R_ARM_THM_MOVW_ABS_NC, 47) + RELOC_NUMBER (R_ARM_THM_MOVT_ABS, 48) + RELOC_NUMBER (R_ARM_THM_MOVW_PREL_NC, 49) + RELOC_NUMBER (R_ARM_THM_MOVT_PREL, 50) + RELOC_NUMBER (R_ARM_THM_JUMP19, 51) + RELOC_NUMBER (R_ARM_THM_JUMP6, 52) + RELOC_NUMBER (R_ARM_THM_ALU_PREL_11_0, 53) + RELOC_NUMBER (R_ARM_THM_PC12, 54) + RELOC_NUMBER (R_ARM_ABS32_NOI, 55) + RELOC_NUMBER (R_ARM_REL32_NOI, 56) + RELOC_NUMBER (R_ARM_ALU_PC_G0_NC, 57) + RELOC_NUMBER (R_ARM_ALU_PC_G0, 58) + RELOC_NUMBER (R_ARM_ALU_PC_G1_NC, 59) + RELOC_NUMBER (R_ARM_ALU_PC_G1, 60) + RELOC_NUMBER (R_ARM_ALU_PC_G2, 61) + RELOC_NUMBER (R_ARM_LDR_PC_G1, 62) + RELOC_NUMBER (R_ARM_LDR_PC_G2, 63) + RELOC_NUMBER (R_ARM_LDRS_PC_G0, 64) + RELOC_NUMBER (R_ARM_LDRS_PC_G1, 65) + RELOC_NUMBER (R_ARM_LDRS_PC_G2, 66) + RELOC_NUMBER (R_ARM_LDC_PC_G0, 67) + RELOC_NUMBER (R_ARM_LDC_PC_G1, 68) + RELOC_NUMBER (R_ARM_LDC_PC_G2, 69) + RELOC_NUMBER (R_ARM_ALU_SB_G0_NC, 70) + RELOC_NUMBER (R_ARM_ALU_SB_G0, 71) + RELOC_NUMBER (R_ARM_ALU_SB_G1_NC, 72) + RELOC_NUMBER (R_ARM_ALU_SB_G1, 73) + RELOC_NUMBER (R_ARM_ALU_SB_G2, 74) + RELOC_NUMBER (R_ARM_LDR_SB_G0, 75) + RELOC_NUMBER (R_ARM_LDR_SB_G1, 76) + RELOC_NUMBER (R_ARM_LDR_SB_G2, 77) + RELOC_NUMBER (R_ARM_LDRS_SB_G0, 78) + RELOC_NUMBER (R_ARM_LDRS_SB_G1, 79) + RELOC_NUMBER (R_ARM_LDRS_SB_G2, 80) + RELOC_NUMBER (R_ARM_LDC_G0, 81) + RELOC_NUMBER (R_ARM_LDC_G1, 82) + RELOC_NUMBER (R_ARM_LDC_G2, 83) + RELOC_NUMBER (R_ARM_MOVW_BREL_NC, 84) + RELOC_NUMBER (R_ARM_MOVT_BREL, 85) + RELOC_NUMBER (R_ARM_MOVW_BREL, 86) + RELOC_NUMBER (R_ARM_THM_MOVW_BREL_NC, 87) + RELOC_NUMBER (R_ARM_THM_MOVT_BREL, 88) + RELOC_NUMBER (R_ARM_THM_MOVW_BREL, 89) + /* 90-93 unallocated */ + RELOC_NUMBER (R_ARM_PLT32_ABS, 94) + RELOC_NUMBER (R_ARM_GOT_ABS, 95) + RELOC_NUMBER (R_ARM_GOT_PREL, 96) + RELOC_NUMBER (R_ARM_GOT_BREL12, 97) + RELOC_NUMBER (R_ARM_GOTOFF12, 98) + RELOC_NUMBER (R_ARM_GOTRELAX, 99) +#ifndef OLD_ARM_ABI + RELOC_NUMBER (R_ARM_GNU_VTENTRY, 100) /* deprecated - old C++ abi */ + RELOC_NUMBER (R_ARM_GNU_VTINHERIT, 101) /* deprecated - old C++ abi */ + RELOC_NUMBER (R_ARM_THM_JUMP11, 102) + RELOC_NUMBER (R_ARM_THM_JUMP8, 103) +#endif + RELOC_NUMBER (R_ARM_TLS_GD32, 104) + RELOC_NUMBER (R_ARM_TLS_LDM32, 105) + RELOC_NUMBER (R_ARM_TLS_LDO32, 106) + RELOC_NUMBER (R_ARM_TLS_IE32, 107) + RELOC_NUMBER (R_ARM_TLS_LE32, 108) + RELOC_NUMBER (R_ARM_TLS_LDO12, 109) + RELOC_NUMBER (R_ARM_TLS_LE12, 110) + RELOC_NUMBER (R_ARM_TLS_IE12GP, 111) + /* 112 - 127 private range */ + RELOC_NUMBER (R_ARM_ME_TOO, 128) /* obsolete */ + + /* Extensions? R=read-only? */ + RELOC_NUMBER (R_ARM_RXPC25, 249) + RELOC_NUMBER (R_ARM_RSBREL32, 250) + RELOC_NUMBER (R_ARM_THM_RPC22, 251) + RELOC_NUMBER (R_ARM_RREL32, 252) + RELOC_NUMBER (R_ARM_RABS32, 253) + RELOC_NUMBER (R_ARM_RPC24, 254) + RELOC_NUMBER (R_ARM_RBASE, 255) + + /* Unofficial names for some of the relocs. */ + FAKE_RELOC (R_ARM_GOTOFF, R_ARM_GOTOFF32) /* 32 bit offset to GOT. */ + FAKE_RELOC (R_ARM_THM_PC22, R_ARM_THM_CALL) + FAKE_RELOC (R_ARM_THM_PC11, R_ARM_THM_JUMP11) + FAKE_RELOC (R_ARM_THM_PC9, R_ARM_THM_JUMP8) + + /* Relocs with both a different name, and (apparently) different meaning in + GNU usage. */ + FAKE_RELOC (R_ARM_GOTPC, R_ARM_BASE_PREL) /* 32 bit PC relative offset to GOT. */ + FAKE_RELOC (R_ARM_GOT32, R_ARM_GOT_BREL) /* 32 bit GOT entry. */ + FAKE_RELOC (R_ARM_ROSEGREL32, R_ARM_SBREL31) /* ??? */ + FAKE_RELOC (R_ARM_AMP_VCALL9, R_ARM_BREL_ADJ) /* Thumb-something. Not used. */ +#ifndef OLD_ARM_ABI + FAKE_RELOC (R_ARM_PC13, R_ARM_LDR_PC_G0) /* Unclear whether meaning is different. */ +#endif END_RELOC_NUMBERS (R_ARM_max) /* The name of the note section used to identify arm variants. */ diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index a87bcc0b2f8..bb377a8ef82 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -98,13 +98,14 @@ Thumb specific format options: %M print Thumb register mask %N print Thumb register mask (with LR) %O print Thumb register mask (with PC) - %T print Thumb condition code (always bits 8-11) %I print cirrus signed shift immediate: bits 0..3|4..6 %<bitfield>B print Thumb branch destination (signed displacement) %<bitfield>W print (bitfield * 4) as a decimal %<bitfield>H print (bitfield * 2) as a decimal %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol - %e print arm SMI operand (bits 0..7,8..19). */ + %<bitfield>c print bitfield as a condition code + %e print arm SMI operand (bits 0..7,8..19). + %s print Thumb right-shift immediate (6..10; 0 == 32). */ /* Note: There is a partial ordering in this table - it must be searched from the top to obtain a correct match. */ @@ -641,11 +642,23 @@ static const struct thumb_opcode thumb_opcodes[] = {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe"}, {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi"}, {ARM_EXT_V6K, 0xbf40, 0xffff, "sev"}, + {ARM_EXT_V6K, 0xbf00, 0xff0f, "nop\t{%4-7d}"}, + + /* ARM V6T2 instructions. */ + {ARM_EXT_V6T2, 0xb900, 0xfd00, "czbne\t%0-2r, %b"}, + {ARM_EXT_V6T2, 0xb100, 0xfd00, "czbeq\t%0-2r, %b"}, + {ARM_EXT_V6T2, 0xbf08, 0xff0f, "it\t%4-7c"}, + {ARM_EXT_V6T2, 0xbf14, 0xff17, "it%3?te\t%4-7c"}, + {ARM_EXT_V6T2, 0xbf04, 0xff17, "it%3?et\t%4-7c"}, + {ARM_EXT_V6T2, 0xbf12, 0xff13, "it%3?te%2?te\t%4-7c"}, + {ARM_EXT_V6T2, 0xbf02, 0xff13, "it%3?et%2?et\t%4-7c"}, + {ARM_EXT_V6T2, 0xbf11, 0xff11, "it%3?te%2?te%1?te\t%4-7c"}, + {ARM_EXT_V6T2, 0xbf01, 0xff11, "it%3?et%2?et%1?et\t%4-7c"}, /* ARM V6. */ {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f"}, {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f"}, - {ARM_EXT_V6, 0x4600, 0xffc0, "cpy\t%0-2r, %3-5r"}, + {ARM_EXT_V6, 0x4600, 0xffc0, "mov\t%0-2r, %3-5r"}, {ARM_EXT_V6, 0xba00, 0xffc0, "rev\t%0-2r, %3-5r"}, {ARM_EXT_V6, 0xba40, 0xffc0, "rev16\t%0-2r, %3-5r"}, {ARM_EXT_V6, 0xbac0, 0xffc0, "revsh\t%0-2r, %3-5r"}, @@ -657,34 +670,27 @@ static const struct thumb_opcode thumb_opcodes[] = /* ARM V5 ISA extends Thumb. */ {ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"}, - /* Note: this is BLX(2). BLX(1) is done in arm-dis.c/print_insn_thumb() - as an extension of the special processing there for Thumb BL. - BL and BLX(1) involve 2 successive 16-bit instructions, which must - always appear together in the correct order. So, the empty - string is put in this table, and the string interpreter takes <empty> - to mean it has a pair of BL-ish instructions. */ + /* This is BLX(2). BLX(1) is a 32-bit instruction. */ {ARM_EXT_V5T, 0x4780, 0xff87, "blx\t%3-6r"}, /* note: 4 bit register number. */ /* ARM V4T ISA (Thumb v1). */ {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop\t\t\t(mov r8, r8)"}, - /* Format 5 instructions do not update the PSR. */ - {ARM_EXT_V4T, 0x1C00, 0xFFC0, "mov\t%0-2r, %3-5r\t\t(add %0-2r, %3-5r, #%6-8d)"}, /* Format 4. */ - {ARM_EXT_V4T, 0x4000, 0xFFC0, "and\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4040, 0xFFC0, "eor\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsl\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsr\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4100, 0xFFC0, "asr\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4140, 0xFFC0, "adc\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4180, 0xFFC0, "sbc\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x41C0, 0xFFC0, "ror\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4000, 0xFFC0, "ands\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4040, 0xFFC0, "eors\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsls\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsrs\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4100, 0xFFC0, "asrs\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4140, 0xFFC0, "adcs\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4180, 0xFFC0, "sbcs\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x41C0, 0xFFC0, "rors\t%0-2r, %3-5r"}, {ARM_EXT_V4T, 0x4200, 0xFFC0, "tst\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4240, 0xFFC0, "neg\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4240, 0xFFC0, "negs\t%0-2r, %3-5r"}, {ARM_EXT_V4T, 0x4280, 0xFFC0, "cmp\t%0-2r, %3-5r"}, {ARM_EXT_V4T, 0x42C0, 0xFFC0, "cmn\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4300, 0xFFC0, "orr\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4340, 0xFFC0, "mul\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4380, 0xFFC0, "bic\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x43C0, 0xFFC0, "mvn\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4300, 0xFFC0, "orrs\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4340, 0xFFC0, "muls\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4380, 0xFFC0, "bics\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x43C0, 0xFFC0, "mvns\t%0-2r, %3-5r"}, /* format 13 */ {ARM_EXT_V4T, 0xB000, 0xFF80, "add\tsp, #%0-6W"}, {ARM_EXT_V4T, 0xB080, 0xFF80, "sub\tsp, #%0-6W"}, @@ -697,9 +703,9 @@ static const struct thumb_opcode thumb_opcodes[] = {ARM_EXT_V4T, 0xB400, 0xFE00, "push\t%N"}, {ARM_EXT_V4T, 0xBC00, 0xFE00, "pop\t%O"}, /* format 2 */ - {ARM_EXT_V4T, 0x1800, 0xFE00, "add\t%0-2r, %3-5r, %6-8r"}, + {ARM_EXT_V4T, 0x1800, 0xFE00, "adds\t%0-2r, %3-5r, %6-8r"}, {ARM_EXT_V4T, 0x1A00, 0xFE00, "sub\t%0-2r, %3-5r, %6-8r"}, - {ARM_EXT_V4T, 0x1C00, 0xFE00, "add\t%0-2r, %3-5r, #%6-8d"}, + {ARM_EXT_V4T, 0x1C00, 0xFE00, "adds\t%0-2r, %3-5r, #%6-8d"}, {ARM_EXT_V4T, 0x1E00, 0xFE00, "sub\t%0-2r, %3-5r, #%6-8d"}, /* format 8 */ {ARM_EXT_V4T, 0x5200, 0xFE00, "strh\t%0-2r, [%3-5r, %6-8r]"}, @@ -709,14 +715,14 @@ static const struct thumb_opcode thumb_opcodes[] = {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b\t%0-2r, [%3-5r, %6-8r]"}, {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b\t%0-2r, [%3-5r, %6-8r]"}, /* format 1 */ - {ARM_EXT_V4T, 0x0000, 0xF800, "lsl\t%0-2r, %3-5r, #%6-10d"}, - {ARM_EXT_V4T, 0x0800, 0xF800, "lsr\t%0-2r, %3-5r, #%6-10d"}, - {ARM_EXT_V4T, 0x1000, 0xF800, "asr\t%0-2r, %3-5r, #%6-10d"}, + {ARM_EXT_V4T, 0x0000, 0xF800, "lsls\t%0-2r, %3-5r, #%6-10d"}, + {ARM_EXT_V4T, 0x0800, 0xF800, "lsrs\t%0-2r, %3-5r, %s"}, + {ARM_EXT_V4T, 0x1000, 0xF800, "asrs\t%0-2r, %3-5r, %s"}, /* format 3 */ - {ARM_EXT_V4T, 0x2000, 0xF800, "mov\t%8-10r, #%0-7d"}, + {ARM_EXT_V4T, 0x2000, 0xF800, "movs\t%8-10r, #%0-7d"}, {ARM_EXT_V4T, 0x2800, 0xF800, "cmp\t%8-10r, #%0-7d"}, - {ARM_EXT_V4T, 0x3000, 0xF800, "add\t%8-10r, #%0-7d"}, - {ARM_EXT_V4T, 0x3800, 0xF800, "sub\t%8-10r, #%0-7d"}, + {ARM_EXT_V4T, 0x3000, 0xF800, "adds\t%8-10r, #%0-7d"}, + {ARM_EXT_V4T, 0x3800, 0xF800, "subs\t%8-10r, #%0-7d"}, /* format 6 */ {ARM_EXT_V4T, 0x4800, 0xF800, "ldr\t%8-10r, [pc, #%0-7W]\t(%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */ /* format 9 */ @@ -734,45 +740,275 @@ static const struct thumb_opcode thumb_opcodes[] = {ARM_EXT_V4T, 0xA000, 0xF800, "add\t%8-10r, pc, #%0-7W\t(adr %8-10r,%0-7a)"}, {ARM_EXT_V4T, 0xA800, 0xF800, "add\t%8-10r, sp, #%0-7W"}, /* format 15 */ - {ARM_EXT_V4T, 0xC000, 0xF800, "stmia\t%8-10r!,%M"}, - {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia\t%8-10r!,%M"}, - /* format 18 */ - {ARM_EXT_V4T, 0xE000, 0xF800, "b\t%0-10B"}, - {ARM_EXT_V4T, 0xE800, 0xF800, "undefined"}, - /* format 19 */ - {ARM_EXT_V4T, 0xF000, 0xF800, ""}, /* special processing required in disassembler */ - {ARM_EXT_V4T, 0xF800, 0xF800, "second half of BL instruction %0-15x"}, - /* format 16 */ - {ARM_EXT_V4T, 0xD000, 0xFF00, "beq\t%0-7B"}, - {ARM_EXT_V4T, 0xD100, 0xFF00, "bne\t%0-7B"}, - {ARM_EXT_V4T, 0xD200, 0xFF00, "bcs\t%0-7B"}, - {ARM_EXT_V4T, 0xD300, 0xFF00, "bcc\t%0-7B"}, - {ARM_EXT_V4T, 0xD400, 0xFF00, "bmi\t%0-7B"}, - {ARM_EXT_V4T, 0xD500, 0xFF00, "bpl\t%0-7B"}, - {ARM_EXT_V4T, 0xD600, 0xFF00, "bvs\t%0-7B"}, - {ARM_EXT_V4T, 0xD700, 0xFF00, "bvc\t%0-7B"}, - {ARM_EXT_V4T, 0xD800, 0xFF00, "bhi\t%0-7B"}, - {ARM_EXT_V4T, 0xD900, 0xFF00, "bls\t%0-7B"}, - {ARM_EXT_V4T, 0xDA00, 0xFF00, "bge\t%0-7B"}, - {ARM_EXT_V4T, 0xDB00, 0xFF00, "blt\t%0-7B"}, - {ARM_EXT_V4T, 0xDC00, 0xFF00, "bgt\t%0-7B"}, - {ARM_EXT_V4T, 0xDD00, 0xFF00, "ble\t%0-7B"}, + {ARM_EXT_V4T, 0xC000, 0xF800, "stmia\t%8-10r!, %M"}, + {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia\t%8-10r!, %M"}, /* format 17 */ - {ARM_EXT_V4T, 0xDE00, 0xFF00, "bal\t%0-7B"}, {ARM_EXT_V4T, 0xDF00, 0xFF00, "swi\t%0-7d"}, - /* format 9 */ - {ARM_EXT_V4T, 0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"}, - {ARM_EXT_V4T, 0x6800, 0xF800, "ldr\t%0-2r, [%3-5r, #%6-10W]"}, - {ARM_EXT_V4T, 0x7000, 0xF800, "strb\t%0-2r, [%3-5r, #%6-10d]"}, - {ARM_EXT_V4T, 0x7800, 0xF800, "ldrb\t%0-2r, [%3-5r, #%6-10d]"}, - /* the rest */ - {ARM_EXT_V1, 0x0000, 0x0000, "undefined instruction %0-15x"}, - {0, 0x0000, 0x0000, 0} + /* format 16 */ + {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B"}, + /* format 18 */ + {ARM_EXT_V4T, 0xE000, 0xF800, "b.n\t%0-10B"}, + + /* The E800 .. FFFF range is unconditionally redirected to the + 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs + are processed via that table. Thus, we can never encounter a + bare "second half of BL/BLX(1)" instruction here. */ + {ARM_EXT_V1, 0x0000, 0x0000, "undefined"}, + {0, 0, 0, 0} +}; + +/* Thumb32 opcodes use the same table structure as the ARM opcodes. + We adopt the convention that hw1 is the high 16 bits of .value and + .mask, hw2 the low 16 bits. + + %-escapes defined for these instructions: + + %% % + %<bitfield>d print bitfield in decimal + %<bitfield>W print bitfield*4 in decimal + %<bitfield>r print bitfield as an ARM register + %<bitfield>c print bitfield as a condition code + + %<bitnum>'c print "c" iff bit is one + %<bitnum>`c print "c" iff bit is zero + %<bitnum>?ab print "a" if bit is one, else "b" + + %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0] + %M print a modified 12-bit immediate (same location) + %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0] + %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4] + %S print a possibly-shifted Rm + + %a print the address of a plain load/store + %A print the address of a coprocessor load/store + %w print the width and signedness of a core load/store + %m print register mask for ldm/stm + + %E print the lsb and width fields of a bfc/bfi instruction + %F print the lsb and width fields of a sbfx/ubfx instruction + %B print an unconditional branch offset + %b print a conditional branch offset + %s print the shift field of an SSAT instruction + %R print the rotation field of an SXT instruction + + With one exception at the bottom (done because BL and BLX(1) need + to come dead last), this table was machine-sorted first in + decreasing order of number of bits set in the mask, then in + increasing numeric order of mask, then in increasing numeric order + of opcode. This order is not the clearest for a human reader, but + is guaranteed never to catch a special-case bit pattern with a more + general mask, which is important, because this instruction encoding + makes heavy use of special-case bit patterns. */ +static const struct arm_opcode thumb32_opcodes[] = +{ + /* Instructions defined in the basic V6T2 set. */ + {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop.w"}, + {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield.w"}, + {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe.w"}, + {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi.w"}, + {ARM_EXT_V6T2, 0xf3af9004, 0xffffffff, "sev.w"}, + {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop.w\t{%0-7d}"}, + + {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex"}, + {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f"}, + {ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f"}, + {ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj\t%16-19r"}, + {ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb\t%16-19r%21'!"}, + {ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia\t%16-19r%21'!"}, + {ARM_EXT_V6T2, 0xf3ef8000, 0xffeff0ff, "mrs\t%8-11r, %20?CSPSR"}, + {ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d"}, + {ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "tbb\t[%16-19r, %0-3r]"}, + {ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "tbh\t[%16-19r, %0-3r]"}, + {ARM_EXT_V6T2, 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d"}, + {ARM_EXT_V6T2, 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d"}, + {ARM_EXT_V6T2, 0xf3de8f00, 0xffffff00, "subs\tpc, lr, #%0-7d"}, + {ARM_EXT_V6T2, 0xf3808000, 0xffe0f0ff, "msr\t%20?CSPSR_%8'c%9'x%10's%11'f, %16-19r"}, + {ARM_EXT_V6T2, 0xe8500f00, 0xfff00fff, "ldrex\t%12-15r, [%16-19r]"}, + {ARM_EXT_V6T2, 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb\t%12-15r, [%16-19r]"}, + {ARM_EXT_V6T2, 0xe800c000, 0xffd0ffe0, "srsdb\t#%0-4d%21'!"}, + {ARM_EXT_V6T2, 0xe980c000, 0xffd0ffe0, "srsia\t#%0-4d%21'!"}, + {ARM_EXT_V6T2, 0xfa0ff080, 0xfffff0c0, "sxth.w\t%8-11r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa1ff080, 0xfffff0c0, "uxth.w\t%8-11r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa2ff080, 0xfffff0c0, "sxtb16\t%8-11r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa3ff080, 0xfffff0c0, "uxtb16\t%8-11r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa4ff080, 0xfffff0c0, "sxtb.w\t%8-11r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa5ff080, 0xfffff0c0, "uxtb.w\t%8-11r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xe8400000, 0xfff000ff, "strex\t%8-11r, %12-15r, [%16-19r]"}, + {ARM_EXT_V6T2, 0xe8d0007f, 0xfff000ff, "ldrexd\t%12-15r, %8-11r, [%16-19r]"}, + {ARM_EXT_V6T2, 0xfa80f000, 0xfff0f0f0, "sadd8\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa80f010, 0xfff0f0f0, "qadd8\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa80f020, 0xfff0f0f0, "shadd8\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd\t%8-11r, %0-3r, %16-19r"}, + {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd\t%8-11r, %0-3r, %16-19r"}, + {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub\t%8-11r, %0-3r, %16-19r"}, + {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub\t%8-11r, %0-3r, %16-19r"}, + {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa90f040, 0xfff0f0f0, "uadd16\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa90f050, 0xfff0f0f0, "uqadd16\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa90f060, 0xfff0f0f0, "uhadd16\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa90f080, 0xfff0f0f0, "rev.w\t%8-11r, %16-19r"}, + {ARM_EXT_V6T2, 0xfa90f090, 0xfff0f0f0, "rev16.w\t%8-11r, %16-19r"}, + {ARM_EXT_V6T2, 0xfa90f0a0, 0xfff0f0f0, "rbit\t%8-11r, %16-19r"}, + {ARM_EXT_V6T2, 0xfa90f0b0, 0xfff0f0f0, "revsh.w\t%8-11r, %16-19r"}, + {ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "saddsubx\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qaddsubx\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shaddsubx\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uaddsubx\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqaddsubx\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhaddsubx\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f080, 0xfff0f0f0, "sel\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfab0f080, 0xfff0f0f0, "clz\t%8-11r, %16-19r"}, + {ARM_EXT_V6T2, 0xfac0f000, 0xfff0f0f0, "ssub8\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfac0f010, 0xfff0f0f0, "qsub8\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfac0f020, 0xfff0f0f0, "shsub8\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfac0f040, 0xfff0f0f0, "usub8\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfac0f050, 0xfff0f0f0, "uqsub8\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfac0f060, 0xfff0f0f0, "uhsub8\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfad0f000, 0xfff0f0f0, "ssub16\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfad0f010, 0xfff0f0f0, "qsub16\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfad0f020, 0xfff0f0f0, "shsub16\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfad0f040, 0xfff0f0f0, "usub16\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfad0f050, 0xfff0f0f0, "uqsub16\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfad0f060, 0xfff0f0f0, "uhsub16\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssubaddx\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsubaddx\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsubaddx\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usubaddx\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsubaddx\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsubaddx\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfb00f000, 0xfff0f0f0, "mul.w\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfb70f000, 0xfff0f0f0, "usad8\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa00f000, 0xffe0f0f0, "lsl%20's.w\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa20f000, 0xffe0f0f0, "lsr%20's.w\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa40f000, 0xffe0f0f0, "asr%20's.w\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa60f000, 0xffe0f0f0, "ror%20's.w\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xe8c00f40, 0xfff00fe0, "strex%4?hb\t%0-3r, %12-15r, [%16-19r]"}, + {ARM_EXT_V6T2, 0xf3200000, 0xfff0f0e0, "ssat16\t%8-11r, #%0-4d, %16-19r"}, + {ARM_EXT_V6T2, 0xf3a00000, 0xfff0f0e0, "usat16\t%8-11r, #%0-4d, %16-19r"}, + {ARM_EXT_V6T2, 0xfb20f000, 0xfff0f0e0, "smuad%4'x\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfb30f000, 0xfff0f0e0, "smulw%4?tb\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfb40f000, 0xfff0f0e0, "smusd%4'x\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfb50f000, 0xfff0f0e0, "smmul%4'r\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa00f080, 0xfff0f0c0, "sxtah\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa10f080, 0xfff0f0c0, "uxtah\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa20f080, 0xfff0f0c0, "sxtab16\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa30f080, 0xfff0f0c0, "uxtab16\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa40f080, 0xfff0f0c0, "sxtab\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa50f080, 0xfff0f0c0, "uxtab\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xf36f0000, 0xffff8020, "bfc\t%8-11r, %E"}, + {ARM_EXT_V6T2, 0xea100f00, 0xfff08f00, "tst.w\t%16-19r, %S"}, + {ARM_EXT_V6T2, 0xea900f00, 0xfff08f00, "teq\t%16-19r, %S"}, + {ARM_EXT_V6T2, 0xeb100f00, 0xfff08f00, "cmn.w\t%16-19r, %S"}, + {ARM_EXT_V6T2, 0xebb00f00, 0xfff08f00, "cmp.w\t%16-19r, %S"}, + {ARM_EXT_V6T2, 0xf0100f00, 0xfbf08f00, "tst.w\t%16-19r, %M"}, + {ARM_EXT_V6T2, 0xf0900f00, 0xfbf08f00, "teq\t%16-19r, %M"}, + {ARM_EXT_V6T2, 0xf1100f00, 0xfbf08f00, "cmn.w\t%16-19r, %M"}, + {ARM_EXT_V6T2, 0xf1b00f00, 0xfbf08f00, "cmp.w\t%16-19r, %M"}, + {ARM_EXT_V6T2, 0xea4f0000, 0xffef8000, "mov%20's.w\t%8-11r, %S"}, + {ARM_EXT_V6T2, 0xea6f0000, 0xffef8000, "mvn%20's.w\t%8-11r, %S"}, + {ARM_EXT_V6T2, 0xe8c00070, 0xfff000f0, "strexd\t%0-3r, %12-15r, %8-11r, [%16-19r]"}, + {ARM_EXT_V6T2, 0xfb000000, 0xfff000f0, "mla\t%8-11r, %16-19r, %0-3r, %12-15r"}, + {ARM_EXT_V6T2, 0xfb000010, 0xfff000f0, "mls\t%8-11r, %16-19r, %0-3r, %12-15r"}, + {ARM_EXT_V6T2, 0xfb700000, 0xfff000f0, "usada8\t%8-11r, %16-19r, %0-3r, %12-15r"}, + {ARM_EXT_V6T2, 0xfb800000, 0xfff000f0, "smull\t%12-15r, %8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfba00000, 0xfff000f0, "umull\t%12-15r, %8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfbc00000, 0xfff000f0, "smlal\t%12-15r, %8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "umlal\t%12-15r, %8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal\t%12-15r, %8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xe8500f00, 0xfff00f00, "ldrex\t%12-15r, [%16-19r, #%0-7W]"}, + {ARM_EXT_V6T2, 0xf7f08000, 0xfff0f000, "smi\t%K"}, + {ARM_EXT_V6T2, 0xf04f0000, 0xfbef8000, "mov%20's.w\t%8-11r, %M"}, + {ARM_EXT_V6T2, 0xf06f0000, 0xfbef8000, "mvn%20's.w\t%8-11r, %M"}, + {ARM_EXT_V6T2, 0xf810f000, 0xff70f000, "pld\t%a"}, + {ARM_EXT_V6T2, 0xfb200000, 0xfff000e0, "smlad%4'x\t%8-11r, %16-19r, %0-3r, %12-15r"}, + {ARM_EXT_V6T2, 0xfb300000, 0xfff000e0, "smlaw%4?tb\t%8-11r, %16-19r, %0-3r, %12-15r"}, + {ARM_EXT_V6T2, 0xfb400000, 0xfff000e0, "smlsd%4'x\t%8-11r, %16-19r, %0-3r, %12-15r"}, + {ARM_EXT_V6T2, 0xfb500000, 0xfff000e0, "smmla%4'r\t%8-11r, %16-19r, %0-3r, %12-15r"}, + {ARM_EXT_V6T2, 0xfb600000, 0xfff000e0, "smmls%4'r\t%8-11r, %16-19r, %0-3r, %12-15r"}, + {ARM_EXT_V6T2, 0xfbc000c0, 0xfff000e0, "smlald%4'x\t%12-15r, %8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfbd000c0, 0xfff000e0, "smlsld%4'x\t%12-15r, %8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xeac00000, 0xfff08030, "pkhbt\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xeac00020, 0xfff08030, "pkhtb\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xf3400000, 0xfff08020, "sbfx\t%8-11r, %16-19r, %F"}, + {ARM_EXT_V6T2, 0xf3c00000, 0xfff08020, "ubfx\t%8-11r, %16-19r, %F"}, + {ARM_EXT_V6T2, 0xf8000e00, 0xff900f00, "str%wt\t%12-15r, %a"}, + {ARM_EXT_V6T2, 0xfb100000, 0xfff000c0, "smla%5?tb%4?tb\t%8-11r, %16-19r, %0-3r, %12-15r"}, + {ARM_EXT_V6T2, 0xfbc00080, 0xfff000c0, "smlal%5?tb%4?tb\t%12-15r, %8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xf3600000, 0xfff08020, "bfi\t%8-11r, %16-19r, %E"}, + {ARM_EXT_V6T2, 0xf8100e00, 0xfe900f00, "ldr%wt\t%12-15r, %a"}, + {ARM_EXT_V6T2, 0xf3000000, 0xffd08020, "ssat\t%8-11r, #%0-4d, %16-19r%s"}, + {ARM_EXT_V6T2, 0xf3800000, 0xffd08020, "usat\t%8-11r, #%0-4d, %16-19r%s"}, + {ARM_EXT_V6T2, 0xee000010, 0xef1000f0, "mcr%28'2\tp%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d"}, + {ARM_EXT_V6T2, 0xee100010, 0xef1000f0, "mrc%28'2\tp%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d"}, + {ARM_EXT_V6T2, 0xf2000000, 0xfbf08000, "addw\t%8-11r, %16-19r, %I"}, + {ARM_EXT_V6T2, 0xf2400000, 0xfbf08000, "movw\t%8-11r, %J"}, + {ARM_EXT_V6T2, 0xf2a00000, 0xfbf08000, "subw\t%8-11r, %16-19r, %I"}, + {ARM_EXT_V6T2, 0xf2c00000, 0xfbf08000, "movt\t%8-11r, %J"}, + {ARM_EXT_V6T2, 0xea000000, 0xffe08000, "and%20's.w\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xea200000, 0xffe08000, "bic%20's.w\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xea400000, 0xffe08000, "orr%20's.w\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xea600000, 0xffe08000, "orn%20's\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xea800000, 0xffe08000, "eor%20's.w\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xeb000000, 0xffe08000, "add%20's.w\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xeb400000, 0xffe08000, "adc%20's.w\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xeb600000, 0xffe08000, "sbc%20's.w\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xeba00000, 0xffe08000, "sub%20's.w\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xebc00000, 0xffe08000, "rsb%20's\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xe8400000, 0xfff00000, "strex\t%8-11r, %12-15r, [%16-19r, #%0-7W]"}, + {ARM_EXT_V6T2, 0xee000000, 0xef0000f0, "cdp%28'2\tp%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d"}, + {ARM_EXT_V6T2, 0xec400000, 0xeff00000, "mcrr%28'2\tp%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, + {ARM_EXT_V6T2, 0xec500000, 0xeff00000, "mrrc%28'2\tp%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, + {ARM_EXT_V6T2, 0xf0000000, 0xfbe08000, "and%20's.w\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xf0200000, 0xfbe08000, "bic%20's.w\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xf0400000, 0xfbe08000, "orr%20's.w\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xf0600000, 0xfbe08000, "orn%20's\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xf0800000, 0xfbe08000, "eor%20's.w\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xf1000000, 0xfbe08000, "add%20's.w\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xf1400000, 0xfbe08000, "adc%20's.w\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xf1600000, 0xfbe08000, "sbc%20's.w\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xf1a00000, 0xfbe08000, "sub%20's.w\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xf1c00000, 0xfbe08000, "rsb%20's\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xe8800000, 0xffd00000, "stmia.w\t%16-19r%21'!, %m"}, + {ARM_EXT_V6T2, 0xe8900000, 0xffd00000, "ldmia.w\t%16-19r%21'!, %m"}, + {ARM_EXT_V6T2, 0xe9000000, 0xffd00000, "stmdb\t%16-19r%21'!, %m"}, + {ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "ldmdb\t%16-19r%21'!, %m"}, + {ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "strd\t%12-15r, %8-11r, [%16-19r]"}, + {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd\t%12-15r, %8-11r, [%16-19r]"}, + {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]"}, + {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]"}, + {ARM_EXT_V6T2, 0xee000010, 0xef100010, "mcr%28'2\tp%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, %5-7d"}, + {ARM_EXT_V6T2, 0xee100010, 0xef100010, "mrc%28'2\tp%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, %5-7d"}, + {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w.w\t%12-15r, %a"}, + {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w.w\t%12-15r, %a"}, + {ARM_EXT_V6T2, 0xec000000, 0xee100000, "stc%28'2%22'l\tp%8-11d, cr%12-15d, %A"}, + {ARM_EXT_V6T2, 0xec100000, 0xee100000, "ldc%28'2%22'l\tp%8-11d, cr%12-15d, %A"}, + {ARM_EXT_V6T2, 0xee000000, 0xef000010, "cdp%28'2\tp%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, %5-7d"}, + + /* Filter out Bcc with cond=E or F, which are used for other instructions. */ + {ARM_EXT_V6T2, 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"}, + {ARM_EXT_V6T2, 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"}, + {ARM_EXT_V6T2, 0xf0008000, 0xf800d000, "b%22-25c.w\t%b"}, + {ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b.w\t%B"}, + + /* These have been 32-bit since the invention of Thumb. */ + {ARM_EXT_V4T, 0xf000c000, 0xf800d000, "blx\t%B"}, + {ARM_EXT_V4T, 0xf000d000, 0xf800d000, "bl\t%B"}, + + /* Fallback. */ + {ARM_EXT_V1, 0x00000000, 0x00000000, "undefined"}, + {0, 0, 0, 0} }; + static char * arm_conditional[] = {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", - "hi", "ls", "ge", "lt", "gt", "le", "", "nv"}; + "hi", "ls", "ge", "lt", "gt", "le", "", "<und>"}; typedef struct { @@ -831,7 +1067,9 @@ static void arm_decode_shift PARAMS ((long, fprintf_ftype, void *)); static int print_insn_arm PARAMS ((bfd_vma, struct disassemble_info *, long)); -static int print_insn_thumb +static int print_insn_thumb16 + PARAMS ((bfd_vma, struct disassemble_info *, long)); +static int print_insn_thumb32 PARAMS ((bfd_vma, struct disassemble_info *, long)); static void parse_disassembler_options PARAMS ((char *)); @@ -1683,7 +1921,7 @@ print_insn_arm (pc, info, given) Return the size of the instruction. */ static int -print_insn_thumb (pc, info, given) +print_insn_thumb16 (pc, info, given) bfd_vma pc; struct disassemble_info *info; long given; @@ -1693,228 +1931,617 @@ print_insn_thumb (pc, info, given) fprintf_ftype func = info->fprintf_func; for (insn = thumb_opcodes; insn->assembler; insn++) - { - if ((given & insn->mask) == insn->value) - { - char * c = insn->assembler; + if ((given & insn->mask) == insn->value) + { + char * c = insn->assembler; + for (; *c; c++) + { + int domaskpc = 0; + int domasklr = 0; + + if (*c != '%') + { + func (stream, "%c", *c); + continue; + } - /* Special processing for Thumb 2 instruction BL sequence: */ - if (!*c) /* Check for empty (not NULL) assembler string. */ - { - long offset; + switch (*++c) + { + case '%': + func (stream, "%%"); + break; - info->bytes_per_chunk = 4; - info->bytes_per_line = 4; + case 'S': + { + long reg; + + reg = (given >> 3) & 0x7; + if (given & (1 << 6)) + reg += 8; - offset = BDISP23 (given); - offset = offset * 2 + pc + 4; + func (stream, "%s", arm_regnames[reg]); + } + break; - if ((given & 0x10000000) == 0) + case 'D': { - func (stream, "blx\t"); - offset &= 0xfffffffc; + long reg; + + reg = given & 0x7; + if (given & (1 << 7)) + reg += 8; + + func (stream, "%s", arm_regnames[reg]); } - else - func (stream, "bl\t"); - - info->print_address_func (offset, info); - return 4; - } - else - { - info->bytes_per_chunk = 2; - info->bytes_per_line = 4; - - given &= 0xffff; - - for (; *c; c++) - { - if (*c == '%') - { - int domaskpc = 0; - int domasklr = 0; - - switch (*++c) - { - case '%': - func (stream, "%%"); - break; - - case 'S': - { - long reg; - - reg = (given >> 3) & 0x7; - if (given & (1 << 6)) - reg += 8; - - func (stream, "%s", arm_regnames[reg]); - } - break; - - case 'D': - { - long reg; - - reg = given & 0x7; - if (given & (1 << 7)) - reg += 8; - - func (stream, "%s", arm_regnames[reg]); - } - break; - - case 'T': - func (stream, "%s", - arm_conditional [(given >> 8) & 0xf]); - break; - - case 'N': - if (given & (1 << 8)) - domasklr = 1; - /* Fall through. */ - case 'O': - if (*c == 'O' && (given & (1 << 8))) - domaskpc = 1; - /* Fall through. */ - case 'M': - { - int started = 0; - int reg; - - func (stream, "{"); - - /* It would be nice if we could spot - ranges, and generate the rS-rE format: */ - for (reg = 0; (reg < 8); reg++) - if ((given & (1 << reg)) != 0) - { - if (started) - func (stream, ", "); - started = 1; - func (stream, "%s", arm_regnames[reg]); - } - - if (domasklr) - { - if (started) - func (stream, ", "); - started = 1; - func (stream, arm_regnames[14] /* "lr" */); - } - - if (domaskpc) - { - if (started) - func (stream, ", "); - func (stream, arm_regnames[15] /* "pc" */); - } - - func (stream, "}"); - } - break; - - - case '0': case '1': case '2': case '3': case '4': - case '5': case '6': case '7': case '8': case '9': - { - int bitstart = *c++ - '0'; - int bitend = 0; - - while (*c >= '0' && *c <= '9') - bitstart = (bitstart * 10) + *c++ - '0'; - - switch (*c) - { - case '-': - { - long reg; - - c++; - while (*c >= '0' && *c <= '9') - bitend = (bitend * 10) + *c++ - '0'; - if (!bitend) - abort (); - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - switch (*c) - { - case 'r': - func (stream, "%s", arm_regnames[reg]); - break; - - case 'd': - func (stream, "%d", reg); - break; - - case 'H': - func (stream, "%d", reg << 1); - break; - - case 'W': - func (stream, "%d", reg << 2); - break; - - case 'a': - /* PC-relative address -- the bottom two - bits of the address are dropped - before the calculation. */ - info->print_address_func - (((pc + 4) & ~3) + (reg << 2), info); - break; - - case 'x': - func (stream, "0x%04x", reg); - break; - - case 'I': - reg = ((reg ^ (1 << bitend)) - (1 << bitend)); - func (stream, "%d", reg); - break; - - case 'B': - reg = ((reg ^ (1 << bitend)) - (1 << bitend)); - (*info->print_address_func) - (reg * 2 + pc + 4, info); - break; - - default: - abort (); - } - } - break; - - case '\'': - c++; - if ((given & (1 << bitstart)) != 0) - func (stream, "%c", *c); - break; - - case '?': - ++c; - if ((given & (1 << bitstart)) != 0) - func (stream, "%c", *c++); - else - func (stream, "%c", *++c); - break; - - default: - abort (); - } - } - break; - - default: - abort (); - } - } - else - func (stream, "%c", *c); - } - } - return 2; - } - } + break; + + case 'N': + if (given & (1 << 8)) + domasklr = 1; + /* Fall through. */ + case 'O': + if (*c == 'O' && (given & (1 << 8))) + domaskpc = 1; + /* Fall through. */ + case 'M': + { + int started = 0; + int reg; + + func (stream, "{"); + + /* It would be nice if we could spot + ranges, and generate the rS-rE format: */ + for (reg = 0; (reg < 8); reg++) + if ((given & (1 << reg)) != 0) + { + if (started) + func (stream, ", "); + started = 1; + func (stream, "%s", arm_regnames[reg]); + } + + if (domasklr) + { + if (started) + func (stream, ", "); + started = 1; + func (stream, arm_regnames[14] /* "lr" */); + } + + if (domaskpc) + { + if (started) + func (stream, ", "); + func (stream, arm_regnames[15] /* "pc" */); + } + + func (stream, "}"); + } + break; + + case 'b': + /* Print ARM V6T2 CZB address: pc+4+6 bits. */ + { + bfd_vma address = (pc + 4 + + ((given & 0x00f8) >> 2) + + ((given & 0x0200) >> 3)); + info->print_address_func (address, info); + } + break; + + case 's': + /* Right shift immediate -- bits 6..10; 1-31 print + as themselves, 0 prints as 32. */ + { + long imm = (given & 0x07c0) >> 6; + if (imm == 0) + imm = 32; + func (stream, "#%d", imm); + } + break; + + case '0': case '1': case '2': case '3': case '4': + case '5': case '6': case '7': case '8': case '9': + { + int bitstart = *c++ - '0'; + int bitend = 0; + + while (*c >= '0' && *c <= '9') + bitstart = (bitstart * 10) + *c++ - '0'; + + switch (*c) + { + case '-': + { + long reg; + + c++; + while (*c >= '0' && *c <= '9') + bitend = (bitend * 10) + *c++ - '0'; + if (!bitend) + abort (); + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + switch (*c) + { + case 'r': + func (stream, "%s", arm_regnames[reg]); + break; + + case 'd': + func (stream, "%d", reg); + break; + + case 'H': + func (stream, "%d", reg << 1); + break; + + case 'W': + func (stream, "%d", reg << 2); + break; + + case 'a': + /* PC-relative address -- the bottom two + bits of the address are dropped + before the calculation. */ + info->print_address_func + (((pc + 4) & ~3) + (reg << 2), info); + break; + + case 'x': + func (stream, "0x%04x", reg); + break; + + case 'I': + reg = ((reg ^ (1 << bitend)) - (1 << bitend)); + func (stream, "%d", reg); + break; + + case 'B': + reg = ((reg ^ (1 << bitend)) - (1 << bitend)); + (*info->print_address_func) + (reg * 2 + pc + 4, info); + break; + + case 'c': + { + /* Must print 0xE as 'al' to distinguish + unconditional B from conditional BAL. */ + if (reg == 0xE) + func (stream, "al"); + else + func (stream, "%s", arm_conditional [reg]); + } + break; + + default: + abort (); + } + } + break; + + case '\'': + c++; + if ((given & (1 << bitstart)) != 0) + func (stream, "%c", *c); + break; + + case '?': + ++c; + if ((given & (1 << bitstart)) != 0) + func (stream, "%c", *c++); + else + func (stream, "%c", *++c); + break; + + default: + abort (); + } + } + break; + + default: + abort (); + } + } + return 2; + } + + /* No match. */ + abort (); +} + +static int +print_insn_thumb32 (pc, info, given) + bfd_vma pc; + struct disassemble_info *info; + long given; +{ + const struct arm_opcode *insn; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + for (insn = thumb32_opcodes; insn->assembler; insn++) + if ((given & insn->mask) == insn->value) + { + char * c = insn->assembler; + for (; *c; c++) + { + if (*c != '%') + { + func (stream, "%c", *c); + continue; + } + + switch (*++c) + { + case '%': + func (stream, "%%"); + break; + + case 'I': + { + unsigned int imm12 = 0; + imm12 |= (given & 0x000000ffu); + imm12 |= (given & 0x00007000u) >> 4; + imm12 |= (given & 0x04000000u) >> 12; + func (stream, "#%u\t; 0x%x", imm12, imm12); + } + break; + + case 'M': + { + unsigned int bits = 0, imm, imm8, mod; + bits |= (given & 0x000000ffu); + bits |= (given & 0x00007000u) >> 4; + bits |= (given & 0x04000000u) >> 15; + imm8 = (bits & 0x0ff); + mod = (bits & 0xf00) >> 8; + switch (mod) + { + case 0: imm = imm8; break; + case 1: imm = ((imm8<<16) | imm8); break; + case 2: imm = ((imm8<<24) | (imm8 << 8)); break; + case 3: imm = ((imm8<<24) | (imm8 << 16) | (imm8 << 8) | imm8); break; + default: + mod = (bits & 0xf80) >> 7; + imm8 = (bits & 0x07f) | 0x80; + imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff); + } + func (stream, "#%u\t; 0x%x", imm, imm); + } + break; + + case 'J': + { + unsigned int imm = 0; + imm |= (given & 0x000000ffu); + imm |= (given & 0x00007000u) >> 4; + imm |= (given & 0x04000000u) >> 15; + imm |= (given & 0x000f0000u) >> 4; + func (stream, "#%u\t; 0x%x", imm, imm); + } + break; + + case 'K': + { + unsigned int imm = 0; + imm |= (given & 0x000f0000u) >> 16; + imm |= (given & 0x00000ff0u) >> 0; + imm |= (given & 0x0000000fu) << 12; + func (stream, "#%u\t; 0x%x", imm, imm); + } + break; + + case 'S': + { + unsigned int reg = (given & 0x0000000fu); + unsigned int stp = (given & 0x00000030u) >> 4; + unsigned int imm = 0; + imm |= (given & 0x000000c0u) >> 6; + imm |= (given & 0x00007000u) >> 10; + + func (stream, "%s", arm_regnames[reg]); + switch (stp) + { + case 0: + if (imm > 0) + func (stream, ", lsl #%u", imm); + break; + + case 1: + if (imm == 0) + imm = 32; + func (stream, ", lsr #%u", imm); + break; + + case 2: + if (imm == 0) + imm = 32; + func (stream, ", asr #%u", imm); + break; + + case 3: + if (imm == 0) + func (stream, ", rrx"); + else + func (stream, ", ror #%u", imm); + } + } + break; + + case 'a': + { + unsigned int Rn = (given & 0x000f0000) >> 16; + unsigned int U = (given & 0x00800000) >> 23; + unsigned int op = (given & 0x00000f00) >> 8; + unsigned int i12 = (given & 0x00000fff); + unsigned int i8 = (given & 0x000000ff); + + func (stream, "[%s", arm_regnames[Rn]); + if (U) /* 12-bit positive immediate offset */ + { + if (i12) + func (stream, ", #%u", i12); + func (stream, "]"); + } + else if (Rn == 15) /* 12-bit negative immediate offset */ + func (stream, ", #-%u]", i12); + else switch (op) + { + case 0x0: /* shifted register offset */ + { + unsigned int Rm = (i8 & 0x0f); + unsigned int sh = (i8 & 0x30) >> 4; + func (stream, ", %s", arm_regnames[Rm]); + if (sh) + func (stream, ", lsl #%u", sh); + func (stream, "]"); + } + break; + + case 0xE: /* 8-bit positive immediate offset */ + if (i8) + func (stream, ", #%u", i8); + func (stream, "]"); + break; + + case 0xC: /* 8-bit negative immediate offset */ + func (stream, ", #-%u]", i8); + break; + + case 0xB: /* 8-bit + preindex with wb */ + if (i8) + func (stream, ", #%u", i8); + func (stream, "]!"); + break; + + case 0x9: /* 8-bit - preindex with wb */ + func (stream, ", #-%u]!", i8); + break; + + case 0xF: /* 8-bit + postindex */ + func (stream, "], #%u", i8); + break; + + case 0xD: /* 8-bit - postindex */ + func (stream, "], #-%u", i8); + break; + + default: + func (stream, ", <undefined>]"); + } + } + break; + + case 'A': + { + unsigned int P = (given & 0x01000000) >> 24; + unsigned int U = (given & 0x00800000) >> 23; + unsigned int W = (given & 0x00400000) >> 21; + unsigned int Rn = (given & 0x000f0000) >> 16; + unsigned int off = (given & 0x000000ff); + + func (stream, "[%s", arm_regnames[Rn]); + if (P) + { + if (off || !U) + func (stream, ", #%c%u", U ? '+' : '-', off * 4); + func (stream, "]"); + if (W) + func (stream, "!"); + } + else + { + func (stream, "], "); + if (W) + func (stream, "#%c%u", U ? '+' : '-', off * 4); + else + func (stream, "{%u}", off); + } + } + break; + + case 'w': + { + unsigned int Sbit = (given & 0x01000000) >> 24; + unsigned int type = (given & 0x00600000) >> 21; + switch (type) + { + case 0: func (stream, Sbit ? "sb" : "b"); break; + case 1: func (stream, Sbit ? "sh" : "h"); break; + case 2: + if (Sbit) + func (stream, "??"); + break; + case 3: + func (stream, "??"); + break; + } + } + break; + + case 'm': + { + int started = 0; + int reg; + + func (stream, "{"); + for (reg = 0; reg < 16; reg++) + if ((given & (1 << reg)) != 0) + { + if (started) + func (stream, ", "); + started = 1; + func (stream, "%s", arm_regnames[reg]); + } + func (stream, "}"); + } + break; + + case 'E': + { + unsigned int msb = (given & 0x0000001f); + unsigned int lsb = 0; + lsb |= (given & 0x000000c0u) >> 6; + lsb |= (given & 0x00007000u) >> 10; + func (stream, "#%u, #%u", lsb, msb - lsb + 1); + } + break; + + case 'F': + { + unsigned int width = (given & 0x0000001f) + 1; + unsigned int lsb = 0; + lsb |= (given & 0x000000c0u) >> 6; + lsb |= (given & 0x00007000u) >> 10; + func (stream, "#%u, #%u", lsb, width); + } + break; + + case 'b': + { + unsigned int S = (given & 0x04000000u) >> 26; + unsigned int J1 = (given & 0x00002000u) >> 13; + unsigned int J2 = (given & 0x00000800u) >> 11; + unsigned int offset = 0; + + offset |= !S << 20; + offset |= J2 << 19; + offset |= J1 << 18; + offset |= (given & 0x003f0000) >> 4; + offset |= (given & 0x000007ff) << 1; + offset -= (1 << 20); + + info->print_address_func ((bfd_vma)offset + pc + 4, info); + } + break; + + case 'B': + { + unsigned int S = (given & 0x04000000u) >> 26; + unsigned int I1 = (given & 0x00002000u) >> 13; + unsigned int I2 = (given & 0x00000800u) >> 11; + unsigned int offset = 0; + + offset |= !S << 24; + offset |= !(I1 ^ S) << 23; + offset |= !(I2 ^ S) << 22; + offset |= (given & 0x03ff0000u) >> 4; + offset |= (given & 0x000007ffu) << 1; + offset -= (1 << 24); + + info->print_address_func ((bfd_vma)offset + pc + 4, info); + } + break; + + case 's': + { + unsigned int shift = 0; + shift |= (given & 0x000000c0u) >> 6; + shift |= (given & 0x00007000u) >> 10; + if (given & 0x00200000u) + func (stream, ", asr #%u", shift); + else if (shift) + func (stream, ", lsl #%u", shift); + /* else print nothing - lsl #0 */ + } + break; + + case 'R': + { + unsigned int rot = (given & 0x00000030) >> 4; + if (rot) + func (stream, ", ror #%u", rot * 8); + } + break; + + case '0': case '1': case '2': case '3': case '4': + case '5': case '6': case '7': case '8': case '9': + { + int bitstart = *c++ - '0'; + int bitend = 0; + unsigned int val; + while (*c >= '0' && *c <= '9') + bitstart = (bitstart * 10) + *c++ - '0'; + + if (*c == '-') + { + c++; + while (*c >= '0' && *c <= '9') + bitend = (bitend * 10) + *c++ - '0'; + if (!bitend) + abort (); + + val = given >> bitstart; + val &= (2 << (bitend - bitstart)) - 1; + } + else + val = (given >> bitstart) & 1; + + switch (*c) + { + case 'd': func (stream, "%u", val); break; + case 'W': func (stream, "%u", val * 4); break; + case 'r': func (stream, "%s", arm_regnames[val]); break; + + case 'c': + if (val == 0xE) + func (stream, "al"); + else + func (stream, "%s", arm_conditional[val]); + break; + + case '\'': + if (val) + func (stream, "%c", c[1]); + c++; + break; + + case '`': + if (!val) + func (stream, "%c", c[1]); + c++; + break; + + case '?': + func (stream, "%c", val ? c[1] : c[2]); + c += 2; + break; + + default: + abort (); + } + } + break; + + default: + abort (); + } + } + return 4; + } /* No match. */ abort (); @@ -2006,10 +2633,11 @@ print_insn (pc, info, little) struct disassemble_info * info; bfd_boolean little; { - unsigned char b[4]; - long given; - int status; - int is_thumb, second_half_valid = 1; + unsigned char b[4]; + long given; + int status; + int is_thumb; + int (*printer) (bfd_vma, struct disassemble_info *, long); if (info->disassembler_options) { @@ -2046,59 +2674,62 @@ print_insn (pc, info, little) } } - info->bytes_per_chunk = 4; info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; + info->bytes_per_line = 4; - if (little) + if (!is_thumb) { - status = info->read_memory_func (pc, (bfd_byte *) &b[0], 4, info); - if (status != 0 && is_thumb) - { - info->bytes_per_chunk = 2; - second_half_valid = 0; - - status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); - b[3] = b[2] = 0; - } - - if (status != 0) - { - info->memory_error_func (status, pc, info); - return -1; - } - - given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); + /* In ARM mode endianness is a straightforward issue: the instruction + is four bytes long and is either ordered 0123 or 3210. */ + printer = print_insn_arm; + info->bytes_per_chunk = 4; + + status = info->read_memory_func (pc, (bfd_byte *)b, 4, info); + if (little) + given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); + else + given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24); } else { - status = info->read_memory_func - (WORD_ADDRESS (pc), (bfd_byte *) &b[0], 4, info); - if (status != 0) + /* In Thumb mode we have the additional wrinkle of two + instruction lengths. Fortunately, the bits that determine + the length of the current instruction are always to be found + in the first two bytes. */ + + info->bytes_per_chunk = 2; + status = info->read_memory_func (pc, (bfd_byte *)b, 2, info); + if (!status) { - info->memory_error_func (status, WORD_ADDRESS (pc), info); - return -1; - } + if (little) + given = (b[0]) | (b[1] << 8); + else + given = (b[1]) | (b[0] << 8); - if (is_thumb) - { - if (pc & 0x2) + /* These bit patterns signal a four-byte Thumb + instruction. */ + if ((given & 0xF800) == 0xF800 + || (given & 0xF800) == 0xF000 + || (given & 0xF800) == 0xE800) { - given = (b[2] << 8) | b[3]; - - status = info->read_memory_func - (WORD_ADDRESS (pc + 4), (bfd_byte *) b, 4, info); - if (status != 0) - second_half_valid = 0; + status = info->read_memory_func (pc + 2, (bfd_byte *)b, 2, info); + if (little) + given = (b[0]) | (b[1] << 8) | (given << 16); else - given |= (b[0] << 24) | (b[1] << 16); + given = (b[1]) | (b[0] << 8) | (given << 16); + + printer = print_insn_thumb32; } else - given = (b[0] << 8) | b[1] | (b[2] << 24) | (b[3] << 16); + printer = print_insn_thumb16; } - else - given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]); } + if (status) + { + info->memory_error_func (status, pc, info); + return -1; + } if (info->flags & INSN_HAS_RELOC) /* If the instruction has a reloc associated with it, then the offset field in the instruction will actually be the @@ -2107,18 +2738,7 @@ print_insn (pc, info, little) addresses, since the addend is not currently pc-relative. */ pc = 0; - if (is_thumb) - status = print_insn_thumb (pc, info, given); - else - status = print_insn_arm (pc, info, given); - - if (is_thumb && status == 4 && second_half_valid == 0) - { - info->memory_error_func (status, WORD_ADDRESS (pc + 4), info); - return -1; - } - - return status; + return printer (pc, info, given); } int |