diff options
author | Joseph Myers <jsm@polyomino.org.uk> | 2006-09-19 18:45:45 +0000 |
---|---|---|
committer | Joseph Myers <jsm@polyomino.org.uk> | 2006-09-19 18:45:45 +0000 |
commit | ba5b57ffaf3307840802afe10bc2bbe0bf7911c3 (patch) | |
tree | 5046fe0eafb531f2e47073298fa15568a5346d56 | |
parent | fdcaea1d4eed2684201a20c0c732f7dc779d73a1 (diff) | |
download | gdb-ba5b57ffaf3307840802afe10bc2bbe0bf7911c3.tar.gz |
2006-09-19 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
bfd/
* archures.c: Add definition for bfd_mach_arm_iWMMXt2.
* cpu-arm.c (processors): Add bfd_mach_arm_iWMMXt2.
(arch_info_struct, bfd_arm_update_notes): Likewise.
(architectures): Likewise.
(bfd_arm_merge_machines): Check for iWMMXt2.
* bfd-in2.h: Rebuild.
gas/
* config/tc-arm.c (enum operand_parse_code): New code OP_RIWR_I32z.
(parse_operands): Handle OP_RIWR_I32z.
(do_iwmmxt_wmerge): New function.
(do_iwmmxt_wldstd): Handle iwmmxt2 case where second operand is
a register.
(do_iwmmxt_wrwrwr_or_imm5): New function.
(insns): Mark instructions as RIWR_I32z as appropriate.
Also add torvsc<b,h,w>, wabs<b,h,w>, wabsdiff<b,h,w>,
waddbhus<l,m>, waddhc, waddwc, waddsubhx, wavg4{r}, wmaddu{x,n},
wmadds{x,n}, wmerge, wmiaxy{n}, wmiawxy{n}, wmul<sm,um>{r},
wmulw<um,sm,l>{r}, wqmiaxy{n}, wqmulm{r}, wqmulwm{r}, wsubaddhx.
(md_begin): Handle IWMMXT2.
(arm_cpus): Add iwmmxt2.
(arm_extensions): Likewise.
(arm_archs): Likewise.
gas/testsuite/
* gas/arm/iwmmxt2.s: New file.
* gas/arm/iwmmxt2.d: New file.
opcodes/
* arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
only be used with the default multiply-add operation, so if N is
set, don't bother printing X. Add new iwmmxt instructions.
(IWMMXT_INSN_COUNT): Update.
(iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
with a 'c' suffix.
(print_insn_coprocessor): Check for iWMMXt2. Handle format
specifiers 'r', 'i'.
-rw-r--r-- | ChangeLog.csl | 44 | ||||
-rw-r--r-- | bfd/archures.c | 1 | ||||
-rw-r--r-- | bfd/bfd-in2.h | 1 | ||||
-rw-r--r-- | bfd/cpu-arm.c | 18 | ||||
-rw-r--r-- | include/opcode/arm.h | 3 | ||||
-rw-r--r-- | opcodes/arm-dis.c | 102 |
6 files changed, 152 insertions, 17 deletions
diff --git a/ChangeLog.csl b/ChangeLog.csl index c89d2fddda1..cf7b0ba8d36 100644 --- a/ChangeLog.csl +++ b/ChangeLog.csl @@ -1,3 +1,47 @@ +2006-09-19 Mark Shinwell <shinwell@codesourcery.com> + Joseph Myers <joseph@codesourcery.com> + Ian Lance Taylor <ian@wasabisystems.com> + Ben Elliston <bje@wasabisystems.com> + + bfd/ + * archures.c: Add definition for bfd_mach_arm_iWMMXt2. + * cpu-arm.c (processors): Add bfd_mach_arm_iWMMXt2. + (arch_info_struct, bfd_arm_update_notes): Likewise. + (architectures): Likewise. + (bfd_arm_merge_machines): Check for iWMMXt2. + * bfd-in2.h: Rebuild. + + gas/ + * config/tc-arm.c (enum operand_parse_code): New code OP_RIWR_I32z. + (parse_operands): Handle OP_RIWR_I32z. + (do_iwmmxt_wmerge): New function. + (do_iwmmxt_wldstd): Handle iwmmxt2 case where second operand is + a register. + (do_iwmmxt_wrwrwr_or_imm5): New function. + (insns): Mark instructions as RIWR_I32z as appropriate. + Also add torvsc<b,h,w>, wabs<b,h,w>, wabsdiff<b,h,w>, + waddbhus<l,m>, waddhc, waddwc, waddsubhx, wavg4{r}, wmaddu{x,n}, + wmadds{x,n}, wmerge, wmiaxy{n}, wmiawxy{n}, wmul<sm,um>{r}, + wmulw<um,sm,l>{r}, wqmiaxy{n}, wqmulm{r}, wqmulwm{r}, wsubaddhx. + (md_begin): Handle IWMMXT2. + (arm_cpus): Add iwmmxt2. + (arm_extensions): Likewise. + (arm_archs): Likewise. + + gas/testsuite/ + * gas/arm/iwmmxt2.s: New file. + * gas/arm/iwmmxt2.d: New file. + + opcodes/ + * arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may + only be used with the default multiply-add operation, so if N is + set, don't bother printing X. Add new iwmmxt instructions. + (IWMMXT_INSN_COUNT): Update. + (iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14 + with a 'c' suffix. + (print_insn_coprocessor): Check for iWMMXt2. Handle format + specifiers 'r', 'i'. + 2006-09-18 Paul Brook <paul@codesourcery.com> gas/ diff --git a/bfd/archures.c b/bfd/archures.c index f4080a63a46..76ef3ae57a3 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -273,6 +273,7 @@ DESCRIPTION .#define bfd_mach_arm_XScale 10 .#define bfd_mach_arm_ep9312 11 .#define bfd_mach_arm_iWMMXt 12 +.#define bfd_mach_arm_iWMMXt2 13 . bfd_arch_ns32k, {* National Semiconductors ns32000 *} . bfd_arch_w65, {* WDC 65816 *} . bfd_arch_tic30, {* Texas Instruments TMS320C30 *} diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index bbea0fa85d3..3662a5dcb6c 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -1874,6 +1874,7 @@ enum bfd_architecture #define bfd_mach_arm_XScale 10 #define bfd_mach_arm_ep9312 11 #define bfd_mach_arm_iWMMXt 12 +#define bfd_mach_arm_iWMMXt2 13 bfd_arch_ns32k, /* National Semiconductors ns32000 */ bfd_arch_w65, /* WDC 65816 */ bfd_arch_tic30, /* Texas Instruments TMS320C30 */ diff --git a/bfd/cpu-arm.c b/bfd/cpu-arm.c index f92d83bd61f..10cf9b5341c 100644 --- a/bfd/cpu-arm.c +++ b/bfd/cpu-arm.c @@ -92,7 +92,8 @@ processors[] = { bfd_mach_arm_4, "strongarm1100" }, { bfd_mach_arm_XScale, "xscale" }, { bfd_mach_arm_ep9312, "ep9312" }, - { bfd_mach_arm_iWMMXt, "iwmmxt" } + { bfd_mach_arm_iWMMXt, "iwmmxt" }, + { bfd_mach_arm_iWMMXt2, "iwmmxt2" } }; static bfd_boolean @@ -137,7 +138,8 @@ static const bfd_arch_info_type arch_info_struct[] = N (bfd_mach_arm_5TE, "armv5te", FALSE, & arch_info_struct[9]), N (bfd_mach_arm_XScale, "xscale", FALSE, & arch_info_struct[10]), N (bfd_mach_arm_ep9312, "ep9312", FALSE, & arch_info_struct[11]), - N (bfd_mach_arm_iWMMXt,"iwmmxt", FALSE, NULL) + N (bfd_mach_arm_iWMMXt, "iwmmxt", FALSE, & arch_info_struct[12]), + N (bfd_mach_arm_iWMMXt2, "iwmmxt2", FALSE, NULL) }; const bfd_arch_info_type bfd_arm_arch = @@ -179,7 +181,9 @@ bfd_arm_merge_machines (bfd *ibfd, bfd *obfd) Intel XScale binary, since these architecture have co-processors which will not both be present on the same physical hardware. */ else if (in == bfd_mach_arm_ep9312 - && (out == bfd_mach_arm_XScale || out == bfd_mach_arm_iWMMXt)) + && (out == bfd_mach_arm_XScale + || out == bfd_mach_arm_iWMMXt + || out == bfd_mach_arm_iWMMXt2)) { _bfd_error_handler (_("\ ERROR: %B is compiled for the EP9312, whereas %B is compiled for XScale"), @@ -188,7 +192,9 @@ ERROR: %B is compiled for the EP9312, whereas %B is compiled for XScale"), return FALSE; } else if (out == bfd_mach_arm_ep9312 - && (in == bfd_mach_arm_XScale || in == bfd_mach_arm_iWMMXt)) + && (in == bfd_mach_arm_XScale + || in == bfd_mach_arm_iWMMXt + || in == bfd_mach_arm_iWMMXt2)) { _bfd_error_handler (_("\ ERROR: %B is compiled for the EP9312, whereas %B is compiled for XScale"), @@ -309,6 +315,7 @@ bfd_arm_update_notes (bfd *abfd, const char *note_section) case bfd_mach_arm_XScale: expected = "XScale"; break; case bfd_mach_arm_ep9312: expected = "ep9312"; break; case bfd_mach_arm_iWMMXt: expected = "iWMMXt"; break; + case bfd_mach_arm_iWMMXt2: expected = "iWMMXt2"; break; } if (strcmp (arch_string, expected) != 0) @@ -355,7 +362,8 @@ architectures[] = { "armv5te", bfd_mach_arm_5TE }, { "XScale", bfd_mach_arm_XScale }, { "ep9312", bfd_mach_arm_ep9312 }, - { "iWMMXt", bfd_mach_arm_iWMMXt } + { "iWMMXt", bfd_mach_arm_iWMMXt }, + { "iWMMXt2", bfd_mach_arm_iWMMXt2 } }; /* Extract the machine number stored in a note section. */ diff --git a/include/opcode/arm.h b/include/opcode/arm.h index f142fca9a5c..24a89cfcb1d 100644 --- a/include/opcode/arm.h +++ b/include/opcode/arm.h @@ -49,6 +49,7 @@ #define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */ #define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */ #define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology coprocessor. */ +#define ARM_CEXT_IWMMXT2 0x00000008 /* Intel Wireless MMX technology coprocessor version 2. */ #define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */ #define FPU_ENDIAN_BIG 0 /* Double words-big-endian. */ @@ -103,6 +104,8 @@ #define ARM_ARCH_XSCALE ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE) #define ARM_ARCH_IWMMXT \ ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT) +#define ARM_ARCH_IWMMXT2 \ + ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT | ARM_CEXT_IWMMXT2) #define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE) #define FPU_VFP_V1 (FPU_VFP_V1xD | FPU_VFP_EXT_V1) diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index cdb94962c79..365a155bed8 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -98,7 +98,11 @@ struct opcode16 %L print as an iWMMXt N/M width field. %Z print the Immediate of a WSHUFH instruction. %l like 'A' except use byte offsets for 'B' & 'H' - versions. */ + versions. + %i print 5-bit immediate in bits 8,3..0 + (print "32" when 0) + %r print register offset address for wldt/wstr instruction +*/ /* Common coprocessor opcodes shared between Arm and Thumb-2. */ @@ -113,7 +117,7 @@ static const struct opcode32 coprocessor_opcodes[] = /* Intel Wireless MMX technology instructions. */ #define FIRST_IWMMXT_INSN 0x0e130130 -#define IWMMXT_INSN_COUNT 47 +#define IWMMXT_INSN_COUNT 73 {ARM_CEXT_IWMMXT, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"}, {ARM_CEXT_XSCALE, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"}, {ARM_CEXT_XSCALE, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"}, @@ -128,37 +132,63 @@ static const struct opcode32 coprocessor_opcodes[] = {ARM_CEXT_XSCALE, 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"}, {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"}, + {ARM_CEXT_XSCALE, 0x0e130190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"}, + {ARM_CEXT_XSCALE, 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"}, {ARM_CEXT_XSCALE, 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"}, {ARM_CEXT_XSCALE, 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e2001a0, 0x0f300ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"}, {ARM_CEXT_XSCALE, 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"}, {ARM_CEXT_XSCALE, 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"}, {ARM_CEXT_XSCALE, 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"}, {ARM_CEXT_XSCALE, 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e800100, 0x0fd00ff0, "wmadd%21?su%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"}, + {ARM_CEXT_XSCALE, 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e800120, 0x0f800ff0, "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e8000a0, 0x0f800ff0, "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e300040, 0x0f300ff0, "wror%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e300148, 0x0f300ffc, "wror%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, + {ARM_CEXT_XSCALE, 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"}, + {ARM_CEXT_XSCALE, 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"}, {ARM_CEXT_XSCALE, 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"}, + {ARM_CEXT_XSCALE, 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"}, {ARM_CEXT_XSCALE, 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, + {ARM_CEXT_XSCALE, 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"}, {ARM_CEXT_XSCALE, 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, + {ARM_CEXT_XSCALE, 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"}, {ARM_CEXT_XSCALE, 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, + {ARM_CEXT_XSCALE, 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"}, {ARM_CEXT_XSCALE, 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"}, {ARM_CEXT_XSCALE, 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"}, {ARM_CEXT_XSCALE, 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e0000c0, 0x0f100fff, "wunpckeh%21?su%22-23w%c\t%12-15g, %16-19g"}, + {ARM_CEXT_XSCALE, 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"}, + {ARM_CEXT_XSCALE, 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"}, + {ARM_CEXT_XSCALE, 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"}, {ARM_CEXT_XSCALE, 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"}, {ARM_CEXT_XSCALE, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"}, @@ -1417,10 +1447,10 @@ static const char *const iwmmxt_wwnames[] = {"b", "h", "w", "d"}; static const char *const iwmmxt_wwssnames[] = -{"b", "bus", "b", "bss", - "h", "hus", "h", "hss", - "w", "wus", "w", "wss", - "d", "dus", "d", "dss" +{"b", "bus", "bc", "bss", + "h", "hus", "hc", "hss", + "w", "wus", "wc", "wss", + "d", "dus", "dc", "dss" }; static const char *const iwmmxt_regnames[] = @@ -1563,7 +1593,8 @@ print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given, { if (insn->value == FIRST_IWMMXT_INSN && info->mach != bfd_mach_arm_XScale - && info->mach != bfd_mach_arm_iWMMXt) + && info->mach != bfd_mach_arm_iWMMXt + && info->mach != bfd_mach_arm_iWMMXt2) insn = insn + IWMMXT_INSN_COUNT; mask = insn->mask; @@ -1977,6 +2008,53 @@ print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given, } break; + case 'r': + { + int imm4 = (given >> 4) & 0xf; + int puw_bits = ((given >> 22) & 6) | ((given >> 21) & 1); + int ubit = (given >> 23) & 1; + const char *rm = arm_regnames [given & 0xf]; + const char *rn = arm_regnames [(given >> 16) & 0xf]; + + switch (puw_bits) + { + case 1: + /* fall through */ + case 3: + func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm); + if (imm4) + func (stream, ", lsl #%d", imm4); + break; + + case 4: + /* fall through */ + case 5: + /* fall through */ + case 6: + /* fall through */ + case 7: + func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm); + if (imm4 > 0) + func (stream, ", lsl #%d", imm4); + func (stream, "]"); + if (puw_bits == 5 || puw_bits == 7) + func (stream, "!"); + break; + + default: + func (stream, "INVALID"); + } + } + break; + + case 'i': + { + long imm5; + imm5 = ((given & 0x100) >> 4) | (given & 0xf); + func (stream, "%ld", (imm5 == 0) ? 32 : imm5); + } + break; + default: abort (); } |