Remove extraneous whitespace

5 files changed, 26 insertions, 17 deletions

diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index 98f7b32f668..d305bdab1a2 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,7 @@
+2001-03-23  Nick Clifton  <nickc@redhat.com>
+
+	* mips.h: Remove extraneous whitespace.
+
 2001-03-22  Hans-Peter Nilsson  <hp@axis.com>
 
 	* cris.h: Add leading comment about PC-relative location.
diff --git a/include/elf/mips.h b/include/elf/mips.h
index 9d04d2149e6..16398f0bc67 100644
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -102,7 +102,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
 /* Code in file uses new ABI (-n32 on Irix 6).  */
 #define EF_MIPS_ABI2		0x00000020
 
-/* Indicates code compiled for a 64-bit machine in 32-bit mode. 
+/* Indicates code compiled for a 64-bit machine in 32-bit mode.
    (regs are 32-bits wide.) */
 #define EF_MIPS_32BITMODE       0x00000100
 
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 1c5b7bab893..57af53c53ec 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2001-03-23  Nick Clifton  <nickc@redhat.com>
+
+	* mips-opc.c: Remove extraneous whitespace.
+	* mips-dis.c: Remove extraneous whitespace.
+
 2001-03-22  Ben Elliston  <bje@redhat.com>
 
 	* cgen-asm.in (@arch@_cgen_assemble_insn): Move tmp_errmsg
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index c016a877230..4af8822df04 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -165,7 +165,7 @@ print_insn_arg (d, l, pc, info)
       if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
         (*info->fprintf_func) (info->stream, "$%s",
                                reg_names[reg]);
-      else                        
+      else
         {
           /* If one is zero use the other. */
           if (reg == 0)
@@ -264,7 +264,7 @@ print_insn_arg (d, l, pc, info)
       break;
 
     case 'H':
-      (*info->fprintf_func) (info->stream, "%d", 
+      (*info->fprintf_func) (info->stream, "%d",
 			     (l >> OP_SH_SEL) & OP_MASK_SEL);
       break;
 
@@ -431,9 +431,9 @@ _print_insn_mips (memaddr, word, info)
      FIXME: Where does mips_target_info come from?  */
   target_processor = mips_target_info.processor;
   mips_isa = mips_target_info.isa;
-#else  
+#else
   set_mips_isa_type (info->mach, &mips_isa, &target_processor);
-#endif  
+#endif
 
   info->bytes_per_chunk = 4;
   info->display_endian = info->endian;
@@ -490,7 +490,7 @@ print_insn_big_mips (memaddr, info)
   /* Only a few tools will work this way.  */
   if (memaddr & 0x01)
     return print_insn_mips16 (memaddr, info);
-#endif  
+#endif
 
 #if SYMTAB_AVAILABLE
   if (info->mach == 16
@@ -499,7 +499,7 @@ print_insn_big_mips (memaddr, info)
 	  && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
 	      == STO_MIPS16)))
     return print_insn_mips16 (memaddr, info);
-#endif  
+#endif
 
   status = (*info->read_memory_func) (memaddr, buffer, 4, info);
   if (status == 0)
@@ -524,7 +524,7 @@ print_insn_little_mips (memaddr, info)
 #if 1
   if (memaddr & 0x01)
     return print_insn_mips16 (memaddr, info);
-#endif  
+#endif
 
 #if SYMTAB_AVAILABLE
   if (info->mach == 16
@@ -533,7 +533,7 @@ print_insn_little_mips (memaddr, info)
 	  && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
 	      == STO_MIPS16)))
     return print_insn_mips16 (memaddr, info);
-#endif  
+#endif
 
   status = (*info->read_memory_func) (memaddr, buffer, 4, info);
   if (status == 0)
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 93822b83246..5fc17ba5652 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -39,15 +39,15 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 
 #define WR_d    INSN_WRITE_GPR_D
 #define WR_t    INSN_WRITE_GPR_T
-#define WR_31   INSN_WRITE_GPR_31       
-#define WR_D    INSN_WRITE_FPR_D        
+#define WR_31   INSN_WRITE_GPR_31
+#define WR_D    INSN_WRITE_FPR_D
 #define WR_T	INSN_WRITE_FPR_T
 #define WR_S	INSN_WRITE_FPR_S
-#define RD_s    INSN_READ_GPR_S         
-#define RD_b    INSN_READ_GPR_S         
-#define RD_t    INSN_READ_GPR_T         
-#define RD_S    INSN_READ_FPR_S         
-#define RD_T    INSN_READ_FPR_T         
+#define RD_s    INSN_READ_GPR_S
+#define RD_b    INSN_READ_GPR_S
+#define RD_t    INSN_READ_GPR_T
+#define RD_S    INSN_READ_FPR_S
+#define RD_T    INSN_READ_FPR_T
 #define RD_R	INSN_READ_FPR_R
 #define WR_CC	INSN_WRITE_COND_CODE
 #define RD_CC	INSN_READ_COND_CODE
@@ -87,7 +87,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 #define V1      INSN_4100
 #define T3      INSN_3900
 
-#define G1      (T3                   \
+#define G1      (T3             \
                  )
 
 #define G2      (T3                   \