[ bfd/ChangeLog ]

2002-12-30  Chris Demetriou  <cgd@broadcom.com>

	* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
	* archures.c (bfd_mach_mipsisa32r2): New define.
	* bfd-in2.h: Regenerate.
	* cpu-mips.c (I_mipsisa32r2): New enum value.
	(arch_info_struct): Add entry for I_mipsisa32r2.
	* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
	(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
	(_bfd_mips_elf_final_write_processing): Add
	bfd_mach_mipsisa32r2 case.
	(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
	binaries marked as using MIPS32 Release 2.

[ binutils/ChangeLog ]
2002-12-30  Chris Demetriou  <cgd@broadcom.com>

	* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
	changes in MIPS -M options.

[ gas/ChangeLog ]
2002-12-30  Chris Demetriou  <cgd@broadcom.com>

	* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
	CPU variants.
	* configure: Regenerate.
	* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
	(macro_build): Handle "K" operand.
	(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
	CPU_HAS_DROR and CPU_HAS_ROR are currently used.
	(mips_ip): New variable "lastpos", and implement "+A", "+B",
	and "+C" operands for MIPS32 Release 2 ins/ext instructions.
	Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
	(validate_mips_insn): Implement "+" as a way to extend the
	allowed operands, and implement "K", "+A", "+B", and "+C"
	operands.
	(OPTION_MIPS32R2): New define.
	(md_longopts): Add entry for OPTION_MIPS32R2.
	(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
	(md_parse_option): Handle OPTION_MIPS32R2.
	(s_mipsset): Reimplement handling of ".set mipsN" options
	and add support for ".set mips32r2".
	(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
	(md_show_usage): Document "-mips32r2" option.
	* doc/as.texinfo: Document "-mips32r2" option.
	* doc/c-mips.texi: Likewise.

[ gas/testsuite/ChangeLog ]
2002-12-30  Chris Demetriou  <cgd@broadcom.com>

	* gas/mips/cp0-names-mips32r2.d: New test.
	* gas/mips/hwr-names-mips32r2.d: New test.
	* gas/mips/hwr-names-numeric.d: New test.
	* gas/mips/hwr-names.s: New test source file.
	* gas/mips/mips32r2.d: New test.
	* gas/mips/mips32r2.s: New test source file.
	* gas/mips/mips32r2-ill.l: New test.
	* gas/mips/mips32r2-ill.s: New test source file.
	* gas/mips/mips.exp: Add mips32r2 architecture data array
	entry.  Run new tests mentioned above.

[ include/elf/ChangeLog ]
2002-12-30  Chris Demetriou  <cgd@broadcom.com>

	* mips.h (E_MIPS_ARCH_32R2): New define.

[ include/opcode/ChangeLog ]
2002-12-30  Chris Demetriou  <cgd@broadcom.com>

	* mips.h: Document "+" as the start of two-character operand
	type names, and add new "K", "+A", "+B", and "+C" operand types.
	(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
	(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
	defines.

[ opcodes/ChangeLog ]
2002-12-30  Chris Demetriou  <cgd@broadcom.com>

	* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
	(mips_hwr_names_mips3264r2): New arrays.
	(mips_arch_choice): New "hwr_names" member.
	(mips_arch_choices): Adjust for structure change, and add a new
	entry for "mips32r2" ISA.
	(mips_hwr_names): New variable.
	(set_default_mips_dis_options): Set mips_hwr_names.
	(parse_mips_dis_option): New "hwr-names" option which sets
	mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
	(print_insn_arg): Change return type to "int"
	and use that to indicate number of characters consumed.
	Add support for "+" operand extension character, "+A", "+B",
	"+C", and "K" operands.
	(print_insn_mips): Adjust for changes to print_insn_arg.
	(print_mips_disassembler_options): Adjust for "hwr-names"
	addition and "reg-names" change.
	* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
	(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
	forms of "sll".  Add new MIPS32 Release 2 instructions: ehb,
	di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
	rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
	Note that hardware rotate instructions (ror, rorv) can be
	used on MIPS32 Release 2, and add the official mnemonics
	for them (rotr, rotrv) and the similar "rotl" mnemonic for
	left-rotate.

13 files changed, 268 insertions, 40 deletions

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index b2a283a9f2b..b58e0d5077d 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,17 @@
+2002-12-30  Chris Demetriou  <cgd@broadcom.com>
+
+	* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
+	* archures.c (bfd_mach_mipsisa32r2): New define.
+	* bfd-in2.h: Regenerate.
+	* cpu-mips.c (I_mipsisa32r2): New enum value.
+	(arch_info_struct): Add entry for I_mipsisa32r2.
+	* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
+	(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
+	(_bfd_mips_elf_final_write_processing): Add
+	bfd_mach_mipsisa32r2 case.
+	(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
+	binaries marked as using MIPS32 Release 2.
+
 2002-12-30    Dmitry Diky <diwil@mail.ru>
 
 	* Makefile.am: Add msp430 target.
diff --git a/bfd/aoutx.h b/bfd/aoutx.h
index d8b465c47b8..998bca76230 100644
--- a/bfd/aoutx.h
+++ b/bfd/aoutx.h
@@ -800,6 +800,7 @@ NAME(aout,machine_type) (arch, machine, unknown)
 	case bfd_mach_mips12000:
 	case bfd_mach_mips16:
 	case bfd_mach_mipsisa32:
+	case bfd_mach_mipsisa32r2:
 	case bfd_mach_mips5:
 	case bfd_mach_mipsisa64:
 	case bfd_mach_mips_sb1:
diff --git a/bfd/archures.c b/bfd/archures.c
index 2ad7267b353..4c93cda6aa0 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -145,6 +145,7 @@ DESCRIPTION
 .#define bfd_mach_mips5                 5
 .#define bfd_mach_mips_sb1              12310201 {* octal 'SB', 01 *}
 .#define bfd_mach_mipsisa32             32
+.#define bfd_mach_mipsisa32r2           33
 .#define bfd_mach_mipsisa64             64
 .  bfd_arch_i386,      {* Intel 386 *}
 .#define bfd_mach_i386_i386 1
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index c72767982ee..cdcf7ae7622 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1572,6 +1572,7 @@ enum bfd_architecture
 #define bfd_mach_mips5                 5
 #define bfd_mach_mips_sb1              12310201 /* octal 'SB', 01 */
 #define bfd_mach_mipsisa32             32
+#define bfd_mach_mipsisa32r2           33
 #define bfd_mach_mipsisa64             64
   bfd_arch_i386,      /* Intel 386 */
 #define bfd_mach_i386_i386 1
diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
index e587535e28b..13355c5c5af 100644
--- a/bfd/cpu-mips.c
+++ b/bfd/cpu-mips.c
@@ -82,6 +82,7 @@ enum
   I_mips16,
   I_mips5,
   I_mipsisa32,
+  I_mipsisa32r2,
   I_mipsisa64,
   I_sb1,
 };
@@ -111,6 +112,7 @@ static const bfd_arch_info_type arch_info_struct[] =
   N (64, 64, bfd_mach_mips16,   "mips:16",        FALSE, NN(I_mips16)),
   N (64, 64, bfd_mach_mips5,    "mips:mips5",     FALSE, NN(I_mips5)),
   N (32, 32, bfd_mach_mipsisa32,  "mips:isa32",   FALSE, NN(I_mipsisa32)),
+  N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)),
   N (64, 64, bfd_mach_mipsisa64,  "mips:isa64",   FALSE, NN(I_mipsisa64)),
   N (64, 64, bfd_mach_mips_sb1, "mips:sb1",       FALSE, 0),
 };
diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index 80a583bc60f..ca79c64b98b 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -3102,6 +3102,8 @@ elf_mips_isa (flags)
       return 32;
     case E_MIPS_ARCH_64:
       return 64;
+    case E_MIPS_ARCH_32R2:
+      return 33;
     }
   return 4;
 }
@@ -3172,6 +3174,10 @@ _bfd_elf_mips_mach (flags)
 	case E_MIPS_ARCH_64:
 	  return bfd_mach_mipsisa64;
 	  break;
+
+	case E_MIPS_ARCH_32R2:
+	  return bfd_mach_mipsisa32r2;
+	  break;
 	}
     }
 
@@ -6047,6 +6053,11 @@ _bfd_mips_elf_final_write_processing (abfd, linker)
 
     case bfd_mach_mipsisa64:
       val = E_MIPS_ARCH_64;
+      break;
+
+    case bfd_mach_mipsisa32r2:
+      val = E_MIPS_ARCH_32R2;
+      break;
     }
 
   elf_elfheader (abfd)->e_flags &= ~(EF_MIPS_ARCH | EF_MIPS_MACH);
@@ -7854,8 +7865,10 @@ _bfd_mips_elf_merge_private_bfd_data (ibfd, obfd)
 	     using 64-bit ISAs.  They will normally use the same data sizes
 	     and calling conventions.  */
 
-	  if ((  (new_isa == 1 || new_isa == 2 || new_isa == 32)
-	       ^ (old_isa == 1 || old_isa == 2 || old_isa == 32)) != 0)
+	  if ((  (new_isa == 1 || new_isa == 2 || new_isa == 32
+		  || new_isa == 33)
+	       ^ (old_isa == 1 || old_isa == 2 || old_isa == 32
+		  || old_isa == 33)) != 0)
 	    {
 	      (*_bfd_error_handler)
 	       (_("%s: ISA mismatch (-mips%d) with previous modules (-mips%d)"),
@@ -8005,6 +8018,8 @@ _bfd_mips_elf_print_private_bfd_data (abfd, ptr)
     fprintf (file, _(" [mips32]"));
   else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_64)
     fprintf (file, _(" [mips64]"));
+  else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32R2)
+    fprintf (file, _(" [mips32r2]"));
   else
     fprintf (file, _(" [unknown ISA]"));
 
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index 87e8a3bac1f..c16c927f7cd 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,7 @@
+2002-12-30  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips.h (E_MIPS_ARCH_32R2): New define.
+
 2002-12-24    Dmitry Diky <diwil@mail.ru>
 
 	* common.h: Define msp430 machine numbers.
diff --git a/include/elf/mips.h b/include/elf/mips.h
index 81451ab55cd..964c59a12e9 100644
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -145,6 +145,9 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
 /* -mips64 code.  */
 #define E_MIPS_ARCH_64          0x60000000
 
+/* -mips32r2 code.  */
+#define E_MIPS_ARCH_32R2        0x70000000
+
 /* The ABI of the file.  Also see EF_MIPS_ABI2 above. */
 #define EF_MIPS_ABI		0x0000F000
 
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 10fbb98f040..6f68432fc35 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,11 @@
+2002-12-30  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips.h: Document "+" as the start of two-character operand
+	type names, and add new "K", "+A", "+B", and "+C" operand types.
+	(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
+	(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
+	defines.
+
 2002-12-24    Dmitry Diky <diwil@mail.ru>
 
 	* msp430.h: New file.  Defines msp430 opcodes.
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index f5f648bd34d..ce6ce0812cf 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -142,6 +142,10 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 #define OP_SH_VECBYTE		22
 #define OP_MASK_VECALIGN	0x7	/* Vector byte-align (alni.ob) op.  */
 #define OP_SH_VECALIGN		21
+#define OP_MASK_INSMSB		0x1f	/* "ins" MSB.  */
+#define OP_SH_INSMSB		11
+#define OP_MASK_EXTMSBD		0x1f	/* "ext" MSBD.  */
+#define OP_SH_EXTMSBD		11
 
 #define	OP_OP_COP0		0x10
 #define	OP_OP_COP1		0x11
@@ -228,6 +232,12 @@ struct mips_opcode
    "J" 19 bit wait function code (OP_*_CODE19)
    "x" accept and ignore register name
    "z" must be zero register
+   "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
+   "+A" 5 bit ins/ext position/lsb (OP_*_SHAMT)
+   "+B" 5 bit "ins" size spec (OP_*_INSMSB).  Requires that "+A"
+	occur first!
+   "+C" 5 bit "ext" msbd spec (OP_*_EXTMSBD).  Requires that "+A"
+	occur first!
 
    Floating point instructions:
    "D" 5 bit destination register (OP_*_FD)
@@ -268,11 +278,16 @@ struct mips_opcode
    "()" parens surrounding optional value
    ","  separates operands
    "[]" brackets around index for vector-op scalar operand specifier (vr5400)
+   "+"  Start of extension sequence.
 
    Characters used so far, for quick reference when adding more:
-   "%[]<>(),"
-   "ABCDEFGHIJLMNOPQRSTUVWXYZ"
+   "%[]<>(),+"
+   "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
    "abcdefhijklopqrstuvwxz"
+
+   Extension character sequences used so far ("+" followed by the
+   following), for quick reference when adding more:
+   "ABC"
 */
 
 /* These are the bits which may be set in the pinfo field of an
@@ -364,6 +379,7 @@ struct mips_opcode
 #define INSN_ISA5                 0x00000100
 #define INSN_ISA32                0x00000200
 #define INSN_ISA64                0x00000400
+#define INSN_ISA32R2              0x00000800
 
 /* Masks used for MIPS-defined ASEs.  */
 #define INSN_ASE_MASK		  0x0000f000
@@ -406,9 +422,12 @@ struct mips_opcode
 #define       ISA_MIPS3       (ISA_MIPS2 | INSN_ISA3)
 #define       ISA_MIPS4       (ISA_MIPS3 | INSN_ISA4)
 #define       ISA_MIPS5       (ISA_MIPS4 | INSN_ISA5)
+
 #define       ISA_MIPS32      (ISA_MIPS2 | INSN_ISA32)
 #define       ISA_MIPS64      (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
 
+#define       ISA_MIPS32R2    (ISA_MIPS32 | INSN_ISA32R2)
+
 /* CPU defines, use instead of hardcoding processor number. Keep this
    in sync with bfd/archures.c in order for machine selection to work.  */
 #define CPU_UNKNOWN	0               /* Gas internal use.  */
@@ -432,6 +451,7 @@ struct mips_opcode
 #define CPU_R12000	12000
 #define CPU_MIPS16	16
 #define CPU_MIPS32	32
+#define CPU_MIPS32R2	33
 #define CPU_MIPS5       5
 #define CPU_MIPS64      64
 #define CPU_SB1         12310201        /* octal 'SB', 01.  */
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 7ff7f953639..98a4b3c70af 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,31 @@
+2002-12-30  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
+	(mips_hwr_names_mips3264r2): New arrays.
+	(mips_arch_choice): New "hwr_names" member.
+	(mips_arch_choices): Adjust for structure change, and add a new
+	entry for "mips32r2" ISA.
+	(mips_hwr_names): New variable.
+	(set_default_mips_dis_options): Set mips_hwr_names.
+	(parse_mips_dis_option): New "hwr-names" option which sets
+	mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
+	(print_insn_arg): Change return type to "int"
+	and use that to indicate number of characters consumed.
+	Add support for "+" operand extension character, "+A", "+B",
+	"+C", and "K" operands.
+	(print_insn_mips): Adjust for changes to print_insn_arg.
+	(print_mips_disassembler_options): Adjust for "hwr-names"
+	addition and "reg-names" change.
+	* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
+	(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
+	forms of "sll".  Add new MIPS32 Release 2 instructions: ehb,
+	di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
+	rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
+	Note that hardware rotate instructions (ror, rorv) can be
+	used on MIPS32 Release 2, and add the official mnemonics
+	for them (rotr, rotrv) and the similar "rotl" mnemonic for
+	left-rotate.
+
 2002-12-30    Dmitry Diky <diwil@mail.ru>
 
 	* configure.in: Add msp430 target.
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 1528aadc5f1..71cf6beacb2 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -50,7 +50,7 @@ static int _print_insn_mips
   PARAMS ((bfd_vma, struct disassemble_info *, enum bfd_endian));
 static int print_insn_mips
   PARAMS ((bfd_vma, unsigned long int, struct disassemble_info *));
-static void print_insn_arg
+static int print_insn_arg
   PARAMS ((const char *, unsigned long, bfd_vma, struct disassemble_info *));
 static int print_insn_mips16
   PARAMS ((bfd_vma, struct disassemble_info *));
@@ -134,6 +134,17 @@ static const char * const mips_cp0_names_mips3264[32] = {
   "c0_taglo",     "c0_taghi",     "c0_errorepc",  "c0_desave",
 };
 
+static const char * const mips_cp0_names_mips3264r2[32] = {
+  "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
+  "c0_context",   "c0_pagemask",  "c0_wired",     "c0_hwrena",
+  "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
+  "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
+  "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
+  "c0_xcontext",  "$21",          "$22",          "c0_debug",
+  "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr",
+  "c0_taglo",     "c0_taghi",     "c0_errorepc",  "c0_desave",
+};
+
 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods.  */
 static const char * const mips_cp0_names_sb1[32] = {
   "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
@@ -146,6 +157,21 @@ static const char * const mips_cp0_names_sb1[32] = {
   "c0_taglo_i",   "c0_taghi_i",   "c0_errorepc",  "c0_desave",
 };
 
+static const char * const mips_hwr_names_numeric[32] = {
+  "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
+  "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
+  "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
+  "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
+};
+
+static const char * const mips_hwr_names_mips3264r2[32] = {
+  "hwr_cpunum",   "hwr_synci_step", "hwr_cc",     "hwr_ccres",
+  "$4",          "$5",            "$6",           "$7",
+  "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
+  "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
+  "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
+};
+
 struct mips_abi_choice {
   const char *name;
   const char * const *gpr_names;
@@ -166,49 +192,50 @@ struct mips_arch_choice {
   int processor;
   int isa;
   const char * const *cp0_names;
+  const char * const *hwr_names;
 };
 
 struct mips_arch_choice mips_arch_choices[] = {
   { "numeric",	0, 0, 0, 0,
-    mips_cp0_names_numeric },
+    mips_cp0_names_numeric, mips_hwr_names_numeric },
   { "r3000",	1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
-    NULL },
+    NULL, NULL },
   { "r3900",	1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
-    NULL },
+    NULL, NULL },
   { "r4000",	1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
-    NULL },
+    NULL, NULL },
   { "r4010",	1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
-    NULL },
+    NULL, NULL },
   { "vr4100",	1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
-    NULL },
+    NULL, NULL },
   { "vr4111",	1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
-    NULL },
+    NULL, NULL },
   { "vr4120",	1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
-    NULL },
+    NULL, NULL },
   { "r4300",	1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
-    NULL },
+    NULL, NULL },
   { "r4400",	1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
-    NULL },
+    NULL, NULL },
   { "r4600",	1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
-    NULL },
+    NULL, NULL },
   { "r4650",	1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
-    NULL },
+    NULL, NULL },
   { "r5000",	1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
-    NULL },
+    NULL, NULL },
   { "vr5400",	1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
-    NULL },
+    NULL, NULL },
   { "vr5500",	1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
-    NULL },
+    NULL, NULL },
   { "r6000",	1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
-    NULL },
+    NULL, NULL },
   { "r8000",	1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
-    NULL },
+    NULL, NULL },
   { "r10000",	1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
-    NULL },
+    NULL, NULL },
   { "r12000",	1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
-    NULL },
+    NULL, NULL },
   { "mips5",	1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
-    NULL },
+    NULL, NULL },
   /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
      Note that MIPS-3D and MDMX are not applicable to MIPS32.  (See
      _MIPS32 Architecture For Programmers Volume I: Introduction to the
@@ -216,19 +243,22 @@ struct mips_arch_choice mips_arch_choices[] = {
      page 1.  */
   { "mips32",	1, bfd_mach_mipsisa32, CPU_MIPS32,
     ISA_MIPS32 | INSN_MIPS16,
-    mips_cp0_names_mips3264 },
+    mips_cp0_names_mips3264, NULL },
+  { "mips32r2",	1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
+    ISA_MIPS32R2 | INSN_MIPS16,
+    mips_cp0_names_mips3264r2, mips_hwr_names_mips3264r2 },
   /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs.  */
   { "mips64",	1, bfd_mach_mipsisa64, CPU_MIPS64,
     ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
-    mips_cp0_names_mips3264 },
+    mips_cp0_names_mips3264, NULL },
   { "sb1",	1, bfd_mach_mips_sb1, CPU_SB1,
     ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
-    mips_cp0_names_sb1 },
+    mips_cp0_names_sb1, NULL },
 
   /* This entry, mips16, is here only for ISA/processor selection; do
      not print its name.  */
   { "",		1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
-    NULL },
+    NULL, NULL },
 };
 
 /* ISA and processor type to disassemble for, and register names to use.
@@ -239,6 +269,7 @@ static int mips_isa;
 static const char * const *mips_gpr_names;
 static const char * const *mips_fpr_names;
 static const char * const *mips_cp0_names;
+static const char * const *mips_hwr_names;
 
 static const struct mips_abi_choice *choose_abi_by_name
   PARAMS ((const char *, unsigned int));
@@ -317,12 +348,13 @@ set_default_mips_dis_options (info)
   const struct mips_arch_choice *chosen_arch;
 
   /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
-     and numeric FPR and CP0 register names.  */
+     and numeric FPR, CP0 register, and HWR names.  */
   mips_isa = ISA_MIPS3;
   mips_processor =  CPU_R3000;
   mips_gpr_names = mips_gpr_names_oldabi;
   mips_fpr_names = mips_fpr_names_numeric;
   mips_cp0_names = mips_cp0_names_numeric;
+  mips_hwr_names = mips_hwr_names_numeric;
 
   /* If an ELF "newabi" binary, use the n32/(n)64 GPR names.  */
   if (info->flavour == bfd_target_elf_flavour && info->symbols != NULL)
@@ -348,6 +380,8 @@ set_default_mips_dis_options (info)
       mips_isa = chosen_arch->isa;
       if (chosen_arch->cp0_names != NULL)
 	mips_cp0_names = chosen_arch->cp0_names;
+      if (chosen_arch->hwr_names != NULL)
+	mips_hwr_names = chosen_arch->hwr_names;
     }
 #endif
 }
@@ -406,6 +440,15 @@ parse_mips_dis_option (option, len)
       return;
     }
 
+  if (strncmp("hwr-names", option, optionlen) == 0
+      && strlen("hwr-names") == optionlen)
+    {
+      chosen_arch = choose_arch_by_name (val, vallen);
+      if (chosen_arch != NULL && chosen_arch->hwr_names != NULL)
+	mips_hwr_names = chosen_arch->hwr_names;
+      return;
+    }
+
   if (strncmp("reg-names", option, optionlen) == 0
       && strlen("reg-names") == optionlen)
     {
@@ -426,6 +469,8 @@ parse_mips_dis_option (option, len)
 	{
 	  if (chosen_arch->cp0_names != NULL)
 	    mips_cp0_names = chosen_arch->cp0_names;
+	  if (chosen_arch->hwr_names != NULL)
+	    mips_hwr_names = chosen_arch->hwr_names;
 	}
       return;
     }
@@ -467,15 +512,16 @@ parse_mips_dis_options (options)
 
 /* Print insn arguments for 32/64-bit code.  */
 
-static void
+static int
 print_insn_arg (d, l, pc, info)
      const char *d;
      register unsigned long int l;
      bfd_vma pc;
      struct disassemble_info *info;
 {
-  int op, delta;
+  int op, delta, consumed;
 
+  consumed = 1;
   switch (*d)
     {
     case ',':
@@ -486,6 +532,42 @@ print_insn_arg (d, l, pc, info)
       (*info->fprintf_func) (info->stream, "%c", *d);
       break;
 
+    case '+':
+      /* Extension character; switch for second char.  */
+      d++;
+      consumed++;
+      switch (*d)
+	{
+	case 'A':
+	  (*info->fprintf_func) (info->stream, "0x%x",
+				 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
+	  break;
+	
+	case 'B':
+	  (*info->fprintf_func) (info->stream, "0x%x",
+				 (((l >> OP_SH_INSMSB) & OP_MASK_INSMSB)
+				   - ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT)
+				  + 1));
+	  break;
+
+	case 'C':
+	  (*info->fprintf_func) (info->stream, "0x%x",
+				 (((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD)
+				  + 1));
+	  break;
+
+	default:
+	  /* xgettext:c-format */
+	  (*info->fprintf_func) (info->stream,
+				 _("# internal error, undefined extension sequence (+%c)"),
+				 *d);
+	  /* Do not eat the trailing newline.  */
+	  if (*d == '\0')
+	    consumed--;
+	  break;
+	}
+      break;
+
     case 's':
     case 'b':
     case 'r':
@@ -653,6 +735,11 @@ print_insn_arg (d, l, pc, info)
 			       (l >> OP_SH_RD) & OP_MASK_RD);
       break;
 
+    case 'K':
+      (*info->fprintf_func) (info->stream, "%s",
+			     mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
+      break;
+
     case 'N':
       (*info->fprintf_func) (info->stream, "$fcc%d",
 			     (l >> OP_SH_BCC) & OP_MASK_BCC);
@@ -737,6 +824,8 @@ print_insn_arg (d, l, pc, info)
 			     *d);
       break;
     }
+
+  return consumed;
 }
 
 /* Check if the object uses NewABI conventions.  */
@@ -843,9 +932,16 @@ print_insn_mips (memaddr, word, info)
 	      d = op->args;
 	      if (d != NULL && *d != '\0')
 		{
+		  int consumed;
+
 		  (*info->fprintf_func) (info->stream, "\t");
-		  for (; *d != '\0'; d++)
-		    print_insn_arg (d, word, memaddr, info);
+		  while (*d != '\0')
+		    {
+		      /* print_insn_arg will not eat the trailing NUL
+			 of (erroneous) multi-character strings.  */
+		      consumed = print_insn_arg (d, word, memaddr, info);
+		      d += consumed;
+		    }
 		}
 
 	      return INSNLEN;
@@ -1514,11 +1610,16 @@ with the -M switch (multiple options should be separated by commas):\n"));
                            Default: based on binary being disassembled.\n"));
 
   fprintf (stream, _("\n\
+  hwr-names=ARCH           Print HWR names according to specified \n\
+			   architecture.\n\
+                           Default: based on binary being disassembled.\n"));
+
+  fprintf (stream, _("\n\
   reg-names=ABI            Print GPR and FPR names according to\n\
                            specified ABI.\n"));
 
   fprintf (stream, _("\n\
-  reg-names=ARCH           Print CP0 register names according to\n\
+  reg-names=ARCH           Print CP0 register and HWR names according to\n\
                            specified architecture.\n"));
 
   fprintf (stream, _("\n\
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 61a2ebd79a5..c35aa065ce7 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -4,7 +4,8 @@
    Contributed by Ralph Campbell and OSF
    Commented and modified by Ian Lance Taylor, Cygnus Support
    Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc.
-   MIPS-3D and MDMX support added by Broadcom Corporation (SiByte).
+   MIPS-3D, MDMX, and MIPS32 Release 2 support added by Broadcom
+   Corporation (SiByte).
 
 This file is part of GDB, GAS, and the GNU binutils.
 
@@ -85,6 +86,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 #define I5	INSN_ISA5
 #define I32	INSN_ISA32
 #define I64     INSN_ISA64
+#define I33	INSN_ISA32R2
 
 /* MIPS64 MIPS-3D ASE support.  */
 #define I16     INSN_MIPS16
@@ -137,8 +139,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* name,    args,	match,	    mask,	pinfo,          	membership */
 {"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,           	I4|I32|G3	},
 {"prefx",   "h,t(b)",	0x4c00000f, 0xfc0007ff, RD_b|RD_t,		I4	},
-{"nop",     "",         0x00000000, 0xffffffff, 0,              	I1      },
-{"ssnop",   "",         0x00000040, 0xffffffff, 0,              	I32|N55	},
+{"nop",     "",         0x00000000, 0xffffffff, 0,              	I1      }, /* sll */
+{"ssnop",   "",         0x00000040, 0xffffffff, 0,              	I32|N55	}, /* sll */
+{"ehb",     "",         0x000000c0, 0xffffffff, 0,              	I33	}, /* sll */
 {"li",      "t,j",      0x24000000, 0xffe00000, WR_t,			I1	}, /* addiu */
 {"li",	    "t,i",	0x34000000, 0xffe00000, WR_t,			I1	}, /* ori */
 {"li",      "t,I",	0,    (int) M_LI,	INSN_MACRO,		I1	},
@@ -478,6 +481,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dctr",    "o(b)",	0xbc050000, 0xfc1f0000, RD_b,			I3	},
 {"dctw",    "o(b)",	0xbc090000, 0xfc1f0000, RD_b,			I3	},
 {"deret",   "",         0x4200001f, 0xffffffff, 0, 			I32|G2	},
+{"di",      "",		0x41606000, 0xffffffff,	WR_t|WR_C0,		I33	},
+{"di",      "t",	0x41606000, 0xffe0ffff,	WR_t|WR_C0,		I33	},
 /* For ddiv, see the comments about div.  */
 {"ddiv",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I3      },
 {"ddiv",    "d,v,t",	0,    (int) M_DDIV_3,	INSN_MACRO,		I3	},
@@ -574,7 +579,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dsub",    "d,v,I",	0,    (int) M_DSUB_I,	INSN_MACRO,		I3	},
 {"dsubu",   "d,v,t",	0x0000002f, 0xfc0007ff,	WR_d|RD_s|RD_t,		I3	},
 {"dsubu",   "d,v,I",	0,    (int) M_DSUBU_I,	INSN_MACRO,		I3	},
+{"ei",      "",		0x41606020, 0xffffffff,	WR_t|WR_C0,		I33	},
+{"ei",      "t",	0x41606020, 0xffe0ffff,	WR_t|WR_C0,		I33	},
 {"eret",    "",         0x42000018, 0xffffffff, 0,      		I3|I32	},
+{"ext",     "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s,    		I33	},
 {"floor.l.d", "D,S",	0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,		I3	},
 {"floor.l.s", "D,S",	0x4600000b, 0xffff003f, WR_D|RD_S|FP_S,		I3	},
 {"floor.w.d", "D,S",	0x4620000f, 0xffff003f, WR_D|RD_S|FP_D,		I2	},
@@ -583,7 +591,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"flushd",  "",		0xbc020000, 0xffffffff, 0, 			L1	},
 {"flushid", "",		0xbc030000, 0xffffffff, 0, 			L1	},
 {"hibernate","",        0x42000023, 0xffffffff,	0, 			V1	},
+{"ins",     "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s,    		I33	},
 {"jr",      "s",	0x00000008, 0xfc1fffff,	UBD|RD_s,		I1	},
+{"jr.hb",   "s",	0x00000408, 0xfc1fffff,	UBD|RD_s,		I33	},
 {"j",       "s",	0x00000008, 0xfc1fffff,	UBD|RD_s,		I1	}, /* jr */
 /* SVR4 PIC code requires special handling for j, so it must be a
    macro.  */
@@ -594,6 +604,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"j",       "a",	0x08000000, 0xfc000000,	UBD,			I1	},
 {"jalr",    "s",	0x0000f809, 0xfc1fffff,	UBD|RD_s|WR_d,		I1	},
 {"jalr",    "d,s",	0x00000009, 0xfc1f07ff,	UBD|RD_s|WR_d,		I1	},
+{"jalr.hb", "s",	0x0000fc09, 0xfc1fffff,	UBD|RD_s|WR_d,		I33	},
+{"jalr.hb", "d,s",	0x00000409, 0xfc1f07ff,	UBD|RD_s|WR_d,		I33	},
 /* SVR4 PIC code requires special handling for jal, so it must be a
    macro.  */
 {"jal",     "d,s",	0,     (int) M_JAL_2,	INSN_MACRO,		I1	},
@@ -705,8 +717,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mfc0",    "t,G,H",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 	I32     },
 {"mfc1",    "t,S",	0x44000000, 0xffe007ff,	LCD|WR_t|RD_S|FP_S,	I1	},
 {"mfc1",    "t,G",	0x44000000, 0xffe007ff,	LCD|WR_t|RD_S|FP_S,	I1	},
+{"mfhc1",   "t,S",	0x44600000, 0xffe007ff,	LCD|WR_t|RD_S|FP_S,	I33	},
+{"mfhc1",   "t,G",	0x44600000, 0xffe007ff,	LCD|WR_t|RD_S|FP_S,	I33	},
 {"mfc2",    "t,G",	0x48000000, 0xffe007ff,	LCD|WR_t|RD_C2,		I1	},
 {"mfc2",    "t,G,H",    0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 	I32     },
+{"mfhc2",   "t,i",	0x48600000, 0xffe00000,	LCD|WR_t|RD_C2,		I33	},
 {"mfc3",    "t,G",	0x4c000000, 0xffe007ff,	LCD|WR_t|RD_C3,		I1	},
 {"mfc3",    "t,G,H",    0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 	I32     },
 {"mfdr",    "t,G",	0x7000003d, 0xffe007ff,	LCD|WR_t|RD_C0,		N5      },
@@ -765,8 +780,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mtc0",    "t,G,H",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   I32     },
 {"mtc1",    "t,S",	0x44800000, 0xffe007ff,	COD|RD_t|WR_S|FP_S,	I1	},
 {"mtc1",    "t,G",	0x44800000, 0xffe007ff,	COD|RD_t|WR_S|FP_S,	I1	},
+{"mthc1",   "t,S",	0x44e00000, 0xffe007ff,	COD|RD_t|WR_S|FP_S,	I33	},
+{"mthc1",   "t,G",	0x44e00000, 0xffe007ff,	COD|RD_t|WR_S|FP_S,	I33	},
 {"mtc2",    "t,G",	0x48800000, 0xffe007ff,	COD|RD_t|WR_C2|WR_CC,	I1	},
 {"mtc2",    "t,G,H",    0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   I32     },
+{"mthc2",   "t,i",	0x48e00000, 0xffe00000,	COD|RD_t|WR_C2|WR_CC,	I33	},
 {"mtc3",    "t,G",	0x4c800000, 0xffe007ff,	COD|RD_t|WR_C3|WR_CC,	I1	},
 {"mtc3",    "t,G,H",    0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   I32     },
 {"mtdr",    "t,G",	0x7080003d, 0xffe007ff,	COD|RD_t|WR_C0,		N5	},
@@ -890,6 +908,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"remu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      I1	},
 {"remu",    "d,v,t",	0,    (int) M_REMU_3,	INSN_MACRO,		I1	},
 {"remu",    "d,v,I",	0,    (int) M_REMU_3I,	INSN_MACRO,		I1	},
+{"rdhwr",   "t,K",	0x7c00003b, 0xffe007ff, WR_t,			I33	},
+{"rdpgpr",  "d,w",	0x41400000, 0xffe007ff, WR_d,			I33	},
 {"rfe",     "",		0x42000010, 0xffffffff,	0,			I1|T3	},
 {"rnas.qh", "X,Q",	0x78200025, 0xfc20f83f,	WR_D|RD_MACC|RD_T|FP_D,	MX	},
 {"rnau.ob", "X,Q",	0x78000021, 0xfc20f83f,	WR_D|RD_MACC|RD_T|FP_D,	MX|SB1	},
@@ -901,8 +921,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"rol",     "d,v,I",	0,    (int) M_ROL_I,	INSN_MACRO,		I1	},
 {"ror",     "d,v,t",	0,    (int) M_ROR,	INSN_MACRO,		I1	},
 {"ror",     "d,v,I",	0,    (int) M_ROR_I,	INSN_MACRO,		I1	},
-{"ror",	    "d,w,<",	0x00200002, 0xffe0003f,	WR_d|RD_t,		N5	},
-{"rorv",    "d,t,s",	0x00000046, 0xfc0007ff,	RD_t|RD_s|WR_d,		N5	},
+{"ror",	    "d,w,<",	0x00200002, 0xffe0003f,	WR_d|RD_t,		N5|I33	},
+{"rorv",    "d,t,s",	0x00000046, 0xfc0007ff,	RD_t|RD_s|WR_d,		N5|I33	},
+{"rotl",    "d,v,t",	0,    (int) M_ROL,	INSN_MACRO,		I33	},
+{"rotl",    "d,v,I",	0,    (int) M_ROL_I,	INSN_MACRO,		I33	},
+{"rotr",    "d,v,t",	0,    (int) M_ROR,	INSN_MACRO,		I33	},
+{"rotr",    "d,v,I",	0,    (int) M_ROR_I,	INSN_MACRO,		I33	},
+{"rotrv",   "d,t,s",	0x00000046, 0xfc0007ff,	RD_t|RD_s|WR_d,		I33	},
 {"round.l.d", "D,S",	0x46200008, 0xffff003f, WR_D|RD_S|FP_D,		I3	},
 {"round.l.s", "D,S",	0x46000008, 0xffff003f, WR_D|RD_S|FP_S,		I3	},
 {"round.w.d", "D,S",	0x4620000c, 0xffff003f, WR_D|RD_S|FP_D,		I2	},
@@ -950,6 +975,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sdr",     "t,o(b)",	0xb4000000, 0xfc000000,	SM|RD_t|RD_b,		I3	},
 {"sdr",     "t,A(b)",	0,    (int) M_SDR_AB,	INSN_MACRO,		I3	},
 {"sdxc1",   "S,t(b)",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b,	I4	},
+{"seb",     "d,w",	0x7C000420, 0xffe007ff,	WR_d|RD_t,		I33	},
+{"seh",     "d,w",	0x7C000620, 0xffe007ff,	WR_d|RD_t,		I33	},
 {"selsl",   "d,v,t",	0x00000005, 0xfc0007ff,	WR_d|RD_s|RD_t,		L1	},
 {"selsr",   "d,v,t",	0x00000001, 0xfc0007ff,	WR_d|RD_s|RD_t,		L1	},
 {"seq",     "d,v,t",	0,    (int) M_SEQ,	INSN_MACRO,		I1	},
@@ -1057,6 +1084,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sync",    "",		0x0000000f, 0xffffffff,	INSN_SYNC,		I2|G1	},
 {"sync.p",  "",		0x0000040f, 0xffffffff,	INSN_SYNC,		I2	},
 {"sync.l",  "",		0x0000000f, 0xffffffff,	INSN_SYNC,		I2	},
+{"synci",   "o(b)",	0x041f0000, 0xfc1f0000,	SM|RD_b,		I33	},
 {"syscall", "",		0x0000000c, 0xffffffff,	TRAP,			I1	},
 {"syscall", "B",	0x0000000c, 0xfc00003f,	TRAP,			I1	},
 {"teqi",    "s,j",	0x040c0000, 0xfc1f0000, RD_s|TRAP,		I2	},
@@ -1125,6 +1153,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"wait",    "J",        0x42000020, 0xfe00003f, TRAP,   		I32|N55	},
 {"waiti",   "",		0x42000020, 0xffffffff,	TRAP,			L1	},
 {"wb", 	    "o(b)",	0xbc040000, 0xfc1f0000, SM|RD_b,		L1	},
+{"wrpgpr",  "d,w",	0x41c00000, 0xffe007ff, RD_t,			I33	},
+{"wsbh",    "d,w",	0x7C0000a0, 0xffe007ff,	WR_d|RD_t,		I33	},
 {"xor",     "d,v,t",	0x00000026, 0xfc0007ff,	WR_d|RD_s|RD_t,		I1	},
 {"xor",     "t,r,I",	0,    (int) M_XOR_I,	INSN_MACRO,		I1	},
 {"xor.ob",  "X,Y,Q",	0x7800000d, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	MX|SB1	},