diff options
| author | Andrew Cagney <cagney@redhat.com> | 2002-06-21 16:20:04 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 2002-06-21 16:20:04 +0000 |
| commit | 92fc193b6c4cff50d5d50f5eb23bdb7bdec76409 (patch) | |
| tree | b3147a97494e575b26dca38f8c58b96837e7d783 | |
| parent | 5e29233fc22b6466e4cbcc15282e2354c70a10ae (diff) | |
| download | gdb-92fc193b6c4cff50d5d50f5eb23bdb7bdec76409.tar.gz | |
Merge with trunk.
111 files changed, 22067 insertions, 1731 deletions
diff --git a/ChangeLog b/ChangeLog index 27ac092f6d2..62a463787f9 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,26 @@ +2002-06-19 Nathanael Nerode <neroden@twcny.rr.com> + + * configure.in: replace ${topsrcdir} with ${srcdir} + + * configure.in: Move definition of libstdcxx_flags + right above usage, rather than waaay earlier. + + * configure.in: Pull definition of is_cross_compiler earlier. + + * configure.in: Rearrange a little. + + * configure.in: Remove references to librx. + * Makefile.in: Remove references to librx. + +2002-06-19 Nathanael Nerode <neroden@twcny.rr.com> + + * configure.in: Eliminate ${gasdir} variable. + +2002-06-18 Dave Brolley <brolley@redhat.com> + + * configure.in: Add support for frv. + * config.sub: Add support for frv. + 2002-06-12 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> * Makefile.in (CFLAGS_FOR_TARGET): Add -O2. diff --git a/Makefile.in b/Makefile.in index 4a761096539..6aa538355aa 100644 --- a/Makefile.in +++ b/Makefile.in @@ -186,7 +186,7 @@ OTHERS = # This is set by the configure script to the list of directories which # should be built using the target tools. -TARGET_CONFIGDIRS = libiberty libgloss $(SPECIAL_LIBS) newlib librx winsup opcodes bsp libstub cygmon libf2c libobjc +TARGET_CONFIGDIRS = libiberty libgloss $(SPECIAL_LIBS) newlib winsup opcodes bsp libstub cygmon libf2c libobjc # Target libraries are put under this directory: # Changed by configure to $(target_alias) if cross. @@ -783,7 +783,6 @@ INSTALL_X11_MODULES = \ # using $(TARGET_FLAGS_TO_PASS). ALL_TARGET_MODULES = \ all-target-libstdc++-v3 \ - all-target-librx \ all-target-newlib \ all-target-libf2c \ all-target-libobjc \ @@ -806,7 +805,6 @@ ALL_TARGET_MODULES = \ # are compiled using the target tools. CONFIGURE_TARGET_MODULES = \ configure-target-libstdc++-v3 \ - configure-target-librx \ configure-target-newlib \ configure-target-libf2c \ configure-target-libobjc \ @@ -932,7 +930,6 @@ CLEAN_MODULES = \ # All of the target modules that can be cleaned CLEAN_TARGET_MODULES = \ clean-target-libstdc++-v3 \ - clean-target-librx \ clean-target-newlib \ clean-target-libf2c \ clean-target-libobjc \ @@ -1747,7 +1744,7 @@ all-target-gperf: configure-target-gperf all-target-libiberty all-target-libstdc all-gprof: all-libiberty all-bfd all-opcodes all-intl all-grep: all-libiberty all-grez: all-libiberty all-bfd all-opcodes -all-gui: all-gdb all-libproc all-target-librx +all-gui: all-gdb all-libproc all-guile: all-gzip: all-libiberty all-hello: all-libiberty @@ -1768,8 +1765,6 @@ configure-target-libffi: $(ALL_GCC_C) all-target-libffi: configure-target-libffi configure-target-libjava: $(ALL_GCC_C) configure-target-zlib configure-target-boehm-gc configure-target-qthreads configure-target-libffi all-target-libjava: configure-target-libjava all-fastjar all-target-zlib all-target-boehm-gc all-target-qthreads all-target-libffi -configure-target-librx: $(ALL_GCC_C) -all-target-librx: configure-target-librx configure-target-libstdc++-v3: $(ALL_GCC_C) all-target-libstdc++-v3: configure-target-libstdc++-v3 all-target-libiberty configure-target-libstub: $(ALL_GCC_C) diff --git a/bfd/ChangeLog b/bfd/ChangeLog index 1a8b4b0fa22..b4af06c79ff 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,72 @@ +2002-06-19 Nick Clifton <nickc@cambridge.redhat.com> + + * elflink.h (size_dynamic_sections): If the target does not + support an ELF style has table, return true, indicating that + nothing needed to be done, rather than false, indicating that the + section's size could not be computed. + +2002-06-18 Dave Brolley <brolley@redhat.com> + + From Catherine Moore, Michael Meissner, Dave Brolley: + * po/SRC-POTFILES.in: Add cpu-frv.c and elf32-frv.c + * targets.c: Support bfd_elf32_frv_vec. + * reloc.c: Add FRV relocs. + * configure.in: Add support for bfd-elf32-frv-vec. + * config.bfd (targ_cpu): Add support for frv-*-elf. + * archures.c: Add frv arch and machines. + * Makefile.am (ALL_MACHINES): Add cpu-frv.lo. + (ALL_MACHINES_CFILES): Add cpu-frv.c. + (BFD32_BACKENDS): Add elf32-frv.lo. + (BFD32_BACKENDS_CFILES): Add elf32-frv.c + (cpu-frv.lo): New target. + (elf32-frv.lo): New target. + * cpu-frv.c: New file. + * elf32-frv.c: New file. + +2002-06-18 Jakub Jelinek <jakub@redhat.com> + + * elfcode.h (elf_object_p): Sanity check eh_shoff == 0 implies + e_shnum == 0. + Only read the first section header if e_shoff is non-zero. + Don't consider e_shstrndx if there are no sections. + +2002-06-17 Tom Rix <trix@redhat.com> + + * elf32-d10v.c (elf_d10v_howto_table): Change R_D10V_10_PCREL_R, + R_D10V_10_PCREL_L and R_D10V_18_PCREL to use + complain_overflow_bitfield. + +2002-06-17 Alan Modra <amodra@bigpond.net.au> + + * opncls.c (bfd_openr): Remove redundant bfd_set_error. + (bfd_fdopenr): Likewise. + (bfd_openstreamr): Likewise. + (bfd_openw): Likewise. + + * targets.c: Sort target vecs. + (_bfd_target_vector): Add aix5coff64_vec, bfd_elf32_sh64_vec, + bfd_elf32_sh64l_vec, bfd_elf32_sh64lnbsd_vec, + bfd_elf32_sh64nbsd_vec, bfd_elf64_sh64_vec, bfd_elf64_sh64l_vec, + bfd_elf64_sh64lnbsd_vec, bfd_elf64_sh64nbsd_vec. + * configure.in: Sort target vecs. Add m88kmach3_vec. + * configure: Regenerate. + +2002-06-16 Hans-Peter Nilsson <hp@bitrange.com> + + * elf64-mmix.c (bpo_reloc_request_sort_fn): Use member + bpo_reloc_no to break sort order ties, not address of items. + +2002-06-16 John David Anglin <dave@hiauly1.hia.nrc.ca> + + * elf-hppa.h (elf_hppa_final_link): Fix formatting in comment. + Skip excluded sections in determing __gp value. + (elf_hppa_final_link_relocate): Use the symbol's address in + R_PARISC_FPTR64 relocations that don't need an opd entry. + * elf64-hppa.c (allocate_dynrel_entries): Simplify code. + (elf64_hppa_finalize_dynreloc): Likewise. + (elf64_hppa_size_dynamic_sections): Move comments and fix typo. + (elf64_hppa_finish_dynamic_symbol): Break up assert. + 2002-06-14 Sergey Grigoriev <serge@leopold.Physik.Uni-Augsburg.DE> * pei-i386.c (COFF_SECTION_ALIGNMENT_ENTRIES): Enable 16 byte diff --git a/bfd/Makefile.am b/bfd/Makefile.am index da399788af5..62afb1df943 100644 --- a/bfd/Makefile.am +++ b/bfd/Makefile.am @@ -58,6 +58,7 @@ ALL_MACHINES = \ cpu-d30v.lo \ cpu-dlx.lo \ cpu-fr30.lo \ + cpu-frv.lo \ cpu-h8300.lo \ cpu-h8500.lo \ cpu-hppa.lo \ @@ -107,6 +108,7 @@ ALL_MACHINES_CFILES = \ cpu-d30v.c \ cpu-dlx.c \ cpu-fr30.c \ + cpu-frv.c \ cpu-h8300.c \ cpu-h8500.c \ cpu-hppa.c \ @@ -202,6 +204,7 @@ BFD32_BACKENDS = \ elf32-d30v.lo \ elf32-dlx.lo \ elf32-fr30.lo \ + elf32-frv.lo \ elf32-gen.lo \ elf32-h8300.lo \ elf32-hppa.lo \ @@ -357,6 +360,7 @@ BFD32_BACKENDS_CFILES = \ elf32-d30v.c \ elf32-dlx.c \ elf32-fr30.c \ + elf32-frv.c \ elf32-gen.c \ elf32-h8300.c \ elf32-hppa.c \ @@ -830,7 +834,6 @@ DISTCLEANFILES = $(BUILD_CFILES) $(BUILD_HFILES) config.status: $(srcdir)/configure $(srcdir)/config.bfd $(srcdir)/configure.host $(SHELL) ./config.status --recheck - # What appears below is generated by a hacked mkdep using gcc -MM. # DO NOT DELETE THIS LINE -- mkdep uses it. @@ -886,6 +889,7 @@ cpu-d10v.lo: cpu-d10v.c $(INCDIR)/filenames.h cpu-d30v.lo: cpu-d30v.c $(INCDIR)/filenames.h cpu-dlx.lo: cpu-dlx.c $(INCDIR)/filenames.h cpu-fr30.lo: cpu-fr30.c $(INCDIR)/filenames.h +cpu-frv.lo: cpu-frv.c $(INCDIR)/filenames.h cpu-h8300.lo: cpu-h8300.c $(INCDIR)/filenames.h cpu-h8500.lo: cpu-h8500.c $(INCDIR)/filenames.h cpu-hppa.lo: cpu-hppa.c $(INCDIR)/filenames.h @@ -1109,6 +1113,10 @@ elf32-fr30.lo: elf32-fr30.c $(INCDIR)/filenames.h elf-bfd.h \ $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ $(INCDIR)/bfdlink.h $(INCDIR)/elf/fr30.h $(INCDIR)/elf/reloc-macros.h \ elf32-target.h +elf32-frv.lo: elf32-frv.c elf-bfd.h $(INCDIR)/elf/common.h \ + $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \ + $(INCDIR)/elf/frv.h $(INCDIR)/elf/reloc-macros.h \ + elf32-target.h elf32-gen.lo: elf32-gen.c $(INCDIR)/filenames.h elf-bfd.h \ $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ $(INCDIR)/bfdlink.h elf32-target.h diff --git a/bfd/Makefile.in b/bfd/Makefile.in index 983ac2f47bc..bb2407229cf 100644 --- a/bfd/Makefile.in +++ b/bfd/Makefile.in @@ -163,18 +163,18 @@ BFD64_LIBS_CFILES = archive64.c # This list is alphabetized to make it easier to keep in sync # with the decls and initializer in archures.c. -ALL_MACHINES = cpu-a29k.lo cpu-alpha.lo cpu-arc.lo cpu-arm.lo cpu-avr.lo cpu-cris.lo cpu-d10v.lo cpu-d30v.lo cpu-dlx.lo cpu-fr30.lo cpu-h8300.lo cpu-h8500.lo cpu-hppa.lo cpu-ia64.lo cpu-i370.lo cpu-i386.lo cpu-i860.lo cpu-i960.lo cpu-m32r.lo cpu-m68hc11.lo cpu-m68hc12.lo cpu-m68k.lo cpu-m88k.lo cpu-m10200.lo cpu-m10300.lo cpu-mcore.lo cpu-mips.lo cpu-mmix.lo cpu-or32.lo cpu-ns32k.lo cpu-openrisc.lo cpu-pdp11.lo cpu-pj.lo cpu-powerpc.lo cpu-rs6000.lo cpu-s390.lo cpu-sh.lo cpu-sparc.lo cpu-tic30.lo cpu-tic54x.lo cpu-tic80.lo cpu-v850.lo cpu-vax.lo cpu-we32k.lo cpu-w65.lo cpu-xstormy16.lo cpu-z8k.lo +ALL_MACHINES = cpu-a29k.lo cpu-alpha.lo cpu-arc.lo cpu-arm.lo cpu-avr.lo cpu-cris.lo cpu-d10v.lo cpu-d30v.lo cpu-dlx.lo cpu-fr30.lo cpu-frv.lo cpu-h8300.lo cpu-h8500.lo cpu-hppa.lo cpu-ia64.lo cpu-i370.lo cpu-i386.lo cpu-i860.lo cpu-i960.lo cpu-m32r.lo cpu-m68hc11.lo cpu-m68hc12.lo cpu-m68k.lo cpu-m88k.lo cpu-m10200.lo cpu-m10300.lo cpu-mcore.lo cpu-mips.lo cpu-mmix.lo cpu-or32.lo cpu-ns32k.lo cpu-openrisc.lo cpu-pdp11.lo cpu-pj.lo cpu-powerpc.lo cpu-rs6000.lo cpu-s390.lo cpu-sh.lo cpu-sparc.lo cpu-tic30.lo cpu-tic54x.lo cpu-tic80.lo cpu-v850.lo cpu-vax.lo cpu-we32k.lo cpu-w65.lo cpu-xstormy16.lo cpu-z8k.lo -ALL_MACHINES_CFILES = cpu-a29k.c cpu-alpha.c cpu-arc.c cpu-arm.c cpu-avr.c cpu-cris.c cpu-d10v.c cpu-d30v.c cpu-dlx.c cpu-fr30.c cpu-h8300.c cpu-h8500.c cpu-hppa.c cpu-ia64.c cpu-i370.c cpu-i386.c cpu-i860.c cpu-i960.c cpu-m32r.c cpu-m68hc11.c cpu-m68hc12.c cpu-m68k.c cpu-m88k.c cpu-m10200.c cpu-m10300.c cpu-mcore.c cpu-mips.c cpu-mmix.c cpu-or32.c cpu-ns32k.c cpu-openrisc.c cpu-pdp11.c cpu-pj.c cpu-powerpc.c cpu-rs6000.c cpu-s390.c cpu-sh.c cpu-sparc.c cpu-tic30.c cpu-tic54x.c cpu-tic80.c cpu-v850.c cpu-vax.c cpu-we32k.c cpu-w65.c cpu-xstormy16.c cpu-z8k.c +ALL_MACHINES_CFILES = cpu-a29k.c cpu-alpha.c cpu-arc.c cpu-arm.c cpu-avr.c cpu-cris.c cpu-d10v.c cpu-d30v.c cpu-dlx.c cpu-fr30.c cpu-frv.c cpu-h8300.c cpu-h8500.c cpu-hppa.c cpu-ia64.c cpu-i370.c cpu-i386.c cpu-i860.c cpu-i960.c cpu-m32r.c cpu-m68hc11.c cpu-m68hc12.c cpu-m68k.c cpu-m88k.c cpu-m10200.c cpu-m10300.c cpu-mcore.c cpu-mips.c cpu-mmix.c cpu-or32.c cpu-ns32k.c cpu-openrisc.c cpu-pdp11.c cpu-pj.c cpu-powerpc.c cpu-rs6000.c cpu-s390.c cpu-sh.c cpu-sparc.c cpu-tic30.c cpu-tic54x.c cpu-tic80.c cpu-v850.c cpu-vax.c cpu-we32k.c cpu-w65.c cpu-xstormy16.c cpu-z8k.c # The .o files needed by all of the 32 bit vectors that are configured into # target_vector in targets.c if configured with --enable-targets=all. -BFD32_BACKENDS = aout-adobe.lo aout-arm.lo aout-cris.lo aout-ns32k.lo aout-sparcle.lo aout-tic30.lo aout0.lo aout32.lo armnetbsd.lo bout.lo cf-i386lynx.lo cf-m68klynx.lo cf-sparclynx.lo coff-a29k.lo coff-apollo.lo coff-arm.lo coff-aux.lo coff-h8300.lo coff-h8500.lo coff-i386.lo coff-go32.lo coff-i860.lo coff-i960.lo coff-m68k.lo coff-m88k.lo coff-mips.lo coff-or32.lo coff-rs6000.lo coff-sh.lo coff-sparc.lo coff-stgo32.lo coff-svm68k.lo coff-tic30.lo coff-tic54x.lo coff-tic80.lo coff-u68k.lo coff-we32k.lo coff-w65.lo coff-z8k.lo cofflink.lo dwarf1.lo ecoff.lo ecofflink.lo efi-app-ia32.lo elf.lo elf32-arc.lo elfarm-oabi.lo elfarm-nabi.lo elf32-avr.lo elf32-cris.lo elf32-d10v.lo elf32-d30v.lo elf32-dlx.lo elf32-fr30.lo elf32-gen.lo elf32-h8300.lo elf32-hppa.lo elf32-i370.lo elf32-i386.lo elf32-i386qnx.lo elf32-i860.lo elf32-i960.lo elf32-ia64.lo elf32-m32r.lo elf32-m68hc11.lo elf32-m68hc12.lo elf32-m68k.lo elf32-m88k.lo elf-m10200.lo elf-m10300.lo elf32-mcore.lo elfxx-mips.lo elf32-mips.lo elf32-openrisc.lo elf32-or32.lo elf32-pj.lo elf32-ppc.lo elf32-s390.lo elf32-sh.lo elf32-sh-lin.lo elf32-sh64.lo elf32-sh64-com.lo elf32-sh-nbsd.lo elf32-sh64-nbsd.lo elf32-sparc.lo elf32-v850.lo elf32-vax.lo elf32-xstormy16.lo elf32.lo elflink.lo elf-strtab.lo elf-eh-frame.lo epoc-pe-arm.lo epoc-pei-arm.lo hp300bsd.lo hp300hpux.lo som.lo i386aout.lo i386bsd.lo i386dynix.lo i386freebsd.lo i386linux.lo i386lynx.lo i386msdos.lo i386netbsd.lo i386mach3.lo i386os9k.lo ieee.lo m68k4knetbsd.lo m68klinux.lo m68klynx.lo m68knetbsd.lo m88kmach3.lo mipsbsd.lo newsos3.lo nlm.lo nlm32-i386.lo nlm32-sparc.lo nlm32-ppc.lo nlm32.lo ns32knetbsd.lo oasys.lo pc532-mach.lo pdp11.lo pe-arm.lo pei-arm.lo pe-i386.lo pei-i386.lo pe-mcore.lo pei-mcore.lo pe-ppc.lo pei-ppc.lo pe-sh.lo pei-sh.lo pe-mips.lo pei-mips.lo peigen.lo ppcboot.lo reloc16.lo riscix.lo sparclinux.lo sparclynx.lo sparcnetbsd.lo sunos.lo vaxnetbsd.lo vax1knetbsd.lo versados.lo vms.lo vms-gsd.lo vms-hdr.lo vms-misc.lo vms-tir.lo xcofflink.lo +BFD32_BACKENDS = aout-adobe.lo aout-arm.lo aout-cris.lo aout-ns32k.lo aout-sparcle.lo aout-tic30.lo aout0.lo aout32.lo armnetbsd.lo bout.lo cf-i386lynx.lo cf-m68klynx.lo cf-sparclynx.lo coff-a29k.lo coff-apollo.lo coff-arm.lo coff-aux.lo coff-h8300.lo coff-h8500.lo coff-i386.lo coff-go32.lo coff-i860.lo coff-i960.lo coff-m68k.lo coff-m88k.lo coff-mips.lo coff-or32.lo coff-rs6000.lo coff-sh.lo coff-sparc.lo coff-stgo32.lo coff-svm68k.lo coff-tic30.lo coff-tic54x.lo coff-tic80.lo coff-u68k.lo coff-we32k.lo coff-w65.lo coff-z8k.lo cofflink.lo dwarf1.lo ecoff.lo ecofflink.lo efi-app-ia32.lo elf.lo elf32-arc.lo elfarm-oabi.lo elfarm-nabi.lo elf32-avr.lo elf32-cris.lo elf32-d10v.lo elf32-d30v.lo elf32-dlx.lo elf32-fr30.lo elf32-frv.lo elf32-gen.lo elf32-h8300.lo elf32-hppa.lo elf32-i370.lo elf32-i386.lo elf32-i386qnx.lo elf32-i860.lo elf32-i960.lo elf32-ia64.lo elf32-m32r.lo elf32-m68hc11.lo elf32-m68hc12.lo elf32-m68k.lo elf32-m88k.lo elf-m10200.lo elf-m10300.lo elf32-mcore.lo elfxx-mips.lo elf32-mips.lo elf32-openrisc.lo elf32-or32.lo elf32-pj.lo elf32-ppc.lo elf32-s390.lo elf32-sh.lo elf32-sh-lin.lo elf32-sh64.lo elf32-sh64-com.lo elf32-sh-nbsd.lo elf32-sh64-nbsd.lo elf32-sparc.lo elf32-v850.lo elf32-vax.lo elf32-xstormy16.lo elf32.lo elflink.lo elf-strtab.lo elf-eh-frame.lo epoc-pe-arm.lo epoc-pei-arm.lo hp300bsd.lo hp300hpux.lo som.lo i386aout.lo i386bsd.lo i386dynix.lo i386freebsd.lo i386linux.lo i386lynx.lo i386msdos.lo i386netbsd.lo i386mach3.lo i386os9k.lo ieee.lo m68k4knetbsd.lo m68klinux.lo m68klynx.lo m68knetbsd.lo m88kmach3.lo mipsbsd.lo newsos3.lo nlm.lo nlm32-i386.lo nlm32-sparc.lo nlm32-ppc.lo nlm32.lo ns32knetbsd.lo oasys.lo pc532-mach.lo pdp11.lo pe-arm.lo pei-arm.lo pe-i386.lo pei-i386.lo pe-mcore.lo pei-mcore.lo pe-ppc.lo pei-ppc.lo pe-sh.lo pei-sh.lo pe-mips.lo pei-mips.lo peigen.lo ppcboot.lo reloc16.lo riscix.lo sparclinux.lo sparclynx.lo sparcnetbsd.lo sunos.lo vaxnetbsd.lo vax1knetbsd.lo versados.lo vms.lo vms-gsd.lo vms-hdr.lo vms-misc.lo vms-tir.lo xcofflink.lo -BFD32_BACKENDS_CFILES = aout-adobe.c aout-arm.c aout-cris.c aout-ns32k.c aout-sparcle.c aout-tic30.c aout0.c aout32.c armnetbsd.c bout.c cf-i386lynx.c cf-m68klynx.c cf-sparclynx.c coff-a29k.c coff-apollo.c coff-arm.c coff-aux.c coff-h8300.c coff-h8500.c coff-i386.c coff-i860.c coff-go32.c coff-i960.c coff-m68k.c coff-m88k.c coff-mips.c coff-or32.c coff-rs6000.c coff-sh.c coff-sparc.c coff-stgo32.c coff-svm68k.c coff-tic30.c coff-tic54x.c coff-tic80.c coff-u68k.c coff-we32k.c coff-w65.c coff-z8k.c cofflink.c dwarf1.c ecoff.c ecofflink.c efi-app-ia32.c elf.c elf32-arc.c elfarm-oabi.c elfarm-nabi.c elf32-avr.c elf32-cris.c elf32-d10v.c elf32-d30v.c elf32-dlx.c elf32-fr30.c elf32-gen.c elf32-h8300.c elf32-hppa.c elf32-i370.c elf32-i386.c elf32-i386qnx.c elf32-i860.c elf32-i960.c elf32-m32r.c elf32-m68k.c elf32-m68hc11.c elf32-m68hc12.c elf32-m88k.c elf-m10200.c elf-m10300.c elf32-mcore.c elfxx-mips.c elf32-mips.c elf32-openrisc.c elf32-or32.c elf32-pj.c elf32-ppc.c elf32-sh64.c elf32-sh64-com.c elf32-s390.c elf32-sh.c elf32-sh-lin.c elf32-sh-nbsd.c elf32-sh64-nbsd.c elf32-sparc.c elf32-v850.c elf32-vax.c elf32-xstormy16.c elf32.c elflink.c elf-strtab.c elf-eh-frame.c epoc-pe-arm.c epoc-pei-arm.c hp300bsd.c hp300hpux.c som.c i386aout.c i386bsd.c i386dynix.c i386freebsd.c i386linux.c i386lynx.c i386msdos.c i386netbsd.c i386mach3.c i386os9k.c ieee.c m68k4knetbsd.c m68klinux.c m68klynx.c m68knetbsd.c m88kmach3.c mipsbsd.c newsos3.c nlm.c nlm32-i386.c nlm32-sparc.c nlm32-ppc.c nlm32.c ns32knetbsd.c oasys.c pc532-mach.c pdp11.c pe-arm.c pei-arm.c pe-i386.c pei-i386.c pe-mcore.c pei-mcore.c pe-ppc.c pei-ppc.c pe-sh.c pei-sh.c pe-mips.c pei-mips.c ppcboot.c reloc16.c riscix.c sparclinux.c sparclynx.c sparcnetbsd.c sunos.c vaxnetbsd.c vax1knetbsd.c versados.c vms.c vms-gsd.c vms-hdr.c vms-misc.c vms-tir.c xcofflink.c +BFD32_BACKENDS_CFILES = aout-adobe.c aout-arm.c aout-cris.c aout-ns32k.c aout-sparcle.c aout-tic30.c aout0.c aout32.c armnetbsd.c bout.c cf-i386lynx.c cf-m68klynx.c cf-sparclynx.c coff-a29k.c coff-apollo.c coff-arm.c coff-aux.c coff-h8300.c coff-h8500.c coff-i386.c coff-i860.c coff-go32.c coff-i960.c coff-m68k.c coff-m88k.c coff-mips.c coff-or32.c coff-rs6000.c coff-sh.c coff-sparc.c coff-stgo32.c coff-svm68k.c coff-tic30.c coff-tic54x.c coff-tic80.c coff-u68k.c coff-we32k.c coff-w65.c coff-z8k.c cofflink.c dwarf1.c ecoff.c ecofflink.c efi-app-ia32.c elf.c elf32-arc.c elfarm-oabi.c elfarm-nabi.c elf32-avr.c elf32-cris.c elf32-d10v.c elf32-d30v.c elf32-dlx.c elf32-fr30.c elf32-frv.c elf32-gen.c elf32-h8300.c elf32-hppa.c elf32-i370.c elf32-i386.c elf32-i386qnx.c elf32-i860.c elf32-i960.c elf32-m32r.c elf32-m68k.c elf32-m68hc11.c elf32-m68hc12.c elf32-m88k.c elf-m10200.c elf-m10300.c elf32-mcore.c elfxx-mips.c elf32-mips.c elf32-openrisc.c elf32-or32.c elf32-pj.c elf32-ppc.c elf32-sh64.c elf32-sh64-com.c elf32-s390.c elf32-sh.c elf32-sh-lin.c elf32-sh-nbsd.c elf32-sh64-nbsd.c elf32-sparc.c elf32-v850.c elf32-vax.c elf32-xstormy16.c elf32.c elflink.c elf-strtab.c elf-eh-frame.c epoc-pe-arm.c epoc-pei-arm.c hp300bsd.c hp300hpux.c som.c i386aout.c i386bsd.c i386dynix.c i386freebsd.c i386linux.c i386lynx.c i386msdos.c i386netbsd.c i386mach3.c i386os9k.c ieee.c m68k4knetbsd.c m68klinux.c m68klynx.c m68knetbsd.c m88kmach3.c mipsbsd.c newsos3.c nlm.c nlm32-i386.c nlm32-sparc.c nlm32-ppc.c nlm32.c ns32knetbsd.c oasys.c pc532-mach.c pdp11.c pe-arm.c pei-arm.c pe-i386.c pei-i386.c pe-mcore.c pei-mcore.c pe-ppc.c pei-ppc.c pe-sh.c pei-sh.c pe-mips.c pei-mips.c ppcboot.c reloc16.c riscix.c sparclinux.c sparclynx.c sparcnetbsd.c sunos.c vaxnetbsd.c vax1knetbsd.c versados.c vms.c vms-gsd.c vms-hdr.c vms-misc.c vms-tir.c xcofflink.c # The .o files needed by all of the 64 bit vectors that are configured into @@ -930,6 +930,7 @@ cpu-d10v.lo: cpu-d10v.c $(INCDIR)/filenames.h cpu-d30v.lo: cpu-d30v.c $(INCDIR)/filenames.h cpu-dlx.lo: cpu-dlx.c $(INCDIR)/filenames.h cpu-fr30.lo: cpu-fr30.c $(INCDIR)/filenames.h +cpu-frv.lo: cpu-frv.c $(INCDIR)/filenames.h cpu-h8300.lo: cpu-h8300.c $(INCDIR)/filenames.h cpu-h8500.lo: cpu-h8500.c $(INCDIR)/filenames.h cpu-hppa.lo: cpu-hppa.c $(INCDIR)/filenames.h @@ -1153,6 +1154,10 @@ elf32-fr30.lo: elf32-fr30.c $(INCDIR)/filenames.h elf-bfd.h \ $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ $(INCDIR)/bfdlink.h $(INCDIR)/elf/fr30.h $(INCDIR)/elf/reloc-macros.h \ elf32-target.h +elf32-frv.lo: elf32-frv.c $(INCDIR)/filenames.h elf-bfd.h \ + $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ + $(INCDIR)/bfdlink.h $(INCDIR)/elf/frv.h $(INCDIR)/elf/reloc-macros.h \ + elf32-target.h elf32-gen.lo: elf32-gen.c $(INCDIR)/filenames.h elf-bfd.h \ $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ $(INCDIR)/bfdlink.h elf32-target.h diff --git a/bfd/archures.c b/bfd/archures.c index 36fc56873d5..063e4fb67b9 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -247,6 +247,13 @@ DESCRIPTION .#define bfd_mach_am33 330 . bfd_arch_fr30, .#define bfd_mach_fr30 0x46523330 +. bfd_arch_frv, +.#define bfd_mach_frv 0 +.#define bfd_mach_frvsimple 1 +.#define bfd_mach_fr300 300 +.#define bfd_mach_fr400 400 +.#define bfd_mach_frvtomcat 499 {* fr500 prototype *} +.#define bfd_mach_fr500 500 . bfd_arch_mcore, . bfd_arch_ia64, {* HP/Intel ia64 *} .#define bfd_mach_ia64_elf64 0 @@ -315,6 +322,7 @@ extern const bfd_arch_info_type bfd_d10v_arch; extern const bfd_arch_info_type bfd_d30v_arch; extern const bfd_arch_info_type bfd_dlx_arch; extern const bfd_arch_info_type bfd_fr30_arch; +extern const bfd_arch_info_type bfd_frv_arch; extern const bfd_arch_info_type bfd_h8300_arch; extern const bfd_arch_info_type bfd_h8500_arch; extern const bfd_arch_info_type bfd_hppa_arch; @@ -369,6 +377,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] = &bfd_d30v_arch, &bfd_dlx_arch, &bfd_fr30_arch, + &bfd_frv_arch, &bfd_h8300_arch, &bfd_h8500_arch, &bfd_hppa_arch, diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index e4319ff91d7..4a8d802d432 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -1637,6 +1637,13 @@ enum bfd_architecture #define bfd_mach_am33 330 bfd_arch_fr30, #define bfd_mach_fr30 0x46523330 + bfd_arch_frv, +#define bfd_mach_frv 0 +#define bfd_mach_frvsimple 1 +#define bfd_mach_fr300 300 +#define bfd_mach_fr400 400 +#define bfd_mach_frvtomcat 499 /* fr500 prototype */ +#define bfd_mach_fr500 500 bfd_arch_mcore, bfd_arch_ia64, /* HP/Intel ia64 */ #define bfd_mach_ia64_elf64 0 @@ -2832,6 +2839,17 @@ value of SUBI insn. */ into 22 bits. */ BFD_RELOC_AVR_CALL, +/* Fujitsu Frv Relocations. */ + BFD_RELOC_FRV_LABEL16, + BFD_RELOC_FRV_LABEL24, + BFD_RELOC_FRV_LO16, + BFD_RELOC_FRV_HI16, + BFD_RELOC_FRV_GPREL12, + BFD_RELOC_FRV_GPRELU12, + BFD_RELOC_FRV_GPREL32, + BFD_RELOC_FRV_GPRELHI, + BFD_RELOC_FRV_GPRELLO, + /* Direct 12 bit. */ BFD_RELOC_390_12, diff --git a/bfd/config.bfd b/bfd/config.bfd index 520c36bcb4e..e87508739f6 100644 --- a/bfd/config.bfd +++ b/bfd/config.bfd @@ -281,6 +281,10 @@ case "${targ}" in targ_defvec=bfd_elf32_fr30_vec ;; + frv-*-elf) + targ_defvec=bfd_elf32_frv_vec + ;; + h8300*-*-elf) targ_defvec=bfd_elf32_h8300_vec diff --git a/bfd/configure b/bfd/configure index a17601132fa..172290bb4d8 100755 --- a/bfd/configure +++ b/bfd/configure @@ -3291,7 +3291,7 @@ EOF fi -for ac_hdr in unistd.h +for ac_hdr in stdlib.h unistd.h sys/stat.h sys/types.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 @@ -3423,11 +3423,24 @@ else #include <fcntl.h> #include <sys/mman.h> +#if HAVE_SYS_TYPES_H +# include <sys/types.h> +#endif + +#if HAVE_STDLIB_H +# include <stdlib.h> +#endif + +#if HAVE_SYS_STAT_H +# include <sys/stat.h> +#endif + +#if HAVE_UNISTD_H +# include <unistd.h> +#endif + /* This mess was copied from the GNU getpagesize.h. */ #ifndef HAVE_GETPAGESIZE -# ifdef HAVE_UNISTD_H -# include <unistd.h> -# endif /* Assume that all systems that can run configure have sys/param.h. */ # ifndef HAVE_SYS_PARAM_H @@ -3535,7 +3548,7 @@ main() } EOF -if { (eval echo configure:3539: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +if { (eval echo configure:3552: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null then ac_cv_func_mmap_fixed_mapped=yes else @@ -3563,17 +3576,17 @@ unistd.h values.h sys/param.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:3567: checking for $ac_hdr" >&5 +echo "configure:3580: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3572 "configure" +#line 3585 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:3577: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:3590: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -3603,12 +3616,12 @@ done __argz_count __argz_stringify __argz_next do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:3607: checking for $ac_func" >&5 +echo "configure:3620: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3612 "configure" +#line 3625 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -3631,7 +3644,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:3635: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3648: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -3660,12 +3673,12 @@ done for ac_func in stpcpy do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:3664: checking for $ac_func" >&5 +echo "configure:3677: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3669 "configure" +#line 3682 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -3688,7 +3701,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:3692: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3705: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -3722,19 +3735,19 @@ EOF if test $ac_cv_header_locale_h = yes; then echo $ac_n "checking for LC_MESSAGES""... $ac_c" 1>&6 -echo "configure:3726: checking for LC_MESSAGES" >&5 +echo "configure:3739: checking for LC_MESSAGES" >&5 if eval "test \"`echo '$''{'am_cv_val_LC_MESSAGES'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3731 "configure" +#line 3744 "configure" #include "confdefs.h" #include <locale.h> int main() { return LC_MESSAGES ; return 0; } EOF -if { (eval echo configure:3738: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3751: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* am_cv_val_LC_MESSAGES=yes else @@ -3755,7 +3768,7 @@ EOF fi fi echo $ac_n "checking whether NLS is requested""... $ac_c" 1>&6 -echo "configure:3759: checking whether NLS is requested" >&5 +echo "configure:3772: checking whether NLS is requested" >&5 # Check whether --enable-nls or --disable-nls was given. if test "${enable_nls+set}" = set; then enableval="$enable_nls" @@ -3775,7 +3788,7 @@ fi EOF echo $ac_n "checking whether included gettext is requested""... $ac_c" 1>&6 -echo "configure:3779: checking whether included gettext is requested" >&5 +echo "configure:3792: checking whether included gettext is requested" >&5 # Check whether --with-included-gettext or --without-included-gettext was given. if test "${with_included_gettext+set}" = set; then withval="$with_included_gettext" @@ -3794,17 +3807,17 @@ fi ac_safe=`echo "libintl.h" | sed 'y%./+-%__p_%'` echo $ac_n "checking for libintl.h""... $ac_c" 1>&6 -echo "configure:3798: checking for libintl.h" >&5 +echo "configure:3811: checking for libintl.h" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3803 "configure" +#line 3816 "configure" #include "confdefs.h" #include <libintl.h> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:3808: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:3821: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -3821,19 +3834,19 @@ fi if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then echo "$ac_t""yes" 1>&6 echo $ac_n "checking for gettext in libc""... $ac_c" 1>&6 -echo "configure:3825: checking for gettext in libc" >&5 +echo "configure:3838: checking for gettext in libc" >&5 if eval "test \"`echo '$''{'gt_cv_func_gettext_libc'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3830 "configure" +#line 3843 "configure" #include "confdefs.h" #include <libintl.h> int main() { return (int) gettext ("") ; return 0; } EOF -if { (eval echo configure:3837: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3850: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* gt_cv_func_gettext_libc=yes else @@ -3849,7 +3862,7 @@ echo "$ac_t""$gt_cv_func_gettext_libc" 1>&6 if test "$gt_cv_func_gettext_libc" != "yes"; then echo $ac_n "checking for bindtextdomain in -lintl""... $ac_c" 1>&6 -echo "configure:3853: checking for bindtextdomain in -lintl" >&5 +echo "configure:3866: checking for bindtextdomain in -lintl" >&5 ac_lib_var=`echo intl'_'bindtextdomain | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -3857,7 +3870,7 @@ else ac_save_LIBS="$LIBS" LIBS="-lintl $LIBS" cat > conftest.$ac_ext <<EOF -#line 3861 "configure" +#line 3874 "configure" #include "confdefs.h" /* Override any gcc2 internal prototype to avoid an error. */ /* We use char because int might match the return type of a gcc2 @@ -3868,7 +3881,7 @@ int main() { bindtextdomain() ; return 0; } EOF -if { (eval echo configure:3872: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3885: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_lib_$ac_lib_var=yes" else @@ -3884,19 +3897,19 @@ fi if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then echo "$ac_t""yes" 1>&6 echo $ac_n "checking for gettext in libintl""... $ac_c" 1>&6 -echo "configure:3888: checking for gettext in libintl" >&5 +echo "configure:3901: checking for gettext in libintl" >&5 if eval "test \"`echo '$''{'gt_cv_func_gettext_libintl'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3893 "configure" +#line 3906 "configure" #include "confdefs.h" int main() { return (int) gettext ("") ; return 0; } EOF -if { (eval echo configure:3900: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3913: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* gt_cv_func_gettext_libintl=yes else @@ -3924,7 +3937,7 @@ EOF # Extract the first word of "msgfmt", so it can be a program name with args. set dummy msgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3928: checking for $ac_word" >&5 +echo "configure:3941: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3958,12 +3971,12 @@ fi for ac_func in dcgettext do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:3962: checking for $ac_func" >&5 +echo "configure:3975: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3967 "configure" +#line 3980 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -3986,7 +3999,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:3990: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:4003: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -4013,7 +4026,7 @@ done # Extract the first word of "gmsgfmt", so it can be a program name with args. set dummy gmsgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4017: checking for $ac_word" >&5 +echo "configure:4030: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4049,7 +4062,7 @@ fi # Extract the first word of "xgettext", so it can be a program name with args. set dummy xgettext; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4053: checking for $ac_word" >&5 +echo "configure:4066: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4081,7 +4094,7 @@ else fi cat > conftest.$ac_ext <<EOF -#line 4085 "configure" +#line 4098 "configure" #include "confdefs.h" int main() { @@ -4089,7 +4102,7 @@ extern int _nl_msg_cat_cntr; return _nl_msg_cat_cntr ; return 0; } EOF -if { (eval echo configure:4093: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:4106: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* CATOBJEXT=.gmo DATADIRNAME=share @@ -4121,7 +4134,7 @@ fi # Extract the first word of "msgfmt", so it can be a program name with args. set dummy msgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4125: checking for $ac_word" >&5 +echo "configure:4138: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4155,7 +4168,7 @@ fi # Extract the first word of "gmsgfmt", so it can be a program name with args. set dummy gmsgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4159: checking for $ac_word" >&5 +echo "configure:4172: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4191,7 +4204,7 @@ fi # Extract the first word of "xgettext", so it can be a program name with args. set dummy xgettext; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4195: checking for $ac_word" >&5 +echo "configure:4208: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4281,7 +4294,7 @@ fi LINGUAS= else echo $ac_n "checking for catalogs to be installed""... $ac_c" 1>&6 -echo "configure:4285: checking for catalogs to be installed" >&5 +echo "configure:4298: checking for catalogs to be installed" >&5 NEW_LINGUAS= for lang in ${LINGUAS=$ALL_LINGUAS}; do case "$ALL_LINGUAS" in @@ -4309,17 +4322,17 @@ echo "configure:4285: checking for catalogs to be installed" >&5 if test "$CATOBJEXT" = ".cat"; then ac_safe=`echo "linux/version.h" | sed 'y%./+-%__p_%'` echo $ac_n "checking for linux/version.h""... $ac_c" 1>&6 -echo "configure:4313: checking for linux/version.h" >&5 +echo "configure:4326: checking for linux/version.h" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 4318 "configure" +#line 4331 "configure" #include "confdefs.h" #include <linux/version.h> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:4323: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:4336: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -4397,7 +4410,7 @@ fi # SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" # ./install, which can be erroneously created by make from ./install.sh. echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6 -echo "configure:4401: checking for a BSD compatible install" >&5 +echo "configure:4414: checking for a BSD compatible install" >&5 if test -z "$INSTALL"; then if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -4480,7 +4493,7 @@ if test "x$cross_compiling" = "xno"; then EXEEXT_FOR_BUILD='$(EXEEXT)' else echo $ac_n "checking for build system executable suffix""... $ac_c" 1>&6 -echo "configure:4484: checking for build system executable suffix" >&5 +echo "configure:4497: checking for build system executable suffix" >&5 if eval "test \"`echo '$''{'bfd_cv_build_exeext'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4508,17 +4521,17 @@ for ac_hdr in stddef.h string.h strings.h stdlib.h time.h unistd.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:4512: checking for $ac_hdr" >&5 +echo "configure:4525: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 4517 "configure" +#line 4530 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:4522: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:4535: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -4548,17 +4561,17 @@ for ac_hdr in fcntl.h sys/file.h sys/time.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:4552: checking for $ac_hdr" >&5 +echo "configure:4565: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 4557 "configure" +#line 4570 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:4562: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:4575: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -4585,12 +4598,12 @@ fi done echo $ac_n "checking whether time.h and sys/time.h may both be included""... $ac_c" 1>&6 -echo "configure:4589: checking whether time.h and sys/time.h may both be included" >&5 +echo "configure:4602: checking whether time.h and sys/time.h may both be included" >&5 if eval "test \"`echo '$''{'ac_cv_header_time'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 4594 "configure" +#line 4607 "configure" #include "confdefs.h" #include <sys/types.h> #include <sys/time.h> @@ -4599,7 +4612,7 @@ int main() { struct tm *tp; ; return 0; } EOF -if { (eval echo configure:4603: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:4616: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* ac_cv_header_time=yes else @@ -4624,12 +4637,12 @@ for ac_hdr in dirent.h sys/ndir.h sys/dir.h ndir.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr that defines DIR""... $ac_c" 1>&6 -echo "configure:4628: checking for $ac_hdr that defines DIR" >&5 +echo "configure:4641: checking for $ac_hdr that defines DIR" >&5 if eval "test \"`echo '$''{'ac_cv_header_dirent_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 4633 "configure" +#line 4646 "configure" #include "confdefs.h" #include <sys/types.h> #include <$ac_hdr> @@ -4637,7 +4650,7 @@ int main() { DIR *dirp = 0; ; return 0; } EOF -if { (eval echo configure:4641: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:4654: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* eval "ac_cv_header_dirent_$ac_safe=yes" else @@ -4662,7 +4675,7 @@ done # Two versions of opendir et al. are in -ldir and -lx on SCO Xenix. if test $ac_header_dirent = dirent.h; then echo $ac_n "checking for opendir in -ldir""... $ac_c" 1>&6 -echo "configure:4666: checking for opendir in -ldir" >&5 +echo "configure:4679: checking for opendir in -ldir" >&5 ac_lib_var=`echo dir'_'opendir | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -4670,7 +4683,7 @@ else ac_save_LIBS="$LIBS" LIBS="-ldir $LIBS" cat > conftest.$ac_ext <<EOF -#line 4674 "configure" +#line 4687 "configure" #include "confdefs.h" /* Override any gcc2 internal prototype to avoid an error. */ /* We use char because int might match the return type of a gcc2 @@ -4681,7 +4694,7 @@ int main() { opendir() ; return 0; } EOF -if { (eval echo configure:4685: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:4698: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_lib_$ac_lib_var=yes" else @@ -4703,7 +4716,7 @@ fi else echo $ac_n "checking for opendir in -lx""... $ac_c" 1>&6 -echo "configure:4707: checking for opendir in -lx" >&5 +echo "configure:4720: checking for opendir in -lx" >&5 ac_lib_var=`echo x'_'opendir | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -4711,7 +4724,7 @@ else ac_save_LIBS="$LIBS" LIBS="-lx $LIBS" cat > conftest.$ac_ext <<EOF -#line 4715 "configure" +#line 4728 "configure" #include "confdefs.h" /* Override any gcc2 internal prototype to avoid an error. */ /* We use char because int might match the return type of a gcc2 @@ -4722,7 +4735,7 @@ int main() { opendir() ; return 0; } EOF -if { (eval echo configure:4726: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:4739: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_lib_$ac_lib_var=yes" else @@ -4747,12 +4760,12 @@ fi for ac_func in fcntl getpagesize setitimer sysconf fdopen getuid getgid do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:4751: checking for $ac_func" >&5 +echo "configure:4764: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 4756 "configure" +#line 4769 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -4775,7 +4788,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:4779: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:4792: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -4810,12 +4823,12 @@ EOF esac echo $ac_n "checking whether strstr must be declared""... $ac_c" 1>&6 -echo "configure:4814: checking whether strstr must be declared" >&5 +echo "configure:4827: checking whether strstr must be declared" >&5 if eval "test \"`echo '$''{'bfd_cv_decl_needed_strstr'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 4819 "configure" +#line 4832 "configure" #include "confdefs.h" #include <stdio.h> @@ -4836,7 +4849,7 @@ int main() { char *(*pfn) = (char *(*)) strstr ; return 0; } EOF -if { (eval echo configure:4840: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:4853: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_decl_needed_strstr=no else @@ -4857,12 +4870,12 @@ EOF fi echo $ac_n "checking whether malloc must be declared""... $ac_c" 1>&6 -echo "configure:4861: checking whether malloc must be declared" >&5 +echo "configure:4874: checking whether malloc must be declared" >&5 if eval "test \"`echo '$''{'bfd_cv_decl_needed_malloc'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 4866 "configure" +#line 4879 "configure" #include "confdefs.h" #include <stdio.h> @@ -4883,7 +4896,7 @@ int main() { char *(*pfn) = (char *(*)) malloc ; return 0; } EOF -if { (eval echo configure:4887: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:4900: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_decl_needed_malloc=no else @@ -4904,12 +4917,12 @@ EOF fi echo $ac_n "checking whether realloc must be declared""... $ac_c" 1>&6 -echo "configure:4908: checking whether realloc must be declared" >&5 +echo "configure:4921: checking whether realloc must be declared" >&5 if eval "test \"`echo '$''{'bfd_cv_decl_needed_realloc'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 4913 "configure" +#line 4926 "configure" #include "confdefs.h" #include <stdio.h> @@ -4930,7 +4943,7 @@ int main() { char *(*pfn) = (char *(*)) realloc ; return 0; } EOF -if { (eval echo configure:4934: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:4947: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_decl_needed_realloc=no else @@ -4951,12 +4964,12 @@ EOF fi echo $ac_n "checking whether free must be declared""... $ac_c" 1>&6 -echo "configure:4955: checking whether free must be declared" >&5 +echo "configure:4968: checking whether free must be declared" >&5 if eval "test \"`echo '$''{'bfd_cv_decl_needed_free'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 4960 "configure" +#line 4973 "configure" #include "confdefs.h" #include <stdio.h> @@ -4977,7 +4990,7 @@ int main() { char *(*pfn) = (char *(*)) free ; return 0; } EOF -if { (eval echo configure:4981: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:4994: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_decl_needed_free=no else @@ -4998,12 +5011,12 @@ EOF fi echo $ac_n "checking whether getenv must be declared""... $ac_c" 1>&6 -echo "configure:5002: checking whether getenv must be declared" >&5 +echo "configure:5015: checking whether getenv must be declared" >&5 if eval "test \"`echo '$''{'bfd_cv_decl_needed_getenv'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 5007 "configure" +#line 5020 "configure" #include "confdefs.h" #include <stdio.h> @@ -5024,7 +5037,7 @@ int main() { char *(*pfn) = (char *(*)) getenv ; return 0; } EOF -if { (eval echo configure:5028: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5041: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_decl_needed_getenv=no else @@ -5211,16 +5224,16 @@ if test "${target}" = "${host}"; then # Not all versions of AIX with -DAIX_CORE_DUMPX_CORE # have c_impl as a member of struct core_dumpx echo $ac_n "checking for c_impl in struct core_dumpx""... $ac_c" 1>&6 -echo "configure:5215: checking for c_impl in struct core_dumpx" >&5 +echo "configure:5228: checking for c_impl in struct core_dumpx" >&5 cat > conftest.$ac_ext <<EOF -#line 5217 "configure" +#line 5230 "configure" #include "confdefs.h" #include <core.h> int main() { struct core_dumpx c; c.c_impl = 0; ; return 0; } EOF -if { (eval echo configure:5224: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5237: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* cat >> confdefs.h <<\EOF #define HAVE_ST_C_IMPL 1 @@ -5287,17 +5300,17 @@ rm -f conftest* do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:5291: checking for $ac_hdr" >&5 +echo "configure:5304: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 5296 "configure" +#line 5309 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:5301: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:5314: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -5325,12 +5338,12 @@ done if test "$ac_cv_header_sys_procfs_h" = yes; then echo $ac_n "checking for prstatus_t in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5329: checking for prstatus_t in sys/procfs.h" >&5 +echo "configure:5342: checking for prstatus_t in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_prstatus_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 5334 "configure" +#line 5347 "configure" #include "confdefs.h" #define _SYSCALL32 @@ -5339,7 +5352,7 @@ int main() { prstatus_t avar ; return 0; } EOF -if { (eval echo configure:5343: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5356: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_prstatus_t=yes else @@ -5361,12 +5374,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_prstatus_t" 1>&6 echo $ac_n "checking for prstatus32_t in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5365: checking for prstatus32_t in sys/procfs.h" >&5 +echo "configure:5378: checking for prstatus32_t in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_prstatus32_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 5370 "configure" +#line 5383 "configure" #include "confdefs.h" #define _SYSCALL32 @@ -5375,7 +5388,7 @@ int main() { prstatus32_t avar ; return 0; } EOF -if { (eval echo configure:5379: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5392: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_prstatus32_t=yes else @@ -5397,12 +5410,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_prstatus32_t" 1>&6 echo $ac_n "checking for prstatus_t.pr_who in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5401: checking for prstatus_t.pr_who in sys/procfs.h" >&5 +echo "configure:5414: checking for prstatus_t.pr_who in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_member_prstatus_t_pr_who'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 5406 "configure" +#line 5419 "configure" #include "confdefs.h" #define _SYSCALL32 @@ -5411,7 +5424,7 @@ int main() { prstatus_t avar; void* aref = (void*) &avar.pr_who ; return 0; } EOF -if { (eval echo configure:5415: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5428: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_member_prstatus_t_pr_who=yes else @@ -5433,12 +5446,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_member_prstatus_t_pr_who" 1>&6 echo $ac_n "checking for prstatus32_t.pr_who in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5437: checking for prstatus32_t.pr_who in sys/procfs.h" >&5 +echo "configure:5450: checking for prstatus32_t.pr_who in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_member_prstatus32_t_pr_who'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 5442 "configure" +#line 5455 "configure" #include "confdefs.h" #define _SYSCALL32 @@ -5447,7 +5460,7 @@ int main() { prstatus32_t avar; void* aref = (void*) &avar.pr_who ; return 0; } EOF -if { (eval echo configure:5451: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5464: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_member_prstatus32_t_pr_who=yes else @@ -5469,12 +5482,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_member_prstatus32_t_pr_who" 1>&6 echo $ac_n "checking for pstatus_t in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5473: checking for pstatus_t in sys/procfs.h" >&5 +echo "configure:5486: checking for pstatus_t in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_pstatus_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 5478 "configure" +#line 5491 "configure" #include "confdefs.h" #define _SYSCALL32 @@ -5483,7 +5496,7 @@ int main() { pstatus_t avar ; return 0; } EOF -if { (eval echo configure:5487: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5500: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_pstatus_t=yes else @@ -5505,12 +5518,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_pstatus_t" 1>&6 echo $ac_n "checking for pxstatus_t in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5509: checking for pxstatus_t in sys/procfs.h" >&5 +echo "configure:5522: checking for pxstatus_t in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_pxstatus_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 5514 "configure" +#line 5527 "configure" #include "confdefs.h" #define _SYSCALL32 @@ -5519,7 +5532,7 @@ int main() { pxstatus_t avar ; return 0; } EOF -if { (eval echo configure:5523: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5536: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_pxstatus_t=yes else @@ -5541,12 +5554,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_pxstatus_t" 1>&6 echo $ac_n "checking for pstatus32_t in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5545: checking for pstatus32_t in sys/procfs.h" >&5 +echo "configure:5558: checking for pstatus32_t in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_pstatus32_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 5550 "configure" +#line 5563 "configure" #include "confdefs.h" #define _SYSCALL32 @@ -5555,7 +5568,7 @@ int main() { pstatus32_t avar ; return 0; } EOF -if { (eval echo configure:5559: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5572: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_pstatus32_t=yes else @@ -5577,12 +5590,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_pstatus32_t" 1>&6 echo $ac_n "checking for prpsinfo_t in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5581: checking for prpsinfo_t in sys/procfs.h" >&5 +echo "configure:5594: checking for prpsinfo_t in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_prpsinfo_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 5586 "configure" +#line 5599 "configure" #include "confdefs.h" #define _SYSCALL32 @@ -5591,7 +5604,7 @@ int main() { prpsinfo_t avar ; return 0; } EOF -if { (eval echo configure:5595: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5608: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_prpsinfo_t=yes else @@ -5613,12 +5626,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_prpsinfo_t" 1>&6 echo $ac_n "checking for prpsinfo32_t in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5617: checking for prpsinfo32_t in sys/procfs.h" >&5 +echo "configure:5630: checking for prpsinfo32_t in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_prpsinfo32_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 5622 "configure" +#line 5635 "configure" #include "confdefs.h" #define _SYSCALL32 @@ -5627,7 +5640,7 @@ int main() { prpsinfo32_t avar ; return 0; } EOF -if { (eval echo configure:5631: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5644: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_prpsinfo32_t=yes else @@ -5649,12 +5662,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_prpsinfo32_t" 1>&6 echo $ac_n "checking for psinfo_t in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5653: checking for psinfo_t in sys/procfs.h" >&5 +echo "configure:5666: checking for psinfo_t in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_psinfo_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 5658 "configure" +#line 5671 "configure" #include "confdefs.h" #define _SYSCALL32 @@ -5663,7 +5676,7 @@ int main() { psinfo_t avar ; return 0; } EOF -if { (eval echo configure:5667: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5680: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_psinfo_t=yes else @@ -5685,12 +5698,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_psinfo_t" 1>&6 echo $ac_n "checking for psinfo32_t in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5689: checking for psinfo32_t in sys/procfs.h" >&5 +echo "configure:5702: checking for psinfo32_t in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_psinfo32_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 5694 "configure" +#line 5707 "configure" #include "confdefs.h" #define _SYSCALL32 @@ -5699,7 +5712,7 @@ int main() { psinfo32_t avar ; return 0; } EOF -if { (eval echo configure:5703: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5716: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_psinfo32_t=yes else @@ -5721,12 +5734,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_psinfo32_t" 1>&6 echo $ac_n "checking for lwpstatus_t in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5725: checking for lwpstatus_t in sys/procfs.h" >&5 +echo "configure:5738: checking for lwpstatus_t in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_lwpstatus_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 5730 "configure" +#line 5743 "configure" #include "confdefs.h" #define _SYSCALL32 @@ -5735,7 +5748,7 @@ int main() { lwpstatus_t avar ; return 0; } EOF -if { (eval echo configure:5739: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5752: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_lwpstatus_t=yes else @@ -5757,12 +5770,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_lwpstatus_t" 1>&6 echo $ac_n "checking for lwpxstatus_t in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5761: checking for lwpxstatus_t in sys/procfs.h" >&5 +echo "configure:5774: checking for lwpxstatus_t in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_lwpxstatus_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 5766 "configure" +#line 5779 "configure" #include "confdefs.h" #define _SYSCALL32 @@ -5771,7 +5784,7 @@ int main() { lwpxstatus_t avar ; return 0; } EOF -if { (eval echo configure:5775: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5788: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_lwpxstatus_t=yes else @@ -5793,12 +5806,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_lwpxstatus_t" 1>&6 echo $ac_n "checking for lwpstatus_t.pr_context in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5797: checking for lwpstatus_t.pr_context in sys/procfs.h" >&5 +echo "configure:5810: checking for lwpstatus_t.pr_context in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_member_lwpstatus_t_pr_context'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 5802 "configure" +#line 5815 "configure" #include "confdefs.h" #define _SYSCALL32 @@ -5807,7 +5820,7 @@ int main() { lwpstatus_t avar; void* aref = (void*) &avar.pr_context ; return 0; } EOF -if { (eval echo configure:5811: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5824: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_member_lwpstatus_t_pr_context=yes else @@ -5829,12 +5842,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_member_lwpstatus_t_pr_context" 1>&6 echo $ac_n "checking for lwpstatus_t.pr_reg in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5833: checking for lwpstatus_t.pr_reg in sys/procfs.h" >&5 +echo "configure:5846: checking for lwpstatus_t.pr_reg in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_member_lwpstatus_t_pr_reg'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 5838 "configure" +#line 5851 "configure" #include "confdefs.h" #define _SYSCALL32 @@ -5843,7 +5856,7 @@ int main() { lwpstatus_t avar; void* aref = (void*) &avar.pr_reg ; return 0; } EOF -if { (eval echo configure:5847: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5860: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_member_lwpstatus_t_pr_reg=yes else @@ -5865,12 +5878,12 @@ EOF echo "$ac_t""$bfd_cv_have_sys_procfs_type_member_lwpstatus_t_pr_reg" 1>&6 echo $ac_n "checking for win32_pstatus_t in sys/procfs.h""... $ac_c" 1>&6 -echo "configure:5869: checking for win32_pstatus_t in sys/procfs.h" >&5 +echo "configure:5882: checking for win32_pstatus_t in sys/procfs.h" >&5 if eval "test \"`echo '$''{'bfd_cv_have_sys_procfs_type_win32_pstatus_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 5874 "configure" +#line 5887 "configure" #include "confdefs.h" #define _SYSCALL32 @@ -5879,7 +5892,7 @@ int main() { win32_pstatus_t avar ; return 0; } EOF -if { (eval echo configure:5883: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:5896: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* bfd_cv_have_sys_procfs_type_win32_pstatus_t=yes else @@ -6022,6 +6035,7 @@ do # use one entry per line, even though this leads to long lines. a29kcoff_big_vec) tb="$tb coff-a29k.lo cofflink.lo" ;; a_out_adobe_vec) tb="$tb aout-adobe.lo aout32.lo" ;; + aix5coff64_vec) tb="$tb coff64-rs6000.lo xcofflink.lo aix5ppc-core.lo"; target_size=64 ;; aout0_big_vec) tb="$tb aout0.lo aout32.lo" ;; aout_arm_big_vec) tb="$tb aout-arm.lo aout32.lo" ;; aout_arm_little_vec) tb="$tb aout-arm.lo aout32.lo" ;; @@ -6054,6 +6068,7 @@ do bfd_elf32_d30v_vec) tb="$tb elf32-d30v.lo elf32.lo $elf" ;; bfd_elf32_dlx_big_vec) tb="$tb elf32-dlx.lo elf32.lo $elf" ;; bfd_elf32_fr30_vec) tb="$tb elf32-fr30.lo elf32.lo $elf" ;; + bfd_elf32_frv_vec) tb="$tb elf32-frv.lo elf32.lo $elf" ;; bfd_elf32_h8300_vec) tb="$tb elf32-h8300.lo elf32.lo $elf" ;; bfd_elf32_hppa_linux_vec) tb="$tb elf32-hppa.lo elf32.lo $elf" ;; bfd_elf32_hppa_vec) tb="$tb elf32-hppa.lo elf32.lo $elf" ;; @@ -6086,23 +6101,19 @@ do bfd_elf32_powerpc_vec) tb="$tb elf32-ppc.lo elf32.lo $elf" ;; bfd_elf32_powerpcle_vec) tb="$tb elf32-ppc.lo elf32.lo $elf" ;; bfd_elf32_s390_vec) tb="$tb elf32-s390.lo elf32.lo $elf" ;; - bfd_elf32_sh_vec) tb="$tb elf32-sh.lo elf32.lo $elf coff-sh.lo" ;; - bfd_elf32_shblin_vec) tb="$tb elf32-sh-lin.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; - bfd_elf32_shl_vec) tb="$tb elf32-sh.lo elf32.lo $elf coff-sh.lo" ;; - bfd_elf32_shlin_vec) tb="$tb elf32-sh-lin.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; - bfd_elf32_shlnbsd_vec) tb="$tb elf32-sh-nbsd.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; - bfd_elf32_shnbsd_vec) tb="$tb elf32-sh-nbsd.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; # FIXME: We include cofflink.lo not because it's needed for # bfd_elf32_sh64[l]_vec, but because we include bfd_elf32_sh[l]_vec # which needs it but does not list it. Should be fixed in right place. bfd_elf32_sh64_vec) tb="$tb elf32-sh64.lo elf32-sh64-com.lo elf32.lo $elf cofflink.lo" target_size=64 ;; bfd_elf32_sh64l_vec) tb="$tb elf32-sh64.lo elf32-sh64-com.lo elf32.lo $elf cofflink.lo" target_size=64 ;; - bfd_elf64_sh64_vec) tb="$tb elf64-sh64.lo elf64.lo $elf" target_size=64 ;; - bfd_elf64_sh64l_vec) tb="$tb elf64-sh64.lo elf64.lo $elf" target_size=64 ;; - bfd_elf32_sh64nbsd_vec) tb="$tb elf32-sh64-nbsd.lo elf32-sh64-com.lo elf32.lo $elf cofflink.lo" ;; bfd_elf32_sh64lnbsd_vec) tb="$tb elf32-sh64-nbsd.lo elf32-sh64-com.lo elf32.lo $elf cofflink.lo" ;; - bfd_elf64_sh64nbsd_vec) tb="$tb elf64-sh64-nbsd.lo elf64.lo $elf" target_size=64 ;; - bfd_elf64_sh64lnbsd_vec) tb="$tb elf64-sh64-nbsd.lo elf64.lo $elf" target_size=64 ;; + bfd_elf32_sh64nbsd_vec) tb="$tb elf32-sh64-nbsd.lo elf32-sh64-com.lo elf32.lo $elf cofflink.lo" ;; + bfd_elf32_sh_vec) tb="$tb elf32-sh.lo elf32.lo $elf coff-sh.lo" ;; + bfd_elf32_shblin_vec) tb="$tb elf32-sh-lin.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; + bfd_elf32_shl_vec) tb="$tb elf32-sh.lo elf32.lo $elf coff-sh.lo" ;; + bfd_elf32_shlin_vec) tb="$tb elf32-sh-lin.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; + bfd_elf32_shlnbsd_vec) tb="$tb elf32-sh-nbsd.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; + bfd_elf32_shnbsd_vec) tb="$tb elf32-sh-nbsd.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; bfd_elf32_sparc_vec) tb="$tb elf32-sparc.lo elf32.lo $elf" ;; bfd_elf32_tradbigmips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo" ;; bfd_elf32_tradlittlemips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo" ;; @@ -6126,6 +6137,10 @@ do bfd_elf64_powerpc_vec) tb="$tb elf64-ppc.lo elf64-gen.lo elf64.lo $elf"; target_size=64 ;; bfd_elf64_powerpcle_vec) tb="$tb elf64-ppc.lo elf64-gen.lo elf64.lo $elf" target_size=64 ;; bfd_elf64_s390_vec) tb="$tb elf64-s390.lo elf64.lo $elf"; target_size=64 ;; + bfd_elf64_sh64_vec) tb="$tb elf64-sh64.lo elf64.lo $elf" target_size=64 ;; + bfd_elf64_sh64l_vec) tb="$tb elf64-sh64.lo elf64.lo $elf" target_size=64 ;; + bfd_elf64_sh64lnbsd_vec) tb="$tb elf64-sh64-nbsd.lo elf64.lo $elf" target_size=64 ;; + bfd_elf64_sh64nbsd_vec) tb="$tb elf64-sh64-nbsd.lo elf64.lo $elf" target_size=64 ;; bfd_elf64_sparc_vec) tb="$tb elf64-sparc.lo elf64.lo $elf"; target_size=64 ;; bfd_elf64_tradbigmips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;; bfd_elf64_tradlittlemips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;; @@ -6135,8 +6150,6 @@ do bfd_powerpc_pei_vec) tb="$tb pei-ppc.lo peigen.lo cofflink.lo" ;; bfd_powerpcle_pe_vec) tb="$tb pe-ppc.lo peigen.lo cofflink.lo" ;; bfd_powerpcle_pei_vec) tb="$tb pei-ppc.lo peigen.lo cofflink.lo" ;; - cisco_core_big_vec) tb="$tb cisco-core.lo" ;; - cisco_core_little_vec) tb="$tb cisco-core.lo" ;; cris_aout_vec) tb="$tb aout-cris.lo" ;; demo_64_vec) tb="$tb demo64.lo aout64.lo"; target_size=64 ;; ecoff_big_vec) tb="$tb coff-mips.lo ecoff.lo ecofflink.lo" ;; @@ -6178,6 +6191,7 @@ do m68knetbsd_vec) tb="$tb m68knetbsd.lo aout32.lo" ;; m68ksysvcoff_vec) tb="$tb coff-svm68k.lo cofflink.lo" ;; m88kbcs_vec) tb="$tb coff-m88k.lo" ;; + m88kmach3_vec) tb="$tb m88kmach3.lo aout32.lo" ;; mcore_pe_big_vec) tb="$tb pe-mcore.lo peigen.lo cofflink.lo" ;; mcore_pe_little_vec) tb="$tb pe-mcore.lo peigen.lo cofflink.lo" ;; mcore_pei_big_vec) tb="$tb pei-mcore.lo peigen.lo cofflink.lo" ;; @@ -6197,7 +6211,6 @@ do ppcboot_vec) tb="$tb ppcboot.lo" ;; riscix_vec) tb="$tb aout32.lo riscix.lo" ;; rs6000coff64_vec) tb="$tb coff64-rs6000.lo xcofflink.lo aix5ppc-core.lo"; target_size=64 ;; - aix5coff64_vec) tb="$tb coff64-rs6000.lo xcofflink.lo aix5ppc-core.lo"; target_size=64 ;; rs6000coff_vec) tb="$tb coff-rs6000.lo xcofflink.lo" ;; shcoff_small_vec) tb="$tb coff-sh.lo cofflink.lo" ;; shcoff_vec) tb="$tb coff-sh.lo cofflink.lo" ;; @@ -6212,10 +6225,7 @@ do sparclynx_aout_vec) tb="$tb sparclynx.lo lynx-core.lo aout32.lo" ;; sparclynx_coff_vec) tb="$tb cf-sparclynx.lo lynx-core.lo" ;; sparcnetbsd_vec) tb="$tb sparcnetbsd.lo aout32.lo" ;; - srec_vec) tb="$tb srec.lo" ;; sunos_big_vec) tb="$tb sunos.lo aout32.lo" ;; - symbolsrec_vec) tb="$tb srec.lo" ;; - tekhex_vec) tb="$tb tekhex.lo" ;; tic30_aout_vec) tb="$tb aout-tic30.lo" ;; tic30_coff_vec) tb="$tb coff-tic30.lo" ;; tic54x_coff0_beh_vec) tb="$tb coff-tic54x.lo" ;; @@ -6234,6 +6244,13 @@ do we32kcoff_vec) tb="$tb coff-we32k.lo" ;; z8kcoff_vec) tb="$tb coff-z8k.lo reloc16.lo" ;; + # These appear out of order in targets.c + srec_vec) tb="$tb srec.lo" ;; + symbolsrec_vec) tb="$tb srec.lo" ;; + tekhex_vec) tb="$tb tekhex.lo" ;; + cisco_core_big_vec) tb="$tb cisco-core.lo" ;; + cisco_core_little_vec) tb="$tb cisco-core.lo" ;; + "") ;; *) { echo "configure: error: *** unknown target vector $vec" 1>&2; exit 1; } ;; esac @@ -6302,10 +6319,10 @@ case ${host64}-${target64}-${want64} in if test -n "$GCC" ; then bad_64bit_gcc=no; echo $ac_n "checking for gcc version with buggy 64-bit support""... $ac_c" 1>&6 -echo "configure:6306: checking for gcc version with buggy 64-bit support" >&5 +echo "configure:6322: checking for gcc version with buggy 64-bit support" >&5 # Add more tests for gcc versions with non-working 64-bit support here. cat > conftest.$ac_ext <<EOF -#line 6309 "configure" +#line 6325 "configure" #include "confdefs.h" :__GNUC__:__GNUC_MINOR__:__i386__: EOF @@ -6346,21 +6363,21 @@ test -n "${selarchs}" && tdefaults="${tdefaults} -DSELECT_ARCHITECTURES='${selar test -n "${havevecs}" && tdefaults="${tdefaults} ${havevecs}" -for ac_hdr in unistd.h +for ac_hdr in stdlib.h unistd.h sys/stat.h sys/types.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:6354: checking for $ac_hdr" >&5 +echo "configure:6370: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 6359 "configure" +#line 6375 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:6364: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:6380: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -6389,12 +6406,12 @@ done for ac_func in getpagesize do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:6393: checking for $ac_func" >&5 +echo "configure:6409: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 6398 "configure" +#line 6414 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -6417,7 +6434,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:6421: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:6437: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -6442,7 +6459,7 @@ fi done echo $ac_n "checking for working mmap""... $ac_c" 1>&6 -echo "configure:6446: checking for working mmap" >&5 +echo "configure:6462: checking for working mmap" >&5 if eval "test \"`echo '$''{'ac_cv_func_mmap_fixed_mapped'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -6450,7 +6467,7 @@ else ac_cv_func_mmap_fixed_mapped=no else cat > conftest.$ac_ext <<EOF -#line 6454 "configure" +#line 6470 "configure" #include "confdefs.h" /* Thanks to Mike Haertel and Jim Avera for this test. @@ -6478,11 +6495,24 @@ else #include <fcntl.h> #include <sys/mman.h> +#if HAVE_SYS_TYPES_H +# include <sys/types.h> +#endif + +#if HAVE_STDLIB_H +# include <stdlib.h> +#endif + +#if HAVE_SYS_STAT_H +# include <sys/stat.h> +#endif + +#if HAVE_UNISTD_H +# include <unistd.h> +#endif + /* This mess was copied from the GNU getpagesize.h. */ #ifndef HAVE_GETPAGESIZE -# ifdef HAVE_UNISTD_H -# include <unistd.h> -# endif /* Assume that all systems that can run configure have sys/param.h. */ # ifndef HAVE_SYS_PARAM_H @@ -6590,7 +6620,7 @@ main() } EOF -if { (eval echo configure:6594: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +if { (eval echo configure:6623: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null then ac_cv_func_mmap_fixed_mapped=yes else @@ -6615,12 +6645,12 @@ fi for ac_func in madvise mprotect do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:6619: checking for $ac_func" >&5 +echo "configure:6648: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 6624 "configure" +#line 6653 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -6643,7 +6673,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:6647: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:6676: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else diff --git a/bfd/configure.in b/bfd/configure.in index 040a068a902..b3f3557db36 100644 --- a/bfd/configure.in +++ b/bfd/configure.in @@ -536,6 +536,7 @@ do # use one entry per line, even though this leads to long lines. a29kcoff_big_vec) tb="$tb coff-a29k.lo cofflink.lo" ;; a_out_adobe_vec) tb="$tb aout-adobe.lo aout32.lo" ;; + aix5coff64_vec) tb="$tb coff64-rs6000.lo xcofflink.lo aix5ppc-core.lo"; target_size=64 ;; aout0_big_vec) tb="$tb aout0.lo aout32.lo" ;; aout_arm_big_vec) tb="$tb aout-arm.lo aout32.lo" ;; aout_arm_little_vec) tb="$tb aout-arm.lo aout32.lo" ;; @@ -568,6 +569,7 @@ do bfd_elf32_d30v_vec) tb="$tb elf32-d30v.lo elf32.lo $elf" ;; bfd_elf32_dlx_big_vec) tb="$tb elf32-dlx.lo elf32.lo $elf" ;; bfd_elf32_fr30_vec) tb="$tb elf32-fr30.lo elf32.lo $elf" ;; + bfd_elf32_frv_vec) tb="$tb elf32-frv.lo elf32.lo $elf" ;; bfd_elf32_h8300_vec) tb="$tb elf32-h8300.lo elf32.lo $elf" ;; bfd_elf32_hppa_linux_vec) tb="$tb elf32-hppa.lo elf32.lo $elf" ;; bfd_elf32_hppa_vec) tb="$tb elf32-hppa.lo elf32.lo $elf" ;; @@ -600,23 +602,19 @@ do bfd_elf32_powerpc_vec) tb="$tb elf32-ppc.lo elf32.lo $elf" ;; bfd_elf32_powerpcle_vec) tb="$tb elf32-ppc.lo elf32.lo $elf" ;; bfd_elf32_s390_vec) tb="$tb elf32-s390.lo elf32.lo $elf" ;; - bfd_elf32_sh_vec) tb="$tb elf32-sh.lo elf32.lo $elf coff-sh.lo" ;; - bfd_elf32_shblin_vec) tb="$tb elf32-sh-lin.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; - bfd_elf32_shl_vec) tb="$tb elf32-sh.lo elf32.lo $elf coff-sh.lo" ;; - bfd_elf32_shlin_vec) tb="$tb elf32-sh-lin.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; - bfd_elf32_shlnbsd_vec) tb="$tb elf32-sh-nbsd.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; - bfd_elf32_shnbsd_vec) tb="$tb elf32-sh-nbsd.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; # FIXME: We include cofflink.lo not because it's needed for # bfd_elf32_sh64[l]_vec, but because we include bfd_elf32_sh[l]_vec # which needs it but does not list it. Should be fixed in right place. bfd_elf32_sh64_vec) tb="$tb elf32-sh64.lo elf32-sh64-com.lo elf32.lo $elf cofflink.lo" target_size=64 ;; bfd_elf32_sh64l_vec) tb="$tb elf32-sh64.lo elf32-sh64-com.lo elf32.lo $elf cofflink.lo" target_size=64 ;; - bfd_elf64_sh64_vec) tb="$tb elf64-sh64.lo elf64.lo $elf" target_size=64 ;; - bfd_elf64_sh64l_vec) tb="$tb elf64-sh64.lo elf64.lo $elf" target_size=64 ;; - bfd_elf32_sh64nbsd_vec) tb="$tb elf32-sh64-nbsd.lo elf32-sh64-com.lo elf32.lo $elf cofflink.lo" ;; bfd_elf32_sh64lnbsd_vec) tb="$tb elf32-sh64-nbsd.lo elf32-sh64-com.lo elf32.lo $elf cofflink.lo" ;; - bfd_elf64_sh64nbsd_vec) tb="$tb elf64-sh64-nbsd.lo elf64.lo $elf" target_size=64 ;; - bfd_elf64_sh64lnbsd_vec) tb="$tb elf64-sh64-nbsd.lo elf64.lo $elf" target_size=64 ;; + bfd_elf32_sh64nbsd_vec) tb="$tb elf32-sh64-nbsd.lo elf32-sh64-com.lo elf32.lo $elf cofflink.lo" ;; + bfd_elf32_sh_vec) tb="$tb elf32-sh.lo elf32.lo $elf coff-sh.lo" ;; + bfd_elf32_shblin_vec) tb="$tb elf32-sh-lin.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; + bfd_elf32_shl_vec) tb="$tb elf32-sh.lo elf32.lo $elf coff-sh.lo" ;; + bfd_elf32_shlin_vec) tb="$tb elf32-sh-lin.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; + bfd_elf32_shlnbsd_vec) tb="$tb elf32-sh-nbsd.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; + bfd_elf32_shnbsd_vec) tb="$tb elf32-sh-nbsd.lo elf32.lo $elf coff-sh.lo cofflink.lo" ;; bfd_elf32_sparc_vec) tb="$tb elf32-sparc.lo elf32.lo $elf" ;; bfd_elf32_tradbigmips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo" ;; bfd_elf32_tradlittlemips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo" ;; @@ -640,6 +638,10 @@ do bfd_elf64_powerpc_vec) tb="$tb elf64-ppc.lo elf64-gen.lo elf64.lo $elf"; target_size=64 ;; bfd_elf64_powerpcle_vec) tb="$tb elf64-ppc.lo elf64-gen.lo elf64.lo $elf" target_size=64 ;; bfd_elf64_s390_vec) tb="$tb elf64-s390.lo elf64.lo $elf"; target_size=64 ;; + bfd_elf64_sh64_vec) tb="$tb elf64-sh64.lo elf64.lo $elf" target_size=64 ;; + bfd_elf64_sh64l_vec) tb="$tb elf64-sh64.lo elf64.lo $elf" target_size=64 ;; + bfd_elf64_sh64lnbsd_vec) tb="$tb elf64-sh64-nbsd.lo elf64.lo $elf" target_size=64 ;; + bfd_elf64_sh64nbsd_vec) tb="$tb elf64-sh64-nbsd.lo elf64.lo $elf" target_size=64 ;; bfd_elf64_sparc_vec) tb="$tb elf64-sparc.lo elf64.lo $elf"; target_size=64 ;; bfd_elf64_tradbigmips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;; bfd_elf64_tradlittlemips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;; @@ -649,8 +651,6 @@ do bfd_powerpc_pei_vec) tb="$tb pei-ppc.lo peigen.lo cofflink.lo" ;; bfd_powerpcle_pe_vec) tb="$tb pe-ppc.lo peigen.lo cofflink.lo" ;; bfd_powerpcle_pei_vec) tb="$tb pei-ppc.lo peigen.lo cofflink.lo" ;; - cisco_core_big_vec) tb="$tb cisco-core.lo" ;; - cisco_core_little_vec) tb="$tb cisco-core.lo" ;; cris_aout_vec) tb="$tb aout-cris.lo" ;; demo_64_vec) tb="$tb demo64.lo aout64.lo"; target_size=64 ;; ecoff_big_vec) tb="$tb coff-mips.lo ecoff.lo ecofflink.lo" ;; @@ -692,6 +692,7 @@ do m68knetbsd_vec) tb="$tb m68knetbsd.lo aout32.lo" ;; m68ksysvcoff_vec) tb="$tb coff-svm68k.lo cofflink.lo" ;; m88kbcs_vec) tb="$tb coff-m88k.lo" ;; + m88kmach3_vec) tb="$tb m88kmach3.lo aout32.lo" ;; mcore_pe_big_vec) tb="$tb pe-mcore.lo peigen.lo cofflink.lo" ;; mcore_pe_little_vec) tb="$tb pe-mcore.lo peigen.lo cofflink.lo" ;; mcore_pei_big_vec) tb="$tb pei-mcore.lo peigen.lo cofflink.lo" ;; @@ -711,7 +712,6 @@ do ppcboot_vec) tb="$tb ppcboot.lo" ;; riscix_vec) tb="$tb aout32.lo riscix.lo" ;; rs6000coff64_vec) tb="$tb coff64-rs6000.lo xcofflink.lo aix5ppc-core.lo"; target_size=64 ;; - aix5coff64_vec) tb="$tb coff64-rs6000.lo xcofflink.lo aix5ppc-core.lo"; target_size=64 ;; rs6000coff_vec) tb="$tb coff-rs6000.lo xcofflink.lo" ;; shcoff_small_vec) tb="$tb coff-sh.lo cofflink.lo" ;; shcoff_vec) tb="$tb coff-sh.lo cofflink.lo" ;; @@ -726,10 +726,7 @@ do sparclynx_aout_vec) tb="$tb sparclynx.lo lynx-core.lo aout32.lo" ;; sparclynx_coff_vec) tb="$tb cf-sparclynx.lo lynx-core.lo" ;; sparcnetbsd_vec) tb="$tb sparcnetbsd.lo aout32.lo" ;; - srec_vec) tb="$tb srec.lo" ;; sunos_big_vec) tb="$tb sunos.lo aout32.lo" ;; - symbolsrec_vec) tb="$tb srec.lo" ;; - tekhex_vec) tb="$tb tekhex.lo" ;; tic30_aout_vec) tb="$tb aout-tic30.lo" ;; tic30_coff_vec) tb="$tb coff-tic30.lo" ;; tic54x_coff0_beh_vec) tb="$tb coff-tic54x.lo" ;; @@ -748,6 +745,13 @@ do we32kcoff_vec) tb="$tb coff-we32k.lo" ;; z8kcoff_vec) tb="$tb coff-z8k.lo reloc16.lo" ;; + # These appear out of order in targets.c + srec_vec) tb="$tb srec.lo" ;; + symbolsrec_vec) tb="$tb srec.lo" ;; + tekhex_vec) tb="$tb tekhex.lo" ;; + cisco_core_big_vec) tb="$tb cisco-core.lo" ;; + cisco_core_little_vec) tb="$tb cisco-core.lo" ;; + "") ;; *) AC_MSG_ERROR(*** unknown target vector $vec) ;; esac diff --git a/bfd/cpu-frv.c b/bfd/cpu-frv.c new file mode 100644 index 00000000000..cd9ff1ef5c6 --- /dev/null +++ b/bfd/cpu-frv.c @@ -0,0 +1,64 @@ +/* BFD support for the FRV processor. + Copyright (C) 2002 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "bfd.h" +#include "sysdep.h" +#include "libbfd.h" + +enum { + I_frv_generic, + I_frv_simple, + I_frv_500, + I_frv_300, +}; + +#define FRV_ARCH(MACHINE, NAME, DEFAULT, NEXT) \ +{ \ + 32, /* 32 bits in a word */ \ + 32, /* 32 bits in an address */ \ + 8, /* 8 bits in a byte */ \ + bfd_arch_frv, /* architecture */ \ + MACHINE, /* which machine */ \ + "frv", /* architecture name */ \ + NAME, /* machine name */ \ + 4, /* default alignment */ \ + DEFAULT, /* is this the default? */ \ + bfd_default_compatible, /* architecture comparison fn */ \ + bfd_default_scan, /* string to architecture convert fn */ \ + NEXT /* next in list */ \ +} + +static const bfd_arch_info_type arch_info_300 + = FRV_ARCH (bfd_mach_fr300, "fr300", false, (bfd_arch_info_type *)0); + +static const bfd_arch_info_type arch_info_400 + = FRV_ARCH (bfd_mach_fr400, "fr400", false, &arch_info_300); + +static const bfd_arch_info_type arch_info_500 + = FRV_ARCH (bfd_mach_fr500, "fr500", false, &arch_info_400); + +static const bfd_arch_info_type arch_info_simple + = FRV_ARCH (bfd_mach_frvsimple, "simple", false, &arch_info_500); + +static const bfd_arch_info_type arch_info_tomcat + = FRV_ARCH (bfd_mach_frvtomcat, "tomcat", false, &arch_info_simple); + +const bfd_arch_info_type bfd_frv_arch + = FRV_ARCH (bfd_mach_frv, "frv", true, &arch_info_tomcat); + diff --git a/bfd/elf-hppa.h b/bfd/elf-hppa.h index 99a66f4e180..d5a3d15d4e7 100644 --- a/bfd/elf-hppa.h +++ b/bfd/elf-hppa.h @@ -1296,22 +1296,22 @@ elf_hppa_final_link (abfd, info) address of the .plt + gp_offset. If no .plt is found, then look for .dlt, .opd and .data (in - that order) and set __gp to the base address of whichever section - is found first. */ + that order) and set __gp to the base address of whichever + section is found first. */ sec = hppa_info->plt_sec; - if (sec) + if (sec && ! (sec->flags & SEC_EXCLUDE)) gp_val = (sec->output_offset + sec->output_section->vma + hppa_info->gp_offset); else { sec = hppa_info->dlt_sec; - if (!sec) + if (!sec || (sec->flags & SEC_EXCLUDE)) sec = hppa_info->opd_sec; - if (!sec) + if (!sec || (sec->flags & SEC_EXCLUDE)) sec = bfd_get_section_by_name (abfd, ".data"); - if (!sec) + if (!sec || (sec->flags & SEC_EXCLUDE)) return false; gp_val = sec->output_offset + sec->output_section->vma; @@ -2074,11 +2074,14 @@ elf_hppa_final_link_relocate (rel, input_bfd, output_bfd, hppa_info->opd_sec->contents + dyn_h->opd_offset + 24); } - /* We want the value of the OPD offset for this symbol, not - the symbol's actual address. */ - value = (dyn_h->opd_offset - + hppa_info->opd_sec->output_offset - + hppa_info->opd_sec->output_section->vma); + if (dyn_h->want_opd) + /* We want the value of the OPD offset for this symbol. */ + value = (dyn_h->opd_offset + + hppa_info->opd_sec->output_offset + + hppa_info->opd_sec->output_section->vma); + else + /* We want the address of the symbol. */ + value += addend; bfd_put_64 (input_bfd, value, hit_data); return bfd_reloc_ok; diff --git a/bfd/elf32-d10v.c b/bfd/elf32-d10v.c index cd0624477eb..6ac5e2dd658 100644 --- a/bfd/elf32-d10v.c +++ b/bfd/elf32-d10v.c @@ -1,5 +1,5 @@ /* D10V-specific support for 32-bit ELF - Copyright 1996, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright 1996, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. Contributed by Martin Hunt (hunt@cygnus.com). This file is part of BFD, the Binary File Descriptor library. @@ -67,10 +67,10 @@ static reloc_howto_type elf_d10v_howto_table[] = HOWTO (R_D10V_10_PCREL_R, /* type */ 2, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ - 8, /* bitsize */ + 7, /* bitsize */ true, /* pc_relative */ 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ + complain_overflow_bitfield, /* complain_on_overflow */ bfd_elf_generic_reloc, /* special_function */ "R_D10V_10_PCREL_R", /* name */ false, /* partial_inplace */ @@ -83,10 +83,10 @@ static reloc_howto_type elf_d10v_howto_table[] = HOWTO (R_D10V_10_PCREL_L, /* type */ 2, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ - 8, /* bitsize */ + 7, /* bitsize */ true, /* pc_relative */ 15, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ + complain_overflow_bitfield, /* complain_on_overflow */ bfd_elf_generic_reloc, /* special_function */ "R_D10V_10_PCREL_L", /* name */ false, /* partial_inplace */ @@ -128,10 +128,10 @@ static reloc_howto_type elf_d10v_howto_table[] = HOWTO (R_D10V_18_PCREL, /* type */ 2, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ + 15, /* bitsize */ true, /* pc_relative */ 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ + complain_overflow_bitfield, /* complain_on_overflow */ bfd_elf_generic_reloc, /* special_function */ "R_D10V_18_PCREL", /* name */ false, /* partial_inplace */ diff --git a/bfd/elf32-frv.c b/bfd/elf32-frv.c new file mode 100644 index 00000000000..cc26b967c52 --- /dev/null +++ b/bfd/elf32-frv.c @@ -0,0 +1,1405 @@ +/* FRV-specific support for 32-bit ELF. + Copyright (C) 2002 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "bfd.h" +#include "sysdep.h" +#include "libbfd.h" +#include "elf-bfd.h" +#include "elf/frv.h" + +/* Forward declarations. */ +static bfd_reloc_status_type elf32_frv_relocate_lo16 + PARAMS ((bfd *, Elf_Internal_Rela *, bfd_byte *, bfd_vma)); +static bfd_reloc_status_type elf32_frv_relocate_hi16 + PARAMS ((bfd *, Elf_Internal_Rela *, bfd_byte *, bfd_vma)); +static bfd_reloc_status_type elf32_frv_relocate_label24 + PARAMS ((bfd *, asection *, Elf_Internal_Rela *, bfd_byte *, bfd_vma)); +static bfd_reloc_status_type elf32_frv_relocate_gprel12 + PARAMS ((struct bfd_link_info *, bfd *, asection *, Elf_Internal_Rela *, bfd_byte *, bfd_vma)); +static bfd_reloc_status_type elf32_frv_relocate_gprelu12 + PARAMS ((struct bfd_link_info *, bfd *, asection *, Elf_Internal_Rela *, bfd_byte *, bfd_vma)); +static bfd_reloc_status_type elf32_frv_relocate_gprello + PARAMS ((struct bfd_link_info *, bfd *, asection *, Elf_Internal_Rela *, bfd_byte *, bfd_vma)); +static bfd_reloc_status_type elf32_frv_relocate_gprelhi + PARAMS ((struct bfd_link_info *, bfd *, asection *, Elf_Internal_Rela *, bfd_byte *, bfd_vma)); +static reloc_howto_type *frv_reloc_type_lookup + PARAMS ((bfd *, bfd_reloc_code_real_type)); +static void frv_info_to_howto_rela + PARAMS ((bfd *, arelent *, Elf32_Internal_Rela *)); +static boolean elf32_frv_relocate_section + PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *, Elf_Internal_Rela *, Elf_Internal_Sym *, asection **)); +static boolean elf32_frv_add_symbol_hook + PARAMS (( bfd *, struct bfd_link_info *, const Elf_Internal_Sym *, const char **, flagword *, asection **, bfd_vma *)); +static bfd_reloc_status_type frv_final_link_relocate + PARAMS ((reloc_howto_type *, bfd *, asection *, bfd_byte *, Elf_Internal_Rela *, bfd_vma)); +static boolean elf32_frv_gc_sweep_hook + PARAMS ((bfd *, struct bfd_link_info *, asection *, const Elf_Internal_Rela *)); +static asection * elf32_frv_gc_mark_hook + PARAMS ((bfd *, struct bfd_link_info *, Elf_Internal_Rela *, struct elf_link_hash_entry *, Elf_Internal_Sym *)); +static boolean elf32_frv_check_relocs + PARAMS ((bfd *, struct bfd_link_info *, asection *, const Elf_Internal_Rela *)); +static int elf32_frv_machine PARAMS ((bfd *)); +static boolean elf32_frv_object_p PARAMS ((bfd *)); +static boolean frv_elf_set_private_flags PARAMS ((bfd *, flagword)); +static boolean frv_elf_copy_private_bfd_data PARAMS ((bfd *, bfd *)); +static boolean frv_elf_merge_private_bfd_data PARAMS ((bfd *, bfd *)); +static boolean frv_elf_print_private_bfd_data PARAMS ((bfd *, PTR)); + +static reloc_howto_type elf32_frv_howto_table [] = +{ + /* This reloc does nothing. */ + HOWTO (R_FRV_NONE, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_FRV_NONE", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + false), /* pcrel_offset */ + + /* A 32 bit absolute relocation. */ + HOWTO (R_FRV_32, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_FRV_32", /* name */ + false, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ + + /* A 16 bit pc-relative relocation. */ + HOWTO (R_FRV_LABEL16, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + true, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_FRV_LABEL16", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + true), /* pcrel_offset */ + + /* A 24-bit pc-relative relocation. */ + HOWTO (R_FRV_LABEL24, /* type */ + 2, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 26, /* bitsize */ + true, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_FRV_LABEL24", /* name */ + false, /* partial_inplace */ + 0x7e03ffff, /* src_mask */ + 0x7e03ffff, /* dst_mask */ + true), /* pcrel_offset */ + + HOWTO (R_FRV_LO16, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_FRV_LO16", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_FRV_HI16, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_FRV_HI16", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_FRV_GPREL12, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 12, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_FRV_GPREL12", /* name */ + false, /* partial_inplace */ + 0xfff, /* src_mask */ + 0xfff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_FRV_GPRELU12, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 12, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_FRV_GPRELU12", /* name */ + false, /* partial_inplace */ + 0xfff, /* src_mask */ + 0x3f03f, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_FRV_GPREL32, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_FRV_GPREL32", /* name */ + false, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_FRV_GPRELHI, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_FRV_GPRELHI", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_FRV_GPRELLO, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_FRV_GPRELLO", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ +}; + +/* GNU extension to record C++ vtable hierarchy. */ +static reloc_howto_type elf32_frv_vtinherit_howto = + HOWTO (R_FRV_GNU_VTINHERIT, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 0, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + NULL, /* special_function */ + "R_FRV_GNU_VTINHERIT", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + false); /* pcrel_offset */ + + /* GNU extension to record C++ vtable member usage. */ +static reloc_howto_type elf32_frv_vtentry_howto = + HOWTO (R_FRV_GNU_VTENTRY, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 0, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_elf_rel_vtable_reloc_fn, /* special_function */ + "R_FRV_GNU_VTENTRY", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + false); /* pcrel_offset */ + +/* Map BFD reloc types to FRV ELF reloc types. */ +#if 0 +struct frv_reloc_map +{ + unsigned int bfd_reloc_val; + unsigned int frv_reloc_val; +}; + +static const struct frv_reloc_map frv_reloc_map [] = +{ + { BFD_RELOC_NONE, R_FRV_NONE }, + { BFD_RELOC_32, R_FRV_32 }, + { BFD_RELOC_FRV_LABEL16, R_FRV_LABEL16 }, + { BFD_RELOC_FRV_LABEL24, R_FRV_LABEL24 }, + { BFD_RELOC_FRV_LO16, R_FRV_LO16 }, + { BFD_RELOC_FRV_HI16, R_FRV_HI16 }, + { BFD_RELOC_FRV_GPREL12, R_FRV_GPREL12 }, + { BFD_RELOC_FRV_GPRELU12, R_FRV_GPRELU12 }, + { BFD_RELOC_FRV_GPREL32, R_FRV_GPREL32 }, + { BFD_RELOC_FRV_GPRELHI, R_FRV_GPRELHI }, + { BFD_RELOC_FRV_GPRELLO, R_FRV_GPRELLO }, + { BFD_RELOC_VTABLE_INHERIT, R_FRV_GNU_VTINHERIT }, + { BFD_RELOC_VTABLE_ENTRY, R_FRV_GNU_VTENTRY }, +}; +#endif + +/* Handle an FRV small data reloc. */ + +static bfd_reloc_status_type +elf32_frv_relocate_gprel12 (info, input_bfd, input_section, relocation, contents, value) + struct bfd_link_info *info; + bfd *input_bfd; + asection *input_section; + Elf_Internal_Rela *relocation; + bfd_byte *contents; + bfd_vma value; +{ + bfd_vma insn; + bfd_vma gp; + struct bfd_link_hash_entry *h; + + h = bfd_link_hash_lookup (info->hash, "_gp", false, false, true); + + gp = (h->u.def.value + + h->u.def.section->output_section->vma + + h->u.def.section->output_offset); + + value -= input_section->output_section->vma; + value -= (gp - input_section->output_section->vma); + + insn = bfd_get_32 (input_bfd, contents + relocation->r_offset); + + value += relocation->r_addend; + + if ((long) value > 0x7ff || (long) value < -0x800) + return bfd_reloc_overflow; + + bfd_put_32 (input_bfd, + (insn & 0xfffff000) | (value & 0xfff), + contents + relocation->r_offset); + + return bfd_reloc_ok; +} + +/* Handle an FRV small data reloc. for the u12 field. */ + +static bfd_reloc_status_type +elf32_frv_relocate_gprelu12 (info, input_bfd, input_section, relocation, contents, value) + struct bfd_link_info *info; + bfd *input_bfd; + asection *input_section; + Elf_Internal_Rela *relocation; + bfd_byte *contents; + bfd_vma value; +{ + bfd_vma insn; + bfd_vma gp; + struct bfd_link_hash_entry *h; + bfd_vma mask; + + h = bfd_link_hash_lookup (info->hash, "_gp", false, false, true); + + gp = (h->u.def.value + + h->u.def.section->output_section->vma + + h->u.def.section->output_offset); + + value -= input_section->output_section->vma; + value -= (gp - input_section->output_section->vma); + + insn = bfd_get_32 (input_bfd, contents + relocation->r_offset); + + value += relocation->r_addend; + + if ((long) value > 0x7ff || (long) value < -0x800) + return bfd_reloc_overflow; + + /* The high 6 bits go into bits 17-12. The low 6 bits go into bits 5-0. */ + mask = 0x3f03f; + insn = (insn & ~mask) | ((value & 0xfc0) << 12) | (value & 0x3f); + + bfd_put_32 (input_bfd, insn, contents + relocation->r_offset); + + return bfd_reloc_ok; +} + +/* Handle an FRV ELF HI16 reloc. */ + +static bfd_reloc_status_type +elf32_frv_relocate_hi16 (input_bfd, relhi, contents, value) + bfd *input_bfd; + Elf_Internal_Rela *relhi; + bfd_byte *contents; + bfd_vma value; +{ + bfd_vma insn; + + insn = bfd_get_32 (input_bfd, contents + relhi->r_offset); + + value += relhi->r_addend; + value = ((value >> 16) & 0xffff); + + insn = (insn & 0xffff0000) | value; + + if ((long) value > 0xffff || (long) value < -0x10000) + return bfd_reloc_overflow; + + bfd_put_32 (input_bfd, insn, contents + relhi->r_offset); + return bfd_reloc_ok; + +} +static bfd_reloc_status_type +elf32_frv_relocate_lo16 (input_bfd, rello, contents, value) + bfd *input_bfd; + Elf_Internal_Rela *rello; + bfd_byte *contents; + bfd_vma value; +{ + bfd_vma insn; + + insn = bfd_get_32 (input_bfd, contents + rello->r_offset); + + value += rello->r_addend; + value = value & 0xffff; + + insn = (insn & 0xffff0000) | value; + + if ((long) value > 0xffff || (long) value < -0x10000) + return bfd_reloc_overflow; + + bfd_put_32 (input_bfd, insn, contents + rello->r_offset); + return bfd_reloc_ok; +} + +/* Perform the relocation for the CALL label24 instruction. */ + +static bfd_reloc_status_type +elf32_frv_relocate_label24 (input_bfd, input_section, rello, contents, value) + bfd *input_bfd; + asection *input_section; + Elf_Internal_Rela *rello; + bfd_byte *contents; + bfd_vma value; +{ + bfd_vma insn; + bfd_vma label6; + bfd_vma label18; + + /* The format for the call instruction is: + + 0 000000 0001111 000000000000000000 + label6 opcode label18 + + The branch calculation is: pc + (4*label24) + where label24 is the concatenation of label6 and label18. */ + + /* Grab the instruction. */ + insn = bfd_get_32 (input_bfd, contents + rello->r_offset); + + value -= input_section->output_section->vma + input_section->output_offset; + value -= rello->r_offset; + value += rello->r_addend; + + value = value >> 2; + + label6 = value & 0xfc0000; + label6 = label6 << 7; + + label18 = value & 0x3ffff; + + insn = insn & 0x803c0000; + insn = insn | label6; + insn = insn | label18; + + bfd_put_32 (input_bfd, insn, contents + rello->r_offset); + + return bfd_reloc_ok; +} + +static bfd_reloc_status_type +elf32_frv_relocate_gprelhi (info, input_bfd, input_section, relocation, contents, value) + struct bfd_link_info *info; + bfd *input_bfd; + asection *input_section; + Elf_Internal_Rela *relocation; + bfd_byte *contents; + bfd_vma value; +{ + bfd_vma insn; + bfd_vma gp; + struct bfd_link_hash_entry *h; + + h = bfd_link_hash_lookup (info->hash, "_gp", false, false, true); + + gp = (h->u.def.value + + h->u.def.section->output_section->vma + + h->u.def.section->output_offset); + + value -= input_section->output_section->vma; + value -= (gp - input_section->output_section->vma); + value += relocation->r_addend; + value = ((value >> 16) & 0xffff); + + if ((long) value > 0xffff || (long) value < -0x10000) + return bfd_reloc_overflow; + + insn = bfd_get_32 (input_bfd, contents + relocation->r_offset); + insn = (insn & 0xffff0000) | value; + + bfd_put_32 (input_bfd, insn, contents + relocation->r_offset); + return bfd_reloc_ok; +} + +static bfd_reloc_status_type +elf32_frv_relocate_gprello (info, input_bfd, input_section, relocation, contents, value) + struct bfd_link_info *info; + bfd *input_bfd; + asection *input_section; + Elf_Internal_Rela *relocation; + bfd_byte *contents; + bfd_vma value; +{ + bfd_vma insn; + bfd_vma gp; + struct bfd_link_hash_entry *h; + + h = bfd_link_hash_lookup (info->hash, "_gp", false, false, true); + + gp = (h->u.def.value + + h->u.def.section->output_section->vma + + h->u.def.section->output_offset); + + value -= input_section->output_section->vma; + value -= (gp - input_section->output_section->vma); + value += relocation->r_addend; + value = value & 0xffff; + + if ((long) value > 0xffff || (long) value < -0x10000) + return bfd_reloc_overflow; + + insn = bfd_get_32 (input_bfd, contents + relocation->r_offset); + insn = (insn & 0xffff0000) | value; + + bfd_put_32 (input_bfd, insn, contents + relocation->r_offset); + + return bfd_reloc_ok; +} + +static reloc_howto_type * +frv_reloc_type_lookup (abfd, code) + bfd * abfd ATTRIBUTE_UNUSED; + bfd_reloc_code_real_type code; +{ + switch (code) + { + default: + break; + + case BFD_RELOC_NONE: + return &elf32_frv_howto_table[ (int) R_FRV_NONE]; + + case BFD_RELOC_32: + case BFD_RELOC_CTOR: + return &elf32_frv_howto_table[ (int) R_FRV_32]; + + case BFD_RELOC_FRV_LABEL16: + return &elf32_frv_howto_table[ (int) R_FRV_LABEL16]; + + case BFD_RELOC_FRV_LABEL24: + return &elf32_frv_howto_table[ (int) R_FRV_LABEL24]; + + case BFD_RELOC_FRV_LO16: + return &elf32_frv_howto_table[ (int) R_FRV_LO16]; + + case BFD_RELOC_FRV_HI16: + return &elf32_frv_howto_table[ (int) R_FRV_HI16]; + + case BFD_RELOC_FRV_GPREL12: + return &elf32_frv_howto_table[ (int) R_FRV_GPREL12]; + + case BFD_RELOC_FRV_GPRELU12: + return &elf32_frv_howto_table[ (int) R_FRV_GPRELU12]; + + case BFD_RELOC_FRV_GPREL32: + return &elf32_frv_howto_table[ (int) R_FRV_GPREL32]; + + case BFD_RELOC_FRV_GPRELHI: + return &elf32_frv_howto_table[ (int) R_FRV_GPRELHI]; + + case BFD_RELOC_FRV_GPRELLO: + return &elf32_frv_howto_table[ (int) R_FRV_GPRELLO]; + + case BFD_RELOC_VTABLE_INHERIT: + return &elf32_frv_vtinherit_howto; + + case BFD_RELOC_VTABLE_ENTRY: + return &elf32_frv_vtentry_howto; + } + + return NULL; +} + +/* Set the howto pointer for an FRV ELF reloc. */ + +static void +frv_info_to_howto_rela (abfd, cache_ptr, dst) + bfd * abfd ATTRIBUTE_UNUSED; + arelent * cache_ptr; + Elf32_Internal_Rela * dst; +{ + unsigned int r_type; + + r_type = ELF32_R_TYPE (dst->r_info); + switch (r_type) + { + case R_FRV_GNU_VTINHERIT: + cache_ptr->howto = &elf32_frv_vtinherit_howto; + break; + + case R_FRV_GNU_VTENTRY: + cache_ptr->howto = &elf32_frv_vtentry_howto; + break; + + default: + cache_ptr->howto = & elf32_frv_howto_table [r_type]; + break; + } +} + +/* Perform a single relocation. By default we use the standard BFD + routines, but a few relocs, we have to do them ourselves. */ + +static bfd_reloc_status_type +frv_final_link_relocate (howto, input_bfd, input_section, contents, rel, relocation) + reloc_howto_type * howto; + bfd * input_bfd; + asection * input_section; + bfd_byte * contents; + Elf_Internal_Rela * rel; + bfd_vma relocation; +{ + return _bfd_final_link_relocate (howto, input_bfd, input_section, + contents, rel->r_offset, relocation, + rel->r_addend); +} + + +/* Relocate an FRV ELF section. + There is some attempt to make this function usable for many architectures, + both USE_REL and USE_RELA ['twould be nice if such a critter existed], + if only to serve as a learning tool. + + The RELOCATE_SECTION function is called by the new ELF backend linker + to handle the relocations for a section. + + The relocs are always passed as Rela structures; if the section + actually uses Rel structures, the r_addend field will always be + zero. + + This function is responsible for adjusting the section contents as + necessary, and (if using Rela relocs and generating a relocateable + output file) adjusting the reloc addend as necessary. + + This function does not have to worry about setting the reloc + address or the reloc symbol index. + + LOCAL_SYMS is a pointer to the swapped in local symbols. + + LOCAL_SECTIONS is an array giving the section in the input file + corresponding to the st_shndx field of each local symbol. + + The global hash table entry for the global symbols can be found + via elf_sym_hashes (input_bfd). + + When generating relocateable output, this function must handle + STB_LOCAL/STT_SECTION symbols specially. The output symbol is + going to be the section symbol corresponding to the output + section, which means that the addend must be adjusted + accordingly. */ + +static boolean +elf32_frv_relocate_section (output_bfd, info, input_bfd, input_section, + contents, relocs, local_syms, local_sections) + bfd * output_bfd ATTRIBUTE_UNUSED; + struct bfd_link_info * info; + bfd * input_bfd; + asection * input_section; + bfd_byte * contents; + Elf_Internal_Rela * relocs; + Elf_Internal_Sym * local_syms; + asection ** local_sections; +{ + Elf_Internal_Shdr * symtab_hdr; + struct elf_link_hash_entry ** sym_hashes; + Elf_Internal_Rela * rel; + Elf_Internal_Rela * relend; + + symtab_hdr = & elf_tdata (input_bfd)->symtab_hdr; + sym_hashes = elf_sym_hashes (input_bfd); + relend = relocs + input_section->reloc_count; + + for (rel = relocs; rel < relend; rel ++) + { + reloc_howto_type * howto; + unsigned long r_symndx; + Elf_Internal_Sym * sym; + asection * sec; + struct elf_link_hash_entry * h; + bfd_vma relocation; + bfd_reloc_status_type r; + const char * name = NULL; + int r_type; + + r_type = ELF32_R_TYPE (rel->r_info); + + if ( r_type == R_FRV_GNU_VTINHERIT + || r_type == R_FRV_GNU_VTENTRY) + continue; + + r_symndx = ELF32_R_SYM (rel->r_info); + + if (info->relocateable) + { + /* This is a relocateable link. We don't have to change + anything, unless the reloc is against a section symbol, + in which case we have to adjust according to where the + section symbol winds up in the output section. */ + if (r_symndx < symtab_hdr->sh_info) + { + sym = local_syms + r_symndx; + + if (ELF_ST_TYPE (sym->st_info) == STT_SECTION) + { + sec = local_sections [r_symndx]; + rel->r_addend += sec->output_offset + sym->st_value; + } + } + + continue; + } + + /* This is a final link. */ + howto = elf32_frv_howto_table + ELF32_R_TYPE (rel->r_info); + h = NULL; + sym = NULL; + sec = NULL; + + if (r_symndx < symtab_hdr->sh_info) + { + sym = local_syms + r_symndx; + sec = local_sections [r_symndx]; + relocation = (sec->output_section->vma + + sec->output_offset + + sym->st_value); + + name = bfd_elf_string_from_elf_section + (input_bfd, symtab_hdr->sh_link, sym->st_name); + name = (name == NULL) ? bfd_section_name (input_bfd, sec) : name; + } + else + { + h = sym_hashes [r_symndx - symtab_hdr->sh_info]; + + while (h->root.type == bfd_link_hash_indirect + || h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; + + name = h->root.root.string; + + if (h->root.type == bfd_link_hash_defined + || h->root.type == bfd_link_hash_defweak) + { + sec = h->root.u.def.section; + relocation = (h->root.u.def.value + + sec->output_section->vma + + sec->output_offset); + } + else if (h->root.type == bfd_link_hash_undefweak) + { + relocation = 0; + } + else + { + if (! ((*info->callbacks->undefined_symbol) + (info, h->root.root.string, input_bfd, + input_section, rel->r_offset, true))) + return false; + relocation = 0; + } + } + + if (r_type == R_FRV_HI16) + r = elf32_frv_relocate_hi16 (input_bfd, rel, contents, relocation); + + else if (r_type == R_FRV_LO16) + r = elf32_frv_relocate_lo16 (input_bfd, rel, contents, relocation); + + else if (r_type == R_FRV_LABEL24) + r = elf32_frv_relocate_label24 (input_bfd, input_section, rel, contents, relocation); + + else if (r_type == R_FRV_GPREL12) + r = elf32_frv_relocate_gprel12 (info, input_bfd, input_section, rel, contents, relocation); + + else if (r_type == R_FRV_GPRELU12) + r = elf32_frv_relocate_gprelu12 (info, input_bfd, input_section, rel, contents, relocation); + + else if (r_type == R_FRV_GPRELLO) + r = elf32_frv_relocate_gprello (info, input_bfd, input_section, rel, contents, relocation); + + else if (r_type == R_FRV_GPRELHI) + r = elf32_frv_relocate_gprelhi (info, input_bfd, input_section, rel, contents, relocation); + + else + r = frv_final_link_relocate (howto, input_bfd, input_section, contents, rel, relocation); + + if (r != bfd_reloc_ok) + { + const char * msg = (const char *) NULL; + + switch (r) + { + case bfd_reloc_overflow: + r = info->callbacks->reloc_overflow + (info, name, howto->name, (bfd_vma) 0, + input_bfd, input_section, rel->r_offset); + break; + + case bfd_reloc_undefined: + r = info->callbacks->undefined_symbol + (info, name, input_bfd, input_section, rel->r_offset, true); + break; + + case bfd_reloc_outofrange: + msg = _("internal error: out of range error"); + break; + + case bfd_reloc_notsupported: + msg = _("internal error: unsupported relocation error"); + break; + + case bfd_reloc_dangerous: + msg = _("internal error: dangerous relocation"); + break; + + default: + msg = _("internal error: unknown error"); + break; + } + + if (msg) + r = info->callbacks->warning + (info, msg, name, input_bfd, input_section, rel->r_offset); + + if (! r) + return false; + } + } + + return true; +} + +/* Return the section that should be marked against GC for a given + relocation. */ + +static asection * +elf32_frv_gc_mark_hook (abfd, info, rel, h, sym) + bfd * abfd; + struct bfd_link_info * info ATTRIBUTE_UNUSED; + Elf_Internal_Rela * rel; + struct elf_link_hash_entry * h; + Elf_Internal_Sym * sym; +{ + if (h != NULL) + { + switch (ELF32_R_TYPE (rel->r_info)) + { + case R_FRV_GNU_VTINHERIT: + case R_FRV_GNU_VTENTRY: + break; + + default: + switch (h->root.type) + { + default: + break; + + case bfd_link_hash_defined: + case bfd_link_hash_defweak: + return h->root.u.def.section; + + case bfd_link_hash_common: + return h->root.u.c.p->section; + } + } + } + else + { + if (!(elf_bad_symtab (abfd) + && ELF_ST_BIND (sym->st_info) != STB_LOCAL) + && ! ((sym->st_shndx <= 0 || sym->st_shndx >= SHN_LORESERVE) + && sym->st_shndx != SHN_COMMON)) + return bfd_section_from_elf_index (abfd, sym->st_shndx); + } + + return NULL; +} + +/* Update the got entry reference counts for the section being removed. */ + +static boolean +elf32_frv_gc_sweep_hook (abfd, info, sec, relocs) + bfd * abfd ATTRIBUTE_UNUSED; + struct bfd_link_info * info ATTRIBUTE_UNUSED; + asection * sec ATTRIBUTE_UNUSED; + const Elf_Internal_Rela * relocs ATTRIBUTE_UNUSED; +{ + return true; +} + + +/* Hook called by the linker routine which adds symbols from an object + file. We use it to put .comm items in .scomm, and not .comm. */ + +static boolean +elf32_frv_add_symbol_hook (abfd, info, sym, namep, flagsp, secp, valp) + bfd *abfd; + struct bfd_link_info *info; + const Elf_Internal_Sym *sym; + const char **namep ATTRIBUTE_UNUSED; + flagword *flagsp ATTRIBUTE_UNUSED; + asection **secp; + bfd_vma *valp; +{ + if (sym->st_shndx == SHN_COMMON + && !info->relocateable + && (int)sym->st_size <= (int)bfd_get_gp_size (abfd)) + { + /* Common symbols less than or equal to -G nn bytes are + automatically put into .sbss. */ + + asection *scomm = bfd_get_section_by_name (abfd, ".scommon"); + + if (scomm == NULL) + { + scomm = bfd_make_section (abfd, ".scommon"); + if (scomm == NULL + || !bfd_set_section_flags (abfd, scomm, (SEC_ALLOC + | SEC_IS_COMMON + | SEC_LINKER_CREATED))) + return false; + } + + *secp = scomm; + *valp = sym->st_size; + } + + return true; +} +/* Look through the relocs for a section during the first phase. + Since we don't do .gots or .plts, we just need to consider the + virtual table relocs for gc. */ + +static boolean +elf32_frv_check_relocs (abfd, info, sec, relocs) + bfd *abfd; + struct bfd_link_info *info; + asection *sec; + const Elf_Internal_Rela *relocs; +{ + Elf_Internal_Shdr *symtab_hdr; + struct elf_link_hash_entry **sym_hashes, **sym_hashes_end; + const Elf_Internal_Rela *rel; + const Elf_Internal_Rela *rel_end; + + if (info->relocateable) + return true; + + symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + sym_hashes = elf_sym_hashes (abfd); + sym_hashes_end = sym_hashes + symtab_hdr->sh_size/sizeof(Elf32_External_Sym); + if (!elf_bad_symtab (abfd)) + sym_hashes_end -= symtab_hdr->sh_info; + + rel_end = relocs + sec->reloc_count; + for (rel = relocs; rel < rel_end; rel++) + { + struct elf_link_hash_entry *h; + unsigned long r_symndx; + + r_symndx = ELF32_R_SYM (rel->r_info); + if (r_symndx < symtab_hdr->sh_info) + h = NULL; + else + h = sym_hashes[r_symndx - symtab_hdr->sh_info]; + + switch (ELF32_R_TYPE (rel->r_info)) + { + /* This relocation describes the C++ object vtable hierarchy. + Reconstruct it for later use during GC. */ + case R_FRV_GNU_VTINHERIT: + if (!_bfd_elf32_gc_record_vtinherit (abfd, sec, h, rel->r_offset)) + return false; + break; + + /* This relocation describes which C++ vtable entries are actually + used. Record for later use during GC. */ + case R_FRV_GNU_VTENTRY: + if (!_bfd_elf32_gc_record_vtentry (abfd, sec, h, rel->r_addend)) + return false; + break; + } + } + + return true; +} + + +/* Return the machine subcode from the ELF e_flags header. */ + +static int +elf32_frv_machine (abfd) + bfd *abfd; +{ + switch (elf_elfheader (abfd)->e_flags & EF_FRV_CPU_MASK) + { + default: break; + case EF_FRV_CPU_FR500: return bfd_mach_fr500; + case EF_FRV_CPU_FR400: return bfd_mach_fr400; + case EF_FRV_CPU_FR300: return bfd_mach_fr300; + case EF_FRV_CPU_SIMPLE: return bfd_mach_frvsimple; + case EF_FRV_CPU_TOMCAT: return bfd_mach_frvtomcat; + } + + return bfd_mach_frv; +} + +/* Set the right machine number for a FRV ELF file. */ + +static boolean +elf32_frv_object_p (abfd) + bfd *abfd; +{ + bfd_default_set_arch_mach (abfd, bfd_arch_frv, elf32_frv_machine (abfd)); + return true; +} + +/* Function to set the ELF flag bits. */ + +static boolean +frv_elf_set_private_flags (abfd, flags) + bfd *abfd; + flagword flags; +{ + elf_elfheader (abfd)->e_flags = flags; + elf_flags_init (abfd) = true; + return true; +} + +/* Copy backend specific data from one object module to another. */ + +static boolean +frv_elf_copy_private_bfd_data (ibfd, obfd) + bfd *ibfd; + bfd *obfd; +{ + if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour + || bfd_get_flavour (obfd) != bfd_target_elf_flavour) + return true; + + BFD_ASSERT (!elf_flags_init (obfd) + || elf_elfheader (obfd)->e_flags == elf_elfheader (ibfd)->e_flags); + + elf_elfheader (obfd)->e_flags = elf_elfheader (ibfd)->e_flags; + elf_flags_init (obfd) = true; + return true; +} + +/* Merge backend specific data from an object file to the output + object file when linking. */ + +static boolean +frv_elf_merge_private_bfd_data (ibfd, obfd) + bfd *ibfd; + bfd *obfd; +{ + flagword old_flags, old_partial; + flagword new_flags, new_partial; + boolean error = false; + char new_opt[80]; + char old_opt[80]; + + new_opt[0] = old_opt[0] = '\0'; + new_flags = elf_elfheader (ibfd)->e_flags; + old_flags = elf_elfheader (obfd)->e_flags; + +#ifdef DEBUG + (*_bfd_error_handler) ("old_flags = 0x%.8lx, new_flags = 0x%.8lx, init = %s, filename = %s", + old_flags, new_flags, elf_flags_init (obfd) ? "yes" : "no", + bfd_get_filename (ibfd)); +#endif + + if (!elf_flags_init (obfd)) /* First call, no flags set. */ + { + elf_flags_init (obfd) = true; + old_flags = new_flags; + } + + else if (new_flags == old_flags) /* Compatible flags are ok. */ + ; + + else /* Possibly incompatible flags. */ + { + /* Warn if different # of gprs are used. Note, 0 means nothing is + said about the size of gprs. */ + new_partial = (new_flags & EF_FRV_GPR_MASK); + old_partial = (old_flags & EF_FRV_GPR_MASK); + if (new_partial == old_partial) + ; + + else if (new_partial == 0) + ; + + else if (old_partial == 0) + old_flags |= new_partial; + + else + { + switch (new_partial) + { + default: strcat (new_opt, " -mgpr-??"); break; + case EF_FRV_GPR_32: strcat (new_opt, " -mgpr-32"); break; + case EF_FRV_GPR_64: strcat (new_opt, " -mgpr-64"); break; + } + + switch (old_partial) + { + default: strcat (old_opt, " -mgpr-??"); break; + case EF_FRV_GPR_32: strcat (old_opt, " -mgpr-32"); break; + case EF_FRV_GPR_64: strcat (old_opt, " -mgpr-64"); break; + } + } + + /* Warn if different # of fprs are used. Note, 0 means nothing is + said about the size of fprs. */ + new_partial = (new_flags & EF_FRV_FPR_MASK); + old_partial = (old_flags & EF_FRV_FPR_MASK); + if (new_partial == old_partial) + ; + + else if (new_partial == 0) + ; + + else if (old_partial == 0) + old_flags |= new_partial; + + else + { + switch (new_partial) + { + default: strcat (new_opt, " -mfpr-?"); break; + case EF_FRV_FPR_32: strcat (new_opt, " -mfpr-32"); break; + case EF_FRV_FPR_64: strcat (new_opt, " -mfpr-64"); break; + case EF_FRV_FPR_NONE: strcat (new_opt, " -msoft-float"); break; + } + + switch (old_partial) + { + default: strcat (old_opt, " -mfpr-?"); break; + case EF_FRV_FPR_32: strcat (old_opt, " -mfpr-32"); break; + case EF_FRV_FPR_64: strcat (old_opt, " -mfpr-64"); break; + case EF_FRV_FPR_NONE: strcat (old_opt, " -msoft-float"); break; + } + } + + /* Warn if different dword support was used. Note, 0 means nothing is + said about the dword support. */ + new_partial = (new_flags & EF_FRV_DWORD_MASK); + old_partial = (old_flags & EF_FRV_DWORD_MASK); + if (new_partial == old_partial) + ; + + else if (new_partial == 0) + ; + + else if (old_partial == 0) + old_flags |= new_partial; + + else + { + switch (new_partial) + { + default: strcat (new_opt, " -mdword-?"); break; + case EF_FRV_DWORD_YES: strcat (new_opt, " -mdword"); break; + case EF_FRV_DWORD_NO: strcat (new_opt, " -mno-dword"); break; + } + + switch (old_partial) + { + default: strcat (old_opt, " -mdword-?"); break; + case EF_FRV_DWORD_YES: strcat (old_opt, " -mdword"); break; + case EF_FRV_DWORD_NO: strcat (old_opt, " -mno-dword"); break; + } + } + + /* Or in flags that accumulate (ie, if one module uses it, mark that the + feature is used. */ + old_flags |= new_flags & (EF_FRV_DOUBLE + | EF_FRV_MEDIA + | EF_FRV_MULADD + | EF_FRV_NON_PIC_RELOCS); + + /* If any module was compiled without -G0, clear the G0 bit. */ + old_flags = ((old_flags & ~ EF_FRV_G0) + | (old_flags & new_flags & EF_FRV_G0)); + + /* If any module was compiled without -mnopack, clear the mnopack bit. */ + old_flags = ((old_flags & ~ EF_FRV_NOPACK) + | (old_flags & new_flags & EF_FRV_NOPACK)); + + /* We don't have to do anything if the pic flags are the same, or the new + module(s) were compiled with -mlibrary-pic. */ + new_partial = (new_flags & EF_FRV_PIC_FLAGS); + old_partial = (old_flags & EF_FRV_PIC_FLAGS); + if ((new_partial == old_partial) || ((new_partial & EF_FRV_LIBPIC) != 0)) + ; + + /* If the old module(s) were compiled with -mlibrary-pic, copy in the pic + flags if any from the new module. */ + else if ((old_partial & EF_FRV_LIBPIC) != 0) + old_flags = (old_flags & ~ EF_FRV_PIC_FLAGS) | new_partial; + + /* If we have mixtures of -fpic and -fPIC, or in both bits. */ + else if (new_partial != 0 && old_partial != 0) + old_flags |= new_partial; + + /* One module was compiled for pic and the other was not, see if we have + had any relocations that are not pic-safe. */ + else + { + if ((old_flags & EF_FRV_NON_PIC_RELOCS) == 0) + old_flags |= new_partial; + else + { + old_flags &= ~ EF_FRV_PIC_FLAGS; +#ifndef FRV_NO_PIC_ERROR + error = true; + (*_bfd_error_handler) + (_("%s: compiled with %s and linked with modules that use non-pic relocations"), + bfd_get_filename (ibfd), + (new_flags & EF_FRV_BIGPIC) ? "-fPIC" : "-fpic"); +#endif + } + } + + /* Warn if different cpu is used (allow a specific cpu to override + the generic cpu). */ + new_partial = (new_flags & EF_FRV_CPU_MASK); + old_partial = (old_flags & EF_FRV_CPU_MASK); + if (new_partial == old_partial) + ; + + else if (new_partial == EF_FRV_CPU_GENERIC) + ; + + else if (old_partial == EF_FRV_CPU_GENERIC) + old_flags = (old_flags & ~EF_FRV_CPU_MASK) | new_partial; + + else + { + switch (new_partial) + { + default: strcat (new_opt, " -mcpu=?"); break; + case EF_FRV_CPU_GENERIC: strcat (new_opt, " -mcpu=frv"); break; + case EF_FRV_CPU_SIMPLE: strcat (new_opt, " -mcpu=simple"); break; + case EF_FRV_CPU_FR500: strcat (new_opt, " -mcpu=fr500"); break; + case EF_FRV_CPU_FR400: strcat (new_opt, " -mcpu=fr400"); break; + case EF_FRV_CPU_FR300: strcat (new_opt, " -mcpu=fr300"); break; + case EF_FRV_CPU_TOMCAT: strcat (new_opt, " -mcpu=tomcat"); break; + } + + switch (old_partial) + { + default: strcat (old_opt, " -mcpu=?"); break; + case EF_FRV_CPU_GENERIC: strcat (old_opt, " -mcpu=frv"); break; + case EF_FRV_CPU_SIMPLE: strcat (old_opt, " -mcpu=simple"); break; + case EF_FRV_CPU_FR500: strcat (old_opt, " -mcpu=fr500"); break; + case EF_FRV_CPU_FR400: strcat (old_opt, " -mcpu=fr400"); break; + case EF_FRV_CPU_FR300: strcat (old_opt, " -mcpu=fr300"); break; + case EF_FRV_CPU_TOMCAT: strcat (old_opt, " -mcpu=tomcat"); break; + } + } + + /* Print out any mismatches from above. */ + if (new_opt[0]) + { + error = true; + (*_bfd_error_handler) + (_("%s: compiled with %s and linked with modules compiled with %s"), + bfd_get_filename (ibfd), new_opt, old_opt); + } + + /* Warn about any other mismatches */ + new_partial = (new_flags & ~ EF_FRV_ALL_FLAGS); + old_partial = (old_flags & ~ EF_FRV_ALL_FLAGS); + if (new_partial != old_partial) + { + old_flags |= new_partial; + error = true; + (*_bfd_error_handler) + (_("%s: uses different unknown e_flags (0x%lx) fields than previous modules (0x%lx)"), + bfd_get_filename (ibfd), (long)new_partial, (long)old_partial); + } + } + + /* If the cpu is -mcpu=simple, then set the -mnopack bit. */ + if ((old_flags & EF_FRV_CPU_MASK) == EF_FRV_CPU_SIMPLE) + old_flags |= EF_FRV_NOPACK; + + /* Update the old flags now with changes made above. */ + old_partial = elf_elfheader (obfd)->e_flags & EF_FRV_CPU_MASK; + elf_elfheader (obfd)->e_flags = old_flags; + if (old_partial != (old_flags & EF_FRV_CPU_MASK)) + bfd_default_set_arch_mach (obfd, bfd_arch_frv, elf32_frv_machine (obfd)); + + if (error) + bfd_set_error (bfd_error_bad_value); + + return !error; +} + + +boolean +frv_elf_print_private_bfd_data (abfd, ptr) + bfd *abfd; + PTR ptr; +{ + FILE *file = (FILE *) ptr; + flagword flags; + + BFD_ASSERT (abfd != NULL && ptr != NULL); + + /* Print normal ELF private data. */ + _bfd_elf_print_private_bfd_data (abfd, ptr); + + flags = elf_elfheader (abfd)->e_flags; + fprintf (file, _("private flags = 0x%lx:"), (long)flags); + + switch (flags & EF_FRV_CPU_MASK) + { + default: break; + case EF_FRV_CPU_SIMPLE: fprintf (file, " -mcpu=simple"); break; + case EF_FRV_CPU_FR500: fprintf (file, " -mcpu=fr500"); break; + case EF_FRV_CPU_FR400: fprintf (file, " -mcpu=fr400"); break; + case EF_FRV_CPU_FR300: fprintf (file, " -mcpu=fr300"); break; + case EF_FRV_CPU_TOMCAT: fprintf (file, " -mcpu=tomcat"); break; + } + + switch (flags & EF_FRV_GPR_MASK) + { + default: break; + case EF_FRV_GPR_32: fprintf (file, " -mgpr-32"); break; + case EF_FRV_GPR_64: fprintf (file, " -mgpr-64"); break; + } + + switch (flags & EF_FRV_FPR_MASK) + { + default: break; + case EF_FRV_FPR_32: fprintf (file, " -mfpr-32"); break; + case EF_FRV_FPR_64: fprintf (file, " -mfpr-64"); break; + case EF_FRV_FPR_NONE: fprintf (file, " -msoft-float"); break; + } + + switch (flags & EF_FRV_DWORD_MASK) + { + default: break; + case EF_FRV_DWORD_YES: fprintf (file, " -mdword"); break; + case EF_FRV_DWORD_NO: fprintf (file, " -mno-dword"); break; + } + + if (flags & EF_FRV_DOUBLE) + fprintf (file, " -mdouble"); + + if (flags & EF_FRV_MEDIA) + fprintf (file, " -mmedia"); + + if (flags & EF_FRV_MULADD) + fprintf (file, " -mmuladd"); + + if (flags & EF_FRV_PIC) + fprintf (file, " -fpic"); + + if (flags & EF_FRV_BIGPIC) + fprintf (file, " -fPIC"); + + if (flags & EF_FRV_NON_PIC_RELOCS) + fprintf (file, " non-pic relocations"); + + if (flags & EF_FRV_G0) + fprintf (file, " -G0"); + + fputc ('\n', file); + return true; +} + + +#define ELF_ARCH bfd_arch_frv +#define ELF_MACHINE_CODE EM_CYGNUS_FRV +#define ELF_MAXPAGESIZE 0x1000 + +#define TARGET_BIG_SYM bfd_elf32_frv_vec +#define TARGET_BIG_NAME "elf32-frv" + +#define elf_info_to_howto_rel NULL +#define elf_info_to_howto frv_info_to_howto_rela +#define elf_backend_relocate_section elf32_frv_relocate_section +#define elf_backend_gc_mark_hook elf32_frv_gc_mark_hook +#define elf_backend_gc_sweep_hook elf32_frv_gc_sweep_hook +#define elf_backend_check_relocs elf32_frv_check_relocs +#define elf_backend_object_p elf32_frv_object_p +#define elf_backend_add_symbol_hook elf32_frv_add_symbol_hook + +#define elf_backend_can_gc_sections 1 + +#define bfd_elf32_bfd_reloc_type_lookup frv_reloc_type_lookup +#define bfd_elf32_bfd_set_private_flags frv_elf_set_private_flags +#define bfd_elf32_bfd_copy_private_bfd_data frv_elf_copy_private_bfd_data +#define bfd_elf32_bfd_merge_private_bfd_data frv_elf_merge_private_bfd_data +#define bfd_elf32_bfd_print_private_bfd_data frv_elf_print_private_bfd_data + +#include "elf32-target.h" diff --git a/bfd/elf64-hppa.c b/bfd/elf64-hppa.c index cc4694348f2..6a69d98d7f7 100644 --- a/bfd/elf64-hppa.c +++ b/bfd/elf64-hppa.c @@ -1532,15 +1532,11 @@ allocate_dynrel_entries (dyn_h, data) for (rent = dyn_h->reloc_entries; rent; rent = rent->next) { - switch (rent->type) - { - case R_PARISC_FPTR64: - /* Allocate one iff we are building a shared library and don't - want an opd entry. */ - if (!x->info->shared && dyn_h->want_opd) - continue; - break; - } + /* Allocate one iff we are building a shared library, the relocation + isn't a R_PARISC_FPTR64, or we don't want an opd entry. */ + if (!shared && rent->type == R_PARISC_FPTR64 && dyn_h->want_opd) + continue; + hppa_info->other_rel_sec->_raw_size += sizeof (Elf64_External_Rela); /* Make sure this symbol gets into the dynamic symbol table if it is @@ -1722,10 +1718,9 @@ elf64_hppa_size_dynamic_sections (output_bfd, info) if (strcmp (name, ".plt") == 0) { + /* Strip this section if we don't need it; see the comment below. */ if (s->_raw_size == 0) { - /* Strip this section if we don't need it; see the - comment below. */ strip = true; } else @@ -1736,24 +1731,29 @@ elf64_hppa_size_dynamic_sections (output_bfd, info) } else if (strcmp (name, ".dlt") == 0) { + /* Strip this section if we don't need it; see the comment below. */ if (s->_raw_size == 0) { - /* Strip this section if we don't need it; see the - comment below. */ strip = true; } } else if (strcmp (name, ".opd") == 0) { + /* Strip this section if we don't need it; see the comment below. */ if (s->_raw_size == 0) { - /* Strip this section if we don't need it; see the - comment below. */ strip = true; } } - else if (strncmp (name, ".rela", 4) == 0) + else if (strncmp (name, ".rela", 5) == 0) { + /* If we don't need this section, strip it from the output file. + This is mostly to handle .rela.bss and .rela.plt. We must + create both sections in create_dynamic_sections, because they + must be created before the linker maps input sections to output + sections. The linker does that before adjust_dynamic_symbol + is called, and it is that function which decides whether + anything needs to go into these sections. */ if (s->_raw_size == 0) { /* If we don't need this section, strip it from the @@ -1951,9 +1951,6 @@ elf64_hppa_finish_dynamic_symbol (output_bfd, info, h, sym) spltrel = hppa_info->plt_rel_sec; sdltrel = hppa_info->dlt_rel_sec; - BFD_ASSERT (stub != NULL && splt != NULL - && sopd != NULL && sdlt != NULL) - /* Incredible. It is actually necessary to NOT use the symbol's real value when building the dynamic symbol table for a shared library. At least for symbols that refer to functions. @@ -1963,6 +1960,8 @@ elf64_hppa_finish_dynamic_symbol (output_bfd, info, h, sym) the original values (in elf64_hppa_link_output_symbol_hook). */ if (dyn_h && dyn_h->want_opd) { + BFD_ASSERT (sopd != NULL) + /* Save away the original value and section index so that we can restore them later. */ dyn_h->st_value = sym->st_value; @@ -1984,6 +1983,8 @@ elf64_hppa_finish_dynamic_symbol (output_bfd, info, h, sym) bfd_vma value; Elf_Internal_Rela rel; + BFD_ASSERT (splt != NULL && spltrel != NULL) + /* We do not actually care about the value in the PLT entry if we are creating a shared library and the symbol is still undefined, we create a dynamic relocation to fill @@ -2034,6 +2035,8 @@ elf64_hppa_finish_dynamic_symbol (output_bfd, info, h, sym) int insn; unsigned int max_offset; + BFD_ASSERT (stub != NULL) + /* Install the generic stub template. We are modifying the contents of the stub section, so we do not @@ -2357,15 +2360,10 @@ elf64_hppa_finalize_dynreloc (dyn_h, data) { Elf64_Internal_Rela rel; - switch (rent->type) - { - case R_PARISC_FPTR64: - /* Allocate one iff we are building a shared library and don't - want an opd entry. */ - if (!info->shared && dyn_h->want_opd) - continue; - break; - } + /* Allocate one iff we are building a shared library, the relocation + isn't a R_PARISC_FPTR64, or we don't want an opd entry. */ + if (!info->shared && rent->type == R_PARISC_FPTR64 && dyn_h->want_opd) + continue; /* Create a dynamic relocation for this entry. diff --git a/bfd/elf64-mmix.c b/bfd/elf64-mmix.c index 55ef061d645..0dc6655f38d 100644 --- a/bfd/elf64-mmix.c +++ b/bfd/elf64-mmix.c @@ -2226,8 +2226,12 @@ bpo_reloc_request_sort_fn (p1, p2) if (r1->value != r2->value) return r1->value > r2->value ? 1 : -1; - /* As a last re-sort, use the address so we get a stable sort. */ - return r1 > r2 ? 1 : (r1 < r2 ? -1 : 0); + /* As a last re-sort, use the relocation number, so we get a stable + sort. The *addresses* aren't stable since items are swapped during + sorting. It depends on the qsort implementation if this actually + happens. */ + return r1->bpo_reloc_no > r2->bpo_reloc_no + ? 1 : (r1->bpo_reloc_no < r2->bpo_reloc_no ? -1 : 0); } /* For debug use only. Dumps the global register allocations resulting diff --git a/bfd/elfcode.h b/bfd/elfcode.h index 3e29c0287b1..f782985a42a 100644 --- a/bfd/elfcode.h +++ b/bfd/elfcode.h @@ -624,6 +624,10 @@ elf_object_p (abfd) if (i_ehdrp->e_shentsize != sizeof (x_shdr) && i_ehdrp->e_shnum != 0) goto got_wrong_format_error; + /* Further sanity check. */ + if (i_ehdrp->e_shoff == 0 && i_ehdrp->e_shnum != 0) + goto got_wrong_format_error; + ebd = get_elf_backend_data (abfd); /* Check that the ELF e_machine field matches what this particular @@ -677,25 +681,28 @@ elf_object_p (abfd) /* Remember the entry point specified in the ELF file header. */ bfd_set_start_address (abfd, i_ehdrp->e_entry); - /* Seek to the section header table in the file. */ - if (bfd_seek (abfd, (file_ptr) i_ehdrp->e_shoff, SEEK_SET) != 0) - goto got_no_match; + if (i_ehdrp->e_shoff != 0) + { + /* Seek to the section header table in the file. */ + if (bfd_seek (abfd, (file_ptr) i_ehdrp->e_shoff, SEEK_SET) != 0) + goto got_no_match; - /* Read the first section header at index 0, and convert to internal - form. */ - if (bfd_bread ((PTR) & x_shdr, (bfd_size_type) sizeof x_shdr, abfd) - != sizeof (x_shdr)) - goto got_no_match; - elf_swap_shdr_in (abfd, &x_shdr, &i_shdr); + /* Read the first section header at index 0, and convert to internal + form. */ + if (bfd_bread ((PTR) & x_shdr, (bfd_size_type) sizeof x_shdr, abfd) + != sizeof (x_shdr)) + goto got_no_match; + elf_swap_shdr_in (abfd, &x_shdr, &i_shdr); - /* If the section count is zero, the actual count is in the first - section header. */ - if (i_ehdrp->e_shnum == SHN_UNDEF) - i_ehdrp->e_shnum = i_shdr.sh_size; + /* If the section count is zero, the actual count is in the first + section header. */ + if (i_ehdrp->e_shnum == SHN_UNDEF) + i_ehdrp->e_shnum = i_shdr.sh_size; - /* And similarly for the string table index. */ - if (i_ehdrp->e_shstrndx == SHN_XINDEX) - i_ehdrp->e_shstrndx = i_shdr.sh_link; + /* And similarly for the string table index. */ + if (i_ehdrp->e_shstrndx == SHN_XINDEX) + i_ehdrp->e_shstrndx = i_shdr.sh_link; + } /* Allocate space for a copy of the section header table in internal form. */ @@ -751,7 +758,7 @@ elf_object_p (abfd) } } - if (i_ehdrp->e_shstrndx) + if (i_ehdrp->e_shstrndx && i_ehdrp->e_shoff) { if (! bfd_section_from_shdr (abfd, i_ehdrp->e_shstrndx)) goto got_no_match; @@ -789,7 +796,7 @@ elf_object_p (abfd) bfd_section_from_shdr with it (since this particular strtab is used to find all of the ELF section names.) */ - if (i_ehdrp->e_shstrndx != 0) + if (i_ehdrp->e_shstrndx != 0 && i_ehdrp->e_shoff) { unsigned int num_sec; diff --git a/bfd/elflink.h b/bfd/elflink.h index 9ba13fd0a28..b442361b611 100644 --- a/bfd/elflink.h +++ b/bfd/elflink.h @@ -3053,7 +3053,7 @@ NAME(bfd_elf,size_dynamic_sections) (output_bfd, soname, rpath, return true; if (! is_elf_hash_table (info)) - return false; + return true; /* Any syms created from now on start with -1 in got.refcount/offset and plt.refcount/offset. */ diff --git a/bfd/opncls.c b/bfd/opncls.c index f110259737a..cdf08df05dd 100644 --- a/bfd/opncls.c +++ b/bfd/opncls.c @@ -152,7 +152,6 @@ bfd_openr (filename, target) target_vec = bfd_find_target (target, nbfd); if (target_vec == NULL) { - bfd_set_error (bfd_error_invalid_target); _bfd_delete_bfd (nbfd); return NULL; } @@ -220,7 +219,8 @@ bfd_fdopenr (filename, target, fd) #else fdflags = fcntl (fd, F_GETFL, NULL); #endif - if (fdflags == -1) return NULL; + if (fdflags == -1) + return NULL; nbfd = _bfd_new_bfd (); if (nbfd == NULL) @@ -229,7 +229,6 @@ bfd_fdopenr (filename, target, fd) target_vec = bfd_find_target (target, nbfd); if (target_vec == NULL) { - bfd_set_error (bfd_error_invalid_target); _bfd_delete_bfd (nbfd); return NULL; } @@ -308,7 +307,6 @@ bfd_openstreamr (filename, target, streamarg) target_vec = bfd_find_target (target, nbfd); if (target_vec == NULL) { - bfd_set_error (bfd_error_invalid_target); _bfd_delete_bfd (nbfd); return NULL; } @@ -354,8 +352,6 @@ bfd_openw (filename, target) bfd *nbfd; const bfd_target *target_vec; - bfd_set_error (bfd_error_system_call); - /* nbfd has to point to head of malloc'ed block so that bfd_close may reclaim it correctly. */ nbfd = _bfd_new_bfd (); diff --git a/bfd/po/SRC-POTFILES.in b/bfd/po/SRC-POTFILES.in index 086d8022d59..dce7d0d0982 100644 --- a/bfd/po/SRC-POTFILES.in +++ b/bfd/po/SRC-POTFILES.in @@ -67,6 +67,7 @@ cpu-d10v.c cpu-d30v.c cpu-dlx.c cpu-fr30.c +cpu-frv.c cpu-h8300.c cpu-h8500.c cpu-hppa.c @@ -127,6 +128,7 @@ elf32-d10v.c elf32-d30v.c elf32-dlx.c elf32-fr30.c +elf32-frv.c elf32-gen.c elf32-h8300.c elf32-hppa.c diff --git a/bfd/reloc.c b/bfd/reloc.c index 8af90fc796a..8d5ee15d81c 100644 --- a/bfd/reloc.c +++ b/bfd/reloc.c @@ -2079,6 +2079,27 @@ ENUMX ENUMX BFD_RELOC_MIPS_JALR COMMENT +ENUM + BFD_RELOC_FRV_LABEL16 +ENUMX + BFD_RELOC_FRV_LABEL24 +ENUMX + BFD_RELOC_FRV_LO16 +ENUMX + BFD_RELOC_FRV_HI16 +ENUMX + BFD_RELOC_FRV_GPREL12 +ENUMX + BFD_RELOC_FRV_GPRELU12 +ENUMX + BFD_RELOC_FRV_GPREL32 +ENUMX + BFD_RELOC_FRV_GPRELHI +ENUMX + BFD_RELOC_FRV_GPRELLO +ENUMDOC + Fujitsu Frv Relocations. +COMMENT COMMENT ENUMDOC MIPS ELF relocations. diff --git a/bfd/targets.c b/bfd/targets.c index 7c6f4f3c94a..49fd7d0cc68 100644 --- a/bfd/targets.c +++ b/bfd/targets.c @@ -481,6 +481,7 @@ to find an alternative output format that is suitable. we can't intermix extern's and initializers. */ extern const bfd_target a29kcoff_big_vec; extern const bfd_target a_out_adobe_vec; +extern const bfd_target aix5coff64_vec; extern const bfd_target aout0_big_vec; extern const bfd_target aout_arm_big_vec; extern const bfd_target aout_arm_little_vec; @@ -513,6 +514,7 @@ extern const bfd_target bfd_elf32_d10v_vec; extern const bfd_target bfd_elf32_d30v_vec; extern const bfd_target bfd_elf32_dlx_big_vec; extern const bfd_target bfd_elf32_fr30_vec; +extern const bfd_target bfd_elf32_frv_vec; extern const bfd_target bfd_elf32_h8300_vec; extern const bfd_target bfd_elf32_hppa_linux_vec; extern const bfd_target bfd_elf32_hppa_vec; @@ -545,6 +547,10 @@ extern const bfd_target bfd_elf32_pjl_vec; extern const bfd_target bfd_elf32_powerpc_vec; extern const bfd_target bfd_elf32_powerpcle_vec; extern const bfd_target bfd_elf32_s390_vec; +extern const bfd_target bfd_elf32_sh64_vec; +extern const bfd_target bfd_elf32_sh64l_vec; +extern const bfd_target bfd_elf32_sh64lnbsd_vec; +extern const bfd_target bfd_elf32_sh64nbsd_vec; extern const bfd_target bfd_elf32_sh_vec; extern const bfd_target bfd_elf32_shblin_vec; extern const bfd_target bfd_elf32_shl_vec; @@ -574,6 +580,10 @@ extern const bfd_target bfd_elf64_mmix_vec; extern const bfd_target bfd_elf64_powerpc_vec; extern const bfd_target bfd_elf64_powerpcle_vec; extern const bfd_target bfd_elf64_s390_vec; +extern const bfd_target bfd_elf64_sh64_vec; +extern const bfd_target bfd_elf64_sh64l_vec; +extern const bfd_target bfd_elf64_sh64lnbsd_vec; +extern const bfd_target bfd_elf64_sh64nbsd_vec; extern const bfd_target bfd_elf64_sparc_vec; extern const bfd_target bfd_elf64_tradbigmips_vec; extern const bfd_target bfd_elf64_tradlittlemips_vec; @@ -646,7 +656,6 @@ extern const bfd_target ppcboot_vec; extern const bfd_target riscix_vec; extern const bfd_target rs6000coff64_vec; extern const bfd_target rs6000coff_vec; -extern const bfd_target aix5coff64_vec; extern const bfd_target shcoff_small_vec; extern const bfd_target shcoff_vec; extern const bfd_target shlcoff_small_vec; @@ -699,15 +708,6 @@ extern const bfd_target ptrace_core_vec; extern const bfd_target sco5_core_vec; extern const bfd_target trad_core_vec; -extern const bfd_target bfd_elf32_sh64_vec; -extern const bfd_target bfd_elf32_sh64l_vec; -extern const bfd_target bfd_elf64_sh64_vec; -extern const bfd_target bfd_elf64_sh64l_vec; - -extern const bfd_target bfd_elf32_sh64nbsd_vec; -extern const bfd_target bfd_elf32_sh64lnbsd_vec; -extern const bfd_target bfd_elf64_sh64nbsd_vec; -extern const bfd_target bfd_elf64_sh64lnbsd_vec; static const bfd_target * const _bfd_target_vector[] = { #ifdef SELECT_VECS @@ -727,6 +727,7 @@ static const bfd_target * const _bfd_target_vector[] = { it wasn't omitted by mistake. */ &a29kcoff_big_vec, &a_out_adobe_vec, + &aix5coff64_vec, &aout0_big_vec, #if 0 /* We have no way of distinguishing these from other a.out variants */ @@ -772,6 +773,7 @@ static const bfd_target * const _bfd_target_vector[] = { &bfd_elf32_d30v_vec, &bfd_elf32_dlx_big_vec, &bfd_elf32_fr30_vec, + &bfd_elf32_frv_vec, &bfd_elf32_h8300_vec, &bfd_elf32_hppa_linux_vec, &bfd_elf32_hppa_vec, @@ -812,6 +814,12 @@ static const bfd_target * const _bfd_target_vector[] = { &bfd_elf32_shlin_vec, &bfd_elf32_shlnbsd_vec, &bfd_elf32_shnbsd_vec, +#ifdef BFD64 + &bfd_elf32_sh64_vec, + &bfd_elf32_sh64l_vec, + &bfd_elf32_sh64lnbsd_vec, + &bfd_elf32_sh64nbsd_vec, +#endif &bfd_elf32_sparc_vec, &bfd_elf32_tradbigmips_vec, &bfd_elf32_tradlittlemips_vec, @@ -836,6 +844,10 @@ static const bfd_target * const _bfd_target_vector[] = { &bfd_elf64_powerpc_vec, &bfd_elf64_powerpcle_vec, &bfd_elf64_s390_vec, + &bfd_elf64_sh64_vec, + &bfd_elf64_sh64l_vec, + &bfd_elf64_sh64lnbsd_vec, + &bfd_elf64_sh64nbsd_vec, #if 0 &bfd_elf64_sparc_vec, #endif diff --git a/bfd/version.h b/bfd/version.h index e1448566304..c32ee045219 100644 --- a/bfd/version.h +++ b/bfd/version.h @@ -1 +1 @@ -#define BFD_VERSION_DATE 20020615 +#define BFD_VERSION_DATE 20020620 diff --git a/config.sub b/config.sub index 4693ac17f95..69f444e7902 100755 --- a/config.sub +++ b/config.sub @@ -231,7 +231,7 @@ case $basic_machine in | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr \ | c4x | clipper \ | d10v | d30v | dlx | dsp16xx \ - | fr30 \ + | fr30 | frv \ | h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \ | i370 | i860 | i960 | ia64 \ | m32r | m68000 | m68k | m88k | mcore \ @@ -288,7 +288,7 @@ case $basic_machine in | clipper-* | cydra-* \ | d10v-* | d30v-* | dlx-* \ | elxsi-* \ - | f30[01]-* | f700-* | fr30-* | fx80-* \ + | f30[01]-* | f700-* | fr30-* | frv-* | fx80-* \ | h8300-* | h8500-* \ | hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \ | i*86-* | i860-* | i960-* | ia64-* \ diff --git a/configure.in b/configure.in index 5962337875f..80b72e8c5e1 100644 --- a/configure.in +++ b/configure.in @@ -45,8 +45,6 @@ host_libs="intl mmalloc libiberty opcodes bfd readline db tcl tk tclX itcl tix libgui zlib" libstdcxx_version="target-libstdc++-v3" -# Don't use libstdc++-v3's flags to configure/build itself. -libstdcxx_flags='`case $$dir in libstdc++-v3 | libjava) ;; *) test ! -f $$r/$(TARGET_SUBDIR)/libstdc++-v3/testsuite_flags || $(SHELL) $$r/$(TARGET_SUBDIR)/libstdc++-v3/testsuite_flags --build-includes;; esac` -L$$r/$(TARGET_SUBDIR)/libstdc++-v3/src -L$$r/$(TARGET_SUBDIR)/libstdc++-v3/src/.libs' # these tools are built for the host environment # Note, the powerpc-eabi build depends on sim occurring before gdb in order to @@ -66,7 +64,6 @@ libgcj="target-libffi \ target_libs="target-libiberty \ target-libgloss \ target-newlib \ - target-librx \ ${libstdcxx_version} \ target-libf2c \ ${libgcj} @@ -118,6 +115,18 @@ appdirs="" # per-host: +# There is no longer anything interesting in the per-host section. + +# per-target: + +# Define is_cross_compiler to save on calls to 'test'. +is_cross_compiler= +if test x"${host}" = x"${target}" ; then + is_cross_compiler=no +else + is_cross_compiler=yes +fi + # Work in distributions that contain no compiler tools, like Autoconf. tentative_cc="" if test -d ${srcdir}/config ; then @@ -351,8 +360,6 @@ if test -n "${host_makefile_frag}" ; then host_makefile_frag=mh-frag fi -# per-target: - case "${target}" in v810*) target_makefile_frag="${target_makefile_frag} config/mt-v810" @@ -402,7 +409,6 @@ case "${enable_target_optspace}:${target}" in esac skipdirs= -gasdir=gas use_gnu_ld= use_gnu_as= @@ -425,19 +431,10 @@ esac # toolchains, we add some directories that should only be useful in a # cross-compiler. -is_cross_compiler= - -if test x"${host}" = x"${target}" ; then - # when doing a native toolchain, don't build the targets - # that are in the 'cross only' list - skipdirs="${skipdirs} ${cross_only}" - is_cross_compiler=no -else - # similarly, don't build the targets in the 'native only' - # list when building a cross compiler - skipdirs="${skipdirs} ${native_only}" - is_cross_compiler=yes -fi +case $is_cross_compiler in + no) skipdirs="${skipdirs} ${cross_only}" ;; + yes) skipdirs="${skipdirs} ${native_only}" ;; +esac # We always want to use the same name for this directory, so that dejagnu # can reliably find it. @@ -497,33 +494,6 @@ if test x"${with_libs}" != x ; then done fi -# If both --with-headers and --with-libs are specified, default to -# --without-newlib. -if test x"${with_headers}" != x && test x"${with_libs}" != x ; then - if test x"${with_newlib}" = x ; then - with_newlib=no - fi -fi - -# Recognize --with-newlib/--without-newlib. -if test x${with_newlib} = xno ; then - skipdirs="${skipdirs} target-newlib" -elif test x${with_newlib} = xyes ; then - skipdirs=`echo " ${skipdirs} " | sed -e 's/ target-newlib / /'` -fi - -# Default to using --with-stabs for certain targets. -if test x${with_stabs} = x ; then - case "${target}" in - mips*-*-irix6*) - ;; - mips*-*-* | alpha*-*-osf*) - with_stabs=yes; - withoptions="${withoptions} --with-stabs" - ;; - esac -fi - # Handle ${copy_dirs} set fnord ${copy_dirs} shift @@ -555,6 +525,32 @@ while test $# != 0 ; do shift; shift done +# If both --with-headers and --with-libs are specified, default to +# --without-newlib. +if test x"${with_headers}" != x && test x"${with_libs}" != x ; then + if test x"${with_newlib}" = x ; then + with_newlib=no + fi +fi + +# Recognize --with-newlib/--without-newlib. +case ${with_newlib} in + no) skipdirs="${skipdirs} target-newlib" ;; + yes) skipdirs=`echo " ${skipdirs} " | sed -e 's/ target-newlib / /'` ;; +esac + +# Default to using --with-stabs for certain targets. +if test x${with_stabs} = x ; then + case "${target}" in + mips*-*-irix6*) + ;; + mips*-*-* | alpha*-*-osf*) + with_stabs=yes; + withoptions="${withoptions} --with-stabs" + ;; + esac +fi + # Configure extra directories which are host specific case "${host}" in @@ -639,7 +635,7 @@ case "${target}" in esac ;; *-*-netware) - noconfigdirs="$noconfigdirs ${libstdcxx_version} target-librx target-newlib target-libiberty target-libgloss ${libgcj}" + noconfigdirs="$noconfigdirs ${libstdcxx_version} target-newlib target-libiberty target-libgloss ${libgcj}" ;; *-*-rtems*) noconfigdirs="$noconfigdirs target-libgloss ${libgcj}" @@ -665,8 +661,6 @@ case "${target}" in alpha*-*-linux*) # newlib is not 64 bit ready noconfigdirs="$noconfigdirs target-newlib target-libgloss" - # linux has rx in libc - skipdirs="$skipdirs target-librx" ;; alpha*-*-freebsd*) noconfigdirs="$noconfigdirs target-newlib target-libgloss" @@ -677,8 +671,6 @@ case "${target}" in ;; sh-*-linux*) noconfigdirs="$noconfigdirs ${libgcj} target-newlib target-libgloss" - # linux has rx in libc - skipdirs="$skipdirs target-librx" ;; sh*-*-pe|mips*-*-pe|*arm-wince-pe) noconfigdirs="$noconfigdirs ${libgcj}" @@ -735,7 +727,7 @@ case "${target}" in noconfigdirs="$noconfigdirs target-libiberty ${libstdcxx_version} ${libgcj}" ;; c4x-*-*) - noconfigdirs="$noconfigdirs ${libstdcxx_version} target-librx target-libgloss ${libgcj}" + noconfigdirs="$noconfigdirs ${libstdcxx_version} target-libgloss ${libgcj}" ;; c54x*-*-* | tic54x-*-*) noconfigdirs="$noconfigdirs ${libstdcxx_version} target-libgloss ${libgcj} gcc gdb newlib" @@ -744,7 +736,7 @@ case "${target}" in noconfigdirs="$noconfigdirs ${libgcj}" ;; d10v-*-*) - noconfigdirs="$noconfigdirs target-librx ${libstdcxx_version} target-libgloss ${libgcj}" + noconfigdirs="$noconfigdirs ${libstdcxx_version} target-libgloss ${libgcj}" ;; d30v-*-*) noconfigdirs="$noconfigdirs ${libgcj}" @@ -755,11 +747,17 @@ case "${target}" in target_configdirs="${target_configdirs} target-bsp target-libstub target-cygmon" fi ;; + frv-*-*) + noconfigdirs="$noconfigdirs ${libgcj}" + if test x${is_cross_compiler} != xno ; then + target_configdirs="${target_configdirs} target-bsp target-cygmon" + fi + ;; h8300*-*-*) noconfigdirs="$noconfigdirs target-libgloss" ;; h8500-*-*) - noconfigdirs="$noconfigdirs ${libstdcxx_version} target-librx target-libgloss ${libgcj} target-libf2c" + noconfigdirs="$noconfigdirs ${libstdcxx_version} target-libgloss ${libgcj} target-libf2c" ;; hppa*64*-*-linux* | parisc*64*-*-linux*) # In this case, it's because the hppa64-linux target is for @@ -799,8 +797,6 @@ case "${target}" in s390*-*-linux*) # The libffi port is not yet in the GCC tree noconfigdirs="$noconfigdirs target-newlib target-libgloss ${libgcj}" - # linux has rx in libc - skipdirs="$skipdirs target-librx" ;; i[3456]86-*-linux*) # This section makes it possible to build newlib natively on linux. @@ -813,13 +809,9 @@ case "${target}" in # Note however, that newlib will only be configured in this situation # if the --with-newlib option has been given, because otherwise # 'target-newlib' will appear in skipdirs. - # linux has rx in libc - skipdirs="$skipdirs target-librx" ;; *-*-linux*) noconfigdirs="$noconfigdirs target-newlib target-libgloss" - # linux has rx in libc - skipdirs="$skipdirs target-librx" ;; i[3456]86-*-mingw32*) target_configdirs="$target_configdirs target-mingw" @@ -846,7 +838,7 @@ case "${target}" in esac ;; i[3456]86-*-pe) - noconfigdirs="$noconfigdirs ${libstdcxx_version} target-librx target-libgloss ${libgcj}" + noconfigdirs="$noconfigdirs ${libstdcxx_version} target-libgloss ${libgcj}" ;; i[3456]86-*-sco3.2v5*) # The linker does not yet know about weak symbols in COFF, @@ -1277,7 +1269,7 @@ fi # --without-gnu-ld options for the configure script. if test x${use_gnu_as} = x ; then - if test x${with_gnu_as} != xno && echo " ${configdirs} " | grep " ${gasdir} " > /dev/null 2>&1 && test -d ${srcdir}/${gasdir} ; then + if test x${with_gnu_as} != xno && echo " ${configdirs} " | grep " gas " > /dev/null 2>&1 && test -d ${srcdir}/gas ; then with_gnu_as=yes withoptions="$withoptions --with-gnu-as" fi @@ -1454,7 +1446,7 @@ if test x${gxx_include_dir} = x; then if test x${enable_version_specific_runtime_libs} = xyes; then gxx_include_dir='${libsubdir}/include/g++' else - . ${topsrcdir}/config.if + . ${srcdir}/config.if gxx_include_dir='${prefix}/include/${libstdcxx_incdir}' fi else @@ -1475,7 +1467,7 @@ case " $skipdirs " in esac # If we're not building GCC, don't discard standard headers. - if test -d ${topsrcdir}/gcc; then + if test -d ${srcdir}/gcc; then FLAGS_FOR_TARGET=$FLAGS_FOR_TARGET' -nostdinc' if test "${build}" != "${host}"; then @@ -1521,7 +1513,7 @@ esac # the previously-installed cross compiler, so don't bother to add # flags for directories within the install tree of the compiler # being built; programs in there won't even run. -if test "${build}" = "${host}" && test -d ${topsrcdir}/gcc; then +if test "${build}" = "${host}" && test -d ${srcdir}/gcc; then # Search for pre-installed headers if nothing else fits. FLAGS_FOR_TARGET=$FLAGS_FOR_TARGET' -B$(build_tooldir)/bin/ -B$(build_tooldir)/lib/ -isystem $(build_tooldir)/include' fi @@ -1535,7 +1527,7 @@ fi if test "x${CC_FOR_TARGET+set}" = xset; then : -elif test -d ${topsrcdir}/gcc; then +elif test -d ${srcdir}/gcc; then CC_FOR_TARGET='$$r/gcc/xgcc -B$$r/gcc/' elif test "$host" = "$target"; then CC_FOR_TARGET='$(CC)' @@ -1551,7 +1543,7 @@ esac if test "x${GCJ_FOR_TARGET+set}" = xset; then : -elif test -d ${topsrcdir}/gcc; then +elif test -d ${srcdir}/gcc; then GCJ_FOR_TARGET='$$r/gcc/gcj -B$$r/gcc/' elif test "$host" = "$target"; then GCJ_FOR_TARGET='gcj' @@ -1563,9 +1555,12 @@ case $GCJ_FOR_TARGET in *) GCJ_FOR_TARGET=$GCJ_FOR_TARGET' $(FLAGS_FOR_TARGET)' ;; esac +# Don't use libstdc++-v3's flags to configure/build itself. +libstdcxx_flags='`case $$dir in libstdc++-v3 | libjava) ;; *) test ! -f $$r/$(TARGET_SUBDIR)/libstdc++-v3/testsuite_flags || $(SHELL) $$r/$(TARGET_SUBDIR)/libstdc++-v3/testsuite_flags --build-includes;; esac` -L$$r/$(TARGET_SUBDIR)/libstdc++-v3/src -L$$r/$(TARGET_SUBDIR)/libstdc++-v3/src/.libs' + if test "x${CXX_FOR_TARGET+set}" = xset; then : -elif test -d ${topsrcdir}/gcc; then +elif test -d ${srcdir}/gcc; then # We add -shared-libgcc to CXX_FOR_TARGET whenever we use xgcc instead # of g++ for linking C++ or Java, because g++ has -shared-libgcc by # default whereas gcc does not. diff --git a/gdb/ChangeLog b/gdb/ChangeLog index 0dbe0a5f740..d8233fe928c 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1770,6 +1770,1895 @@ Fri May 17 14:26:19 2002 J"orn Rennecke <joern.rennecke@superh.com> * gdbserver/server.c (gdbserver_usage): New function. (main): Call it. +2002-06-19 Andrew Cagney <cagney@redhat.com> + + * regcache.h: Update copyright. + (struct regcache, struct gdbarch): Add opaque declarations. + (current_regcache): Declare global variable. + (regcache_read, regcache_write): Add gdbarch parameter. + (regcache_save, regcache_save_no_passthrough) + (regcache_restore, regcache_restore_no_passthrough) + (regcache_dup, regcache_dup_no_passthrough) + (regcache_cpy, regcache_cpy_no_passthrough) + (deprecated_grub_regcache_for_registers) + (deprecated_grub_regcache_for_register_valid) + (regcache_valid_p): Add function declarations. + + * regcache.c: Update copyright. + (regcache_descr_handle): New global variable. + (struct regcache_descr): Define. + (init_legacy_regcache_descr, init_regcache_descr): New functions. + (regcache_descr, xfree_regcache_descr): New functions. + (struct regcache): Define. + (regcache_xmalloc, regcache_xfree): New functions. + (regcache_cpy, regcache_cpy_no_passthrough): New functions. + (regcache_dup, regcache_dup_no_passthrough): New functions. + (regcache_valid_p, regcache_read_as_address): New functions. + (deprecated_grub_regcache_for_registers): New function. + (deprecated_grub_regcache_for_register_valid): New function. + (current_regcache): New global variable. + (register_buffer): Add regcache parameter. Update calls. + (regcache_read, regcache_write): Add regcache parameter. Rewrite. + (read_register_gen, write_register_gen): Update register_buffer + call. Test for legacy_p instead of gdbarch_register_read_p or + gdbarch_register_write_p. + (regcache_collect): Update register_buffer call. + (build_regcache): Rewrite. Use deprecated grub functions. + (regcache_save, regcache_save_no_passthrough): New functions. + (regcache_restore, regcache_restore_no_passthrough): New + functions. + (_initialize_regcache): Create the regcache_data_handle. Swap + current_regcache global variable. + + * sh-tdep.c (sh_pseudo_register_read): Add current_regcache + parameter to regcache_read and regcache_write calls. + (sh4_register_read): Ditto. + (sh64_pseudo_register_read): Ditto. + (sh64_register_read): Ditto. + (sh_pseudo_register_write): Ditto. + (sh4_register_write): Ditto. + (sh64_pseudo_register_write): Ditto. + (sh64_register_write): Ditto. + + * defs.h (XCALLOC): Define. + +2002-06-19 Grace Sainsbury <graces@redhat.com> + + * config/m68k/tm-m68k.h (GDB_MULTI_ARCH): Added (set to 0). + * m68k-tdep.c (m68k_gdbarch_init): Added. + (m68k_dump_tdep): Added. + +2002-06-19 Daniel Jacobowitz <drow@mvista.com> + + * ada-lang.c (fill_in_ada_prototype): Update comment. + +2002-06-19 Daniel Jacobowitz <drow@mvista.com> + + * mips-tdep.c (enum mips_abi): Explicitly start at 0. Add + MIPS_ABI_LAST. + (mips_abi_string, mips_abi_strings): New. + (struct gdbarch_tdep): Remove mips_abi_string, add found_abi. + (mips_gdbarch_init): Set tdep->found_abi. Don't set + tdep->mips_abi_string. Honor mips_abi_string. Default to + O32 if no ABI is found. + (mips_dump_tdep): Use mips_abi_strings. + (mips_abi_update): New function. + (_initialize_mips_tdep): Initialize mips_abi_string. Add + ``set mips abi'' and ``show mips abi''. Check the size of + mips_abi_strings. + +2002-06-19 Andrew Cagney <cagney@redhat.com> + + * i386-linux-tdep.c (i386_linux_register_name): Make return type + constant. + +2002-06-18 Joel Brobecker <brobecker@gnat.com> + + * alpha-tdep.c (heuristic_proc_desc): Compute the size of the + current frame using only the first stack size adjustment. All + subsequent size adjustments are not considered to be part of + the "static" part of the current frame. + Compute the address of the saved registers relative to the + Frame Pointer ($fp) instead of the Stack Pointer if $fp is + in use in this frame. + +2002-06-18 Don Howard <dhoward@redhat.com> + + * valops.c (value_ind): Use value_at_lazy() when dereferencing + type int expressions. Thanks to Jim Blandy <jimb@redhat.com> for + suggesting this solution. + +2002-06-18 Andrew Cagney <ac131313@redhat.com> + + * config/romp/xm-rtbsd.h: Delete file. + * config/romp/rtbsd.mh: Delete file. + +2002-06-18 Keith Seitz <keiths@redhat.com> + + * breakpoint.c (condition_command): Post breakpoint_modify + when a condition is added to an existing breakpoint. + (commands_command): Likewise for commands. + (set_ignore_count): Likewise for ignore counts. + If no tty, do not simply return, still need to send event + notification. + (ignore_command): Only print a newline if the command came + from a tty. + Don't call breakpoints_changed, since this is now properly + handled by set_ignore_count. + +2002-06-18 Andrew Cagney <cagney@redhat.com> + + * MAINTAINERS: Note that cris-elf target can be compiled with + -Werror. + * cris-tdep.c (cris_register_name): Make return type constant. + (cris_breakpoint_from_pc): Ditto. + +2002-06-18 Michal Ludvig <mludvig@suse.cz> + + * frame.h (struct frame_info): Change type of context to + 'struct context'. + +2002-06-17 Andrew Cagney <cagney@redhat.com> + + * gdbarch.sh (REGISTER_NAME): Change return type a constant string + pointer. + * gdbarch.h, gdbarch.c: Regenerate. + * config/mips/tm-mips.h (mips_register_name): Update. + * i386-tdep.h (i386_register_name): Update. + * mips-tdep.c (mips_register_name): Update + * alpha-tdep.c (alpha_register_name): Update. + * arch-utils.c (legacy_register_name): Update. + * arch-utils.h (legacy_register_name): Update. + * avr-tdep.c (avr_register_name): Update. + * ia64-tdep.c (ia64_register_name): Update. + * i386-tdep.c (i386_register_name): Update. + * sparc-tdep.c (sparc32_register_name): Update. + (sparc64_register_name): Update. + (sparclite_register_name): Update. + (sparclet_register_name): Update. + * sh-tdep.c (sh_generic_register_name): Update. + (sh_sh_register_name): Update. + (sh_sh3_register_name): Update. + (sh_sh3e_register_name): Update. + (sh_sh_dsp_register_name): Update. + (sh_sh3_dsp_register_name): Update. + (sh_sh4_register_name): Update. + (sh_sh64_register_name): Update. + * s390-tdep.c (s390_register_name): Update. + * rs6000-tdep.c (rs6000_register_name): Update. + * ns32k-tdep.c (ns32k_register_name_32082): Update. + (ns32k_register_name_32382): Update. + * d10v-tdep.c (d10v_ts2_register_name): Update. + (d10v_ts3_register_name): Update. + * xstormy16-tdep.c (xstormy16_register_name): Update. + * vax-tdep.c (vax_register_name): Update. + * v850-tdep.c (v850_register_name): Update. + * m68hc11-tdep.c (m68hc11_register_name): Update. + * mn10300-tdep.c (mn10300_generic_register_name): Update. + (am33_register_name): Update. + +2002-06-17 Grace Sainsbury <graces@redhat.com> + + * m68k-tdep.c: Reindented. + +2002-06-17 Andrew Cagney <ac131313@redhat.com> + + * gdb_indent.sh: Add prgregset_t, fpregset_t, and gregset_t to the + list of predefined types. + +2002-06-16 Mark Kettenis <kettenis@gnu.org> + + * config/i386/tm-i386.h (REGISTER_VIRTUAL_TYPE, + REGISTER_CONVERTIBLE, REGISTER_CONVERT_TO_VIRTUAL, + REGISTER_CONVERT_TO_RAW): Remove defines. + (i386_register_virtual_type, i386_register_convertible, + i386_register_convert_to_virtual, i386_register_convert_to_raw): + Remove prototypes. + * i386-tdep.c (i386_gdbarch_init): Adjust for removal of the + macros mentioned above. + + * config/i386/tm-i386lynx.h (SAVED_PC_AFTER_CALL): Remove define. + (i386lynx_saved_pc_after_call): Remove prototype. + * i386ly-tdep.c: Include "i386-tdep.h". + (i386lynx_saved_pc_after_call): Make static. Use + read_memory_nobpt instead of read_memory. Use + read_memory_unsigned_integer instead of read_memory_integer. + (i386lynx_init_abi): New function. + (i386lynx_coff_osabi_sniffer): New function. + (_initialize_i386bsd_tdep): New function. + + * config/i386/tm-i386.h (PARM_BOUNDARY, CALL_DUMMY, + CALL_DUMMY_LENGTH, CALL_DUMMY_START_OFFSET, + CALL_DUMMY_BREAKPOINT_OFFSET, FIX_CALL_DUMMY): Remove defines. + (i386_fix_call_dummy): Remove prototype. + * i386-tdep.c (i386_call_dummy_words): New variable. + (i386_gdbarch_init): Adjust for removal of the + macros mentioned above. + +2002-06-15 Andrew Cagney <ac131313@redhat.com> + + * command.h (add_setshow_auto_boolean_cmd): Replace + add_set_auto_boolean_cmd. + * cli/cli-decode.c (add_setshow_auto_boolean_cmd): Replace + add_set_auto_boolean_cmd. + * cli/cli-decode.h (add_set_auto_boolean_cmd): Delete declaration. + * mips-tdep.c (_initialize_mips_tdep): Update ``set mips + mask-address'' command. + (show_mask_address): Add cmd parameter. + * remote.c (add_packet_config_cmd): Update. Change type of + set_func and show_func to cmd_sfunc_ftype. + (_initialize_remote): Update `set remote Z-packet' + (show_remote_protocol_qSymbol_packet_cmd): Add cmd parameter. + (show_remote_protocol_e_packet_cmd): Ditto. + (show_remote_protocol_E_packet_cmd): Ditto. + (show_remote_protocol_P_packet_cmd): Ditto. + (show_remote_protocol_Z_software_bp_packet_cmd): Ditto. + (show_remote_protocol_Z_hardware_bp_packet_cmd): Ditto. + (show_remote_protocol_Z_write_wp_packet_cmd): Ditto. + (show_remote_protocol_Z_read_wp_packet_cmd): Ditto. + (show_remote_protocol_Z_access_wp_packet_cmd): Ditto. + (show_remote_protocol_Z_packet_cmd): Ditto. + (show_remote_protocol_binary_download_cmd): Ditto. + (show_remote_cmd): Pass NULL to all of above. + +2002-06-15 Mark Kettenis <kettenis@gnu.org> + + * config/i386/tm-i386.h (PUSH_ARGUMENTS, STORE_STRUCT_RETURN, + DEPRECATED_EXTRACT_RETURN_VALUE, STORE_RETURN_VALUE, + DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS, PUSH_DUMMY_FRAME, + POP_FRAME): Remove defines. + (i386_push_arguments, i386_store_struct_return, + i386_extract_return_value, i386_store_return_value, + i386_extract_struct_value_address, i386_push_dummy_frame, + i386_pop_frame): Renove prototypes. + * i386-tdep.c (i386_gdbarch_init): Adjust for removal of the + macros mentioned above. + +2002-06-15 Andrew Cagney <ac131313@redhat.com> + + * cli/cli-decode.c (add_setshow_boolean_cmd): Replace + add_set_boolean_cmd. + (add_setshow_cmd): New function. + * command.h (add_setshow_boolean_cmd): Replace + add_set_boolean_cmd. + * remote-rdi.c (_initialize_remote_rdi): Update ``set rdiheartbeat'' + and ``set rdiromatzero''. + * maint.c (_initialize_maint_cmds): Update commented out code. + * cli/cli-decode.h (add_set_boolean_cmd): Delete declaration. + * target.c (initialize_targets): Update `set + trust-readonly-sections'. + * remote.c (_initialize_remote): Update `set remotebreak'. + +2002-06-15 Mark Kettenis <kettenis@gnu.org> + + * config/i386/tm-i386.h (FUNCTION_START_OFFSET, INNER_THAN, + BREAKPOINT, DECR_PC_AFTER_BREAK): Removed. + * i386-tdep.c (i386_skip_prologue): Adjust function signature to + fit into multi-arch framework. + (i386_breakpoint_from_pc): New function. + (i386_gdbarch_init): Adjust for removal of the macros mentioned + above. + + * config/i386/tm-i386.h (FRAMELESS_FUNCTION_INVOCATION, + FRAME_ARGS_ADDRESS, FRAME_LOCALS_ADDRESS, FRAME_NUM_ARGS, + FRAME_ARGS_SKIP, FRAME_INIT_SAVED_REGS): Remove defines. + (i386_frameless_function_invocation, i386_frame_num_args, + i386_frame_init_saved_regs): Remove prototypes. + * i386-tdep.c (i386_gdbarch_init): Adjust for removal of the + macros mentioned above. + +2002-06-15 Andrew Cagney <ac131313@redhat.com> + + * cli/cli-decode.c (set_cmd_cfunc): Update. + (set_cmd_sfunc): Update. + * command.h (cmd_cfunc_ftype, cmd_sfunc_ftype): Declare. + (set_cmd_sfunc, set_cmd_cfunc): Update. + * cli/cli-decode.h: Update. + +2002-06-15 Mark Kettenis <kettenis@gnu.org> + + * i386-sol2-tdep.c (i386_sol2_osabi_sniffer): New function. + (_initialize_i386_sol2_tdep): Register i386_sol2_osabi_sniffer. + +2002-06-15 Andrew Cagney <ac131313@redhat.com> + + * defs.h (auto_boolean): Declare enum. + * command.h (cmd_auto_boolean): Delete enum. + * mips-tdep.c (mask_address_var): Update. + (mips_mask_address_p): Update. + (show_mask_address): Update. + * remote.c (struct packet_config): Update. + (update_packet_config): Update. + (show_packet_config_cmd): Update. + (packet_ok): Update. + (add_packet_config_cmd): Update. + (_initialize_remote): + * command.h: Update. + * cli/cli-setshow.c (parse_auto_binary_operation): Update. + (do_setshow_command): Update. + * cli/cli-decode.c (add_set_auto_boolean_cmd): Update. + * cli/cli-decode.h: Update. + +2002-06-15 Mark Kettenis <kettenis@gnu.org> + + * config/i386/tm-cygwin.h, config/i386/tm-fbsd.h, + config/i386/tm-go32.h, config/i386/tm-i386gnu.h, + config/i386/tm-i386sol2.h, config/i386/tm-i386v4.h, + config/i386/tm-linux.h, config/i386/tm-nbsd.h, + config/i386/tm-obsd.h (HAVE_I387_REGS): Remove define. + * config/i386/tm-i386.h: Unconditionally define FLOAT_INFO. + + * i386-tdep.c (i386_coff_osabi_sniffer): Add "coff-go32" to the + list of DJGPP COFF targets. + + * config/i386/tm-i386.h (REGISTER_SIZE): Remove define. + (NUM_GREGS, NUM_FREGS, NUM_SSE_REGS): Remove defines. + (FP_REGNUM, SP_REGNUM, PC_REGNUM, PS_REGNUM): Remove defines. + (FP0_REGNUM): Remove define. + (MAX_REGISTER_RAW_SIZE, MAX_REGISTER_VIRTUAL_SIZE, + MAX_REGISTER_VIRTUAL_SIZE): Remove define. + (i386_register_virtual_size): Remove protoype. + * i386-tdep.c (i386_register_virtual_size): Removed. + (i386_extract_return_value, i386_store_return_value): Use + FP0_REGNUM instead of NUM_FREGS to determine whether the + floating-point registers are available. + (i386_gdbarch_init): Tweak FIXME about FPU registers. + Adjust for removal of macros mentioned above. + +2002-06-15 Mark Kettenis <kettenis@gnu.org> + + * i386v4-nat.c: Include "i386-tdep.h". Reformat and tweak various + comments. + (fill_gregset, supply_gregset, supply_fpregset, fill_fpregset): + Remove prototypes. + (supply_gregset, fill_gregset): Remove use of register keyword and + remove declaration for regmap. Use I386_NUM_GREGS instead of + NUM_REGS and NUM_FREGS. + (FPREGSET_FSAVE_OFFSET): Remove. + (supply_fpregset, fill_fpregset): Use FPO_REGNUM instead of + NUM_FREGS to determine whether the floating-point registers are + available. + + * i386gnu-nat.c (supply_gregset, gnu_fetch_registers, + gnu_store_registers): Replace usage of NUM_GREGS with + I386_NUM_GREGS. + + * i386-linux-nat.c (OLD_CANNOT_FETCH_REGISTER, + OLD_CANNOT_STORE_REGISTER, supply_gregset, fill_gregset): Replace + usage of NUM_GREGS with I386_NUM_GREGS. + + * i386-linux-nat.c (fill_gregset): Remove redundant parentheses. + + * i386bsd-nat.c: Include "i386-tdep.h". + (supply_gregset, fill_gregset): Replace usage of NUM_GREGS with + I386_NUM_GREGS. + + * i386v-nat.c: Remove copnditional inclusion of <asm/debugreg.h>, + and associated comment. They no longer make any sense, since we + don't use this file anymore on Linux. + + * config/i386/tm-i386.h (MAX_NUM_REGS): Removed. + * i386-tdep.c (i386_register_offset, i386_register_size): Use + I386_SSE_NUM_REGS instead of MAX_NUM_REGS for the number of + elements in these arrays. + (_initialize_i386_tdep): Use I386_SSE_NUM_REGS instead of + MAX_NUM_REGS. + +2002-06-15 Mark Kettenis <kettenis@gnu.org> + + * osabi.h (gdb_osabi): Add GDB_OSABI_LYNXOS. + * osabi.c (gdb_osabi_names): Add entry for "LynxOS". + +2002-06-14 Andrew Cagney <cagney@redhat.com> + + * gdbarch.sh (DEPRECATED_EXTRACT_RETURN_VALUE): Rename + EXTRACT_RETURN_VALUE. + (DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS): Rename + EXTRACT_STRUCT_VALUE_ADDRESS. + * gdbarch.h, gdbarch.c: Regenerate. + + * values.c (value_being_returned): Handle + DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS. + (EXTRACT_RETURN_VALUE): Define as DEPRECATED_EXTRACT_RETURN_VALUE. + + * arm-linux-tdep.c (arm_linux_init_abi): Update. + * arm-tdep.c (arm_gdbarch_init): Update. + * avr-tdep.c (avr_gdbarch_init): Update. + * cris-tdep.c (cris_gdbarch_init): Update. + * d10v-tdep.c (d10v_gdbarch_init): Update. + * ia64-tdep.c (ia64_gdbarch_init): Update. + * m68hc11-tdep.c (m68hc11_gdbarch_init): Update. + * rs6000-tdep.c (rs6000_gdbarch_init): Update. + * s390-tdep.c (s390_gdbarch_init): Update. + * sh-tdep.c (sh_gdbarch_init): Update. + * s390-tdep.c (s390_gdbarch_init): Update. + * sparc-tdep.c (sparc_gdbarch_init): Update. + * ns32k-tdep.c (ns32k_gdbarch_init): Update. + * v850-tdep.c (v850_gdbarch_init): Update. + * vax-tdep.c (vax_gdbarch_init): Update. + * x86-64-tdep.c (x86_64_gdbarch_init): Update. + * xstormy16-tdep.c (xstormy16_gdbarch_init): Update. + + * config/arc/tm-arc.h: Update. + * config/d30v/tm-d30v.h: Update. + * config/fr30/tm-fr30.h: Update. + * config/h8300/tm-h8300.h: Update. + * config/h8500/tm-h8500.h: Update. + * config/i386/tm-i386.h: Update. + * config/i386/tm-ptx.h: Update. + * config/i386/tm-symmetry.h: Update. + * config/i960/tm-i960.h: Update. + * config/m32r/tm-m32r.h: Update. + * config/m68k/tm-delta68.h: Update. + * config/m68k/tm-linux.h: Update. + * config/m68k/tm-m68k.h: Update. + * config/m88k/tm-m88k.h: Update. + * config/mcore/tm-mcore.h: Update. + * config/mips/tm-mips.h: Update. + * config/mn10200/tm-mn10200.h: Update. + * config/pa/tm-hppa.h: Update. + * config/pa/tm-hppa64.h: Update. + * config/sparc/tm-sp64.h: Update. + * config/sparc/tm-sparc.h: Update. + * config/sparc/tm-sparclet.h: Update. + * config/z8k/tm-z8k.h: Update. + +2002-06-14 Andrew Cagney <cagney@redhat.com> + + * Makefile.in (i386_linux_tdep_h): Define. + (i386_tdep_h, i387_tdep_h): Define. + (i386-linux-nat.o): Add $(i386_linux_tdep_h), + $(i386_tdep_h) and $(i387_tdep_h). + * i386-linux-nat.c: Include "i386-linux-tdep.h". + +2002-06-14 Mark Kettenis <kettenis@gnu.org> + + * config/i386/tm-i386.h (START_INFERIOR_TRAPS_EXPECTED): Removed. + Already covered by the default. + + * config/i386/tm-i386.h (TARGET_LONG_DOUBLE_FORMAT, + TARGET_LONG_DOUBLE_BIT): Remove. * i386-tdep.c + (i386_gdbarch_init): Initialize long_double_format and long_double + bit. + + * config/i386/i386sol2.mt (TDEPFILES): Add i386-sol2-tdep.o and + i386bsd-tdep.o. Remove solib.o, solib-svr4.o and solib-legacy.o. + Move these to ... + * config/i386/i386sol2.mh: ... here. + * config/i386/tm-i386sol2.h (STAB_REG_TO_REGNUM): Remove define. + (sigtramp_saved_pc, I386V4_SIGTRAMP_SAVED_PC): Don't #undef. + (SIGCONTEXT_PC_OFFSET): Remove define. + (IN_SIGTRAMP): Remove define. + * i386-sol2-tdep.c: New file. + + * config/i386/i386nw.mt (TM_FILE): Change to tm-i386.h. + * config/i386/tm-i386nw.h: Removed. + + * config/i386/tm-fbsd.h (STAB_REG_TO_REGNUM, + USE_STRUCT_CONVENTION): Remove defines. + (JB_ELEMENT_SIZE, JB_PC, GET_LONGJMP_TARGET): Remove defines. + (get_longjmp_target): Remove prototype. + (IN_SIGTRAMP): Remove define. + (i386bsd_in_sigtramp): Remove prototype. + (i386bsd_sigtramp_start, i386bsd_sigtramp_end): Turn into a + function. Update comment accordingly + (SIGTRAMP_START, SIGTRAMP): Adjust definition accordingly. + (FRAME_SAVED_PC): Remove define. + (i386bsd_frame_saved_pc): Remove prototype. + * config/i386/tm-nbsd.h (JB_ELEMENT_SIZE, JB_PC, + GET_LONGJMP_TARGET): Remove defines. + (get_longjmp_target): Remove prototype. + (IN_SIGTRAMP): Remove define. + (i386bsd_in_sigtramp): Remove prototype. + (i386bsd_sigtramp_start, i386bsd_sigtramp_end): Turn into a + function. Update comment accordingly + (SIGTRAMP_START, SIGTRAMP): Adjust definition accordingly. + (FRAME_SAVED_PC): Remove define. + (i386bsd_frame_saved_pc): Remove prototype. + * config/i386/tm-nbsdaout.h (i386nbsd_aout_use_struct_convention): + Remove prototype. + (USE_STRUCT_CONVENTION): Remove prototype. + * i386bsd-nat.c (i386bsd_sigcontext_pc_offset): Remove + declaration. + (_initialize_i386bsd_nat): Revise logic to determine some + constants at compile time when compiling a native GDB. Warn if + things don't match up with what we expect. + * i386bsd-tdep.c (i386bsd_sigtramp_start, i386bsd_sigtramp_end): + Remove variables. + (i386bsd_in_sigtramp): Rename tp i386bsd_pc_in_sigtramp. Rewrite + to use date stored in `struct gdbarch_tdep'. + (i386bsd_sigcontext_offset): Remove varaible. + (i386bsd_sigtramp_saved_pc): Make public. Rewrite to use data + stored in `struct gdbarch_tdep'. + (i386bsd_frame_saved_pc): Make static. + (i386bsd_sigtramp_start, i386bsd_sigtramp_end): New functions. + (i386bsd_sc_pc_offset, i386nbsd_sc_pc_offset, + i386fbsd_sigtramp_start, i386fbsd_sigtramp_end, + i386fbsd4_sc_pc_offset): New variables. + (i386bsd_init_abi, i386nbsd_init_abi, i386nbsdelf_init_abi, + i386fbsdaout_init_abi, i386fbsd_init_abi, i386fbsd4_init_abi): New + functions. + (i386bsd_aout_osabi_sniffer, _initialize_i386bsd_tdep): New + functions. + * i386fbsd-nat.c (_initialize_i386fbsd_nat): Fix type in comment. + Modify the value of i386fbsd_sigtramp_start and + i386fbsd_sigtramp_end instead of i386bsd_sigtramp_start and + i386fbsd_sigtramp_end. + * i386nbsd-tdep.c: (i386nbsd_aout_use_struct_convention): Remove + function. + + * config/i386/tm-linux.h (I386_LINUX_ORIG_EAX_REGNUM): Move + define to i386-linux-tdep.h. + (NUM_REGS, MAX_NUM_REGS, REGISTER_BYTES, REGISTER_NAME, + REGISTER_BYTE, REGISTER_RAW_SIZE, STAB_REG_TO_REGNUM): Remove + defines. + (i386_linux_register_name, i386_linux_register_byte, + i386_linux_register_raw_size): Remove prototypes. + (i386_linux_svr4_fetch_link_map_offsets): Remove prototype. + (SVR4_FETCH_LINK_MAP_OFFSETS): Remove define. + (IN_SIGTRAMP, FRAME_CHAIN, FRAME_SAVED_PC, SAVED_PC_AFTER_CALL, + TARGET_WRITE_PC): Remove defines. + (i386_linux_in_sigtramp, i386_linux_frame_chain, + i386_linux_frame_saved_pc, i386_linux_saved_pc_after_call, + i386_linux_write_pc): Remove prototypes. + (JB_ELEMENT_SIZE, JB_PC, GET_LONGJMP_TARGET): Remove defines. + (get_longjmp_target): Remove prototype. + * i386-linux-tdep.h: New file. + * i386-linux-nat.c: Include "i386-linux-tdep.h". + * i386-linux-tdep.c: Include "i386-tdep.h" and + "i386-linux-tdep.h". + (i386_linux_register_name, i386_linux_register_byte, + i386_linux_register_raw_size, i386_linux_in_sigtramp, + i386_linux_write_pc, i386_linux_svr4_fetch_link_map_offsets): + Make static. + (i386_linux_init_abi): New function. + (_initialize_i386_linux_tdep): New function. + + * config/i386/tm-i386.h (SAVED_PC_AFTER_CALL): Remove define. + (i386_saved_pc_after_call): Remove prototype. + (MAX_NUM_REGS): Increase to deal with Linux's orig_eax "register". + (REGISTER_NAME, STAB_REG_TO_REGNUM, SDB_REG_TO_REGNUM, + DWARF_REG_TO_REGNUM, DWARF2_REG_TO_REGNUM): Remove defines. + (i386_register_name, i386_stab_reg_to_regnum, + i386_dwarf_reg_to_regnum): Remove prototypes. + (SIZEOF_GREGS, SIZEOF_FPU_REGS, SIZEOF_FPU_CTL_REGS, + SIZEOF_SSE_REGS): Remove defines. + (REGISTER_BYTES): Remove define. + (REGISTER_BYTE, REGISTER_RAW_SIZE): Remove defines. + (i386_register_byte, i386_register_raw_size): Remove prototypes. + (FRAME_CHAIN, FRAME_SAVED_PC): Remove defines. + (i386_frame_chain, i386_frame_saved_pc): Remove prototypes. + * config/i386/tm-i386v4.h (FRAME_CHAIN_VALID): Remove define. + (JB_ELEMENT_SIZE, JB_PC, JB_EBX, JB_ESI, JB_EDI, JB_EBP, JB_ESP, + JB_EDX, GET_LONGJMP_TARGET): Remove defines. + (get_longjmp_target): Remove prototype. + (I386V4_SIGTRAMP_SAVED_PC, IN_SIGTRAMP): Remove defines. + (sigtramp_saved_pc): Remove define. + (i386v4_sigtramp_saved_pc): Remove prototype. + * config/i386/tm-go32.h (FRAME_CHAIN, + FRAMELESS_FUNCTION_INVOCATION, FRAME_SAVED_PC): Remove defines. + (i386go32_frame_saved_pc): Remove prototype. + (JB_ELEMENT_SIZE, JB_PC, GET_LONGJMP_TARGET): Remove defines. + (get_longjmp_target): Remove prototype. + * i386-tdep.h: Include "osabi.h". + (enum i386_abi): Removed. + (enum struct_return): New enum. + (struct gdbarch_tdep): Remove abi member, add osabi, jb_pc_offset, + struct_return, sigtramp_saved_pc, sigtramp_start, sigtramp_end and + sc_pc_offset members. + (i386_gdbarch_register_os_abi): Remove prototype. + (I386_NUM_GREGS, I386_NUM_FREGS, I386_NUM_XREGS, + I386_SSE_NUM_REGS): New defines. + (I386_SIZEOF_GREGS, I386_SIZEOF_FREGS, I386_SIZEOF_XREGS, + I386_SSE_SIZEOF_REGS): New defines. + (i386_register_name, i386_register_byte, i386_register_raw_size): + New prototypes. + (i386_elf_init_abi, i386_svr4_init_abi): New prototypes. + (i386bsd_sigtramp_saved_pc): New prototype. + * i386-tdep.c: Don't include "elf-bfd.h". + (i386_stab_reg_to_regnum, i386_dwarf_reg_to_regnum, + i386_frame_chain, i386_saved_pc_after_call): Make static. + (i386_frame_saved_pc): Rewrite to call architecture dependent + function to deal with signal handlers. Make static. + (i386go32_frame_saved_pc): Removed. + [GET_LONGJMP_TARGET] (JB_PC, JB_ELEMENT_SIZE, get_longjmp_target): + Removed. + (i386_get_longjmp_target): New function. + (default_struct_convention, pcc_struct_convention, + reg_struct_convention, valid_conventions, struct_convention): New + variables. + (i386_use_struct_convention): New function. + (i386v4_sigtramp_saved_pc): Renamed to + i386_svr4_sigtramp_saved_pc. Made static. Moved. + (i386_pc_in_sigtramp): New function. + (i386_abi_names): Removed. + (ABI_TAG_OS_GNU_LINUX, ABI_TAG_OS_GNU_HURD, + ABI_TAG_OS_GNU_SOLARIS, ABI_TAG_OS_FREEBSD, ABI_TAG_OS_NETBSD): + Removed. + (process_note_sections, i386_elf_abi_from_note, i386_elf_abi, + i386_gdbarch_register_os_abi): Removed. + (struct i386_abi_handler): Removed. + (i386_abi_handler_list): Removed. + (i386_svr4_pc_in_sigtramp, i386_go32_pc_in_sigtramp): New + functions. + (i386_elf_init_abi, i386_svr4_init_abi, i386_go32_init_abi, + i386_nw_init_abi): New functions. + (i386_gdbarch_init): Rewritten to use generic OS ABI framework. + Use set_gdbarch_xxx() calls instead of relying on macros for a + number of calls. + (i386_coff_osabi_sniffer, i386_nlm_osabi_sniffer): New functions. + (_initialize_i386_tdep): Add new 'struct-convcention' command. + Register the various architecture variants defined in this file. + +2002-06-14 Daniel Jacobowitz <drow@mvista.com> + + * gdbtypes.h (TYPE_FLAG_VARARGS): Update comment. + (struct main_type): Remove arg_types member. Update comments for + struct field. + (TYPE_ARG_TYPES): Remove. + (TYPE_FN_FIELD_ARGS): Update. + (smash_to_method_type): Update prototype. + + * c-typeprint.c (cp_type_print_method_args): Take method type + instead of argument list. Use new argument layout. Simplify. + (c_type_print_args): Use new argument layout. Simplify. + (c_type_print_base): Update call to cp_type_print_method_args. + * dwarf2read.c (dwarf2_add_member_fn): Remove unneeded type + argument; use die->type instead. Update call to + smash_to_method_type. + (read_structure_scope): Update call to dwarf2_add_member_fn. + * gdbtypes.c (allocate_stub_method): Update comment. + (smash_to_method_type): Take new NARGS and VARARGS arguments. + Use new argument layout. + (check_stub_method): Use new argument layout. Don't count + void as an argument. + (print_arg_types): Update comments. Use new argument layout. + (recursive_dump_type): Don't print arg_types member. + * hpread.c (hpread_read_struct_type): Use new argument layout. + (fixup_class_method_type): Likewise. + (hpread_type_lookup): Likewise. + * stabsread.c (read_type): Update calls to read_args and + smash_to_method_type. + (read_args): Use new argument layout. Simplify. + * valops.c (typecmp): Use new argument layout. Update parameters + and comments. Simplify. + (hand_function_call): Use new argument layout. + (search_struct_method): Update call to typecmp. + (find_overload_match): Use new argument layout. + +2002-06-13 Daniel Jacobowitz <drow@mvista.com> + + * NEWS: Mention multithreaded debug support for gdbserver. + +2002-06-13 Daniel Jacobowitz <drow@mvista.com> + + * MAINTAINERS: Mention NEWS. + +2002-06-13 Daniel Jacobowitz <drow@mvista.com> + + * gdbserver/regcache.c: Add comment. + +2002-06-13 Daniel Jacobowitz <drow@mvista.com> + + * mips-tdep.c (PROC_SYMBOL): Add warning comment. + (struct mips_objfile_private, compare_pdr_entries): New. + (non_heuristic_proc_desc): Read the ".pdr" section if it + is present. + +2002-06-12 Andrew Cagney <ac131313@redhat.com> + + * arm-tdep.c (arm_push_arguments): Rewrite using a two-pass loop. + (arm_debug): New static variable. + (_initialize_arm_tdep): Add ``set debug arm'' command. + +2002-06-12 Andrew Cagney <ac131313@redhat.com> + + * Makefile.in (sim_arm_h): Define. + (arm-tdep.o): Add $(sim_arm_h) and $(gdb_assert_h). + * arm-tdep.c: Include "gdb/sim-arm.h" and "gdb_assert.h". + (arm_register_sim_regno): New function, map an internal REGNUM + onto a simulator register number. + (arm_gdbarch_init): Set register_sim_regno. + +2002-06-09 Aldy Hernandez <aldyh@redhat.com> + + * MAINTAINERS: Add self. + +2002-06-11 Jim Blandy <jimb@redhat.com> + + * source.c (source_info): Mention whether the symtab has + information about preprocessor macros. + + Call the command `info macro', not `show macro'. + * macrocmd.c (info_macro_command): Renamed from `show_macro_command'. + Fix error message. + (_initialize_macrocmd): Register `info_macro_command' in + `infolist', not `showlist'. + +2002-06-11 Daniel Jacobowitz <drow@mvista.com> + + * mips-tdep.c (MIPS_FPU_TYPE, FP_REGISTER_DOUBLE, MIPS_EABI) + (MIPS_LAST_FP_ARG_REGNUM, MIPS_LAST_ARG_REGNUM) + (MIPS_DEFAULT_SAVED_REGSIZE, MIPS_REGS_HAVE_HOME_P) + (MIPS_DEFAULT_STACK_ARGSIZE, GDB_TARGET_IS_MIPS64) + (MIPS_DEFAULT_MASK_ADDRESS_P): Remove obsolete definitions. Define + unconditionally. + (set_mipsfpu_single_command, set_mipsfpu_double_command) + (set_mipsfpu_none_command): Remove if (GDB_MULTI_ARCH). + (_initialize_mips_tdep): Remove dead code. + * config/mips/tm-irix5.h (MIPS_LAST_ARG_REGNUM) + (MIPS_DEFAULT_STACK_ARGSIZE, MIPS_REGS_HAVE_HOME_P): Remove. + * config/mips/tm-irix6.h (MIPS_LAST_ARG_REGNUM) + (MIPS_DEFAULT_STACK_ARGSIZE, MIPS_REGS_HAVE_HOME_P): Remove. + * config/mips/tm-mips.h (MIPS_EABI, MIPS_LAST_ARG_REGNUM, + MIPS_LAST_FP_ARG_REGNUM): Remove. + +2002-06-11 Daniel Jacobowitz <drow@mvista.com> + + * gdbserver/thread-db.c: New file. + * gdbserver/proc-service.c: New file. + * gdbserver/acinclude.m4: New file. + * gdbserver/Makefile.in: Add GDBSERVER_LIBS, gdb_proc_service_h, + proc-service.o, and thread-db.o. + (linux-low.o): Add USE_THREAD_DB. + * gdbserver/acconfig.h: Add HAVE_PRGREGSET_T, HAVE_PRFPREGSET_T, + HAVE_LWPID_T, HAVE_PSADDR_T, and PRFPREGSET_T_BROKEN. + * gdbserver/aclocal.m4: Regenerated. + * gdbserver/config.in: Regenerated. + * gdbserver/configure: Regenerated. + * gdbserver/configure.in: Check for proc_service.h, sys/procfs.h, + thread_db.h, and linux/elf.h headrs. + Check for lwpid_t, psaddr_t, prgregset_t, prfpregset_t, and + PRFPREGSET_T_BROKEN. Introduce srv_thread_depfiles and USE_THREAD_DB. + Check for -lthread_db and thread support. + * gdbserver/configure.srv: Enable thread_db support for ARM, i386, MIPS, + PowerPC, and SuperH. + * gdbserver/i387-fp.c: Constify arguments. + * gdbserver/i387-fp.h: Likewise. + * gdbserver/inferiors.c: (struct thread_info): Renamed from + `struct inferior_info'. Remove PID member. Use generic inferior + list header. All uses updated. + (inferiors, signal_pid): Removed. + (all_threads): New variable. + (get_thread): Define. + (add_inferior_to_list): New function. + (for_each_inferior): New function. + (change_inferior_id): New function. + (add_inferior): Removed. + (remove_inferior): New function. + (add_thread): New function. + (free_one_thread): New function. + (remove_thread): New function. + (clear_inferiors): Use for_each_inferior and free_one_thread. + (find_inferior): New function. + (find_inferior_id): New function. + (inferior_target_data): Update argument type. + (set_inferior_target_data): Likewise. + (inferior_regcache_data): Likewise. + (set_inferior_regcache_data): Likewise. + * gdbserver/linux-low.c (linux_bp_reinsert): Remove. + (all_processes, stopping_threads, using_thrads) + (struct pending_signals, debug_threads, pid_of): New. + (inferior_pid): Replace with macro. + (struct inferior_linux_data): Remove. + (get_stop_pc, add_process): New functions. + (linux_create_inferior): Restore SIGRTMIN+1 before calling exec. + Use add_process and add_thread. + (linux_attach_lwp): New function, based on old linux_attach. Use + add_process and add_thread. Set stop_expected for new threads. + (linux_attach): New function. + (linux_kill_one_process): New function. + (linux_kill): Kill all LWPs. + (linux_thread_alive): Use find_inferior_id. + (check_removed_breakpoints, status_pending_p): New functions. + (linux_wait_for_process): Renamed from linux_wait_for_one_inferior. + Update. Use WNOHANG. Wait for cloned processes also. Update process + struct for the found process. + (linux_wait_for_event): New function. + (linux_wait): Use it. Support LWPs. + (send_sigstop, wait_for_sigstop, stop_all_processes) + (linux_resume_one_process, linux_continue_one_process): New functions. + (linux_resume): Support LWPs. + (REGISTER_RAW_SIZE): Remove. + (fetch_register): Use register_size instead. Call supply_register. + (usr_store_inferior_registers): Likewise. Call collect_register. + Fix recursive case. + (regsets_fetch_inferior_registers): Improve error message. + (regsets_store_inferior_registers): Add debugging. + (linux_look_up_symbols): Call thread_db_init if USE_THREAD_DB. + (unstopped_p, linux_signal_pid): New functions. + (linux_target_ops): Add linux_signal_pid. + (linux_init_signals): New function. + (initialize_low): Call it. Initialize using_threads. + * gdbserver/regcache.c (inferior_regcache_data): Add valid + flag. + (get_regcache): Fetch registers lazily. Add fetch argument + and update all callers. + (regcache_invalidate_one, regcache_invalidate): New + functions. + (new_register_cache): Renamed from create_register_cache. + Return the new regcache. + (free_register_cache): Change argument to a void *. + (registers_to_string, registers_from_string): Call get_regcache + with fetch flag set. + (register_data): Make static. Pass fetch flag to get_regcache. + (supply_register): Call get_regcache with fetch flag clear. + (collect_register): Call get_regcache with fetch flag set. + (collect_register_as_string): New function. + * gdbserver/regcache.h: Update. + * gdbserver/remote-utils.c (putpkt): Flush after debug output and use + stderr. + Handle input interrupts while waiting for an ACK. + (input_interrupt): Use signal_pid method. + (getpkt): Flush after debug output and use stderr. + (outreg): Use collect_register_as_string. + (new_thread_notify, dead_thread_notify): New functions. + (prepare_resume_reply): Check using_threads. Set thread_from_wait + and general_thread. + (look_up_one_symbol): Flush after debug output. + * gdbserver/server.c (step_thread, server_waiting): New variables. + (start_inferior): Don't use signal_pid. Update call to mywait. + (attach_inferior): Update call to mywait. + (handle_query): Handle qfThreadInfo and qsThreadInfo. + (main): Don't fetch/store registers explicitly. Use + set_desired_inferior. Support proposed ``Hs'' packet. Update + calls to mywait. + * gdbserver/server.h: Update. + (struct inferior_list, struct_inferior_list_entry): New. + * gdbserver/target.c (set_desired_inferior): New. + (write_inferior_memory): Constify. + (mywait): New function. + * gdbserver/target.h: Update. + (struct target_ops): New signal_pid method. + (mywait): Removed macro, added prototype. + + * gdbserver/linux-low.h (regset_func): Removed. + (regset_fill_func, regset_store_func): New. + (enum regset_type): New. + (struct regset_info): Add type field. Use new operation types. + (struct linux_target_ops): stop_pc renamed to get_pc. + Add decr_pc_after_break and breakpoint_at. + (get_process, get_thread_proess, get_process_thread) + (strut process_info, all_processes, linux_attach_lwp) + (thread_db_init): New. + + * gdbserver/linux-arm-low.c (arm_get_pc, arm_set_pc, + arm_breakpoint, arm_breakpoint_len, arm_breakpoint_at): New. + (the_low_target): Add new members. + * gdbserver/linux-i386-low.c (i386_store_gregset, i386_store_fpregset) + (i386_store_fpxregset): Constify. + (target_regsets): Add new kind identifier. + (i386_get_pc): Renamed from i386_stop_pc. Simplify. + (i386_set_pc): Add debugging. + (i386_breakpoint_at): New function. + (the_low_target): Add new members. + * gdbserver/linux-mips-low.c (mips_get_pc, mips_set_pc) + (mips_breakpoint, mips_breakpoint_len, mips_reinsert_addr) + (mips_breakpoint_at): New. + (the_low_target): Add new members. + * gdbserver/linux-ppc-low.c (ppc_get_pc, ppc_set_pc) + (ppc_breakpoint, ppc_breakpoint_len, ppc_breakpoint_at): New. + (the_low_target): Add new members. + * gdbserver/linux-sh-low.c (sh_get_pc, sh_set_pc) + (sh_breakpoint, sh_breakpoint_len, sh_breakpoint_at): New. + (the_low_target): Add new members. + * gdbserver/linux-x86-64-low.c (target_regsets): Add new kind + identifier. + +2002-06-11 Michal Ludvig <mludvig@suse.cz> + + * dwarf2cfi.c (unwind_tmp_obstack_init): New. + (unwind_tmp_obstack_free, parse_frame_info) + (update_context, cfi_read_fp, cfi_write_fp) + (cfi_frame_chain, cfi_init_extra_frame_info) + (cfi_virtual_frame_pointer): Use the above function. + * dwarf2cfi.c: Reindented (using 'indent dwarf2cfi.c'). + +2002-06-11 Corinna Vinschen <vinschen@redhat.com> + + * v850-tdep.c (v850_type_is_scalar): New function. + (v850_use_struct_convention): Match current gcc implementation + as close as possible. + (v850_push_arguments): Fix stack_offset handling. Don't write + struct_addr into register. This is done by v850_store_struct_return. + (v850_extract_return_value): Care for structs. + (v850_store_return_value): Ditto. + (v850_store_struct_return): Actually write address. + +2002-06-11 Michal Ludvig <mludvig@suse.cz> + + * x86-64-tdep.c (x86_64_skip_prologue): Fix to work on functions + without debug information too. + +2002-06-10 Andrew Cagney <ac131313@redhat.com> + + * gdbarch.sh (PRINT_FLOAT_INFO): Add frame and ui_file parameters. + Make multi-arch pure. + * gdbarch.h, gdbarch.c: Re-generate. + * arm-tdep.c (arm_print_float_info): Update. + * arch-utils.h (default_print_float_info): Update. + * arch-utils.c (default_print_float_info): Update. + * infcmd.c (float_info): Update call. + +2002-06-10 Andrew Cagney <ac131313@redhat.com> + + * Makefile.in (init.c): Move the call to _initialize_gdbtypes to + the front of the initialize list. + +2002-06-10 Andrew Cagney <ac131313@redhat.com> + + * infrun.c (struct inferior_status): Replace fields + selected_frame_address and selected_level with field + selected_frame_id. + (save_inferior_status): Update. Use get_frame_id. + (struct restore_selected_frame_args): Delete. + (restore_selected_frame): Update. Use frame_find_by_id. + (restore_inferior_status): Update. + + * breakpoint.h (struct breakpoint): Change type of + watchpoint_frame to frame_id. + * breakpoint.c (insert_breakpoints): Use frame_find_by_id. Remove + call to get_current_frame. + (do_enable_breakpoint): Use frame_find_by_id. Remove call to + get_current_frame. + (watchpoint_check): Use frame_find_by_id. + + * frame.h (record_selected_frame): Delete declaration. + * stack.c (record_selected_frame): Delete function. + + * frame.h (struct frame_id): Define. + (get_frame_id): Declare. + (frame_find_by_id): Declare. + * frame.c (frame_find_by_id): New function. + (get_frame_id): New function. + +2002-06-10 Andrey Volkov <avolkov@transas.com> + + * ser-e7kpc.c: Fix duplicated define and call of + _initialize_ser_e7000pc + +2002-06-09 Daniel Jacobowitz <drow@mvista.com> + + * signals/signals.c (target_signal_from_host): Fix #ifdef + SIGRTMIN case. + (do_target_signal_to_host): Likewise. + +2002-06-09 Daniel Jacobowitz <drow@mvista.com> + + * mips-tdep.c (mips_find_abi_section): New function. + (mips_gdbarch_init): Call it. + +2002-06-09 Mark Kettenis <kettenis@gnu.org> + + * solib-svr4.c (init_fetch_link_map_offsets): Simply return + legacy_fetch_link_map_offsets. Adjust comment to reflect reality + after Andrew's 2002-06-08 gdbarch change. + +2002-06-09 Mark Kettenis <kettenis@gnu.org> + + * i386-linux-nat.c (suppy_gregset): Don't supply + I386_LINUX_ORIG_EAX_REGNUM if there isn't room for it in GDB's + register cache. + (fill_gregset): Don't fetch it under the same circumstances. + +2002-06-09 Andrew Cagney <cagney@redhat.com> + + * Makefile.in (callback_h): Define. + (remote_sim_h): Update path to remote-sim.h. + (remote-rdp.o): Add $(callback_h). + (remote-sim.o): Use $(callback_h). + * remote-sim.c: Include "gdb/callback.h" and "gdb/remote-sim.h". + * remote-rdp.c: Include "gdb/callback.h". + +2002-06-09 Mark Kettenis <kettenis@gnu.org> + + * osabi.h (gdb_osabi): Add GDB_OSABI_GO32 and GDB_OSABI_NETWARE. + * osabi.c (gdb_osabi_names): Add "DJGPP" and "NetWare". + +2002-06-08 Andrew Cagney <ac131313@redhat.com> + + * sparcl-tdep.c: Use __CYGWIN__ instead of __CYGWIN32__. + * rdi-share/serpardr.c: Ditto. + * rdi-share/unixcomm.c: Ditto. + * rdi-share/serdrv.c: Ditto. + * rdi-share/hostchan.h: Ditto. + * rdi-share/hostchan.c: Ditto. + * rdi-share/host.h: Ditto. + * rdi-share/devsw.c: Ditto. + + * objfiles.h: Change type of obj_private to void pointer. + * pa64solib.c: Update copyright. Don't include "assert.h", use + strcmp instead of STREQ, use LONGEST, do not use PTR + * somsolib.c: Ditto. + + * config/djgpp/fnchange.lst: Fix problems with bfd/elf32-i386.c, + bfd/elf32-i386qnx.c, bfd/elf32-sh.c, bfd/elf32-sh64-nbsd.c, + bfd/elf64-sh64-nbsd.c bfd/elf64-sh64.c. + +2002-06-08 Andrew Cagney <ac131313@redhat.com> + + * frame.c (GET_SAVED_REGISTER): Delete macro definition. + (default_get_saved_register): Delete function. + * gdbarch.sh (GET_SAVED_REGISTER): Set default to + generic_unwind_get_saved_register. + * gdbarch.h, gdbarch.c: Re-generate. + +2002-06-08 Andrew Cagney <ac131313@redhat.com> + + * gdbarch.sh (FRAME_CHAIN_VALID): Set default to + generic_func_frame_chain_valid. + * gdbarch.h, gdbarch.c: Re-generate. + * blockframe.c (generic_func_frame_chain_valid): Only check + PC_IN_CALL_DUMMY when generic dummy frames. Don't worry about + passing FP to PC_IN_CALL_DUMMY. + Fix PR gdb/360. + +2002-06-08 Andrew Cagney <ac131313@redhat.com> + + * gdbarch.sh (struct gdbarch_data): Add field init_p. + (register_gdbarch_data): Initialize init_p. + (gdbarch_data): Initialize data pointer using the init function. + (init_gdbarch_data): Delete function. + (gdbarch_update_p): Update. + (initialize_non_multiarch): Update. + (struct gdbarch): Add field initialized_p. + * gdbarch.h, gdbarch.c: Re-generate. + +2002-06-07 Michal Ludvig <mludvig@suse.cz> + + * x86-64-linux-nat.c (x86_64_fxsave_offset): New. + (supply_fpregset, fill_fpregset): Don't call i387_*_fxsave, + better do the things actually here. + * x86-64-tdep.c (x86_64_register_name2nr): New. + (x86_64_register_name): Renamed to x86_64_register_nr2name. + (x86_64_gdbarch_init): Respect the above change. + * x86-64-tdep.h (x86_64_register_name2nr) + (x86_64_register_nr2name): Add prototypes. + * config/i386/x86-64linux.mt (TDEPFILES): Remove i387-tdep.o. + +2002-06-06 Michael Snyder <msnyder@redhat.com> + + * d10v-tdep.c (d10v_push_arguments): Handle struct_return. + Delete extra braces and re-indent. + (d10v_store_return_value): Char return values + must be shifted over by one byte in R0. + (d10v_extract_return_value): Delete extra braces, re-indent. + +2002-06-06 Elena Zannoni <ezannoni@redhat.com> + + * d10v-tdep.c (d10v_read_sp, d10v_read_fp): Add prototype. + (d10v_register_virtual_type): Make $fp and $sp be pointer to data. + (d10v_integer_to_address): Rewrite. + (d10v_frame_init_saved_regs): When reading fp and sp registers use + the d10v specific functions which take care of converting to the + correct space. + +2002-06-06 Elena Zannoni <ezannoni@redhat.com> + + * config/djgpp/fnchange.lst: Add testsuite files altivec-abi.c, + altivec-abi.exp, altivec-regs.c, altivec-regs.exp. + +2002-06-02 Andrew Cagney <ac131313@redhat.com> + + * config/alpha/nm-linux.h: Add "config/" prefix to tm, nm and xm + includes. + * config/tm-linux.h: Ditto. + * config/alpha/tm-alphalinux.h: Ditto. + * config/arm/nm-linux.h, config/arm/tm-linux.h: Ditto. + * config/arm/xm-nbsd.h, config/i386/nm-gnu.h: Ditto. + * config/i386/nm-i386lynx.h, config/i386/nm-i386sol2.h: Ditto. + * config/i386/nm-i386v4.h, config/i386/nm-i386v42mp.h: Ditto. + * config/i386/nm-linux.h, config/i386/nm-m3.h: Ditto. + * config/i386/nm-ptx4.h, config/i386/nm-x86-64.h: Ditto. + * config/i386/tm-i386gnu.h, config/i386/tm-i386lynx.h: Ditto. + * config/i386/tm-i386m3.h, config/i386/tm-i386sco5.h: Ditto. + * config/i386/tm-i386v4.h, config/i386/tm-linux.h: Ditto. + * config/i386/tm-ptx4.h, config/i386/tm-vxworks.h: Ditto. + * config/i386/xm-i386v4.h, config/i386/xm-nbsd.h: Ditto. + * config/i386/xm-ptx.h, config/i386/xm-ptx4.h: Ditto. + * config/i960/tm-vx960.h, config/ia64/nm-aix.h: Ditto. + * config/ia64/nm-linux.h, config/ia64/tm-aix.h: Ditto. + * config/ia64/tm-linux.h, config/ia64/xm-aix.h: Ditto. + * config/m68k/nm-linux.h, config/m68k/nm-m68klynx.h: Ditto. + * config/m68k/nm-sysv4.h, config/m68k/tm-linux.h: Ditto. + * config/m68k/tm-m68klynx.h, config/m68k/tm-m68kv4.h: Ditto. + * config/m68k/tm-sun2os4.h, config/m68k/tm-sun3os4.h: Ditto. + * config/m68k/tm-vx68.h, config/m68k/xm-m68kv4.h: Ditto. + * config/m68k/xm-nbsd.h, config/m88k/nm-delta88v4.h: Ditto. + * config/m88k/tm-delta88v4.h, config/m88k/xm-delta88v4.h: Ditto. + * config/mips/nm-irix5.h, config/mips/nm-linux.h: Ditto. + * config/mips/tm-linux.h, config/mips/tm-mips64.h: Ditto. + * config/mips/tm-mipsm3.h, config/mips/tm-mipsv4.h: Ditto. + * config/mips/tm-vxmips.h, config/mips/xm-irix5.h: Ditto. + * config/mips/xm-mipsv4.h, config/ns32k/xm-nbsd.h: Ditto. + * config/pa/nm-hppao.h, config/powerpc/nm-linux.h: Ditto. + * config/powerpc/tm-linux.h, config/powerpc/tm-vxworks.h: Ditto. + * config/powerpc/xm-aix.h, config/rs6000/nm-rs6000ly.h: Ditto. + * config/rs6000/tm-rs6000ly.h, config/rs6000/xm-aix4.h: Ditto. + * config/sh/tm-linux.h, config/sparc/nm-linux.h: Ditto. + * config/sparc/nm-sparclynx.h, config/sparc/nm-sun4sol2.h: Ditto. + * config/sparc/tm-linux.h, config/sparc/tm-sp64linux.h: Ditto. + * config/sparc/tm-sp64sim.h, config/sparc/tm-sparclynx.h: Ditto. + * config/sparc/tm-sun4os4.h, config/sparc/tm-sun4sol2.h: Ditto. + * config/sparc/tm-vxsparc.h, config/sparc/xm-sun4sol2.h: Ditto. + +2002-05-04 Aidan Skinner <aidan@velvet.net> + + * ada-exp.tab.c: New file + * ada-exp.y: New file + * ada-lang.c: New file + * ada-lang.h: New file + * ada-lex.c: New file + * ada-lex.l: New file + * ada-tasks.c: New file + * ada-typeprint.c: New file + * ada-valprint.c: New file + +2002-06-02 Jason Thorpe <thorpej@wasabisystems.com> + + * ppcnbsd-tdep.c (ppcnbsd_init_abi): Don't set + use_struct_convention to ppc_sysv_abi_broken_use_struct_convention. + +2002-06-02 Jason Thorpe <thorpej@wasabisystems.com> + + * config/rs6000/aix4.mt (TDEPFILES): Use ppc-sysv-tdep.o + insetead of ppc-linux-tdep.o. + * config/rs6000/rs6000.mt (TDEPFILES): Likewise. + * config/rs6000/rs6000lynx.mt (TDEPFILES): Likewise. + +2002-06-02 Andrew Cagney <ac131313@redhat.com> + + 2002-05-07 Christian Groessler <chris@groessler.org> + * z8k-tdep.c (z8k_print_register_hook): Fix display of 32 and 64 + bit register contents for little endian hosts. + +2002-06-01 Andrew Cagney <ac131313@redhat.com> + + * MAINTAINERS: Mention that any `HP/UX reader' can be changed by + any maintainer. + +2002-06-01 Andrew Cagney <ac131313@redhat.com> + + * gdbarch.h: Regenerate. + +2002-06-01 Andrew Cagney <ac131313@redhat.com> + + * MAINTAINERS: Add everyone to write-after-approval list. + +2002-06-01 Andrew Cagney <ac131313@redhat.com> + + * stack.c (frame_info): Use frame_register_unwind instead of + saved_regs. Mention when the SP is on the stack or in a register. + + * frame.h (frame_register_unwind_ftype): Define. Document. + (struct frame_info): Add field register_unwind and + register_unwind_cache. + (frame_register_unwind): Declare. + (generic_unwind_get_saved_register): Declare. + + * frame.c (frame_register_unwind): New function. + (generic_unwind_get_saved_register): New function. + + * blockframe.c (generic_call_dummy_register_unwind): New function. + (frame_saved_regs_register_unwind): New function. + (set_unwind_by_pc): New function. + (create_new_frame): New function. + (get_prev_frame): New function. + +2002-05-30 Andrew Cagney <ac131313@redhat.com> + + * a29k-share/: Delete directory. + * remote-vx29k.c: Delete file. + +2002-05-30 Jason Thorpe <thorpej@wasabisystems.com> + + * config/djgpp/fnchange.lst: Add ns32knbsd-nat.c, ns32knbsd-tdep.c, + ppcnbsd-nat.c, ppcnbsd-tdep.c, sparcnbsd-nat.c, and sparcnbsd-tdep.c. + +2002-05-30 Jason Thorpe <thorpej@wasabisystems.com> + + * Makefile.in (ALLDEPFILES): Add sparc64nbsd-nat.c, + sparcnbsd-nat.c, and sparcnbsd-tdep.c. + (sparc64nbsd-nat.o) + (sparcnbsd-nat.o) + (sparcnbsd-tdep.o): New dependency lists. + * NEWS: Note new UltraSPARC NetBSD native configuration. + * configure.host (sparc64-*-netbsd*): New host. + * configure.tgt (sparc-*-netbsdelf*) + (sparc-*-netbsd*): Set gdb_target to nbsd. + (sparc64-*-netbsd*): New target. + * sparc64nbsd-nat.c: New file. + * sparcnbsd-nat.c: New file. + * sparcnbsd-tdep.c: New file. + * sparcnbsd-tdep.h: New file. + * config/sparc/nbsd.mt: New file. + * config/sparc/nbsd64.mh: New file. + * config/sparc/nbsd64.mt: New file. + * config/sparc/nbsdaout.mh (NATDEPFILES): Remove corelow.o, + sparc-nat.o, and solib.o. Add sparcnbsd-nat.o. + (HOST_IPC): Remove. + * config/sparc/nbsdaout.mt: Remove. + * config/sparc/nbsdelf.mh (NATDEPFILES): Remove corelow.o, + sparc-nat.o, and solib.o. Add sparcnbsd-nat.o. + (HOST_IPC): Remove. + * config/sparc/nbsdelf.mt: Remove. + * config/sparc/nm-nbsd.h: Update copyright years. Remove all + sparc-nat.c compatiblity defines. + * config/sparc/tm-nbsd.h: Update copyright years. Include solib.h. + (GDB_MULTI_ARCH): Set to GDB_MULTI_ARCH_PARTIAL. + * config/sparc/tm-nbsd64.h: New file. + * config/sparc/tm-nbsdaout.h: Remove. + * config/sparc/xm-nbsd.h: Remove. + +2002-05-30 Jason Thorpe <thorpej@wasabisystems.com> + + * Makefile.in (sparc-tdep.o): Add osabi.h to dependency list. + * sparc-tdep.c: Include osabi.h. + (gdbarch_tdep): Add osabi member. + (_initialize_sparc_tdep): Use gdbarch_register. + (sparc_gdbarch_init): Use generic OS ABI framework. + (sparc_dump_tdep): New function. + +2002-05-30 Kevin Buettner <kevinb@redhat.com> + + * corefile.c (do_captured_read_memory_integer): Return non-zero + result. + (safe_read_memory_integer): Copy result of memory read when + status is non-zero. Also, add comments. + +2002-05-20 Jason Thorpe <thorpej@wasabisystems.com> + + * Makefile.in (ppc_tdep_h): Define. + (ppc-linux-nat.o) + (ppc-linux-tdep.o) + (rs6000-tdep.o): Use $(ppc_tdep_h). + (ppc-sysv-tdep.o) + (ppcnbsd-nat.o) + (ppcnbsd-tdep.o): New dependency lists. + * ppc-tdep.h: Use generic OS ABI framework. + * ppc-linux-tdep.c (_initialize_ppc_linux_tdep) + (ppc_linux_init_abi): New functions. + (ppc_sysv_abi_broken_use_struct_convention) + (ppc_sysv_abi_use_struct_convention) + (ppc_sysv_abi_push_arguments): Move to... + * ppc-sysv-tdep.c: ...here. + * ppcnbsd-nat.c: Don't include gdbcore.h and regcache.h. + * rs6000-tdep.c (process_note_abi_tag_sections) + (get_elfosabi): Remove. + (rs6000_gdbarch_init): Use generic OS ABI framework. + (rs6000_dump_tdep): New function. + (_initialize_rs6000_tdep): Use gdbarch_register. + * config/powerpc/linux.mt (TDEPFILES): Add ppc-sysv-tdep.o. + * config/powerpc/nbsd.mh (NATDEPFILES): Remove solib-legacy.o. + * config/powerpc/aix.mt (TDEPFILES): Use ppc-sysv-tdep.o instead + of ppc-linux-tdep.o. + * config/powerpc/nbsd.mt (TDEPFILES): Likewise. + * config/powerpc/ppc-eabi.mt (TDEPFILES): Likewise. + * config/powerpc/ppc-sim.mt (TDEPFILES): Likewise. + * config/powerpc/ppcle-eabi.mt (TDEPFILES): Likewise. + * config/powerpc/ppcle-sim.mt (TDEPFILES): Likewise. + * config/powerpc/vxworks.mt (TDEPFILES): Likewise. + +2002-05-29 Jim Blandy <jimb@redhat.com> + + * macroscope.c (default_macro_scope): Put `void' in empty argument + list. + +2002-05-29 Andrew Cagney <ac131313@redhat.com> + + * Makefile.in (arch-utils.o): Add $(sim_regno_h). + * arch-utils.c: Include "sim-regno.h". + * gdbarch.sh: Don't include "sim-regno.h". + * gdbarch.h, gdbarch.c: Regenerate. + * sim-regno.h (legacy_register_sim_regno): Move declaration from + here. + * arch-utils.h (legacy_register_sim_regno): To here. + * remote-sim.c (legacy_register_sim_regno): Move function from + here. + * arch-utils.c (legacy_register_sim_regno): To here. + +2002-05-28 Andrew Cagney <ac131313@redhat.com> + + * sim-regno.h: New file. + * Makefile.in (sim_regno_h): Define. + (d10v-tdep.o, remote-sim.o): Add dependency on $(sim_regno_h). + * remote-sim.c: Include "sim-regno.h" and "gdb_assert.h". + (legacy_register_sim_regno): New function. + (one2one_register_sim_regno): New function. + (gdbsim_fetch_register): Rewrite. + (gdbsim_store_register): Only store a register when + REGISTER_SIM_REGNO is valid. + * d10v-tdep.c: Include "sim-regno.h". + (d10v_ts2_register_sim_regno): Add legacy_regiter_sim_regno check. + (d10v_ts3_register_sim_regno): Ditto. + * gdbarch.sh: Include "sim-regno.h". + (REGISTER_SIM_REGNO): Set default to legacy_register_sim_regno. + * gdbarch.h, gdbarch.c: Regenerate. + * arch-utils.h (default_register_sim_regno): Delete declaration. + * arch-utils.c (default_register_sim_regno): Delete function. + +2002-05-28 Jason Thorpe <thorpej@wasabisystems.com> + + * ppcnbsd-nat.c: Rewrite. + * ppcnbsd-tdep.c: New file. + * ppcnbsd-tdep.h: New file. + * config/powerpc/nbsd.mh (NATDEPFILES): Remove corelow.o, + solib.o, and solib-svr4.o. + * config/powerpc/nbsd.mt (TDEPFILES): Add ppcnbsd-tdep.o, + nbsd-tdep.o, and corelow.o. + +2002-05-28 Andrew Cagney <ac131313@redhat.com> + + * MAINTAINERS (--enable-gdb-build-warnings): Rewrite script to use + `tr' and `sed'. Mention that `broken' targets are not expected to + build. + +2002-05-27 Michal Ludvig <mludvig@suse.cz> + + * x86-64-tdep.c (x86_64_skip_prologue): Remove obsolete note. + Let PC point right after the prologue before looking up symbols. + +2002-05-27 Martin M. Hunt <hunt@redhat.com> + + * i386-tdep.c (i386_register_virtual_type): Return + builtin_type_vec128i for SSE registers. + + * gdbtypes.h (builtin_type_vec128i): Declare. + + * gdbtypes.c (build_builtin_type_vec128i): New function. + (builtin_type_v2_double, builtin_type_v4_int64): New types. + (builtin_type_vec128i): New type for SSE2 128-bit registers. + (build_gdbtypes): Initialize new builtin vector types. + (_initialize_gdbtypes): Register new vector types with gdbarch. + +2002-05-26 Jason Thorpe <thorpej@wasabisystems.com> + + * MAINTAINERS: ns32k is not longer an obsolete candidate, + since it has been multi-arch'd. + * NEWS: Note that ns32k-*-* is now partial multi-arch. + Move Alpha and VAX multi-arch news entries to same section + as other multi-arch news. + +2002-05-26 Jason Thorpe <thorpej@wasabisystems.com> + + * ns32k-tdep.c: include gdbtypes.h, inferior.h, regcache.h, + target.s, arch-utils.h, ns32k-tdep.h. Make many functions + static. Rename some register numbers to put them in ns32k-tdep + private namespace. + (ns32k_get_saved_register, ns32k_gdbarch_init_32082, + ns32k_gdbarch_init_32382, ns32k_gdbarch_init, ns32k_dump_tdep): New + functions. + (_initialize_ns32k_tdep): Use gdbarch_register. + * ns32k-tdep.h: New file. + * ns32knbsd-tdep.c: New file. + * config/ns32k/nbsdaout.mt (TDEPFILES): Add ns32knbsd-tdep.o. + * config/ns32k/tm-nbsd.h: Include "ns32k/tm-ns32k.h". + (IN_SOLIB_CALL_TRAMPOLINE, REGISTER_NAME, NUM_REGS, + REGISTER_BYTES, REGISTER_BYTE): Remove. + * config/ns32k/tm-ns32k.h: New file. + * config/ns32k/tm-umax.h: Remove. + +2002-05-26 Jason Thorpe <thorpej@wasabisystems.com> + + * ns32k-tdep.c (ns32k_saved_pc_after_call, + ns32k_store_struct_return, ns32k_extract_return_value, + ns32k_store_return_value, ns32k_extract_struct_value_address): New + functions. + * config/ns32k/tm-umax.h (SAVED_PC_AFTER_CALL): Define as + ns32k_saved_pc_after_call. + (STORE_STRUCT_RETURN): Define as ns32k_store_struct_return. + (EXTRACT_RETURN_VALUE): Define as ns32k_extract_return_value. + (STORE_RETURN_VALUE): Define as ns32k_store_return_value. + (EXTRACT_STRUCT_VALUE_ADDRESS): Define as + ns32k_extract_struct_value_address. + +2002-05-26 Jason Thorpe <thorpej@wasabisystems.com> + + * ns32k-tdep.c (ns32k_call_dummy_words, sizeof_ns32k_call_dummy_words, + ns32k_fix_call_dummy): New. + * config/ns32k/tm-umax.h (CALL_DUMMY_WORDS): Define as + ns32k_call_dummy_words. + (SIZEOF_CALL_DUMMY_WORDS): Define as sizeof_ns32k_call_dummy_words. + (CALL_DUMMY, CALL_DUMMY_LENGTH, CALL_DUMMY_ADDR, + CALL_DUMMY_NARGS): Remove. + (FIX_CALL_DUMMY): Define as ns32k_fix_call_dummy. + +2002-05-26 Jason Thorpe <thorpej@wasabisystems.com> + + * ns32k-tdep.c (ns32k_breakpoint_from_pc, ns32k_frame_chain, + ns32k_frame_saved_pc, ns32k_frame_args_address, + ns32k_frame_locals_address, ns32k_frame_init_saved_regs, + ns32k_push_dummy_frame, ns32k_pop_frame): New functions. + * config/ns32k/tm-nbsd.h (FRAME_SAVED_PC): Remove. + * config/ns32k/tm-umax.h (INNER_THAN): Define as core_addr_lessthan. + (BREAKPOINT_FROM_PC): Define as ns32k_breakpoint_from_pc. + (BREAKPOINT): Remove.. + (FRAME_CHAIN): Define as ns32k_frame_chain. + (FRAME_SAVED_PC): Define as ns32k_frame_saved_pc. + (FRAME_ARGS_ADDRESS): Define as ns32k_frame_args_address. + (FRAME_LOCALS_ADDRESS): Define as ns32k_frame_locals_address. + (FRAME_FIND_SAVED_REGS): Remove. + (FRAME_INIT_SAVED_REGS): Define as ns32k_frame_init_saved_regs. + (PUSH_DUMMY_FRAME): Define as ns32k_push_dummy_frame. + (POP_FRAME): Define as ns32k_pop_frame. + +2002-05-26 Jason Thorpe <thorpej@wasabisystems.com> + + * ns32k-tdep.c (ns32k_register_byte_32082, + ns32k_register_byte_32382, ns32k_register_raw_size, + ns32k_register_virtual_size, ns32k_register_virtual_type): New + functions. + * config/ns32k/tm-nbsd.h (REGISTER_BYTE): Define as + ns32k_register_byte_32382. + * config/ns32k/tm-umax.h: Update copyright years. + (REGISTER_BYTE): Define as ns32k_register_byte_32082. + (REGISTER_RAW_SIZE): Define as ns32k_register_raw_size. + (REGISTER_VIRTUAL_SIZE): Define as ns32k_register_virtual_size. + (REGISTER_VIRTUAL_TYPE): Define as ns32k_register_virtual_type. + (ns32k_get_enter_addr): Fix prototype. + +2002-05-26 Jason Thorpe <thorpej@wasabisystems.com> + + * ns32k-tdep.c: Update copyright years. + (ns32k_register_name_32082): New function. + (ns32k_register_name_32382): Ditto. + * config/ns32k/tm-nbsd.h (REGISTER_NAMES): Remove. + (REGISTER_NAME): Define as ns32k_register_name_32382. + * config/ns32k/tm-umax.h (REGISTER_NAMES): Remove. + (REGISTER_NAME): Define as ns32k_register_name_32082. + +2002-05-24 Jim Blandy <jimb@redhat.com> + + * dwarf2read.c (free_line_header): Use xfree, not free. + +2002-05-24 Jason Thorpe <thorpej@wasabisystems.com> + + * config/djgpp/fnchange.lst: Add alphabsd-nat.c, + alphabsd-tdep.c, mipsnbsd-nat.c, and mipsnbsd-tdep.c + +2002-05-23 Andrew Cagney <ac131313@redhat.com> + + * PROBLEMS: Mention s390 and FreeBSD 4.4 build problems. + +2002-05-23 Andrew Cagney <ac131313@redhat.com> + + From Ross Alexander at NEC Europe: + * config/pa/hpux11w.mh (NATDEPFILES): Add solib.o. + +2002-05-23 Michael Snyder <msnyder@redhat.com> + + * cli/cli-dump.c (restore_command): Use parse_and_eval_long + for input, rather than parse_and_eval_address. + +2002-05-23 Andrew Cagney <ac131313@redhat.com> + + * d10v-tdep.c: Include "gdb/sim-d10v.h" instead of "sim-d10v.h". + * Makefile.in (sim_d10v_h): Update definition. + +2002-05-24 Andrew Cagney <cagney@redhat.com> + + * d10v-tdep.c (d10v_gdbarch_init): Revert old code included in + change `2002-05-22 Michael Snyder' below. + (d10v_push_arguments): Ditto. + (d10v_extract_return_value): Ditto. + +2002-05-23 Jim Blandy <jimb@redhat.com> + + * macrotab.c (check_for_redefinition): Don't complain if the new + definition is the same as the previous one. Take more arguments + to allow the comparison. + (macro_define_object, macro_define_function): Pass more arguments + to check_for_redefinition. + +2002-05-22 Michael Snyder <msnyder@redhat.com> + + * d10v-tdep.c: Change a few macros to enums for ease of debugging. + (d10v_frame_chain_valid): Add PC_IN_CALL_DUMMY clause. + (d10v_frame_saved_pc): Add PC_IN_CALL_DUMMY clause. + (d10v_frame_chain): Bail immediately if PC_IN_CALL_DUMMY. + Don't bail if return_pc is PC_IN_CALL_DUMMY. + Add a temp variable to save a call (and a memory read). + (d10v_init_extra_frame_info): Get fi->pc from callee's return_pc + if possible (so that PC_IN_CALL_DUMMY will work). + +2002-05-22 Corinna Vinschen <vinschen@redhat.com> + + * MAINTAINERS: Remove status `OBSOLETE' from v850. + +2002-05-22 Michal Ludvig <mludvig@suse.cz> + + * dwarf2cfi.c (frame_state_for): Added safety check for a valid + fde->cie_ptr. + (dwarf2_build_frame_info): Corrected handling of eh_frame. + (dwarf2_build_frame_info): Add offset to fde->initial_location + so that frames of shared libraries are mapped correctly. + (execute_stack_op): Change type of 'result' from ULONGEST to + CORE_ADDR. + +2002-05-22 Jason Thorpe <thorpej@wasabisystems.com> + + * config/alpha/tm-nbsd.h: Include solib.h. + +2002-05-22 Jason Thorpe <thorpej@wasabisystems.com> + + * alphanbsd-tdep.c (alphanbsd_sigtramp_offset): Don't make + assumptions about the host's byte order. + +2002-05-22 Jason Thorpe <thorpej@wasabisystems.com> + + * Makefile.in (alphanbsd-tdep.o, shnbsd-tdep.o): Add solib-svr4.h + to dependency list. + * alphanbsd-tdep.c: Include solib-svr4.h. + * shnbsd-tdep.c: Ditto. + +2002-05-22 Jason Thorpe <thorpej@wasabisystems.com> + + * Makefile.in (armnbsd-tdep.o): Add solib-svr4.h and + nbsd-tdep.h to dependency list. + * configure.host (arm*-*-netbsdelf*, arm*-*-netbsd*, + i[3456]86-*-netbsdaout*, i[3456]86-*-netbsd*, m68*-*-netbsd*, + ns32k-*-netbsd*, sparc-*-netbsdaout*, sparc-*-netbsd*): Use + nbsdaout.mh and nbsdelf.mh consistently. + * configure.tgt (i[3456]86-*-netbsd*, m68*-*-netbsd*, + ns32k-*-netbsd*, sparc-*-netbsdelf*, sparc-*-netbsd*) Use + nbsdaout.mt and nbsdelf.mh consistently. + * armnbsd-tdep.c: Include nbsd-tdep.h and solib-svr4.h. + (arm_netbsd_elf_init_abi): Use set_solib_svr4_fetch_link_map_offsets + to set nbsd_ilp32_solib_svr4_fetch_link_map_offsets. + * config/nm-nbsd.h: Garbage-collect SVR4_SHARED_LIBS. Move + a.out shared library stuff from here... + * config/nm-nbsdaout.h: ...to here. + * config/tm-nbsd.h: Remove. + * config/alpha/nm-nbsd.h (SVR4_SHARED_LIBS): Remove. + * config/arm/nbsd.mh: Remove. + * config/arm/nbsd.mt (TDEPFILES): Remove solib-sunos.o, add + nbsd-tdep.o. + * config/arm/nbsdaout.mh: New file. + * config/arm/nbsdelf.mh: New file. + * config/arm/nm-nbsdaout.h: New file. + * config/i386/nbsd.mh: Remove. + * config/i386/nbsd.mt: Remove. + * config/i386/nbsdaout.mh: New file. + * config/i386/nbsdaout.mt: New file. + * config/i386/nbsdelf.mh (NAT_FILE): Use nm-nbsd.h. + * config/i386/nbsdelf.mt (TM_FILE): Use tm-nbsd.h. + * config/i386/nm-nbsd.h (REGISTER_U_ADDR, + i386_register_u_addr): Remove. + * config/i386/nm-nbsdaout.h: New file. + * config/i386/nm-nbsdelf.h: Remove. + * config/i386/tm-nbsd.h: Don't include config/tm-nbsd.h. + (USE_STRUCT_CONVENTION): Remove. + * config/i386/tm-nbsdaout.h: New file. + * config/i386/tm-nbsdelf.h: Remove. + * config/m68k/nbsd.mh: Remove. + * config/m68k/nbsd.mt: Remove. + * config/m68k/nbsdaout.mh: New file. + * config/m68k/nbsdaout.mt: New file. + * config/m68k/nm-nbsd.h: Use config/nm-nbsd.h. + * config/m68k/nm-nbsdaout.h: New file. + * config/m68k/tm-nbsd.h: Don't include config/tm-nbsd.h. + (IN_SOLIB_CALL_TRAMPOLINE): Define. + * config/ns32k/nbsd.mh: Remove. + * config/ns32k/nbsd.mt: Remove. + * config/ns32k/nbsdaout.mh: New file. + * config/ns32k/nbsdaout.mt: New file. + * config/ns32k/nm-nbsd.h: Include config/nm-nbsd.h. + * config/ns32k/nm-nbsdaout.h: New file. + * config/ns32k/tm-nbsd.h: Don't include config/tm-nbsd.h. + (IN_SOLIB_CALL_TRAMPOLINE): Define. + * config/powerpc/nm-nbsd.h: Include config/nm-nbsd.h. + (SVR4_SHARED_LIBS): Remove. + * config/powerpc/tm-nbsd.h: Dont' include config/tm-nbsd.h. + * config/sparc/nbsd.mh: Remove. + * config/sparc/nbsd.mt: Remove. + * config/sparc/nbsdaout.mh: New file. + * config/sparc/nbsdaout.mt: New file. + * config/sparc/nbsdelf.mh (NAT_FILE): Use nm-nbsd.h. + * config/sparc/nbsdelf.mt: New file. + * config/sparc/nm-nbsdaout.h: New file. + * config/sparc/nm-nbsdelf.h: Remove. + * config/sparc/tm-nbsd.h: Don't include config/tm-nbsd.h. + * config/sparc/tm-nbsdaout.h: New file. + +2002-05-21 Jason Thorpe <thorpej@wasabisystems.com> + + * Makefile.in (ALLDEPFILES): Add mipsnbsd-nat.c and + mipsnbsd-tdep.c + (mipsnbsd-nat.o, mipsnbsd-tdep.o): New dependency lists. + +2002-05-21 Jason Thorpe <thorpej@wasabisystems.com> + + * Makefile.in (ALLDEPFILES): Add shnbsd-tdep.c and + shnbsd-nat.c. + (shnbsd-tdep.o, shnbsd-nat.o): New dependency lists. + +2002-05-21 Jason Thorpe <thorpej@wasabisystems.com> + + * NEWS: Note new MIPS NetBSD native configuration. + * configure.host (mips*-*-netbsd*): New host. + * configure.tgt (mips*-*-netbsd*): New target. + * mipsnbsd-nat.c: New file. + * mipsnbsd-tdep.c: New file. + * mipsnbsd-tdep.h: New file. + * config/mips/nbsd.mh: New file. + * config/mips/nbsd.mt: New file. + * config/mips/nm-nbsd.h: New file. + * config/mips/tm-nbsd.h: New file. + +2002-05-21 Jason Thorpe <thorpej@wasabisystems.com> + + * Makefile.in (SFILES): Add osabi.c. + (COMMON_OBS): Add osabi.o. + (osabi.o): New dependency list. + * osabi.c: New file. + * osabi.h: New file. + * doc/gdbint.texinfo: Document new generic OS ABI framework. + + * Makefile.in (alpha_tdep_h): Define and use instead of + alpha-tdep.h. + * alpha-tdep.c (alpha_abi_names, process_note_abi_tag_sections, + get_elfosabi, alpha_abi_handler_list, alpha_gdbarch_register_os_abi): + Remove. + (alpha_gdbarch_init, alpha_dump_tdep): Use generic OS ABI framework. + * alpha-tdep.h: Include osabi.h. + (alpha_abi): Remove. + (gdbarch_tdep): Use generic OS ABI framework. + * alpha-linux-tdep.c (_initialize_alpha_linux_tdep): Use + gdbarch_register_osabi. + * alpha-osf1-tdep.c (_initialize_alpha_osf1_tdep): Likewise. + * alphafbsd-tdep.c (_initialize_alphafbsd_tdep): Likewise. + * alphanbsd-tdep.c (_initialize_alphanbsd_tdep): Likewise. + + * Makefile.in (sh_tdep_h): Add osabi.h. + * sh-tdep.h (sh_osabi): Remove. + (gdbarch_tdep): Use generic OS ABI framework. + * sh-tdep.c (sh_osabi_names, process_note_abi_tag_sections, + sh_osabi_handler_list, sh_gdbarch_register_os_abi): Remove. + (sh_gdbarch_init, sh_dump_tdep): Use generic OS ABI framework. + * shnbsd-tdep.c (_initialize_shnbsd_tdep): Use gdbarch_register_osabi. + + * Makefile.in (arm_tdep_h): Define and use instead of arm-tdep.h. + * arm-linux-tdep.c (_initialize_arm_linux_tdep): Use + gdbarch_register_osabi. + * arm-tdep.c (arm_abi_names, process_note_abi_tag_sections, + arm_abi_handler_list, arm_gdbarch_register_os_abi): Remove. + (get_elfosabi): Rename to... + (arm_elf_osabi_sniffer): ...this. Adjust to use generic OS + ABI framework support routines. + (arm_gdbarch_init): Use generic OS ABI framework. + (arm_dump_tdep): Likewise. + (_initialize_arm_tdep): Likewise. + * arm-tdep.h: Include osabi.h. + (arm_abi): Remove. + (gdbarch_tdep): Remove arm_abi and abi_name members. Add + osabi member. + (arm_gdbarch_register_os_abi): Remove prototype. + * armnbsd-tdep.c (arm_netbsd_aout_osabi_sniffer): New function. + (_initialize_arm_netbsd_tdep): Use gdbarch_register_osabi. + + * Makefile.in (mips-tdep.o): Add osabi.h to dependency list. + * mips-tdep.c: Include osabi.h. + (gdbarch_tdep, mips_gdbarch_init, mips_dump_tdep): Use generic + OS ABI framework. + +2002-05-20 Kazu Hirata <kazu@cs.umass.edu> + + * h8300-tdep.c: Fix formatting. + +2002-05-20 Elena Zannoni <ezannoni@redhat.com> + + * rs6000-tdep.c (rs6000_do_registers_info): Simplify code for + printing vector registers. + +2002-05-19 Andrew Cagney <ac131313@redhat.com> + + From Fernando Nasser: + * remote.c (remote_async_open_1): Re-throw the exception when the + connection fails. + (remote_cisco_open): Ditto. + (remote_open_1): Ditto. + +2002-05-19 Andrew Cagney <ac131313@redhat.com> + + * remote.c (remote_start_remote_dummy): Add uiout parameter. + (remote_start_remote): Add uiout parameter. Pass through to + remote_start_remote_dummy. + (remote_open_1): Use catch_exception instead of catch_errors. + (remote_async_open_1): Ditto. + (remote_cisco_open): Ditto. + +2002-05-19 Andrew Cagney <ac131313@redhat.com> + + * remote.c (remote_start_remote): Replace PTR with void pointer. + (sigint_remote_twice_token, sigint_remote_token): Ditto. Make + static. + +2002-05-18 Andrew Cagney <ac131313@redhat.com> + + * gdb_indent.sh: Allow the script to be run in the sim directory. + +2002-05-18 Mark Kettenis <kettenis@gnu.org> + + * config/i386/nm-cygwin.h (NO_PTRACE_H): Remove define. + * config/i386/nm-go32.h (NO_PTRACE_H): Remove define. + + * corelow.c (core_open): Only call set_gdbarch_from_file if + exec_bfd is NULL. + +2002-05-17 Andrey Volkov <avolkov@transas.com> + + * h8300-tdep.c: Add support of EXR register + * config/h8300/tm-h8300.h: Ditto. + +2002-05-17 Andrey Volkov <avolkov@transas.com> + + * h8300-tdep.c: Add additional CCR flags (I,UI,H,U) + +2002-05-17 Andrey Volkov <avolkov@transas.com> + + * h8300-tdep.c: Change literal regnums to REGNO. + +2002-05-17 Jim Blandy <jimb@redhat.com> + + * NEWS: Note addition of macro support. + + Expand preprocessor macros in C expressions. + * c-lang.h: #include "macroexp.h", for macro_lookup_ftype. + (scan_macro_expansion, scanning_macro_expansion, + finished_macro_expansion): New function declarations. + (expression_macro_lookup_func, expression_macro_lookup_baton): New + variable declarations. + * parser-defs.h (expression_context_pc): New declaration. + * parse.c (expression_context_pc): New variable. + (parse_exp_1): Set expression_context_pc, as well as + expression_context_block. + * c-exp.y (yylex): If we're not already reading the result of a + macro expansion, try to macro-expand the next token. When we're + done scanning a macro expansion, switch back to the mainline text. + Commas and `if's in a macro's expansion don't terminate the input. + * c-lang.c: #include "macroscope.h" and "gdb_assert.h". + (macro_original_text, macro_expanded_text, + expression_macro_lookup_func, expression_macro_lookup_baton): New + variables. + (scan_macro_expansion, scanning_macro_expansion, + finished_macro_expansion, scan_macro_cleanup, null_macro_lookup, + c_preprocess_and_parse): New functions. + (c_language_defn, cplus_language_defn, asm_language_defn): Call + c_preprocess_and_parse, instead of c_parse. + * Makefile.in (c_lang_h): Note that this #includes macroexp.h. + (c-lang.o): Note dependency on macroscope.h and gdb_assert.h. + +Fri May 17 14:26:19 2002 J"orn Rennecke <joern.rennecke@superh.com> + + * sh-tdep.c (gdb_print_insn_sh64): Delete. + (gdb_print_insn_sh): Just set info->endian and use print_insn_sh. + (sh_gdbarch_init): Always use gdb_print_insn_sh. + +2002-05-17 Corinna Vinschen <vinschen@redhat.com> + + * NEWS: Add section for multi-arched targets. Add v850 to that section. + +2002-05-17 Jason Thorpe <thorpej@wasabisystems.com> + + * Makefile.in (sh_tdep_h): Define and use. + * config/sh/tm-sh.h (sh_osabi, sh_abi, gdbarch_tdep, + register enum): Move to... + * * sh-tdep.h: ...here. + * sh-tdep.c: Include sh-tdep.h. + * sh3-rom.c: Likewise. + * shnbsd-tdep.c: Likewise. + +2002-05-16 Michael Snyder <msnyder@redhat.com> + + * arm-tdep.c: Spelling fix in comment. + +2002-05-16 Jim Blandy <jimb@redhat.com> + + Add commands for manually expanding macros and showing their + definitions. + * macrocmd.c, macroscope.c, macroscope.h: New files. + * Makefile.in (SFILES): Add macrocmd.c, macroscope.c. + (macroscope_h): New variable. + (HFILES_NO_SRCDIR): Add macroscope.h. + (COMMON_OBS): Add macrocmd.o, macroscope.o. + (macroscope.o, macrocmd.o): New rules. + + Teach the Dwarf 2 reader to read macro information. + * dwarf2read.c: #include "macrotab.h". + (dwarf_macinfo_buffer): New variable. + (struct dwarf2_pinfo): New members: dwarf_macinfo_buffer, and + dwarf_macinfo_size. + (DWARF_MACINFO_BUFFER, DWARF_MACINFO_SIZE): New macros. + (dwarf2_missing_macinfo_section, dwarf2_macros_too_long, + dwarf2_macros_not_terminated, dwarf2_macro_outside_file, + dwarf2_macro_unmatched_end_file, dwarf2_macro_malformed_definition, + dwarf2_macro_spaces_in_definition): New complaints. + (dwarf2_has_info): Initialize dwarf_macinfo_offset. + (dwarf2_build_psymtabs): Read the .dwarf_macinfo section. + (dwarf2_build_psymtabs_hard): Record the buffer and its size in + the partial symbol table. + (psymtab_to_symtab_1): Set the macinfo buffer and size globals + from what's recorded in the partial symbol table. + (read_file_scope): If the compilation unit has a + `DW_AT_macro_info' attribute, read its macro information. + * Makefile.in (dwarf2read.o): Depend on macrotab.h. + +2002-05-16 Daniel Jacobowitz <drow@mvista.com> + + Fix PR gdb/546 + * ser-tcp.c: Don't include <netinet/udp.h>. + +2002-05-16 Stephane Carrez <stcarrez@nerim.fr> + + * MAINTAINERS: Update my email address. + +2002-05-16 Richard Earnshaw <rearnsha@arm.com> + + * config/arm/nm-nbsd.h: Use "config/nm-nbsd.h" to include generic + include file of the same name. + +2002-05-16 Corinna Vinschen <vinschen@redhat.com> + + * configure.tgt: Mark v850 as multi-arched. + * config/v850/tm-v850.h: Remove file. + * config/v850/v850.mt: Eliminate TM_FILE. + +2002-05-16 Corinna Vinschen <vinschen@redhat.com> + + * v850-tdep.c: Full multi-arch. + * config/v850/tm-v850.h: Eliminate or move to v850-tdep.c everything. + Define GDB_MULTI_ARCH to 2. + +2002-05-16 Pierre Muller <muller@ics.u-strasbg.fr> + + * p-exp.y (current_type): New static variable. + Carries the type of the expression at the position that is parsed. + (push_current_type, pop_current_type): Two new functions. Used + to store/restore current_type in expression on specific tokens. + (search_field): New static variable. Set to one after parsing a point + as at that point only a FIELDNAME token should be searched. + (FIELDNAME): New token. After a point only a token belonging to + current_type type definition is allowed. + (all over token rules): reset and change current_type according + to rules. + (exp '[' rule): insert implicit array index field if + exp is a pascal string type. + +2002-05-16 Corinna Vinschen <vinschen@redhat.com> + + * v850-tdep.c: Fix comment for v850_scan_prologue. Remove extra + frame info. Use frame_info's saved_regs instead of matching member + in extra_frame_info throughout. + (v850_frame_init_saved_regs): New function. + (v850_init_extra_frame_info): Move most functionality into + v850_frame_init_saved_regs(). + * config/v850/tm-v850.h (EXTRA_FRAME_INFO): Remove definition. + (v850_frame_find_saved_regs): Remove declaration. + (FRAME_FIND_SAVED_REGS): Remove definition. + (v850_frame_init_saved_regs): Add declaration. + (FRAME_INIT_SAVED_REGS): Add definition. + +2002-05-16 Corinna Vinschen <vinschen@redhat.com> + + * v850-tdep.c: Begin multi-arch'ing v850. + (v850_target_architecture_hook): Remove function. + (v850_gdbarch_init): New function. Add code previously in + v850_target_architecture_hook(). + (_initialize_v850_tdep): Don't set target_architecture_hook. + Call register_gdbarch_init() instead. + +2002-05-16 Daniel Jacobowitz <drow@mvista.com> + + * gdbtypes.h (struct cplus_struct_type): Remove args field. + * hpread.c (hpread_read_struct_type): Remove assignments to args. + (fixup_class_method_type): Likewise. + +2002-05-15 Daniel Jacobowitz <drow@mvista.com> + + From Martin Pool <mbp@samba.org>: + * gdbserver/server.c (gdbserver_usage): New function. + (main): Call it. + 2002-05-15 Jim Blandy <jimb@redhat.com> Add macro structures to GDB's symbol tables. Nobody puts anything diff --git a/gdb/MAINTAINERS b/gdb/MAINTAINERS index f86c42c484f..aa7257c4bbb 100644 --- a/gdb/MAINTAINERS +++ b/gdb/MAINTAINERS @@ -72,7 +72,7 @@ maintainer works with the native maintainer when resolving API issues. avr --target=avr ,-Werror Theodore A. Roth troth@verinet.com - cris --target=cris-elf -w + cris --target=cris-elf ,-Werror Orjan Friberg orjanf@axis.com d10v --target=d10v-elf ,-Werror diff --git a/gdb/ada-lang.c b/gdb/ada-lang.c index 2c4f1d94d41..db1d7d4f185 100644 --- a/gdb/ada-lang.c +++ b/gdb/ada-lang.c @@ -4280,15 +4280,7 @@ ada_add_block_symbols (block, name, namespace, objfile, wild) /* Function Types */ /* Assuming that SYM is the symbol for a function, fill in its type - with prototype information, if it is not already there. - - Why is there provision in struct type for BOTH an array of argument - types (TYPE_ARG_TYPES) and for an array of typed fields, whose - comment suggests it may also represent argument types? I presume - this is some attempt to save space. The problem is that argument - names in Ada are significant. Therefore, for Ada we use the - (apparently older) TYPE_FIELD_* stuff to store argument types. */ - + with prototype information, if it is not already there. */ static void fill_in_ada_prototype (func) diff --git a/gdb/alpha-tdep.c b/gdb/alpha-tdep.c index 8a87a8a5e50..564896fdc94 100644 --- a/gdb/alpha-tdep.c +++ b/gdb/alpha-tdep.c @@ -277,7 +277,7 @@ push_sigtramp_desc (CORE_ADDR low_addr) } -static char * +static const char * alpha_register_name (int regno) { static char *register_names[] = @@ -649,11 +649,13 @@ heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, struct frame_info *next_frame) { CORE_ADDR sp = read_next_frame_reg (next_frame, SP_REGNUM); + CORE_ADDR vfp = sp; CORE_ADDR cur_pc; int frame_size; int has_frame_reg = 0; unsigned long reg_mask = 0; int pcreg = -1; + int regno; if (start_pc == 0) return NULL; @@ -678,7 +680,12 @@ heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, if ((word & 0xffff0000) == 0x23de0000) /* lda $sp,n($sp) */ { if (word & 0x8000) - frame_size += (-word) & 0xffff; + { + /* Consider only the first stack allocation instruction + to contain the static size of the frame. */ + if (frame_size == 0) + frame_size += (-word) & 0xffff; + } else /* Exit loop if a positive stack adjustment is found, which usually means that the stack cleanup code in the function @@ -690,7 +697,16 @@ heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, { int reg = (word & 0x03e00000) >> 21; reg_mask |= 1 << reg; - temp_saved_regs[reg] = sp + (short) word; + + /* Do not compute the address where the register was saved yet, + because we don't know yet if the offset will need to be + relative to $sp or $fp (we can not compute the address relative + to $sp if $sp is updated during the execution of the current + subroutine, for instance when doing some alloca). So just store + the offset for the moment, and compute the address later + when we know whether this frame has a frame pointer or not. + */ + temp_saved_regs[reg] = (short) word; /* Starting with OSF/1-3.2C, the system libraries are shipped without local symbols, but they still contain procedure @@ -719,8 +735,15 @@ heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, } else if ((word & 0xffe0ffff) == 0x6be08001) /* ret zero,reg,1 */ pcreg = (word >> 16) & 0x1f; - else if (word == 0x47de040f) /* bis sp,sp fp */ - has_frame_reg = 1; + else if (word == 0x47de040f || word == 0x47fe040f) /* bis sp,sp fp */ + { + /* ??? I am not sure what instruction is 0x47fe040f, and I + am suspecting that there was a typo and should have been + 0x47fe040f. I'm keeping it in the test above until further + investigation */ + has_frame_reg = 1; + vfp = read_next_frame_reg (next_frame, ALPHA_GCC_FP_REGNUM); + } } if (pcreg == -1) { @@ -759,6 +782,18 @@ heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc, PROC_FRAME_REG (&temp_proc_desc) = ALPHA_GCC_FP_REGNUM; else PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM; + + /* At this point, we know which of the Stack Pointer or the Frame Pointer + to use as the reference address to compute the saved registers address. + But in both cases, the processing above has set vfp to this reference + address, so just need to increment the offset of each saved register + by this address. */ + for (regno = 0; regno < NUM_REGS; regno++) + { + if (reg_mask & 1 << regno) + temp_saved_regs[regno] += vfp; + } + PROC_FRAME_OFFSET (&temp_proc_desc) = frame_size; PROC_REG_MASK (&temp_proc_desc) = reg_mask; PROC_PC_REG (&temp_proc_desc) = (pcreg == -1) ? ALPHA_RA_REGNUM : pcreg; diff --git a/gdb/arch-utils.c b/gdb/arch-utils.c index c0569f2a110..d60eeb36ed7 100644 --- a/gdb/arch-utils.c +++ b/gdb/arch-utils.c @@ -118,6 +118,22 @@ legacy_register_sim_regno (int regnum) } int +legacy_register_sim_regno (int regnum) +{ + /* Only makes sense to supply raw registers. */ + gdb_assert (regnum >= 0 && regnum < NUM_REGS); + /* NOTE: cagney/2002-05-13: The old code did it this way and it is + suspected that some GDB/SIM combinations may rely on this + behavour. The default should be one2one_register_sim_regno + (below). */ + if (REGISTER_NAME (regnum) != NULL + && REGISTER_NAME (regnum)[0] != '\0') + return regnum; + else + return LEGACY_SIM_REGNO_IGNORE; +} + +int generic_frameless_function_invocation_not (struct frame_info *fi) { return 0; @@ -147,7 +163,7 @@ generic_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) return 0; } -char * +const char * legacy_register_name (int i) { #ifdef REGISTER_NAMES diff --git a/gdb/arch-utils.h b/gdb/arch-utils.h index 9dfa70cefdc..7ceb8b70b84 100644 --- a/gdb/arch-utils.h +++ b/gdb/arch-utils.h @@ -52,7 +52,7 @@ extern gdbarch_frameless_function_invocation_ftype generic_frameless_function_in extern gdbarch_return_value_on_stack_ftype generic_return_value_on_stack_not; /* Map onto old REGISTER_NAMES. */ -extern char *legacy_register_name (int i); +extern const char *legacy_register_name (int i); /* Accessor for old global function pointer for disassembly. */ extern int legacy_print_insn (bfd_vma vma, disassemble_info *info); diff --git a/gdb/avr-tdep.c b/gdb/avr-tdep.c index 43ac3098c72..79f8d6b3a06 100644 --- a/gdb/avr-tdep.c +++ b/gdb/avr-tdep.c @@ -158,7 +158,7 @@ struct gdbarch_tdep /* Lookup the name of a register given it's number. */ -static char * +static const char * avr_register_name (int regnum) { static char *register_names[] = { diff --git a/gdb/breakpoint.c b/gdb/breakpoint.c index 1861370eaa7..187061e45e7 100644 --- a/gdb/breakpoint.c +++ b/gdb/breakpoint.c @@ -553,6 +553,7 @@ condition_command (char *arg, int from_tty) error ("Junk at end of expression"); } breakpoints_changed (); + breakpoint_modify_event (b->number); return; } @@ -592,6 +593,7 @@ commands_command (char *arg, int from_tty) free_command_lines (&b->commands); b->commands = l; breakpoints_changed (); + breakpoint_modify_event (b->number); return; } error ("No breakpoint number %d.", bnum); @@ -7071,18 +7073,20 @@ set_ignore_count (int bptnum, int count, int from_tty) if (b->number == bptnum) { b->ignore_count = count; - if (!from_tty) - return; - else if (count == 0) - printf_filtered ("Will stop next time breakpoint %d is reached.", - bptnum); - else if (count == 1) - printf_filtered ("Will ignore next crossing of breakpoint %d.", - bptnum); - else - printf_filtered ("Will ignore next %d crossings of breakpoint %d.", - count, bptnum); + if (from_tty) + { + if (count == 0) + printf_filtered ("Will stop next time breakpoint %d is reached.", + bptnum); + else if (count == 1) + printf_filtered ("Will ignore next crossing of breakpoint %d.", + bptnum); + else + printf_filtered ("Will ignore next %d crossings of breakpoint %d.", + count, bptnum); + } breakpoints_changed (); + breakpoint_modify_event (b->number); return; } @@ -7119,8 +7123,8 @@ ignore_command (char *args, int from_tty) set_ignore_count (num, longest_to_int (value_as_long (parse_and_eval (p))), from_tty); - printf_filtered ("\n"); - breakpoints_changed (); + if (from_tty) + printf_filtered ("\n"); } /* Call FUNCTION on each of the breakpoints diff --git a/gdb/cli/cli-decode.c b/gdb/cli/cli-decode.c index 3f510ac87d1..a6fadd91360 100644 --- a/gdb/cli/cli-decode.c +++ b/gdb/cli/cli-decode.c @@ -53,8 +53,7 @@ do_cfunc (struct cmd_list_element *c, char *args, int from_tty) } void -set_cmd_cfunc (struct cmd_list_element *cmd, - void (*cfunc) (char *args, int from_tty)) +set_cmd_cfunc (struct cmd_list_element *cmd, cmd_cfunc_ftype *cfunc) { if (cfunc == NULL) cmd->func = NULL; @@ -70,9 +69,7 @@ do_sfunc (struct cmd_list_element *c, char *args, int from_tty) } void -set_cmd_sfunc (struct cmd_list_element *cmd, - void (*sfunc) (char *args, int from_tty, - struct cmd_list_element * c)) +set_cmd_sfunc (struct cmd_list_element *cmd, cmd_sfunc_ftype *sfunc) { if (sfunc == NULL) cmd->func = NULL; @@ -328,6 +325,35 @@ add_set_or_show_cmd (char *name, return c; } +/* Add element named NAME to both the command SET_LIST and SHOW_LIST. + CLASS is as in add_cmd. VAR_TYPE is the kind of thing we are + setting. VAR is address of the variable being controlled by this + command. SET_FUNC and SHOW_FUNC are the callback functions (if + non-NULL). SET_DOC and SHOW_DOC are the documentation strings. */ + +static struct cmd_list_element * +add_setshow_cmd (char *name, + enum command_class class, + var_types var_type, void *var, + char *set_doc, char *show_doc, + cmd_sfunc_ftype *set_func, cmd_sfunc_ftype *show_func, + struct cmd_list_element **set_list, + struct cmd_list_element **show_list) +{ + struct cmd_list_element *set; + struct cmd_list_element *show; + set = add_set_or_show_cmd (name, set_cmd, class, var_type, var, + set_doc, set_list); + if (set_func != NULL) + set_cmd_sfunc (set, set_func); + show = add_set_or_show_cmd (name, show_cmd, class, var_type, var, + show_doc, show_list); + if (show_func != NULL) + set_cmd_sfunc (show, show_func); + /* The caller often wants to modify set to include info like an + enumeration. */ + return set; +} struct cmd_list_element * add_set_cmd (char *name, @@ -363,42 +389,48 @@ add_set_enum_cmd (char *name, return c; } -/* Add element named NAME to command list LIST (the list for set - or some sublist thereof). - CLASS is as in add_cmd. - VAR is address of the variable which will contain the value. - DOC is the documentation string. */ -struct cmd_list_element * -add_set_auto_boolean_cmd (char *name, - enum command_class class, - enum cmd_auto_boolean *var, - char *doc, - struct cmd_list_element **list) +/* Add an auto-boolean command named NAME to both the set and show + command list lists. CLASS is as in add_cmd. VAR is address of the + variable which will contain the value. DOC is the documentation + string. FUNC is the corresponding callback. */ +void +add_setshow_auto_boolean_cmd (char *name, + enum command_class class, + enum auto_boolean *var, + char *set_doc, char *show_doc, + cmd_sfunc_ftype *set_func, + cmd_sfunc_ftype *show_func, + struct cmd_list_element **set_list, + struct cmd_list_element **show_list) { static const char *auto_boolean_enums[] = { "on", "off", "auto", NULL }; struct cmd_list_element *c; - c = add_set_cmd (name, class, var_auto_boolean, var, doc, list); + c = add_setshow_cmd (name, class, var_auto_boolean, var, + set_doc, show_doc, set_func, show_func, + set_list, show_list); c->enums = auto_boolean_enums; - return c; } -/* Add element named NAME to command list LIST (the list for set - or some sublist thereof). - CLASS is as in add_cmd. - VAR is address of the variable which will contain the value. - DOC is the documentation string. */ -struct cmd_list_element * -add_set_boolean_cmd (char *name, - enum command_class class, - int *var, - char *doc, - struct cmd_list_element **list) +/* Add element named NAME to both the set and show command LISTs (the + list for set/show or some sublist thereof). CLASS is as in + add_cmd. VAR is address of the variable which will contain the + value. SET_DOC and SHOW_DOR are the documentation strings. */ +void +add_setshow_boolean_cmd (char *name, + enum command_class class, + int *var, char *set_doc, char *show_doc, + cmd_sfunc_ftype *set_func, + cmd_sfunc_ftype *show_func, + struct cmd_list_element **set_list, + struct cmd_list_element **show_list) { static const char *boolean_enums[] = { "on", "off", NULL }; struct cmd_list_element *c; - c = add_set_cmd (name, class, var_boolean, var, doc, list); + c = add_setshow_cmd (name, class, var_boolean, var, + set_doc, show_doc, + set_func, show_func, + set_list, show_list); c->enums = boolean_enums; - return c; } /* Where SETCMD has already been added, add the corresponding show diff --git a/gdb/cli/cli-decode.h b/gdb/cli/cli-decode.h index 72436f04657..e8563ff5c59 100644 --- a/gdb/cli/cli-decode.h +++ b/gdb/cli/cli-decode.h @@ -69,12 +69,11 @@ struct cmd_list_element to one of the below. */ union { - /* If type is not_set_cmd, call it like this: */ - void (*cfunc) (char *args, int from_tty); - - /* If type is set_cmd or show_cmd, first set the variables, and - then call this. */ - void (*sfunc) (char *args, int from_tty, struct cmd_list_element * c); + /* If type is not_set_cmd, call it like this: */ + cmd_cfunc_ftype *cfunc; + /* If type is set_cmd or show_cmd, first set the variables, + and then call this: */ + cmd_sfunc_ftype *sfunc; } function; @@ -294,18 +293,6 @@ extern struct cmd_list_element *add_set_enum_cmd (char *name, char *doc, struct cmd_list_element **list); -extern struct cmd_list_element *add_set_auto_boolean_cmd (char *name, - enum command_class class, - enum cmd_auto_boolean *var, - char *doc, - struct cmd_list_element **list); - -extern struct cmd_list_element *add_set_boolean_cmd (char *name, - enum command_class class, - int *var, - char *doc, - struct cmd_list_element **list); - extern struct cmd_list_element *add_show_from_set (struct cmd_list_element *, struct cmd_list_element **); diff --git a/gdb/cli/cli-setshow.c b/gdb/cli/cli-setshow.c index f967b0c3eba..94ba94e16dd 100644 --- a/gdb/cli/cli-setshow.c +++ b/gdb/cli/cli-setshow.c @@ -34,9 +34,8 @@ static int parse_binary_operation (char *); -static enum cmd_auto_boolean parse_auto_binary_operation (const char *arg); -static enum cmd_auto_boolean +static enum auto_boolean parse_auto_binary_operation (const char *arg) { if (arg != NULL && *arg != '\0') @@ -48,18 +47,18 @@ parse_auto_binary_operation (const char *arg) || strncmp (arg, "1", length) == 0 || strncmp (arg, "yes", length) == 0 || strncmp (arg, "enable", length) == 0) - return CMD_AUTO_BOOLEAN_TRUE; + return AUTO_BOOLEAN_TRUE; else if (strncmp (arg, "off", length) == 0 || strncmp (arg, "0", length) == 0 || strncmp (arg, "no", length) == 0 || strncmp (arg, "disable", length) == 0) - return CMD_AUTO_BOOLEAN_FALSE; + return AUTO_BOOLEAN_FALSE; else if (strncmp (arg, "auto", length) == 0 || (strncmp (arg, "-1", length) == 0 && length > 1)) - return CMD_AUTO_BOOLEAN_AUTO; + return AUTO_BOOLEAN_AUTO; } error ("\"on\", \"off\" or \"auto\" expected."); - return CMD_AUTO_BOOLEAN_AUTO; /* pacify GCC */ + return AUTO_BOOLEAN_AUTO; /* pacify GCC */ } static int @@ -167,7 +166,7 @@ do_setshow_command (char *arg, int from_tty, struct cmd_list_element *c) *(int *) c->var = parse_binary_operation (arg); break; case var_auto_boolean: - *(enum cmd_auto_boolean *) c->var = parse_auto_binary_operation (arg); + *(enum auto_boolean *) c->var = parse_auto_binary_operation (arg); break; case var_uinteger: if (arg == NULL) @@ -296,15 +295,15 @@ do_setshow_command (char *arg, int from_tty, struct cmd_list_element *c) fputs_filtered (*(int *) c->var ? "on" : "off", stb->stream); break; case var_auto_boolean: - switch (*(enum cmd_auto_boolean*) c->var) + switch (*(enum auto_boolean*) c->var) { - case CMD_AUTO_BOOLEAN_TRUE: + case AUTO_BOOLEAN_TRUE: fputs_filtered ("on", stb->stream); break; - case CMD_AUTO_BOOLEAN_FALSE: + case AUTO_BOOLEAN_FALSE: fputs_filtered ("off", stb->stream); break; - case CMD_AUTO_BOOLEAN_AUTO: + case AUTO_BOOLEAN_AUTO: fputs_filtered ("auto", stb->stream); break; default: diff --git a/gdb/command.h b/gdb/command.h index db7a7402584..00110ce555d 100644 --- a/gdb/command.h +++ b/gdb/command.h @@ -51,14 +51,6 @@ typedef enum cmd_types } cmd_types; -/* Reasonable values for an AUTO_BOOLEAN variable. */ -enum cmd_auto_boolean -{ - CMD_AUTO_BOOLEAN_TRUE, - CMD_AUTO_BOOLEAN_FALSE, - CMD_AUTO_BOOLEAN_AUTO -}; - /* Types of "set" or "show" command. */ typedef enum var_types { @@ -67,9 +59,9 @@ typedef enum var_types var_boolean, /* "on" / "true" / "enable" or "off" / "false" / "disable" or - "auto. *VAR is an ``enum cmd_auto_boolean''. NOTE: In general - a custom show command will need to be implemented - one that - for "auto" prints both the "auto" and the current auto-selected + "auto. *VAR is an ``enum auto_boolean''. NOTE: In general a + custom show command will need to be implemented - one that for + "auto" prints both the "auto" and the current auto-selected value. */ var_auto_boolean, @@ -132,12 +124,14 @@ extern struct cmd_list_element *add_abbrev_prefix_cmd (char *, /* Set the commands corresponding callback. */ +typedef void cmd_cfunc_ftype (char *args, int from_tty); extern void set_cmd_cfunc (struct cmd_list_element *cmd, - void (*cfunc) (char *args, int from_tty)); + cmd_cfunc_ftype *cfunc); +typedef void cmd_sfunc_ftype (char *args, int from_tty, + struct cmd_list_element *c); extern void set_cmd_sfunc (struct cmd_list_element *cmd, - void (*sfunc) (char *args, int from_tty, - struct cmd_list_element * c)); + cmd_sfunc_ftype *sfunc); extern void set_cmd_completer (struct cmd_list_element *cmd, char **(*completer) (char *text, char *word)); @@ -229,17 +223,24 @@ extern struct cmd_list_element *add_set_enum_cmd (char *name, char *doc, struct cmd_list_element **list); -extern struct cmd_list_element *add_set_auto_boolean_cmd (char *name, - enum command_class class, - enum cmd_auto_boolean *var, - char *doc, - struct cmd_list_element **list); - -extern struct cmd_list_element *add_set_boolean_cmd (char *name, - enum command_class class, - int *var, - char *doc, - struct cmd_list_element **list); +extern void add_setshow_auto_boolean_cmd (char *name, + enum command_class class, + enum auto_boolean *var, + char *set_doc, char *show_doc, + cmd_sfunc_ftype *set_func, + cmd_sfunc_ftype *show_func, + struct cmd_list_element **set_list, + struct cmd_list_element **show_list); + +extern void add_setshow_boolean_cmd (char *name, + enum command_class class, + int *var, + char *set_doc, + char *show_doc, + cmd_sfunc_ftype *set_func, + cmd_sfunc_ftype *show_func, + struct cmd_list_element **set_list, + struct cmd_list_element **show_list); extern struct cmd_list_element *add_show_from_set (struct cmd_list_element *, struct cmd_list_element diff --git a/gdb/config/i386/tm-cygwin.h b/gdb/config/i386/tm-cygwin.h index 1d49133a05b..2710ef70ca3 100644 --- a/gdb/config/i386/tm-cygwin.h +++ b/gdb/config/i386/tm-cygwin.h @@ -25,7 +25,6 @@ #else #undef HAVE_SSE_REGS #endif /* CONTEXT_EXTENDED_REGISTERS */ -#define HAVE_I387_REGS #include "i386/tm-i386.h" diff --git a/gdb/config/i386/tm-fbsd.h b/gdb/config/i386/tm-fbsd.h index f51859d0b46..87d0e08b26c 100644 --- a/gdb/config/i386/tm-fbsd.h +++ b/gdb/config/i386/tm-fbsd.h @@ -21,7 +21,6 @@ #ifndef TM_FBSD_H #define TM_FBSD_H -#define HAVE_I387_REGS #include "i386/tm-i386.h" /* These defines allow the recognition of sigtramps as a function name diff --git a/gdb/config/i386/tm-go32.h b/gdb/config/i386/tm-go32.h index 79370e778a2..85e0888ef80 100644 --- a/gdb/config/i386/tm-go32.h +++ b/gdb/config/i386/tm-go32.h @@ -22,7 +22,6 @@ #define TM_GO32_H #undef HAVE_SSE_REGS /* FIXME! go32-nat.c needs to support XMMi registers */ -#define HAVE_I387_REGS #include "i386/tm-i386.h" diff --git a/gdb/config/i386/tm-i386.h b/gdb/config/i386/tm-i386.h index 0ea151b4a14..8ec3d4de852 100644 --- a/gdb/config/i386/tm-i386.h +++ b/gdb/config/i386/tm-i386.h @@ -32,249 +32,11 @@ struct frame_saved_regs; struct value; struct type; -/* Offset from address of function to start of its code. - Zero on most machines. */ - -#define FUNCTION_START_OFFSET 0 - -/* Advance PC across any function entry prologue instructions to reach some - "real" code. */ - -#define SKIP_PROLOGUE(frompc) (i386_skip_prologue (frompc)) - -extern int i386_skip_prologue (int); - -/* Stack grows downward. */ - -#define INNER_THAN(lhs,rhs) ((lhs) < (rhs)) - -/* Sequence of bytes for breakpoint instruction. */ - -#define BREAKPOINT {0xcc} - -/* Amount PC must be decremented by after a breakpoint. This is often the - number of bytes in BREAKPOINT but not always. */ - -#define DECR_PC_AFTER_BREAK 1 - -/* Say how long (ordinary) registers are. This is a piece of bogosity - used in push_word and a few other places; REGISTER_RAW_SIZE is the - real way to know how big a register is. */ - -#define REGISTER_SIZE 4 - -/* This register file is parameterized by two macros: - HAVE_I387_REGS --- register file should include i387 registers - HAVE_SSE_REGS --- register file should include SSE registers - If HAVE_SSE_REGS is #defined, then HAVE_I387_REGS must also be #defined. - - However, GDB code should not test those macros with #ifdef, since - that makes code which is annoying to multi-arch. Instead, GDB code - should check the values of NUM_GREGS, NUM_FREGS, and NUM_SSE_REGS, - which will eventually get mapped onto architecture vector entries. - - It's okay to use the macros in tm-*.h files, though, since those - files will get completely replaced when we multi-arch anyway. */ - -/* Number of general registers, present on every 32-bit x86 variant. */ -#define NUM_GREGS (16) - -/* Number of floating-point unit registers. */ -#ifdef HAVE_I387_REGS -#define NUM_FREGS (16) -#else -#define NUM_FREGS (0) -#endif - -/* Number of SSE registers. */ -#ifdef HAVE_SSE_REGS -#define NUM_SSE_REGS (9) -#else -#define NUM_SSE_REGS (0) -#endif - -/* Largest number of registers we could have in any configuration. */ -#define MAX_NUM_REGS (16 + 16 + 9 + 1) - -/* Register numbers of various important registers. - Note that some of these values are "real" register numbers, - and correspond to the general registers of the machine, - and some are "phony" register numbers which are too large - to be actual register numbers as far as the user is concerned - but do serve to get the desired values when passed to read_register. */ - -#define FP_REGNUM 5 /* (ebp) Contains address of executing stack - frame */ -#define SP_REGNUM 4 /* (usp) Contains address of top of stack */ -#define PC_REGNUM 8 /* (eip) Contains program counter */ -#define PS_REGNUM 9 /* (ps) Contains processor status */ - -/* First FPU data register. */ -#ifdef HAVE_I387_REGS -#define FP0_REGNUM 16 -#else -#define FP0_REGNUM 0 -#endif - - -/* Largest value REGISTER_RAW_SIZE can have. */ -#define MAX_REGISTER_RAW_SIZE 16 - -/* Return the size in bytes of the virtual type of register REG. */ -#define REGISTER_VIRTUAL_SIZE(reg) i386_register_virtual_size ((reg)) -extern int i386_register_virtual_size (int reg); - -/* Largest value REGISTER_VIRTUAL_SIZE can have. */ -#define MAX_REGISTER_VIRTUAL_SIZE 16 - -/* Return the GDB type object for the "standard" data type of data in - register REGNUM. */ - -#define REGISTER_VIRTUAL_TYPE(regnum) i386_register_virtual_type (regnum) -extern struct type *i386_register_virtual_type (int regnum); - -/* Return true iff register REGNUM's virtual format is different from - its raw format. */ - -#define REGISTER_CONVERTIBLE(regnum) i386_register_convertible (regnum) -extern int i386_register_convertible (int regnum); - -/* Convert data from raw format for register REGNUM in buffer FROM to - virtual format with type TYPE in buffer TO. */ - -#define REGISTER_CONVERT_TO_VIRTUAL(regnum, type, from, to) \ - i386_register_convert_to_virtual ((regnum), (type), (from), (to)) -extern void i386_register_convert_to_virtual (int regnum, struct type *type, - char *from, char *to); - -/* Convert data from virtual format with type TYPE in buffer FROM to - raw format for register REGNUM in buffer TO. */ - -#define REGISTER_CONVERT_TO_RAW(type, regnum, from, to) \ - i386_register_convert_to_raw ((type), (regnum), (from), (to)) -extern void i386_register_convert_to_raw (struct type *type, int regnum, - char *from, char *to); - /* Print out the i387 floating point state. */ -#ifdef HAVE_I387_REGS extern void i387_float_info (void); #define FLOAT_INFO { i387_float_info (); } -#endif - - -#define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \ - i386_push_arguments ((nargs), (args), (sp), (struct_return), (struct_addr)) -extern CORE_ADDR i386_push_arguments (int nargs, struct value **args, - CORE_ADDR sp, int struct_return, - CORE_ADDR struct_addr); - -/* Store the address of the place in which to copy the structure the - subroutine will return. This is called from call_function. */ - -#define STORE_STRUCT_RETURN(addr, sp) \ - i386_store_struct_return ((addr), (sp)) -extern void i386_store_struct_return (CORE_ADDR addr, CORE_ADDR sp); - -/* Extract from an array REGBUF containing the (raw) register state - a function return value of type TYPE, and copy that, in virtual format, - into VALBUF. */ - -#define DEPRECATED_EXTRACT_RETURN_VALUE(type, regbuf, valbuf) \ - i386_extract_return_value ((type), (regbuf), (valbuf)) -extern void i386_extract_return_value (struct type *type, char *regbuf, - char *valbuf); - -/* Write into the appropriate registers a function return value stored - in VALBUF of type TYPE, given in virtual format. */ - -#define STORE_RETURN_VALUE(type, valbuf) \ - i386_store_return_value ((type), (valbuf)) -extern void i386_store_return_value (struct type *type, char *valbuf); - -/* Extract from an array REGBUF containing the (raw) register state - the address in which a function should return its structure value, - as a CORE_ADDR. */ - -#define DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS(regbuf) \ - i386_extract_struct_value_address ((regbuf)) -extern CORE_ADDR i386_extract_struct_value_address (char *regbuf); - -/* Determine whether the function invocation represented by FRAME does - not have a from on the stack associated with it. If it does not, - return non-zero, otherwise return zero. */ - -#define FRAMELESS_FUNCTION_INVOCATION(frame) \ - i386_frameless_function_invocation (frame) -extern int i386_frameless_function_invocation (struct frame_info *frame); - -#define FRAME_ARGS_ADDRESS(fi) ((fi)->frame) - -#define FRAME_LOCALS_ADDRESS(fi) ((fi)->frame) - -/* Return number of args passed to a frame. Can return -1, meaning no way - to tell, which is typical now that the C compiler delays popping them. */ - -#define FRAME_NUM_ARGS(fi) (i386_frame_num_args(fi)) - -extern int i386_frame_num_args (struct frame_info *); - -/* Return number of bytes at start of arglist that are not really args. */ - -#define FRAME_ARGS_SKIP 8 - -/* Put here the code to store, into a struct frame_saved_regs, - the addresses of the saved registers of frame described by FRAME_INFO. - This includes special registers such as pc and fp saved in special - ways in the stack frame. sp is even more special: - the address we return for it IS the sp for the next frame. */ - -extern void i386_frame_init_saved_regs (struct frame_info *); -#define FRAME_INIT_SAVED_REGS(FI) i386_frame_init_saved_regs (FI) - - - -/* Things needed for making the inferior call functions. */ - -/* "An argument's size is increased, if necessary, to make it a - multiple of [32 bit] words. This may require tail padding, - depending on the size of the argument" - from the x86 ABI. */ -#define PARM_BOUNDARY 32 - -/* Push an empty stack frame, to record the current PC, etc. */ - -#define PUSH_DUMMY_FRAME { i386_push_dummy_frame (); } - -extern void i386_push_dummy_frame (void); - -/* Discard from the stack the innermost frame, restoring all registers. */ - -#define POP_FRAME { i386_pop_frame (); } - -extern void i386_pop_frame (void); -/* this is - * call 11223344 (32 bit relative) - * int3 - */ - -#define CALL_DUMMY { 0x223344e8, 0xcc11 } - -#define CALL_DUMMY_LENGTH 8 - -#define CALL_DUMMY_START_OFFSET 0 /* Start execution at beginning of dummy */ - -#define CALL_DUMMY_BREAKPOINT_OFFSET 5 - -/* Insert the specified number of args and function address - into a call sequence of the above form stored at DUMMYNAME. */ - -#define FIX_CALL_DUMMY(dummyname, pc, fun, nargs, args, type, gcc_p) \ - i386_fix_call_dummy (dummyname, pc, fun, nargs, args, type, gcc_p) -extern void i386_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, - int nargs, struct value **args, - struct type *type, int gcc_p); - /* FIXME: kettenis/2000-06-12: These do not belong here. */ extern void print_387_control_word (unsigned int); extern void print_387_status_word (unsigned int); diff --git a/gdb/config/i386/tm-i386gnu.h b/gdb/config/i386/tm-i386gnu.h index f1835423a72..638cb03f2a0 100644 --- a/gdb/config/i386/tm-i386gnu.h +++ b/gdb/config/i386/tm-i386gnu.h @@ -39,7 +39,6 @@ FIXME: This is probably native-dependent too. */ #define ATTACH_DETACH 1 -#define HAVE_I387_REGS #include "i386/tm-i386.h" /* We use stabs-in-ELF with the DWARF register numbering scheme. */ diff --git a/gdb/config/i386/tm-i386lynx.h b/gdb/config/i386/tm-i386lynx.h index 2da0b7c8dee..03fe4ff8bf7 100644 --- a/gdb/config/i386/tm-i386lynx.h +++ b/gdb/config/i386/tm-i386lynx.h @@ -1,5 +1,5 @@ /* Macro definitions for Intel 386 running under LynxOS. - Copyright 1993, 1995 Free Software Foundation, Inc. + Copyright 1993, 1995, 2002 Free Software Foundation, Inc. This file is part of GDB. @@ -26,9 +26,4 @@ /* Most definitions from sysv could be used. */ #include "i386/tm-i386.h" -#undef SAVED_PC_AFTER_CALL - -#define SAVED_PC_AFTER_CALL i386lynx_saved_pc_after_call -CORE_ADDR i386lynx_saved_pc_after_call (); - #endif /* TM_I386LYNX_H */ diff --git a/gdb/config/i386/tm-i386sol2.h b/gdb/config/i386/tm-i386sol2.h index 7473f3bbc91..a63e8a011ff 100644 --- a/gdb/config/i386/tm-i386sol2.h +++ b/gdb/config/i386/tm-i386sol2.h @@ -21,7 +21,6 @@ #ifndef TM_I386SOL2_H #define TM_I386SOL2_H 1 -#define HAVE_I387_REGS #include "i386/tm-i386v4.h" /* If the current gcc for for this target does not produce correct diff --git a/gdb/config/i386/tm-linux.h b/gdb/config/i386/tm-linux.h index 7bfdf03895c..e64ae8a257f 100644 --- a/gdb/config/i386/tm-linux.h +++ b/gdb/config/i386/tm-linux.h @@ -24,7 +24,6 @@ #define TM_LINUX_H #define I386_GNULINUX_TARGET -#define HAVE_I387_REGS #ifdef HAVE_PTRACE_GETFPXREGS #define FILL_FPXREGSET #define HAVE_SSE_REGS diff --git a/gdb/config/i386/tm-nbsd.h b/gdb/config/i386/tm-nbsd.h index 55ef6fa56fc..ac61d93a8cf 100644 --- a/gdb/config/i386/tm-nbsd.h +++ b/gdb/config/i386/tm-nbsd.h @@ -21,7 +21,6 @@ #ifndef TM_NBSD_H #define TM_NBSD_H -#define HAVE_I387_REGS #define HAVE_SSE_REGS #include "i386/tm-i386.h" diff --git a/gdb/config/i386/tm-obsd.h b/gdb/config/i386/tm-obsd.h index d26b03bf41d..f3b111adcaa 100644 --- a/gdb/config/i386/tm-obsd.h +++ b/gdb/config/i386/tm-obsd.h @@ -21,7 +21,6 @@ #ifndef TM_OBSD_H #define TM_OBSD_H -#define HAVE_I387_REGS #include "i386/tm-i386.h" /* OpenBSD uses the old gcc convention for struct returns. */ diff --git a/gdb/config/m68k/tm-m68k.h b/gdb/config/m68k/tm-m68k.h index 40bd25aa626..8f0f6a843a9 100644 --- a/gdb/config/m68k/tm-m68k.h +++ b/gdb/config/m68k/tm-m68k.h @@ -21,6 +21,8 @@ #include "regcache.h" +#define GDB_MULTI_ARCH 0 + /* Generic 68000 stuff, to be included by other tm-*.h files. */ #define TARGET_LONG_DOUBLE_FORMAT &floatformat_m68881_ext diff --git a/gdb/config/mips/tm-mips.h b/gdb/config/mips/tm-mips.h index f573e96fd58..d53156cf817 100644 --- a/gdb/config/mips/tm-mips.h +++ b/gdb/config/mips/tm-mips.h @@ -93,7 +93,7 @@ extern int in_sigtramp (CORE_ADDR, char *); /* Given the register index, return the name of the corresponding register. */ -extern char *mips_register_name (int regnr); +extern const char *mips_register_name (int regnr); #define REGISTER_NAME(i) mips_register_name (i) /* Initializer for an array of names of registers. diff --git a/gdb/config/romp/rtbsd.mh b/gdb/config/romp/rtbsd.mh deleted file mode 100644 index 1efa116fa18..00000000000 --- a/gdb/config/romp/rtbsd.mh +++ /dev/null @@ -1,8 +0,0 @@ -# IBM RT/PC running BSD unix. -# This file contributed at NYU, where we are using the RT to remote -# debug an a29k running unix. No attempt, as of 7/16/91, has been made -# to support debugging of RT executables. -NATDEPFILES corelow.o core-aout.o infptrace.o inftarg.o fork-child.o -MH_CFLAGS=-DHOSTING_ONLY # No debugging of RT executables -XM_FILE= xm-rtbsd.h -CC=gcc -traditional # hc/pcc just can't cut it. diff --git a/gdb/config/romp/xm-rtbsd.h b/gdb/config/romp/xm-rtbsd.h deleted file mode 100644 index e7918163ee2..00000000000 --- a/gdb/config/romp/xm-rtbsd.h +++ /dev/null @@ -1,37 +0,0 @@ -/* Definitions to host GDB on an IBM RT/PC running BSD Unix. - Copyright 1986, 1987, 1989, 1991, 1992 Free Software Foundation, Inc. - Contributed by David Wood @ New York University (wood@lab.ultra.nyu.edu). - - This file is part of GDB. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, - Boston, MA 02111-1307, USA. */ - -/* This OS has the wait structure */ -#define HAVE_WAIT_STRUCT - -#ifdef HOSTING_ONLY -/* - * This next two defines are to get GDB up and running as a host to - * do remote debugging. I know there is a gdb for the RT, but there wasn't - * an xconfig/rt* file. - */ -#define KERNEL_U_ADDR_BSD /* This may be correct, but hasn't been tested */ -#define REGISTER_U_ADDR(a,b,c) \ - (printf("GDB can not debug IBM RT/PC BSD executables (yet)\n"),\ - quit(),0) -#else -#include "GDB for the RT is not included in the distribution" -#endif diff --git a/gdb/cris-tdep.c b/gdb/cris-tdep.c index b28d3bb83f7..b223f8734ee 100644 --- a/gdb/cris-tdep.c +++ b/gdb/cris-tdep.c @@ -762,7 +762,7 @@ cris_skip_prologue_main (CORE_ADDR pc, int frameless_p) adjusts pcptr (if necessary) to point to the actual memory location where the breakpoint should be inserted. */ -unsigned char * +const unsigned char * cris_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) { static unsigned char break_insn[] = {0x38, 0xe9}; @@ -995,7 +995,7 @@ cris_abi_v2_store_return_value (struct type *type, char *valbuf) /* Return the name of register regno as a string. Return NULL for an invalid or unimplemented register. */ -char * +const char * cris_register_name (int regno) { static char *cris_genreg_names[] = diff --git a/gdb/d10v-tdep.c b/gdb/d10v-tdep.c index 4fe1c6228be..856e18ed2de 100644 --- a/gdb/d10v-tdep.c +++ b/gdb/d10v-tdep.c @@ -187,7 +187,7 @@ enum ts2_regnums TS2_A0_REGNUM = 35 }; -static char * +static const char * d10v_ts2_register_name (int reg_nr) { static char *register_names[] = @@ -213,7 +213,7 @@ enum ts3_regnums TS3_A0_REGNUM = 32 }; -static char * +static const char * d10v_ts3_register_name (int reg_nr) { static char *register_names[] = diff --git a/gdb/defs.h b/gdb/defs.h index b1a050da896..10327389e2b 100644 --- a/gdb/defs.h +++ b/gdb/defs.h @@ -222,6 +222,14 @@ enum precision_type unspecified_precision }; +/* A generic, not quite boolean, enumeration. */ +enum auto_boolean +{ + AUTO_BOOLEAN_TRUE, + AUTO_BOOLEAN_FALSE, + AUTO_BOOLEAN_AUTO +}; + /* the cleanup list records things that have to be undone if an error happens (descriptors to be closed, memory to be freed, etc.) Each link in the chain records a function to call and an @@ -840,7 +848,7 @@ extern void xfree (void *); ``struct foo *foo = xmalloc (sizeof bar)'' and ``struct foo *foo = (struct foo *) xmalloc (sizeof bar)''. */ #define XMALLOC(TYPE) ((TYPE*) xmalloc (sizeof (TYPE))) -#define XCALLOC(NR, TYPE) ((TYPE*) xcalloc ((NR), sizeof (TYPE))); +#define XCALLOC(NMEMB, TYPE) ((TYPE*) xcalloc ((NMEMB), sizeof (TYPE))) /* Like asprintf/vasprintf but get an internal_error if the call fails. */ diff --git a/gdb/frame.h b/gdb/frame.h index 03a71c7a097..a0a965edf24 100644 --- a/gdb/frame.h +++ b/gdb/frame.h @@ -133,7 +133,12 @@ struct frame_info /* If dwarf2 unwind frame informations is used, this structure holds all related unwind data. */ - struct unwind_contect *context; + struct context *context; + + /* See description above. Return the register value for the + previous frame. */ + frame_register_unwind_ftype *register_unwind; + void *register_unwind_cache; /* See description above. Return the register value for the previous frame. */ diff --git a/gdb/gdb_indent.sh b/gdb/gdb_indent.sh index 1e727fe2309..0d0829a4a13 100755 --- a/gdb/gdb_indent.sh +++ b/gdb/gdb_indent.sh @@ -54,7 +54,10 @@ esac # Run indent per GDB specs -types="-T FILE `cat *.h | sed -n \ +types="\ +-T FILE \ +-T prgregset_t -T fpregset_t -T gregset_t \ +`cat *.h | sed -n \ -e 's/^.*[^a-z0-9_]\([a-z0-9_]*_ftype\).*$/-T \1/p' \ -e 's/^.*[^a-z0-9_]\([a-z0-9_]*_func\).*$/-T \1/p' \ -e 's/^typedef.*[^a-zA-Z0-9_]\([a-zA-Z0-9_]*[a-zA-Z0-9_]\);$/-T \1/p' \ diff --git a/gdb/gdbarch.c b/gdb/gdbarch.c index 55041aca53a..079c768584b 100644 --- a/gdb/gdbarch.c +++ b/gdb/gdbarch.c @@ -2838,7 +2838,7 @@ set_gdbarch_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, gdbarch->dwarf2_reg_to_regnum = dwarf2_reg_to_regnum; } -char * +const char * gdbarch_register_name (struct gdbarch *gdbarch, int regnr) { gdb_assert (gdbarch != NULL); diff --git a/gdb/gdbarch.h b/gdb/gdbarch.h index 7d73294bfc9..c1443c88c8d 100644 --- a/gdb/gdbarch.h +++ b/gdb/gdbarch.h @@ -659,8 +659,8 @@ extern void set_gdbarch_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, gdbarch_d #define REGISTER_NAME(regnr) (legacy_register_name (regnr)) #endif -typedef char * (gdbarch_register_name_ftype) (int regnr); -extern char * gdbarch_register_name (struct gdbarch *gdbarch, int regnr); +typedef const char * (gdbarch_register_name_ftype) (int regnr); +extern const char * gdbarch_register_name (struct gdbarch *gdbarch, int regnr); extern void set_gdbarch_register_name (struct gdbarch *gdbarch, gdbarch_register_name_ftype *register_name); #if (GDB_MULTI_ARCH > GDB_MULTI_ARCH_PARTIAL) && defined (REGISTER_NAME) #error "Non multi-arch definition of REGISTER_NAME" diff --git a/gdb/gdbarch.sh b/gdb/gdbarch.sh index 6d6c2d02f18..2bdc3871d0a 100755 --- a/gdb/gdbarch.sh +++ b/gdb/gdbarch.sh @@ -458,7 +458,7 @@ f:2:DWARF_REG_TO_REGNUM:int:dwarf_reg_to_regnum:int dwarf_regnr:dwarf_regnr:::no # to map one to one onto the sdb register numbers. f:2:SDB_REG_TO_REGNUM:int:sdb_reg_to_regnum:int sdb_regnr:sdb_regnr:::no_op_reg_to_regnum::0 f:2:DWARF2_REG_TO_REGNUM:int:dwarf2_reg_to_regnum:int dwarf2_regnr:dwarf2_regnr:::no_op_reg_to_regnum::0 -f:2:REGISTER_NAME:char *:register_name:int regnr:regnr:::legacy_register_name::0 +f:2:REGISTER_NAME:const char *:register_name:int regnr:regnr:::legacy_register_name::0 v:2:REGISTER_SIZE:int:register_size::::0:-1 v:2:REGISTER_BYTES:int:register_bytes::::0:-1 f:2:REGISTER_BYTE:int:register_byte:int reg_nr:reg_nr::0:0 diff --git a/gdb/i386-linux-nat.c b/gdb/i386-linux-nat.c index 26f5aaf85ab..fe610211f8e 100644 --- a/gdb/i386-linux-nat.c +++ b/gdb/i386-linux-nat.c @@ -171,7 +171,7 @@ kernel_u_size (void) #endif /* Registers we shouldn't try to fetch. */ -#define OLD_CANNOT_FETCH_REGISTER(regno) ((regno) >= NUM_GREGS) +#define OLD_CANNOT_FETCH_REGISTER(regno) ((regno) >= I386_NUM_GREGS) /* Fetch one register. */ @@ -237,7 +237,7 @@ old_fetch_inferior_registers (int regno) } /* Registers we shouldn't try to store. */ -#define OLD_CANNOT_STORE_REGISTER(regno) ((regno) >= NUM_GREGS) +#define OLD_CANNOT_STORE_REGISTER(regno) ((regno) >= I386_NUM_GREGS) /* Store one register. */ @@ -311,7 +311,7 @@ supply_gregset (elf_gregset_t *gregsetp) elf_greg_t *regp = (elf_greg_t *) gregsetp; int i; - for (i = 0; i < NUM_GREGS; i++) + for (i = 0; i < I386_NUM_GREGS; i++) supply_register (i, (char *) (regp + regmap[i])); if (I386_LINUX_ORIG_EAX_REGNUM < NUM_REGS) @@ -328,8 +328,8 @@ fill_gregset (elf_gregset_t *gregsetp, int regno) elf_greg_t *regp = (elf_greg_t *) gregsetp; int i; - for (i = 0; i < NUM_GREGS; i++) - if ((regno == -1 || regno == i)) + for (i = 0; i < I386_NUM_GREGS; i++) + if (regno == -1 || regno == i) regcache_collect (i, regp + regmap[i]); if ((regno == -1 || regno == I386_LINUX_ORIG_EAX_REGNUM) diff --git a/gdb/i386-linux-tdep.c b/gdb/i386-linux-tdep.c index 12a2ab9004d..8fa9261e3c3 100644 --- a/gdb/i386-linux-tdep.c +++ b/gdb/i386-linux-tdep.c @@ -38,7 +38,7 @@ /* Return the name of register REG. */ -static char * +static const char * i386_linux_register_name (int reg) { /* Deal with the extra "orig_eax" pseudo register. */ diff --git a/gdb/i386-sol2-tdep.c b/gdb/i386-sol2-tdep.c index 714f5db9b36..206e85cfe72 100644 --- a/gdb/i386-sol2-tdep.c +++ b/gdb/i386-sol2-tdep.c @@ -48,12 +48,27 @@ i386_sol2_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) } +static enum gdb_osabi +i386_sol2_osabi_sniffer (bfd *abfd) +{ + /* If we have a section named .SUNW_version, then it is almost + certainly Solaris 2. */ + if (bfd_get_section_by_name (abfd, ".SUNW_version")) + return GDB_OSABI_SOLARIS; + + return GDB_OSABI_UNKNOWN; +} + /* Provide a prototype to silence -Wmissing-prototypes. */ void _initialize_i386_sol2_tdep (void); void _initialize_i386_sol2_tdep (void) { + /* Register and ELF OS ABI sniffer for Solaris 2 binaries. */ + gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_elf_flavour, + i386_sol2_osabi_sniffer); + gdbarch_register_osabi (bfd_arch_i386, GDB_OSABI_SOLARIS, i386_sol2_init_abi); } diff --git a/gdb/i386-tdep.c b/gdb/i386-tdep.c index f0723fa660b..1a838f2a491 100644 --- a/gdb/i386-tdep.c +++ b/gdb/i386-tdep.c @@ -58,11 +58,11 @@ static char *i386_register_names[] = /* i386_register_offset[i] is the offset into the register file of the start of register number i. We initialize this from i386_register_size. */ -static int i386_register_offset[MAX_NUM_REGS]; +static int i386_register_offset[I386_SSE_NUM_REGS]; /* i386_register_size[i] is the number of bytes of storage in GDB's register array occupied by register i. */ -static int i386_register_size[MAX_NUM_REGS] = { +static int i386_register_size[I386_SSE_NUM_REGS] = { 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, @@ -78,7 +78,7 @@ static int i386_register_size[MAX_NUM_REGS] = { /* Return the name of register REG. */ -char * +const char * i386_register_name (int reg) { if (reg < 0) @@ -106,14 +106,6 @@ i386_register_raw_size (int reg) return i386_register_size[reg]; } -/* Return the size in bytes of the virtual type of register REG. */ - -int -i386_register_virtual_size (int reg) -{ - return TYPE_LENGTH (REGISTER_VIRTUAL_TYPE (reg)); -} - /* Convert stabs register number REG to the appropriate register number used by GDB. */ @@ -674,8 +666,8 @@ i386_frame_init_saved_regs (struct frame_info *fip) /* Return PC of first real instruction. */ -int -i386_skip_prologue (int pc) +CORE_ADDR +i386_skip_prologue (CORE_ADDR pc) { unsigned char op; int i; @@ -757,6 +749,24 @@ i386_skip_prologue (int pc) return (codestream_tell ()); } +/* Use the program counter to determine the contents and size of a + breakpoint instruction. Return a pointer to a string of bytes that + encode a breakpoint instruction, store the length of the string in + *LEN and optionally adjust *PC to point to the correct memory + location for inserting the breakpoint. + + On the i386 we have a single breakpoint that fits in a single byte + and can be inserted anywhere. */ + +static const unsigned char * +i386_breakpoint_from_pc (CORE_ADDR *pc, int *len) +{ + static unsigned char break_insn[] = { 0xcc }; /* int 3 */ + + *len = sizeof (break_insn); + return break_insn; +} + void i386_push_dummy_frame (void) { @@ -777,6 +787,19 @@ i386_push_dummy_frame (void) write_register (FP_REGNUM, fp); } +/* The i386 call dummy sequence: + + call 11223344 (32-bit relative) + int 3 + + It is 8 bytes long. */ + +static LONGEST i386_call_dummy_words[] = +{ + 0x223344e8, + 0xcc11 +}; + /* Insert the (relative) function address into the call sequence stored at DYMMY. */ @@ -905,7 +928,7 @@ i386_extract_return_value (struct type *type, char *regbuf, char *valbuf) if (TYPE_CODE (type) == TYPE_CODE_FLT) { - if (NUM_FREGS == 0) + if (FP0_REGNUM == 0) { warning ("Cannot find floating-point return value."); memset (valbuf, 0, len); @@ -959,7 +982,7 @@ i386_store_return_value (struct type *type, char *valbuf) unsigned int fstat; char buf[FPU_REG_RAW_SIZE]; - if (NUM_FREGS == 0) + if (FP0_REGNUM == 0) { warning ("Cannot set floating-point return value."); return; @@ -1340,8 +1363,8 @@ i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) tdep->osabi = osabi; /* The i386 default settings don't include the SSE registers. - FIXME: kettenis/20020509: They do include the FPU registers for - now, which is not quite right. */ + FIXME: kettenis/20020614: They do include the FPU registers for + now, which probably is not quite right. */ tdep->num_xmm_regs = 0; tdep->jb_pc_offset = -1; @@ -1362,55 +1385,106 @@ i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) alignment. */ set_gdbarch_long_double_bit (gdbarch, 96); + /* NOTE: tm-i386aix.h, tm-i386bsd.h, tm-i386os9k.h, tm-ptx.h, + tm-symmetry.h currently override this. Sigh. */ + set_gdbarch_num_regs (gdbarch, I386_NUM_GREGS + I386_NUM_FREGS); + + set_gdbarch_sp_regnum (gdbarch, 4); + set_gdbarch_fp_regnum (gdbarch, 5); + set_gdbarch_pc_regnum (gdbarch, 8); + set_gdbarch_ps_regnum (gdbarch, 9); + set_gdbarch_fp0_regnum (gdbarch, 16); + + /* Use the "default" register numbering scheme for stabs and COFF. */ + set_gdbarch_stab_reg_to_regnum (gdbarch, i386_stab_reg_to_regnum); + set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_stab_reg_to_regnum); + + /* Use the DWARF register numbering scheme for DWARF and DWARF 2. */ + set_gdbarch_dwarf_reg_to_regnum (gdbarch, i386_dwarf_reg_to_regnum); + set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_dwarf_reg_to_regnum); + + /* We don't define ECOFF_REG_TO_REGNUM, since ECOFF doesn't seem to + be in use on any of the supported i386 targets. */ + + set_gdbarch_register_name (gdbarch, i386_register_name); + set_gdbarch_register_size (gdbarch, 4); + set_gdbarch_register_bytes (gdbarch, I386_SIZEOF_GREGS + I386_SIZEOF_FREGS); + set_gdbarch_register_byte (gdbarch, i386_register_byte); + set_gdbarch_register_raw_size (gdbarch, i386_register_raw_size); + set_gdbarch_max_register_raw_size (gdbarch, 16); + set_gdbarch_max_register_virtual_size (gdbarch, 16); + set_gdbarch_register_virtual_type (gdbarch, i386_register_virtual_type); + set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); set_gdbarch_use_generic_dummy_frames (gdbarch, 0); /* Call dummy code. */ set_gdbarch_call_dummy_location (gdbarch, ON_STACK); + set_gdbarch_call_dummy_start_offset (gdbarch, 0); set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 5); set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); + set_gdbarch_call_dummy_length (gdbarch, 8); set_gdbarch_call_dummy_p (gdbarch, 1); + set_gdbarch_call_dummy_words (gdbarch, i386_call_dummy_words); + set_gdbarch_sizeof_call_dummy_words (gdbarch, + sizeof (i386_call_dummy_words)); set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); + set_gdbarch_fix_call_dummy (gdbarch, i386_fix_call_dummy); + + set_gdbarch_register_convertible (gdbarch, i386_register_convertible); + set_gdbarch_register_convert_to_virtual (gdbarch, + i386_register_convert_to_virtual); + set_gdbarch_register_convert_to_raw (gdbarch, i386_register_convert_to_raw); set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register); set_gdbarch_push_arguments (gdbarch, i386_push_arguments); set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_on_stack); + /* "An argument's size is increased, if necessary, to make it a + multiple of [32-bit] words. This may require tail padding, + depending on the size of the argument" -- from the x86 ABI. */ + set_gdbarch_parm_boundary (gdbarch, 32); + + set_gdbarch_deprecated_extract_return_value (gdbarch, + i386_extract_return_value); + set_gdbarch_push_arguments (gdbarch, i386_push_arguments); + set_gdbarch_push_dummy_frame (gdbarch, i386_push_dummy_frame); + set_gdbarch_pop_frame (gdbarch, i386_pop_frame); + set_gdbarch_store_struct_return (gdbarch, i386_store_struct_return); + set_gdbarch_store_return_value (gdbarch, i386_store_return_value); + set_gdbarch_deprecated_extract_struct_value_address (gdbarch, + i386_extract_struct_value_address); set_gdbarch_use_struct_convention (gdbarch, i386_use_struct_convention); + set_gdbarch_frame_init_saved_regs (gdbarch, i386_frame_init_saved_regs); + set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); + + /* Stack grows downward. */ + set_gdbarch_inner_than (gdbarch, core_addr_lessthan); + + set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); + set_gdbarch_decr_pc_after_break (gdbarch, 1); + set_gdbarch_function_start_offset (gdbarch, 0); + /* The following redefines make backtracing through sigtramp work. They manufacture a fake sigtramp frame and obtain the saved pc in sigtramp from the sigcontext structure which is pushed by the kernel on the user stack, along with a pointer to it. */ + set_gdbarch_frame_args_skip (gdbarch, 8); + set_gdbarch_frameless_function_invocation (gdbarch, + i386_frameless_function_invocation); set_gdbarch_frame_chain (gdbarch, i386_frame_chain); set_gdbarch_frame_chain_valid (gdbarch, file_frame_chain_valid); set_gdbarch_frame_saved_pc (gdbarch, i386_frame_saved_pc); + set_gdbarch_frame_args_address (gdbarch, default_frame_address); + set_gdbarch_frame_locals_address (gdbarch, default_frame_address); set_gdbarch_saved_pc_after_call (gdbarch, i386_saved_pc_after_call); + set_gdbarch_frame_num_args (gdbarch, i386_frame_num_args); set_gdbarch_pc_in_sigtramp (gdbarch, i386_pc_in_sigtramp); - /* NOTE: tm-i386aix.h, tm-i386bsd.h, tm-i386os9k.h, tm-ptx.h, - tm-symmetry.h currently override this. Sigh. */ - set_gdbarch_num_regs (gdbarch, I386_NUM_GREGS + I386_NUM_FREGS); - - /* Use the "default" register numbering scheme for stabs and COFF. */ - set_gdbarch_stab_reg_to_regnum (gdbarch, i386_stab_reg_to_regnum); - set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_stab_reg_to_regnum); - - /* Use the DWARF register numbering scheme for DWARF and DWARF 2. */ - set_gdbarch_dwarf_reg_to_regnum (gdbarch, i386_dwarf_reg_to_regnum); - set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_dwarf_reg_to_regnum); - - /* We don't define ECOFF_REG_TO_REGNUM, since ECOFF doesn't seem to - be in use on any of the supported i386 targets. */ - - set_gdbarch_register_bytes (gdbarch, I386_SIZEOF_GREGS + I386_SIZEOF_FREGS); - set_gdbarch_register_name (gdbarch, i386_register_name); - set_gdbarch_register_byte (gdbarch, i386_register_byte); - set_gdbarch_register_raw_size (gdbarch, i386_register_raw_size); - /* Hook in ABI-specific overrides, if they have been registered. */ gdbarch_init_osabi (info, gdbarch, osabi); @@ -1420,7 +1494,8 @@ i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) static enum gdb_osabi i386_coff_osabi_sniffer (bfd *abfd) { - if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0) + if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 + || strcmp (bfd_get_target (abfd), "coff-go32") == 0) return GDB_OSABI_GO32; return GDB_OSABI_UNKNOWN; @@ -1447,7 +1522,7 @@ _initialize_i386_tdep (void) int i, offset; offset = 0; - for (i = 0; i < MAX_NUM_REGS; i++) + for (i = 0; i < I386_SSE_NUM_REGS; i++) { i386_register_offset[i] = offset; offset += i386_register_size[i]; diff --git a/gdb/i386-tdep.h b/gdb/i386-tdep.h index 64af99d1e66..61a817822c4 100644 --- a/gdb/i386-tdep.h +++ b/gdb/i386-tdep.h @@ -157,7 +157,7 @@ struct gdbarch_tdep + I386_SIZEOF_XREGS) /* Return the name of register REG. */ -extern char *i386_register_name (int reg); +extern char const *i386_register_name (int reg); /* Return the offset into the register array of the start of register number REG. */ diff --git a/gdb/i386bsd-nat.c b/gdb/i386bsd-nat.c index a941d5b468c..3ab22a9bab8 100644 --- a/gdb/i386bsd-nat.c +++ b/gdb/i386bsd-nat.c @@ -43,6 +43,7 @@ typedef struct fpreg fpregset_t; #endif #include "gregset.h" +#include "i386-tdep.h" /* In older BSD versions we cannot get at some of the segment @@ -125,7 +126,7 @@ supply_gregset (gregset_t *gregsetp) { int i; - for (i = 0; i < NUM_GREGS; i++) + for (i = 0; i < I386_NUM_GREGS; i++) { if (CANNOT_FETCH_REGISTER (i)) supply_register (i, NULL); @@ -143,7 +144,7 @@ fill_gregset (gregset_t *gregsetp, int regno) { int i; - for (i = 0; i < NUM_GREGS; i++) + for (i = 0; i < I386_NUM_GREGS; i++) if ((regno == -1 || regno == i) && ! CANNOT_STORE_REGISTER (i)) regcache_collect (i, REG_ADDR (gregsetp, i)); } diff --git a/gdb/i386gnu-nat.c b/gdb/i386gnu-nat.c index 329ef2fd17a..3fa99a34d88 100644 --- a/gdb/i386gnu-nat.c +++ b/gdb/i386gnu-nat.c @@ -99,7 +99,7 @@ void supply_gregset (gdb_gregset_t *gregs) { int i; - for (i = 0; i < NUM_GREGS; i++) + for (i = 0; i < I386_NUM_GREGS; i++) supply_register (i, REG_ADDR (gregs, i)); } @@ -124,7 +124,7 @@ gnu_fetch_registers (int regno) error ("Can't fetch registers from thread %d: No such thread", PIDGET (inferior_ptid)); - if (regno < NUM_GREGS || regno == -1) + if (regno < I386_NUM_GREGS || regno == -1) { thread_state_t state; @@ -143,7 +143,7 @@ gnu_fetch_registers (int regno) proc_debug (thread, "fetching all register"); - for (i = 0; i < NUM_GREGS; i++) + for (i = 0; i < I386_NUM_GREGS; i++) supply_register (i, REG_ADDR (state, i)); thread->fetched_regs = ~0; } @@ -156,7 +156,7 @@ gnu_fetch_registers (int regno) } } - if (regno >= NUM_GREGS || regno == -1) + if (regno >= I386_NUM_GREGS || regno == -1) { proc_debug (thread, "fetching floating-point registers"); @@ -211,7 +211,7 @@ gnu_store_registers (int regno) error ("Couldn't store registers into thread %d: No such thread", PIDGET (inferior_ptid)); - if (regno < NUM_GREGS || regno == -1) + if (regno < I386_NUM_GREGS || regno == -1) { thread_state_t state; thread_state_data_t old_state; @@ -238,7 +238,7 @@ gnu_store_registers (int regno) { int check_regno; - for (check_regno = 0; check_regno < NUM_GREGS; check_regno++) + for (check_regno = 0; check_regno < I386_NUM_GREGS; check_regno++) if ((thread->fetched_regs & (1 << check_regno)) && memcpy (REG_ADDR (&old_state, check_regno), REG_ADDR (state, check_regno), @@ -265,7 +265,7 @@ gnu_store_registers (int regno) proc_debug (thread, "storing all registers"); - for (i = 0; i < NUM_GREGS; i++) + for (i = 0; i < I386_NUM_GREGS; i++) if (register_valid[i]) fill (state, i); } @@ -284,7 +284,7 @@ gnu_store_registers (int regno) #undef fill - if (regno >= NUM_GREGS || regno == -1) + if (regno >= I386_NUM_GREGS || regno == -1) { proc_debug (thread, "storing floating-point registers"); diff --git a/gdb/i386ly-tdep.c b/gdb/i386ly-tdep.c index 92b544deabd..69c37501d59 100644 --- a/gdb/i386ly-tdep.c +++ b/gdb/i386ly-tdep.c @@ -1,5 +1,5 @@ /* Target-dependent code for Intel 386 running LynxOS. - Copyright 1993, 1996, 2000, 2001 Free Software Foundation, Inc. + Copyright 1993, 1996, 2000, 2001, 2002 Free Software Foundation, Inc. This file is part of GDB. @@ -19,27 +19,62 @@ Boston, MA 02111-1307, USA. */ #include "defs.h" -#include "inferior.h" -#include "target.h" #include "gdbcore.h" +#include "inferior.h" #include "regcache.h" +#include "target.h" + +#include "i386-tdep.h" -/* Return the PC of the caller from the call frame. Assumes the subr prologue - has already been executed, and the frame pointer setup. If this is the - outermost frame, we check to see if we are in a system call by examining the - previous instruction. If so, then the return PC is actually at SP+4 because - system calls use a different calling sequence. */ +/* Return the PC of the caller from the call frame. Assumes the subr + prologue has already been executed, and the frame pointer setup. + If this is the outermost frame, we check to see if we are in a + system call by examining the previous instruction. If so, then the + return PC is actually at SP+4 because system calls use a different + calling sequence. */ -CORE_ADDR +static CORE_ADDR i386lynx_saved_pc_after_call (struct frame_info *frame) { char opcode[7]; static const unsigned char call_inst[] = - {0x9a, 0, 0, 0, 0, 8, 0}; /* lcall 0x8,0x0 */ + { 0x9a, 0, 0, 0, 0, 8, 0 }; /* lcall 0x8,0x0 */ - read_memory (frame->pc - 7, opcode, 7); + read_memory_nobpt (frame->pc - 7, opcode, 7); if (memcmp (opcode, call_inst, 7) == 0) - return read_memory_integer (read_register (SP_REGNUM) + 4, 4); + return read_memory_unsigned_integer (read_register (SP_REGNUM) + 4, 4); + + return read_memory_unsigned_integer (read_register (SP_REGNUM), 4); +} + + +/* LynxOS. */ +static void +i386lynx_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) +{ + set_gdbarch_saved_pc_after_call (gdbarch, i386lynx_saved_pc_after_call); +} + + +static enum gdb_osabi +i386lynx_coff_osabi_sniffer (bfd *abfd) +{ + if (strcmp (bfd_get_target (abfd), "coff-i386-lynx") == 0) + return GDB_OSABI_LYNXOS; + + return GDB_OSABI_UNKNOWN; +} + + +/* Provide a prototype to silence -Wmissing-prototypes. */ +void _initialize_i386lynx_tdep (void); + +void +_initialize_i386bsd_tdep (void) +{ + gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, + i386lynx_coff_osabi_sniffer); - return read_memory_integer (read_register (SP_REGNUM), 4); + gdbarch_register_osabi (bfd_arch_i386, GDB_OSABI_LYNXOS, + i386lynx_init_abi); } diff --git a/gdb/i386v-nat.c b/gdb/i386v-nat.c index 672ddfbf808..c603b281966 100644 --- a/gdb/i386v-nat.c +++ b/gdb/i386v-nat.c @@ -46,20 +46,9 @@ #include <sys/ioctl.h> #include <fcntl.h> - -/* FIXME: 1998-10-21/jsm: The following used to be just "#include - <sys/debugreg.h>", but the the Linux kernel (version 2.1.x) and - glibc 2.0.x are not in sync; including <sys/debugreg.h> will result - in an error. With luck, these losers will get their act together - and we can trash this hack in the near future. */ - #ifdef TARGET_HAS_HARDWARE_WATCHPOINTS -#ifdef HAVE_ASM_DEBUGREG_H -#include <asm/debugreg.h> -#else #include <sys/debugreg.h> #endif -#endif #include <sys/file.h> #include "gdb_stat.h" diff --git a/gdb/i386v4-nat.c b/gdb/i386v4-nat.c index c67f1fb2f44..7de8c148034 100644 --- a/gdb/i386v4-nat.c +++ b/gdb/i386v4-nat.c @@ -1,5 +1,6 @@ -/* Native-dependent code for SVR4 Unix running on i386's, for GDB. - Copyright 1988, 1989, 1991, 1992, 1996, 1997, 1998, 1999, 2000, 2001 +/* Native-dependent code for SVR4 Unix running on i386's. + Copyright 1988, 1989, 1991, 1992, 1996, 1997, 1998, 1999, 2000, + 2001, 2002 Free Software Foundation, Inc. This file is part of GDB. @@ -27,8 +28,9 @@ #ifdef HAVE_SYS_REG_H #include <sys/reg.h> #endif -#include "i387-tdep.h" +#include "i386-tdep.h" +#include "i387-tdep.h" #ifdef HAVE_SYS_PROCFS_H @@ -37,15 +39,16 @@ /* Prototypes for supply_gregset etc. */ #include "gregset.h" -/* The /proc interface divides the target machine's register set up into - two different sets, the general register set (gregset) and the floating - point register set (fpregset). For each set, there is an ioctl to get - the current register set and another ioctl to set the current values. +/* The `/proc' interface divides the target machine's register set up + into two different sets, the general purpose register set (gregset) + and the floating-point register set (fpregset). For each set, + there is an ioctl to get the current register set and another ioctl + to set the current values. - The actual structure passed through the ioctl interface is, of course, - naturally machine dependent, and is different for each set of registers. - For the i386 for example, the general register set is typically defined - by: + The actual structure passed through the ioctl interface is, of + course, naturally machine dependent, and is different for each set + of registers. For the i386 for example, the general-purpose + register set is typically defined by: typedef int gregset_t[19]; (in <sys/regset.h>) @@ -55,36 +58,38 @@ #define UESP 17 #define SS 18 - and the floating point set by: - - typedef struct fpregset - { - union - { - struct fpchip_state // fp extension state // - { - int state[27]; // 287/387 saved state // - int status; // status word saved at exception // - } fpchip_state; - struct fp_emul_space // for emulators // - { - char fp_emul[246]; - char fp_epad[2]; - } fp_emul_space; - int f_fpregs[62]; // union of the above // - } fp_reg_set; - long f_wregs[33]; // saved weitek state // + and the floating-point set by: + + typedef struct fpregset { + union { + struct fpchip_state // fp extension state // + { + int state[27]; // 287/387 saved state // + int status; // status word saved at // + // exception // + } fpchip_state; + struct fp_emul_space // for emulators // + { + char fp_emul[246]; + char fp_epad[2]; + } fp_emul_space; + int f_fpregs[62]; // union of the above // + } fp_reg_set; + long f_wregs[33]; // saved weitek state // } fpregset_t; - These routines provide the packing and unpacking of gregset_t and - fpregset_t formatted data. + Incidentally fpchip_state contains the FPU state in the same format + as used by the "fsave" instruction, and that's the only thing we + support here. I don't know how the emulator stores it state. The + Weitek stuff definitely isn't supported. - */ + The routines defined here, provide the packing and unpacking of + gregset_t and fpregset_t formatted data. */ #ifdef HAVE_GREGSET_T -/* This is a duplicate of the table in i386-xdep.c. */ - +/* Mapping between the general-purpose registers in `/proc' + format and GDB's register array layout. */ static int regmap[] = { EAX, ECX, EDX, EBX, @@ -93,92 +98,63 @@ static int regmap[] = DS, ES, FS, GS, }; -/* Prototypes for local functions */ - -void fill_gregset (gregset_t *, int); - -void supply_gregset (gregset_t *); - -void supply_fpregset (fpregset_t *); - -void fill_fpregset (fpregset_t *, int); - - -/* FIXME: These routine absolutely depends upon (NUM_REGS - NUM_FREGS) - being less than or equal to the number of registers that can be stored - in a gregset_t. Note that with the current scheme there will typically - be more registers actually stored in a gregset_t that what we know - about. This is bogus and should be fixed. */ - -/* Given a pointer to a general register set in /proc format (gregset_t *), - unpack the register contents and supply them as gdb's idea of the current - register values. */ +/* Fill GDB's register array with the general-purpose register values + in *GREGSETP. */ void supply_gregset (gregset_t *gregsetp) { - register int regi; - register greg_t *regp = (greg_t *) gregsetp; - extern int regmap[]; - - for (regi = 0; regi < (NUM_REGS - NUM_FREGS); regi++) - { - supply_register (regi, (char *) (regp + regmap[regi])); - } + greg_t *regp = (greg_t *) gregsetp; + int i; + + for (i = 0; i < I386_NUM_GREGS; i++) + supply_register (i, (char *) (regp + regmap[i])); } +/* Fill register REGNO (if it is a general-purpose register) in + *GREGSETPS with the value in GDB's register array. If REGNO is -1, + do this for all registers. */ + void fill_gregset (gregset_t *gregsetp, int regno) { - int regi; - register greg_t *regp = (greg_t *) gregsetp; - extern int regmap[]; - - for (regi = 0; regi < (NUM_REGS - NUM_FREGS); regi++) - { - if ((regno == -1) || (regno == regi)) - { - *(regp + regmap[regi]) = *(int *) ®isters[REGISTER_BYTE (regi)]; - } - } + greg_t *regp = (greg_t *) gregsetp; + int i; + + for (i = 0; i < I386_NUM_GREGS; i++) + if (regno == -1 || regno == i) + regcache_collect (i, regp + regmap[i]); } #endif /* HAVE_GREGSET_T */ -#if defined (HAVE_FPREGSET_T) - -/* Given a pointer to a floating point register set in /proc format - (fpregset_t *), unpack the register contents and supply them as gdb's - idea of the current floating point register values. */ +#ifdef HAVE_FPREGSET_T -/* FIXME: Assumes that fpregsetp contains an i387 FSAVE area. */ -#if !defined(FPREGSET_FSAVE_OFFSET) -#define FPREGSET_FSAVE_OFFSET 0 -#endif +/* Fill GDB's register array with the floating-point register values in + *FPREGSETP. */ void supply_fpregset (fpregset_t *fpregsetp) { - if (NUM_FREGS == 0) + if (FP0_REGNUM == 0) return; - i387_supply_fsave ((char *) fpregsetp + FPREGSET_FSAVE_OFFSET); + i387_supply_fsave ((char *) fpregsetp); } -/* Given a pointer to a floating point register set in /proc format - (fpregset_t *), update the register specified by REGNO from gdb's idea - of the current floating point register set. If REGNO is -1, update - them all. */ +/* Fill register REGNO (if it is a floating-point register) in + *FPREGSETP with the value in GDB's register array. If REGNO is -1, + do this for all registers. */ void fill_fpregset (fpregset_t *fpregsetp, int regno) { - if (NUM_FREGS == 0) + if (FP0_REGNUM == 0) return; - i387_fill_fsave ((char *) fpregsetp + FPREGSET_FSAVE_OFFSET, regno); + i387_fill_fsave ((char *) fpregsetp, regno); } -#endif /* defined (HAVE_FPREGSET_T) */ +#endif /* HAVE_FPREGSET_T */ #endif /* HAVE_SYS_PROCFS_H */ diff --git a/gdb/ia64-tdep.c b/gdb/ia64-tdep.c index 44210d7d065..89009de0ce9 100644 --- a/gdb/ia64-tdep.c +++ b/gdb/ia64-tdep.c @@ -243,7 +243,7 @@ struct gdbarch_tdep #define FIND_GLOBAL_POINTER \ (gdbarch_tdep (current_gdbarch)->find_global_pointer) -static char * +static const char * ia64_register_name (int reg) { return ia64_register_names[reg]; diff --git a/gdb/infrun.c b/gdb/infrun.c index cb8f1086341..ec6c7d98da5 100644 --- a/gdb/infrun.c +++ b/gdb/infrun.c @@ -3906,7 +3906,6 @@ struct inferior_status CORE_ADDR step_resume_break_address; int stop_after_trap; int stop_soon_quietly; - CORE_ADDR selected_frame_address; struct regcache *stop_registers; /* These are here because if call_function_by_hand has written some @@ -3917,6 +3916,9 @@ struct inferior_status /* A frame unique identifier. */ struct frame_id selected_frame_id; + /* A frame unique identifier. */ + struct frame_id selected_frame_id; + int breakpoint_proceeded; int restore_stack_info; int proceed_to_finish; diff --git a/gdb/m68hc11-tdep.c b/gdb/m68hc11-tdep.c index 38ec7e348e4..eb8fb748057 100644 --- a/gdb/m68hc11-tdep.c +++ b/gdb/m68hc11-tdep.c @@ -255,7 +255,7 @@ m68hc11_store_pseudo_register (int regno) } } -static char * +static const char * m68hc11_register_name (int reg_nr) { if (reg_nr < 0) diff --git a/gdb/m68k-tdep.c b/gdb/m68k-tdep.c index 1c4bc4d4d1f..05a3e50fdec 100644 --- a/gdb/m68k-tdep.c +++ b/gdb/m68k-tdep.c @@ -81,11 +81,11 @@ delta68_frame_args_address (struct frame_info *frame_info) return frame_info->frame + 12; else if (frameless_look_for_prologue (frame_info)) { - /* Check for an interrupted system call */ - if (frame_info->next && frame_info->next->signal_handler_caller) - return frame_info->next->frame + 16; - else - return frame_info->frame + 4; + /* Check for an interrupted system call */ + if (frame_info->next && frame_info->next->signal_handler_caller) + return frame_info->next->frame + 16; + else + return frame_info->frame + 4; } else return frame_info->frame; @@ -226,7 +226,8 @@ m68k_pop_frame (void) } if (fsr.regs[PS_REGNUM]) { - write_register (PS_REGNUM, read_memory_integer (fsr.regs[PS_REGNUM], 4)); + write_register (PS_REGNUM, + read_memory_integer (fsr.regs[PS_REGNUM], 4)); } write_register (FP_REGNUM, read_memory_integer (fp, 4)); write_register (PC_REGNUM, read_memory_integer (fp + 4, 4)); @@ -278,7 +279,7 @@ m68k_skip_prologue (CORE_ADDR ip) If so, ensure we don't go past it. If not, assume "infinity". */ sal = find_pc_line (ip, 0); - limit = (sal.end) ? sal.end : (CORE_ADDR) ~ 0; + limit = (sal.end) ? sal.end : (CORE_ADDR) ~0; while (ip < limit) { @@ -298,7 +299,7 @@ m68k_skip_prologue (CORE_ADDR ip) else if (op == P_FMOVM) ip += 10; /* Skip fmovm */ else - break; /* Found unknown code, bail out. */ + break; /* Found unknown code, bail out. */ } return (ip); } @@ -314,7 +315,7 @@ m68k_find_saved_regs (struct frame_info *frame_info, /* First possible address for a pc in a call dummy for this frame. */ CORE_ADDR possible_call_dummy_start = - (frame_info)->frame - CALL_DUMMY_LENGTH - FP_REGNUM * 4 - 4 - 8 * 12; + (frame_info)->frame - CALL_DUMMY_LENGTH - FP_REGNUM * 4 - 4 - 8 * 12; int nextinsn; memset (saved_regs, 0, sizeof (*saved_regs)); @@ -367,7 +368,7 @@ m68k_find_saved_regs (struct frame_info *frame_info, next_addr += read_memory_integer (pc += 2, 4), pc += 4; } - for ( ; ; ) + for (;;) { nextinsn = 0xffff & read_memory_integer (pc, 2); regmask = read_memory_integer (pc + 2, 2); @@ -636,9 +637,8 @@ m68k_get_longjmp_target (CORE_ADDR *pc) buf = alloca (TARGET_PTR_BIT / TARGET_CHAR_BIT); sp = read_register (SP_REGNUM); - if (target_read_memory (sp + SP_ARG0, /* Offset of first arg on stack */ - buf, - TARGET_PTR_BIT / TARGET_CHAR_BIT)) + if (target_read_memory (sp + SP_ARG0, /* Offset of first arg on stack */ + buf, TARGET_PTR_BIT / TARGET_CHAR_BIT)) return 0; jb_addr = extract_address (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT); @@ -677,9 +677,40 @@ m68k_saved_pc_after_call (struct frame_info *frame) return read_memory_integer (read_register (SP_REGNUM), 4); } +/* Function: m68k_gdbarch_init + Initializer function for the m68k gdbarch vector. + Called by gdbarch. Sets up the gdbarch vector(s) for this target. */ + +static struct gdbarch * +m68k_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) +{ + struct gdbarch_tdep *tdep = NULL; + struct gdbarch *gdbarch; + + /* find a candidate among the list of pre-declared architectures. */ + arches = gdbarch_list_lookup_by_info (arches, &info); + if (arches != NULL) + return (arches->gdbarch); + +#if 0 + tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); +#endif + + gdbarch = gdbarch_alloc (&info, 0); + + return gdbarch; +} + + +static void +m68k_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) +{ + +} void _initialize_m68k_tdep (void) { + gdbarch_register (bfd_arch_m68k, m68k_gdbarch_init, m68k_dump_tdep); tm_print_insn = print_insn_m68k; } diff --git a/gdb/maint.c b/gdb/maint.c index ddaa390b683..f09703f7729 100644 --- a/gdb/maint.c +++ b/gdb/maint.c @@ -783,16 +783,15 @@ passes without a response from the target, an error occurs.", &setlist), #ifdef NOTYET - /* FIXME: cagney/2001-09-24: A patch introducing a - add_set_boolean_cmd() is pending, the below should probably use - it. A patch implementing profiling is pending, this just sets up - the framework. */ - tmpcmd = add_set_cmd ("profile", class_maintenance, - var_boolean, &maintenance_profile_p, - "Set internal profiling.\n\ -When enabled GDB is profiled.", - &maintenance_set_cmdlist); - set_cmd_sfunc (tmpcmd, maintenance_set_profile_cmd); - add_show_from_set (tmpcmd, &maintenance_show_cmdlist); + /* FIXME: cagney/2002-06-15: A patch implementing profiling is + pending, this just sets up the framework. */ + tmpcmd = add_setshow_boolean_cmd ("profile", class_maintenance, + var_boolean, &maintenance_profile_p, "\ +Set internal profiling.\n\ +When enabled GDB is profiled.", "\ +Show internal profiling.\n", + maintenance_set_profile_cmd, NULL, + &maintenance_set_cmdlist, + &maintenance_show_cmdlist); #endif } diff --git a/gdb/mi/ChangeLog b/gdb/mi/ChangeLog index 096154f9ebb..1c67aca6262 100644 --- a/gdb/mi/ChangeLog +++ b/gdb/mi/ChangeLog @@ -26,6 +26,21 @@ Use enum to handle actions to be performed instead of overloading catch_errors return result and the mi return result. +2002-06-17 Keith Seitz <keiths@redhat.com> + + * gdbmi.texinfo: Update command examples with real MI behavior. + +2002-05-20 Keith Seitz <keiths@redhat.com> + + * mi-main.c (captured_mi_execute_command): Add uiout parameter. + "data" is now a structure which is used to pass data to/from this + function to mi_execute_command. + Modify function to comply with requirements from catch_exceptions. + Store real return result and command's return result in data. + (mi_execute_command): Use catch_exceptions. + Use enum to handle actions to be performed instead of overloading + catch_errors return result and the mi return result. + 2002-04-14 Andrew Cagney <ac131313@redhat.com> * mi-main.c (mi_cmd_exec_return): diff --git a/gdb/mi/gdbmi.texinfo b/gdb/mi/gdbmi.texinfo index f924214caa5..a71b7026964 100644 --- a/gdb/mi/gdbmi.texinfo +++ b/gdb/mi/gdbmi.texinfo @@ -8,7 +8,7 @@ @c @ifinfo @c This file documents GDB/MI, a Machine Interface to GDB. -@c Copyright 2000, 2001 Free Software Foundation, Inc. +@c Copyright 2000, 2001, 2002 Free Software Foundation, Inc. @c Contributed by Cygnus Solutions. @c Permission is granted to copy, distribute and/or modify this document @@ -36,7 +36,7 @@ @c @page @c @vskip 0pt plus 1filll -@c Copyright @copyright{} 2000, 2001 Free Software Foundation, Inc. +@c Copyright @copyright{} 2000, 2001, 2002 Free Software Foundation, Inc. @c Permission is granted to copy, distribute and/or modify this document @c under the terms of the GNU Free Documentation License, Version 1.1 or @@ -355,7 +355,7 @@ following line is passed to @sc{gdb/mi} as input, while @samp{<-} means the output received from @sc{gdb/mi}. @subsubheading Target Stop - +@c Ummm... There is no "-stop" command. This assumes async, no? Here's an example of stopping the inferior process: @example @@ -378,7 +378,9 @@ Here's an example of a simple CLI command being passed through @example -> print 1+2 -<- ~3\n +<- &"print 1+2\n" +<- ~"$1 = 3\n" +<- ^done <- (@value{GDBP}) @end example @@ -396,7 +398,7 @@ Here's what happens if you pass a non-existent command: @example -> -rubbish -<- error,"Rubbish not found" +<- ^error,msg="Undefined MI command: rubbish" <- (@value{GDBP}) @end example diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c index d7f6d855ea0..fb46b0262ac 100644 --- a/gdb/mips-tdep.c +++ b/gdb/mips-tdep.c @@ -61,14 +61,27 @@ enum enum mips_abi { - MIPS_ABI_UNKNOWN, + MIPS_ABI_UNKNOWN = 0, MIPS_ABI_N32, MIPS_ABI_O32, MIPS_ABI_O64, MIPS_ABI_EABI32, - MIPS_ABI_EABI64 + MIPS_ABI_EABI64, + MIPS_ABI_LAST }; +static const char *mips_abi_string; + +static const char *mips_abi_strings[] = { + "auto", + "n32", + "o32", + "o64", + "eabi32", + "eabi64", + NULL +}; + struct frame_extra_info { mips_extra_func_info_t proc_desc; @@ -117,7 +130,7 @@ struct gdbarch_tdep /* mips options */ enum mips_abi mips_abi; - const char *mips_abi_string; + enum mips_abi found_abi; enum mips_fpu_type mips_fpu_type; int mips_last_arg_regnum; int mips_last_fp_arg_regnum; @@ -270,7 +283,7 @@ static struct cmd_list_element *showmipscmdlist = NULL; char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES; char **mips_processor_reg_names = mips_generic_reg_names; -char * +const char * mips_register_name (int i) { return mips_processor_reg_names[i]; @@ -469,19 +482,19 @@ mips_register_convert_to_raw (struct type *virtual_type, int n, } /* Should the upper word of 64-bit addresses be zeroed? */ -enum cmd_auto_boolean mask_address_var = CMD_AUTO_BOOLEAN_AUTO; +enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; static int mips_mask_address_p (void) { switch (mask_address_var) { - case CMD_AUTO_BOOLEAN_TRUE: + case AUTO_BOOLEAN_TRUE: return 1; - case CMD_AUTO_BOOLEAN_FALSE: + case AUTO_BOOLEAN_FALSE: return 0; break; - case CMD_AUTO_BOOLEAN_AUTO: + case AUTO_BOOLEAN_AUTO: return MIPS_DEFAULT_MASK_ADDRESS_P; default: internal_error (__FILE__, __LINE__, @@ -491,17 +504,17 @@ mips_mask_address_p (void) } static void -show_mask_address (char *cmd, int from_tty) +show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c) { switch (mask_address_var) { - case CMD_AUTO_BOOLEAN_TRUE: + case AUTO_BOOLEAN_TRUE: printf_filtered ("The 32 bit mips address mask is enabled\n"); break; - case CMD_AUTO_BOOLEAN_FALSE: + case AUTO_BOOLEAN_FALSE: printf_filtered ("The 32 bit mips address mask is disabled\n"); break; - case CMD_AUTO_BOOLEAN_AUTO: + case AUTO_BOOLEAN_AUTO: printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n", mips_mask_address_p () ? "enabled" : "disabled"); break; @@ -4247,6 +4260,19 @@ mips_find_abi_section (bfd *abfd, asection *sect, void *obj) warning ("unsupported ABI %s.", name + 8); } +static enum mips_abi +global_mips_abi (void) +{ + int i; + + for (i = 0; mips_abi_strings[i] != NULL; i++) + if (mips_abi_strings[i] == mips_abi_string) + return (enum mips_abi) i; + + internal_error (__FILE__, __LINE__, + "unknown ABI string"); +} + static struct gdbarch * mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) @@ -4256,7 +4282,7 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch *gdbarch; struct gdbarch_tdep *tdep; int elf_flags; - enum mips_abi mips_abi; + enum mips_abi mips_abi, found_abi, wanted_abi; enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; /* Reset the disassembly info, in case it was set to something @@ -4305,6 +4331,11 @@ mips_gdbarch_init (struct gdbarch_info info, if (mips_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) bfd_map_over_sections (info.abfd, mips_find_abi_section, &mips_abi); + /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN. + Use the ABI from the last architecture if there is one. */ + if (info.abfd == NULL && arches != NULL) + mips_abi = gdbarch_tdep (arches->gdbarch)->found_abi; + /* Try the architecture for any hint of the corect ABI */ if (mips_abi == MIPS_ABI_UNKNOWN && info.bfd_arch_info != NULL @@ -4325,11 +4356,22 @@ mips_gdbarch_init (struct gdbarch_info info, break; } } + #ifdef MIPS_DEFAULT_ABI if (mips_abi == MIPS_ABI_UNKNOWN) mips_abi = MIPS_DEFAULT_ABI; #endif + if (mips_abi == MIPS_ABI_UNKNOWN) + mips_abi = MIPS_ABI_O32; + + /* Now that we have found what the ABI for this binary would be, + check whether the user is overriding it. */ + found_abi = mips_abi; + wanted_abi = global_mips_abi (); + if (wanted_abi != MIPS_ABI_UNKNOWN) + mips_abi = wanted_abi; + if (gdbarch_debug) { fprintf_unfiltered (gdb_stdlog, @@ -4338,6 +4380,9 @@ mips_gdbarch_init (struct gdbarch_info info, fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", mips_abi); + fprintf_unfiltered (gdb_stdlog, + "mips_gdbarch_init: found_mips_abi = %d\n", + found_abi); } /* try to find a pre-existing architecture */ @@ -4368,12 +4413,12 @@ mips_gdbarch_init (struct gdbarch_info info, set_gdbarch_double_bit (gdbarch, 64); set_gdbarch_long_double_bit (gdbarch, 64); set_gdbarch_register_raw_size (gdbarch, mips_register_raw_size); + tdep->found_abi = found_abi; tdep->mips_abi = mips_abi; switch (mips_abi) { case MIPS_ABI_O32: - tdep->mips_abi_string = "o32"; tdep->mips_default_saved_regsize = 4; tdep->mips_default_stack_argsize = 4; tdep->mips_fp_register_double = 0; @@ -4387,7 +4432,6 @@ mips_gdbarch_init (struct gdbarch_info info, set_gdbarch_long_long_bit (gdbarch, 64); break; case MIPS_ABI_O64: - tdep->mips_abi_string = "o64"; tdep->mips_default_saved_regsize = 8; tdep->mips_default_stack_argsize = 8; tdep->mips_fp_register_double = 1; @@ -4401,7 +4445,6 @@ mips_gdbarch_init (struct gdbarch_info info, set_gdbarch_long_long_bit (gdbarch, 64); break; case MIPS_ABI_EABI32: - tdep->mips_abi_string = "eabi32"; tdep->mips_default_saved_regsize = 4; tdep->mips_default_stack_argsize = 4; tdep->mips_fp_register_double = 0; @@ -4415,7 +4458,6 @@ mips_gdbarch_init (struct gdbarch_info info, set_gdbarch_long_long_bit (gdbarch, 64); break; case MIPS_ABI_EABI64: - tdep->mips_abi_string = "eabi64"; tdep->mips_default_saved_regsize = 8; tdep->mips_default_stack_argsize = 8; tdep->mips_fp_register_double = 1; @@ -4429,7 +4471,6 @@ mips_gdbarch_init (struct gdbarch_info info, set_gdbarch_long_long_bit (gdbarch, 64); break; case MIPS_ABI_N32: - tdep->mips_abi_string = "n32"; tdep->mips_default_saved_regsize = 4; tdep->mips_default_stack_argsize = 8; tdep->mips_fp_register_double = 1; @@ -4454,19 +4495,8 @@ mips_gdbarch_init (struct gdbarch_info info, tm_print_insn_info.mach = bfd_mach_mips8000; break; default: - tdep->mips_abi_string = "default"; - tdep->mips_default_saved_regsize = MIPS_REGSIZE; - tdep->mips_default_stack_argsize = MIPS_REGSIZE; - tdep->mips_fp_register_double = (REGISTER_VIRTUAL_SIZE (FP0_REGNUM) == 8); - tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1; - tdep->mips_last_fp_arg_regnum = FPA0_REGNUM + 8 - 1; - tdep->mips_regs_have_home_p = 1; - tdep->gdb_target_is_mips64 = 0; - tdep->default_mask_address_p = 0; - set_gdbarch_long_bit (gdbarch, 32); - set_gdbarch_ptr_bit (gdbarch, 32); - set_gdbarch_long_long_bit (gdbarch, 64); - break; + internal_error (__FILE__, __LINE__, + "unknown ABI in switch"); } /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE @@ -4579,6 +4609,18 @@ mips_gdbarch_init (struct gdbarch_info info, } static void +mips_abi_update (char *ignore_args, int from_tty, + struct cmd_list_element *c) +{ + struct gdbarch_info info; + + /* Force the architecture to update, and (if it's a MIPS architecture) + mips_gdbarch_init will take care of the rest. */ + gdbarch_info_init (&info); + gdbarch_update_p (info); +} + +static void mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) { struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); @@ -4619,7 +4661,7 @@ mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) fprintf_unfiltered (file, "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", tdep->mips_abi, - tdep->mips_abi_string); + mips_abi_strings[tdep->mips_abi]); fprintf_unfiltered (file, "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", mips_mask_address_p (), @@ -4995,6 +5037,11 @@ _initialize_mips_tdep (void) static struct cmd_list_element *mipsfpulist = NULL; struct cmd_list_element *c; + mips_abi_string = mips_abi_strings [MIPS_ABI_UNKNOWN]; + if (MIPS_ABI_LAST + 1 + != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) + internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync"); + gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); if (!tm_print_insn) /* Someone may have already set it */ tm_print_insn = gdb_print_insn_mips; @@ -5037,6 +5084,21 @@ This option can be set to one of:\n\ &setmipscmdlist), &showmipscmdlist); + /* Allow the user to override the ABI. */ + c = add_set_enum_cmd + ("abi", class_obscure, mips_abi_strings, &mips_abi_string, + "Set the ABI used by this program.\n" + "This option can be set to one of:\n" + " auto - the default ABI associated with the current binary\n" + " o32\n" + " o64\n" + " n32\n" + " eabi32\n" + " eabi64", + &setmipscmdlist); + add_show_from_set (c, &showmipscmdlist); + set_cmd_sfunc (c, mips_abi_update); + /* Let the user turn off floating point and set the fence post for heuristic_proc_start. */ @@ -5083,13 +5145,13 @@ search. The only need to set it is when debugging a stripped executable.", /* Allow the user to control whether the upper bits of 64-bit addresses should be zeroed. */ - c = add_set_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, - "Set zeroing of upper 32 bits of 64-bit addresses.\n\ -Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to allow GDB to determine\n\ -the correct value.\n", - &setmipscmdlist); - add_cmd ("mask-address", no_class, show_mask_address, - "Show current mask-address value", &showmipscmdlist); + add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\ +Set zeroing of upper 32 bits of 64-bit addresses.\n\ +Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ +allow GDB to determine the correct value.\n", "\ +Show zeroing of upper 32 bits of 64-bit addresses.", + NULL, show_mask_address, + &setmipscmdlist, &showmipscmdlist); /* Allow the user to control the size of 32 bit registers within the raw remote packet. */ diff --git a/gdb/mn10300-tdep.c b/gdb/mn10300-tdep.c index 5d3da69c0b9..35301017701 100644 --- a/gdb/mn10300-tdep.c +++ b/gdb/mn10300-tdep.c @@ -89,7 +89,7 @@ register_name (int reg, char **regs, long sizeof_regs) return regs[reg]; } -static char * +static const char * mn10300_generic_register_name (int reg) { static char *regs[] = @@ -102,7 +102,7 @@ mn10300_generic_register_name (int reg) } -static char * +static const char * am33_register_name (int reg) { static char *regs[] = diff --git a/gdb/ns32k-tdep.c b/gdb/ns32k-tdep.c index 4e9f9608f91..ae81ebe4eb5 100644 --- a/gdb/ns32k-tdep.c +++ b/gdb/ns32k-tdep.c @@ -36,7 +36,7 @@ static CORE_ADDR ns32k_get_enter_addr (CORE_ADDR); static int ns32k_localcount (CORE_ADDR enter_pc); static void flip_bytes (void *, int); -static char * +static const char * ns32k_register_name_32082 (int regno) { static char *register_names[] = @@ -55,7 +55,7 @@ ns32k_register_name_32082 (int regno) return (register_names[regno]); } -static char * +static const char * ns32k_register_name_32382 (int regno) { static char *register_names[] = diff --git a/gdb/regcache.c b/gdb/regcache.c index 5da651272d1..11ed8c4f70d 100644 --- a/gdb/regcache.c +++ b/gdb/regcache.c @@ -1,7 +1,6 @@ /* Cache and manage the values of registers for GDB, the GNU debugger. - - Copyright 1986, 1987, 1989, 1991, 1994, 1995, 1996, 1998, 2000, - 2001, 2002 Free Software Foundation, Inc. + Copyright 1986, 1987, 1989, 1991, 1994, 1995, 1996, 1998, 2000, 2001 + Free Software Foundation, Inc. This file is part of GDB. @@ -34,361 +33,6 @@ * Here is the actual register cache. */ -/* Per-architecture object describing the layout of a register cache. - Computed once when the architecture is created */ - -struct gdbarch_data *regcache_data_handle; - -struct regcache_descr -{ - /* The architecture this descriptor belongs to. */ - struct gdbarch *gdbarch; - - /* Is this a ``legacy'' register cache? Such caches reserve space - for raw and pseudo registers and allow access to both. */ - int legacy_p; - - /* The raw register cache. This should contain just [0 - .. NUM_RAW_REGISTERS). However, for older targets, it contains - space for the full [0 .. NUM_RAW_REGISTERS + - NUM_PSEUDO_REGISTERS). */ - int nr_raw_registers; - long sizeof_raw_registers; - long sizeof_raw_register_valid_p; - - /* Offset, in bytes, of reach register in the raw register cache. - Pseudo registers have an offset even though they don't - (shouldn't) have a correspoinding space in the register cache. - It is to keep existing code, that relies on - write/write_register_bytes working. */ - long *register_offset; - - /* The cooked / frame / virtual register space. The registers in - the range [0..NR_RAW_REGISTERS) should be mapped directly onto - the corresponding raw register. The next [NR_RAW_REGISTERS - .. NR_REGISTERS) should have been mapped, via - gdbarch_register_read/write onto either raw registers or memory. */ - int nr_registers; - long *sizeof_register; - long max_register_size; - -}; - -static void * -init_legacy_regcache_descr (struct gdbarch *gdbarch) -{ - int i; - struct regcache_descr *descr; - /* FIXME: cagney/2002-05-11: gdbarch_data() should take that - ``gdbarch'' as a parameter. */ - gdb_assert (gdbarch != NULL); - - descr = XMALLOC (struct regcache_descr); - descr->gdbarch = gdbarch; - descr->legacy_p = 1; - - /* FIXME: cagney/2002-05-11: Shouldn't be including pseudo-registers - in the register buffer. Unfortunatly some architectures do. */ - descr->nr_registers = NUM_REGS + NUM_PSEUDO_REGS; - descr->nr_raw_registers = descr->nr_registers; - descr->sizeof_raw_register_valid_p = descr->nr_registers; - - /* FIXME: cagney/2002-05-11: Instead of using REGISTER_BYTE() this - code should compute the offets et.al. at runtime. This currently - isn't possible because some targets overlap register locations - - see the mess in read_register_bytes() and write_register_bytes() - registers. */ - descr->sizeof_register = XCALLOC (descr->nr_registers, long); - descr->register_offset = XCALLOC (descr->nr_registers, long); - descr->max_register_size = 0; - for (i = 0; i < descr->nr_registers; i++) - { - descr->register_offset[i] = REGISTER_BYTE (i); - descr->sizeof_register[i] = REGISTER_RAW_SIZE (i); - if (descr->max_register_size < REGISTER_RAW_SIZE (i)) - descr->max_register_size = REGISTER_RAW_SIZE (i); - } - - /* Come up with the real size of the registers buffer. */ - descr->sizeof_raw_registers = REGISTER_BYTES; /* OK use. */ - for (i = 0; i < descr->nr_registers; i++) - { - long regend; - /* Keep extending the buffer so that there is always enough - space for all registers. The comparison is necessary since - legacy code is free to put registers in random places in the - buffer separated by holes. Once REGISTER_BYTE() is killed - this can be greatly simplified. */ - /* FIXME: cagney/2001-12-04: This code shouldn't need to use - REGISTER_BYTE(). Unfortunatly, legacy code likes to lay the - buffer out so that certain registers just happen to overlap. - Ulgh! New targets use gdbarch's register read/write and - entirely avoid this uglyness. */ - regend = descr->register_offset[i] + descr->sizeof_register[i]; - if (descr->sizeof_raw_registers < regend) - descr->sizeof_raw_registers = regend; - } - set_gdbarch_data (gdbarch, regcache_data_handle, descr); - return descr; -} - -static void * -init_regcache_descr (struct gdbarch *gdbarch) -{ - int i; - struct regcache_descr *descr; - gdb_assert (gdbarch != NULL); - - /* If an old style architecture, construct the register cache - description using all the register macros. */ - if (!gdbarch_register_read_p (gdbarch) - && !gdbarch_register_write_p (gdbarch)) - return init_legacy_regcache_descr (gdbarch); - - descr = XMALLOC (struct regcache_descr); - descr->gdbarch = gdbarch; - descr->legacy_p = 0; - - /* Total size of the register space. The raw registers should - directly map onto the raw register cache while the pseudo's are - either mapped onto raw-registers or memory. */ - descr->nr_registers = NUM_REGS + NUM_PSEUDO_REGS; - - /* Construct a strictly RAW register cache. Don't allow pseudo's - into the register cache. */ - descr->nr_raw_registers = NUM_REGS; - descr->sizeof_raw_register_valid_p = NUM_REGS; - - /* Lay out the register cache. The pseud-registers are included in - the layout even though their value isn't stored in the register - cache. Some code, via read_register_bytes() access a register - using an offset/length rather than a register number. - - NOTE: cagney/2002-05-22: Only REGISTER_VIRTUAL_TYPE() needs to be - used when constructing the register cache. It is assumed that - register raw size, virtual size and type length of the type are - all the same. */ - - { - long offset = 0; - descr->sizeof_register = XCALLOC (descr->nr_registers, long); - descr->register_offset = XCALLOC (descr->nr_registers, long); - descr->max_register_size = 0; - for (i = 0; i < descr->nr_registers; i++) - { - descr->sizeof_register[i] = TYPE_LENGTH (REGISTER_VIRTUAL_TYPE (i)); - descr->register_offset[i] = offset; - offset += descr->sizeof_register[i]; - if (descr->max_register_size < descr->sizeof_register[i]) - descr->max_register_size = descr->sizeof_register[i]; - } - /* Set the real size of the register cache buffer. */ - /* FIXME: cagney/2002-05-22: Should only need to allocate space - for the raw registers. Unfortunatly some code still accesses - the register array directly using the global registers[]. - Until that code has been purged, play safe and over allocating - the register buffer. Ulgh! */ - descr->sizeof_raw_registers = offset; - /* = descr->register_offset[descr->nr_raw_registers]; */ - } - - set_gdbarch_data (gdbarch, regcache_data_handle, descr); - - /* Sanity check. Confirm that the assumptions about gdbarch are - true. The REGCACHE_DATA_HANDLE is set before doing the checks so - that targets using the generic methods supplied by regcache don't - go into infinite recursion trying to, again, create the regcache. */ - for (i = 0; i < descr->nr_registers; i++) - { - gdb_assert (descr->sizeof_register[i] == REGISTER_RAW_SIZE (i)); - gdb_assert (descr->sizeof_register[i] == REGISTER_VIRTUAL_SIZE (i)); - gdb_assert (descr->register_offset[i] == REGISTER_BYTE (i)); - } - /* gdb_assert (descr->sizeof_raw_registers == REGISTER_BYTES (i)); */ - return descr; -} - -static struct regcache_descr * -regcache_descr (struct gdbarch *gdbarch) -{ - return gdbarch_data (gdbarch, regcache_data_handle); -} - -static void -xfree_regcache_descr (struct gdbarch *gdbarch, void *ptr) -{ - struct regcache_descr *descr = ptr; - if (descr == NULL) - return; - xfree (descr->register_offset); - xfree (descr->sizeof_register); - descr->register_offset = NULL; - descr->sizeof_register = NULL; - xfree (descr); -} - -/* The register cache for storing raw register values. */ - -struct regcache -{ - struct regcache_descr *descr; - char *raw_registers; - char *raw_register_valid_p; - /* If a value isn't in the cache should the corresponding target be - queried for a value. */ - int passthrough_p; -}; - -struct regcache * -regcache_xmalloc (struct gdbarch *gdbarch) -{ - struct regcache_descr *descr; - struct regcache *regcache; - gdb_assert (gdbarch != NULL); - descr = regcache_descr (gdbarch); - regcache = XMALLOC (struct regcache); - regcache->descr = descr; - regcache->raw_registers - = XCALLOC (descr->sizeof_raw_registers, char); - regcache->raw_register_valid_p - = XCALLOC (descr->sizeof_raw_register_valid_p, char); - regcache->passthrough_p = 0; - return regcache; -} - -void -regcache_xfree (struct regcache *regcache) -{ - if (regcache == NULL) - return; - xfree (regcache->raw_registers); - xfree (regcache->raw_register_valid_p); - xfree (regcache); -} - -void -do_regcache_xfree (void *buf) -{ - regcache_xfree (buf); -} - -struct regcache * -regcache_xmalloc_with_cleanup (struct gdbarch *gdbarch) -{ - struct regcache *regcache = regcache_xmalloc (gdbarch); - make_cleanup (do_regcache_xfree, regcache); - return regcache; -} - -void -regcache_cpy (struct regcache *dst, struct regcache *src) -{ - int i; - char *buf; - gdb_assert (src != NULL && dst != NULL); - gdb_assert (src->descr->gdbarch == dst->descr->gdbarch); - gdb_assert (src != dst); - /* FIXME: cagney/2002-05-17: To say this bit is bad is being polite. - It keeps the existing code working where things rely on going - through to the register cache. */ - if (src == current_regcache && src->descr->legacy_p) - { - /* ULGH!!!! Old way. Use REGISTER bytes and let code below - untangle fetch. */ - read_register_bytes (0, dst->raw_registers, REGISTER_BYTES); - return; - } - /* FIXME: cagney/2002-05-17: To say this bit is bad is being polite. - It keeps the existing code working where things rely on going - through to the register cache. */ - if (dst == current_regcache && dst->descr->legacy_p) - { - /* ULGH!!!! Old way. Use REGISTER bytes and let code below - untangle fetch. */ - write_register_bytes (0, src->raw_registers, REGISTER_BYTES); - return; - } - buf = alloca (src->descr->max_register_size); - for (i = 0; i < src->descr->nr_raw_registers; i++) - { - /* Should we worry about the valid bit here? */ - regcache_read (src, i, buf); - regcache_write (dst, i, buf); - } -} - -void -regcache_cpy_no_passthrough (struct regcache *dst, struct regcache *src) -{ - int i; - gdb_assert (src != NULL && dst != NULL); - gdb_assert (src->descr->gdbarch == dst->descr->gdbarch); - /* NOTE: cagney/2002-05-17: Don't let the caller do a no-passthrough - move of data into the current_regcache(). Doing this would be - silly - it would mean that valid_p would be completly invalid. */ - gdb_assert (dst != current_regcache); - memcpy (dst->raw_registers, src->raw_registers, - dst->descr->sizeof_raw_registers); - memcpy (dst->raw_register_valid_p, src->raw_register_valid_p, - dst->descr->sizeof_raw_register_valid_p); -} - -struct regcache * -regcache_dup (struct regcache *src) -{ - struct regcache *newbuf; - gdb_assert (current_regcache != NULL); - newbuf = regcache_xmalloc (src->descr->gdbarch); - regcache_cpy (newbuf, src); - return newbuf; -} - -struct regcache * -regcache_dup_no_passthrough (struct regcache *src) -{ - struct regcache *newbuf; - gdb_assert (current_regcache != NULL); - newbuf = regcache_xmalloc (src->descr->gdbarch); - regcache_cpy_no_passthrough (newbuf, src); - return newbuf; -} - -int -regcache_valid_p (struct regcache *regcache, int regnum) -{ - gdb_assert (regcache != NULL); - gdb_assert (regnum >= 0 && regnum < regcache->descr->nr_raw_registers); - return regcache->raw_register_valid_p[regnum]; -} - -CORE_ADDR -regcache_read_as_address (struct regcache *regcache, int regnum) -{ - char *buf; - gdb_assert (regcache != NULL); - gdb_assert (regnum >= 0 && regnum < regcache->descr->nr_raw_registers); - buf = alloca (regcache->descr->sizeof_register[regnum]); - regcache_read (regcache, regnum, buf); - return extract_address (buf, regcache->descr->sizeof_register[regnum]); -} - -char * -deprecated_grub_regcache_for_registers (struct regcache *regcache) -{ - return regcache->raw_registers; -} - -char * -deprecated_grub_regcache_for_register_valid (struct regcache *regcache) -{ - return regcache->raw_register_valid_p; -} - -/* Global structure containing the current regcache. */ -/* FIXME: cagney/2002-05-11: The two global arrays registers[] and - register_valid[] currently point into this structure. */ -struct regcache *current_regcache; - /* NOTE: this is a write-through cache. There is no "dirty" bit for recording if the register values have been changed (eg. by the user). Therefore all registers must be written back to the @@ -453,9 +97,10 @@ register_changed (int regnum) else return a pointer to the start of the cache buffer. */ static char * -register_buffer (struct regcache *regcache, int regnum) +register_buffer (int regnum) { - return regcache->raw_registers + regcache->descr->register_offset[regnum]; + gdb_assert (regnum >= 0 && regnum < (NUM_REGS + NUM_PSEUDO_REGS)); + return ®isters[REGISTER_BYTE (regnum)]; } /* Return whether register REGNUM is a real register. */ @@ -666,52 +311,22 @@ legacy_read_register_gen (int regnum, char *myaddr) if (!register_cached (regnum)) fetch_register (regnum); - memcpy (myaddr, register_buffer (current_regcache, regnum), + memcpy (myaddr, register_buffer (regnum), REGISTER_RAW_SIZE (regnum)); } void -regcache_read (struct regcache *regcache, int regnum, char *buf) +regcache_read (int rawnum, char *buf) { - gdb_assert (regcache != NULL && buf != NULL); - gdb_assert (regnum >= 0 && regnum < regcache->descr->nr_raw_registers); - if (regcache->descr->legacy_p - && regcache->passthrough_p) - { - gdb_assert (regcache == current_regcache); - /* For moment, just use underlying legacy code. Ulgh!!! This - silently and very indirectly updates the regcache's regcache - via the global register_valid[]. */ - legacy_read_register_gen (regnum, buf); - return; - } - /* Make certain that the register cache is up-to-date with respect - to the current thread. This switching shouldn't be necessary - only there is still only one target side register cache. Sigh! - On the bright side, at least there is a regcache object. */ - if (regcache->passthrough_p) - { - gdb_assert (regcache == current_regcache); - if (! ptid_equal (registers_ptid, inferior_ptid)) - { - registers_changed (); - registers_ptid = inferior_ptid; - } - if (!register_cached (regnum)) - fetch_register (regnum); - } - /* Copy the value directly into the register cache. */ - memcpy (buf, (regcache->raw_registers - + regcache->descr->register_offset[regnum]), - regcache->descr->sizeof_register[regnum]); + gdb_assert (rawnum >= 0 && rawnum < (NUM_REGS + NUM_PSEUDO_REGS)); + /* For moment, just use underlying legacy code. Ulgh!!! */ + legacy_read_register_gen (rawnum, buf); } void read_register_gen (int regnum, char *buf) { - gdb_assert (current_regcache != NULL); - gdb_assert (current_regcache->descr->gdbarch == current_gdbarch); - if (current_regcache->descr->legacy_p) + if (! gdbarch_register_read_p (current_gdbarch)) { legacy_read_register_gen (regnum, buf); return; @@ -747,80 +362,30 @@ legacy_write_register_gen (int regnum, char *myaddr) /* If we have a valid copy of the register, and new value == old value, then don't bother doing the actual store. */ if (register_cached (regnum) - && (memcmp (register_buffer (current_regcache, regnum), myaddr, size) - == 0)) + && memcmp (register_buffer (regnum), myaddr, size) == 0) return; else target_prepare_to_store (); } - memcpy (register_buffer (current_regcache, regnum), myaddr, size); + memcpy (register_buffer (regnum), myaddr, size); set_register_cached (regnum, 1); store_register (regnum); } void -regcache_write (struct regcache *regcache, int regnum, char *buf) +regcache_write (int rawnum, char *buf) { - gdb_assert (regcache != NULL && buf != NULL); - gdb_assert (regnum >= 0 && regnum < regcache->descr->nr_raw_registers); - - if (regcache->passthrough_p - && regcache->descr->legacy_p) - { - /* For moment, just use underlying legacy code. Ulgh!!! This - silently and very indirectly updates the regcache's buffers - via the globals register_valid[] and registers[]. */ - gdb_assert (regcache == current_regcache); - legacy_write_register_gen (regnum, buf); - return; - } - - /* On the sparc, writing %g0 is a no-op, so we don't even want to - change the registers array if something writes to this register. */ - if (CANNOT_STORE_REGISTER (regnum)) - return; - - /* Handle the simple case first -> not write through so just store - value in cache. */ - if (!regcache->passthrough_p) - { - memcpy ((regcache->raw_registers - + regcache->descr->register_offset[regnum]), buf, - regcache->descr->sizeof_register[regnum]); - regcache->raw_register_valid_p[regnum] = 1; - return; - } - - /* Make certain that the correct cache is selected. */ - gdb_assert (regcache == current_regcache); - if (! ptid_equal (registers_ptid, inferior_ptid)) - { - registers_changed (); - registers_ptid = inferior_ptid; - } - - /* If we have a valid copy of the register, and new value == old - value, then don't bother doing the actual store. */ - if (regcache_valid_p (regcache, regnum) - && (memcmp (register_buffer (regcache, regnum), buf, - regcache->descr->sizeof_register[regnum]) == 0)) - return; - - target_prepare_to_store (); - memcpy (register_buffer (regcache, regnum), buf, - regcache->descr->sizeof_register[regnum]); - regcache->raw_register_valid_p[regnum] = 1; - store_register (regnum); + gdb_assert (rawnum >= 0 && rawnum < (NUM_REGS + NUM_PSEUDO_REGS)); + /* For moment, just use underlying legacy code. Ulgh!!! */ + legacy_write_register_gen (rawnum, buf); } void write_register_gen (int regnum, char *buf) { - gdb_assert (current_regcache != NULL); - gdb_assert (current_regcache->descr->gdbarch == current_gdbarch); - if (current_regcache->descr->legacy_p) + if (! gdbarch_register_write_p (current_gdbarch)) { legacy_write_register_gen (regnum, buf); return; @@ -999,10 +564,10 @@ supply_register (int regnum, char *val) set_register_cached (regnum, 1); if (val) - memcpy (register_buffer (current_regcache, regnum), val, + memcpy (register_buffer (regnum), val, REGISTER_RAW_SIZE (regnum)); else - memset (register_buffer (current_regcache, regnum), '\000', + memset (register_buffer (regnum), '\000', REGISTER_RAW_SIZE (regnum)); /* On some architectures, e.g. HPPA, there are a few stray bits in @@ -1022,8 +587,7 @@ supply_register (int regnum, char *val) void regcache_collect (int regnum, void *buf) { - memcpy (buf, register_buffer (current_regcache, regnum), - REGISTER_RAW_SIZE (regnum)); + memcpy (buf, register_buffer (regnum), REGISTER_RAW_SIZE (regnum)); } @@ -1191,53 +755,37 @@ reg_flush_command (char *command, int from_tty) static void build_regcache (void) { - current_regcache = regcache_xmalloc (current_gdbarch); - current_regcache->passthrough_p = 1; - registers = deprecated_grub_regcache_for_registers (current_regcache); - register_valid = deprecated_grub_regcache_for_register_valid (current_regcache); -} - -void -regcache_save (struct regcache *regcache) -{ - int i; - gdb_assert (current_regcache != NULL && regcache != NULL); - gdb_assert (current_regcache->descr->gdbarch == regcache->descr->gdbarch); - regcache_cpy (regcache, current_regcache); -} - -void -regcache_save_no_passthrough (struct regcache *regcache) -{ - gdb_assert (current_regcache != NULL && regcache != NULL); - gdb_assert (current_regcache->descr->gdbarch == regcache->descr->gdbarch); - regcache_cpy_no_passthrough (regcache, current_regcache); -} - -void -regcache_restore (struct regcache *regcache) -{ int i; - gdb_assert (current_regcache != NULL && regcache != NULL); - gdb_assert (current_regcache->descr->gdbarch == regcache->descr->gdbarch); - regcache_cpy (current_regcache, regcache); -} - -void -regcache_restore_no_passthrough (struct regcache *regcache) -{ - char *regcache_registers; - gdb_assert (current_regcache != NULL && regcache != NULL); - gdb_assert (current_regcache->descr->gdbarch == regcache->descr->gdbarch); - regcache_cpy_no_passthrough (current_regcache, regcache); + int sizeof_register_valid; + /* Come up with the real size of the registers buffer. */ + int sizeof_registers = REGISTER_BYTES; /* OK use. */ + for (i = 0; i < NUM_REGS + NUM_PSEUDO_REGS; i++) + { + long regend; + /* Keep extending the buffer so that there is always enough + space for all registers. The comparison is necessary since + legacy code is free to put registers in random places in the + buffer separated by holes. Once REGISTER_BYTE() is killed + this can be greatly simplified. */ + /* FIXME: cagney/2001-12-04: This code shouldn't need to use + REGISTER_BYTE(). Unfortunatly, legacy code likes to lay the + buffer out so that certain registers just happen to overlap. + Ulgh! New targets use gdbarch's register read/write and + entirely avoid this uglyness. */ + regend = REGISTER_BYTE (i) + REGISTER_RAW_SIZE (i); + if (sizeof_registers < regend) + sizeof_registers = regend; + } + registers = xmalloc (sizeof_registers); + sizeof_register_valid = ((NUM_REGS + NUM_PSEUDO_REGS) + * sizeof (*register_valid)); + register_valid = xmalloc (sizeof_register_valid); + memset (register_valid, 0, sizeof_register_valid); } void _initialize_regcache (void) { - regcache_data_handle = register_gdbarch_data (init_regcache_descr, - xfree_regcache_descr); - REGISTER_GDBARCH_SWAP (current_regcache); register_gdbarch_swap (®isters, sizeof (registers), NULL); register_gdbarch_swap (®ister_valid, sizeof (register_valid), NULL); register_gdbarch_swap (NULL, 0, build_regcache); diff --git a/gdb/regcache.h b/gdb/regcache.h index 17e01386fe8..4e854d31667 100644 --- a/gdb/regcache.h +++ b/gdb/regcache.h @@ -1,7 +1,6 @@ /* Cache and manage the values of registers for GDB, the GNU debugger. - - Copyright 1986, 1987, 1989, 1991, 1994, 1995, 1996, 1998, 2000, - 2001, 2002 Free Software Foundation, Inc. + Copyright 1986, 1987, 1989, 1991, 1994, 1995, 1996, 1998, 2000, 2001 + Free Software Foundation, Inc. This file is part of GDB. @@ -23,20 +22,11 @@ #ifndef REGCACHE_H #define REGCACHE_H -struct regcache; - -extern struct regcache *current_regcache; - -void regcache_xfree (struct regcache *regcache); -struct regcache *regcache_xmalloc (struct gdbarch *gdbarch); - /* Transfer a raw register [0..NUM_REGS) between core-gdb and the regcache. */ -void regcache_read (struct regcache *regcache, int rawnum, char *buf); -void regcache_write (struct regcache *regcache, int rawnum, char *buf); -int regcache_valid_p (struct regcache *regcache, int regnum); -CORE_ADDR regcache_read_as_address (struct regcache *regcache, int rawnum); +void regcache_read (int rawnum, char *buf); +void regcache_write (int rawnum, char *buf); /* Transfer a raw register [0..NUM_REGS) between the regcache and the target. These functions are called by the target in response to a @@ -57,25 +47,6 @@ extern char *registers; extern signed char *register_valid; -/* Save/restore the register cache using the regbuf. The operation is - write through - it is strictly for code that needs to restore the - target's registers to a previous state. - - ``no passthrough'' versions do not go through to the target. They - only save values already in the cache. */ - -extern void regcache_save (struct regcache *regcache); -extern void regcache_restore (struct regcache *regcache); -extern struct regcache *regcache_dup (struct regcache *regcache); -extern void regcache_save_no_passthrough (struct regcache *regcache); -extern void regcache_restore_no_passthrough (struct regcache *regcache); -extern struct regcache *regcache_dup_no_passthrough (struct regcache *regcache); -extern void regcache_cpy (struct regcache *dest, struct regcache *src); -extern void regcache_cpy_no_passthrough (struct regcache *dest, struct regcache *src); - -extern char *deprecated_grub_regcache_for_registers (struct regcache *); -extern char *deprecated_grub_regcache_for_register_valid (struct regcache *); - extern int register_cached (int regnum); extern void set_register_cached (int regnum, int state); diff --git a/gdb/remote-rdi.c b/gdb/remote-rdi.c index 5243f9bd28f..228e3d98c37 100644 --- a/gdb/remote-rdi.c +++ b/gdb/remote-rdi.c @@ -1041,24 +1041,24 @@ _initialize_remote_rdi (void) "Withough an argument, it will display current state.\n", &maintenancelist); - add_show_from_set - (add_set_boolean_cmd - ("rdiromatzero", no_class, &rom_at_zero, - "Set target has ROM at addr 0.\n" - "A true value disables vector catching, false enables vector catching.\n" - "This is evaluated at the time the 'target rdi' command is executed\n", - &setlist), - &showlist); - - add_show_from_set - (add_set_boolean_cmd - ("rdiheartbeat", no_class, &rdi_heartbeat, - "Set enable for ADP heartbeat packets.\n" - "I don't know why you would want this. If you enable them,\n" - "it will confuse ARM and EPI JTAG interface boxes as well\n" - "as the Angel Monitor.\n", - &setlist), - &showlist); + add_setshow_boolean_cmd + ("rdiromatzero", no_class, &rom_at_zero, + "Set target has ROM at addr 0.\n" + "A true value disables vector catching, false enables vector catching.\n" + "This is evaluated at the time the 'target rdi' command is executed\n", + "Show if target has ROM at addr 0.\n", + NULL, NULL, + &setlist, &showlist); + + add_setshow_boolean_cmd + ("rdiheartbeat", no_class, &rdi_heartbeat, + "Set enable for ADP heartbeat packets.\n" + "I don't know why you would want this. If you enable them,\n" + "it will confuse ARM and EPI JTAG interface boxes as well\n" + "as the Angel Monitor.\n", + "Show enable for ADP heartbeat packets.\n", + NULL, NULL, + &setlist, &showlist); } /* A little dummy to make linking with the library succeed. */ diff --git a/gdb/remote.c b/gdb/remote.c index a1b90b7a5a4..8231a574ff9 100644 --- a/gdb/remote.c +++ b/gdb/remote.c @@ -583,7 +583,7 @@ struct packet_config { char *name; char *title; - enum cmd_auto_boolean detect; + enum auto_boolean detect; enum packet_support support; }; @@ -602,13 +602,13 @@ update_packet_config (struct packet_config *config) { switch (config->detect) { - case CMD_AUTO_BOOLEAN_TRUE: + case AUTO_BOOLEAN_TRUE: config->support = PACKET_ENABLE; break; - case CMD_AUTO_BOOLEAN_FALSE: + case AUTO_BOOLEAN_FALSE: config->support = PACKET_DISABLE; break; - case CMD_AUTO_BOOLEAN_AUTO: + case AUTO_BOOLEAN_AUTO: config->support = PACKET_SUPPORT_UNKNOWN; break; } @@ -632,12 +632,12 @@ show_packet_config_cmd (struct packet_config *config) } switch (config->detect) { - case CMD_AUTO_BOOLEAN_AUTO: + case AUTO_BOOLEAN_AUTO: printf_filtered ("Support for remote protocol `%s' (%s) packet is auto-detected, currently %s.\n", config->name, config->title, support); break; - case CMD_AUTO_BOOLEAN_TRUE: - case CMD_AUTO_BOOLEAN_FALSE: + case AUTO_BOOLEAN_TRUE: + case AUTO_BOOLEAN_FALSE: printf_filtered ("Support for remote protocol `%s' (%s) packet is currently %s.\n", config->name, config->title, support); break; @@ -648,11 +648,8 @@ static void add_packet_config_cmd (struct packet_config *config, char *name, char *title, - void (*set_func) (char *args, int from_tty, - struct cmd_list_element * - c), - void (*show_func) (char *name, - int from_tty), + cmd_sfunc_ftype *set_func, + cmd_sfunc_ftype *show_func, struct cmd_list_element **set_remote_list, struct cmd_list_element **show_remote_list, int legacy) @@ -664,7 +661,7 @@ add_packet_config_cmd (struct packet_config *config, char *cmd_name; config->name = name; config->title = title; - config->detect = CMD_AUTO_BOOLEAN_AUTO; + config->detect = AUTO_BOOLEAN_AUTO; config->support = PACKET_SUPPORT_UNKNOWN; xasprintf (&set_doc, "Set use of remote protocol `%s' (%s) packet", name, title); @@ -672,12 +669,10 @@ add_packet_config_cmd (struct packet_config *config, name, title); /* set/show TITLE-packet {auto,on,off} */ xasprintf (&cmd_name, "%s-packet", title); - set_cmd = add_set_auto_boolean_cmd (cmd_name, class_obscure, - &config->detect, set_doc, - set_remote_list); - set_cmd_sfunc (set_cmd, set_func); - show_cmd = add_cmd (cmd_name, class_obscure, show_func, show_doc, - show_remote_list); + add_setshow_auto_boolean_cmd (cmd_name, class_obscure, + &config->detect, set_doc, show_doc, + set_func, show_func, + set_remote_list, show_remote_list); /* set/show remote NAME-packet {auto,on,off} -- legacy */ if (legacy) { @@ -730,7 +725,7 @@ packet_ok (const char *buf, struct packet_config *config) switch (config->support) { case PACKET_ENABLE: - if (config->detect == CMD_AUTO_BOOLEAN_AUTO) + if (config->detect == AUTO_BOOLEAN_AUTO) /* If the stub previously indicated that the packet was supported then there is a protocol error.. */ error ("Protocol error: %s (%s) conflicting enabled responses.", @@ -765,7 +760,8 @@ set_remote_protocol_qSymbol_packet_cmd (char *args, int from_tty, } static void -show_remote_protocol_qSymbol_packet_cmd (char *args, int from_tty) +show_remote_protocol_qSymbol_packet_cmd (char *args, int from_tty, + struct cmd_list_element *c) { show_packet_config_cmd (&remote_protocol_qSymbol); } @@ -781,7 +777,8 @@ set_remote_protocol_e_packet_cmd (char *args, int from_tty, } static void -show_remote_protocol_e_packet_cmd (char *args, int from_tty) +show_remote_protocol_e_packet_cmd (char *args, int from_tty, + struct cmd_list_element *c) { show_packet_config_cmd (&remote_protocol_e); } @@ -798,7 +795,8 @@ set_remote_protocol_E_packet_cmd (char *args, int from_tty, } static void -show_remote_protocol_E_packet_cmd (char *args, int from_tty) +show_remote_protocol_E_packet_cmd (char *args, int from_tty, + struct cmd_list_element *c) { show_packet_config_cmd (&remote_protocol_E); } @@ -816,7 +814,8 @@ set_remote_protocol_P_packet_cmd (char *args, int from_tty, } static void -show_remote_protocol_P_packet_cmd (char *args, int from_tty) +show_remote_protocol_P_packet_cmd (char *args, int from_tty, + struct cmd_list_element *c) { show_packet_config_cmd (&remote_protocol_P); } @@ -846,7 +845,8 @@ set_remote_protocol_Z_software_bp_packet_cmd (char *args, int from_tty, } static void -show_remote_protocol_Z_software_bp_packet_cmd (char *args, int from_tty) +show_remote_protocol_Z_software_bp_packet_cmd (char *args, int from_tty, + struct cmd_list_element *c) { show_packet_config_cmd (&remote_protocol_Z[Z_PACKET_SOFTWARE_BP]); } @@ -859,7 +859,8 @@ set_remote_protocol_Z_hardware_bp_packet_cmd (char *args, int from_tty, } static void -show_remote_protocol_Z_hardware_bp_packet_cmd (char *args, int from_tty) +show_remote_protocol_Z_hardware_bp_packet_cmd (char *args, int from_tty, + struct cmd_list_element *c) { show_packet_config_cmd (&remote_protocol_Z[Z_PACKET_HARDWARE_BP]); } @@ -872,7 +873,8 @@ set_remote_protocol_Z_write_wp_packet_cmd (char *args, int from_tty, } static void -show_remote_protocol_Z_write_wp_packet_cmd (char *args, int from_tty) +show_remote_protocol_Z_write_wp_packet_cmd (char *args, int from_tty, + struct cmd_list_element *c) { show_packet_config_cmd (&remote_protocol_Z[Z_PACKET_WRITE_WP]); } @@ -885,7 +887,8 @@ set_remote_protocol_Z_read_wp_packet_cmd (char *args, int from_tty, } static void -show_remote_protocol_Z_read_wp_packet_cmd (char *args, int from_tty) +show_remote_protocol_Z_read_wp_packet_cmd (char *args, int from_tty, + struct cmd_list_element *c) { show_packet_config_cmd (&remote_protocol_Z[Z_PACKET_READ_WP]); } @@ -898,7 +901,8 @@ set_remote_protocol_Z_access_wp_packet_cmd (char *args, int from_tty, } static void -show_remote_protocol_Z_access_wp_packet_cmd (char *args, int from_tty) +show_remote_protocol_Z_access_wp_packet_cmd (char *args, int from_tty, + struct cmd_list_element *c) { show_packet_config_cmd (&remote_protocol_Z[Z_PACKET_ACCESS_WP]); } @@ -906,7 +910,7 @@ show_remote_protocol_Z_access_wp_packet_cmd (char *args, int from_tty) /* For compatibility with older distributions. Provide a ``set remote Z-packet ...'' command that updates all the Z packet types. */ -static enum cmd_auto_boolean remote_Z_packet_detect; +static enum auto_boolean remote_Z_packet_detect; static void set_remote_protocol_Z_packet_cmd (char *args, int from_tty, @@ -921,7 +925,8 @@ set_remote_protocol_Z_packet_cmd (char *args, int from_tty, } static void -show_remote_protocol_Z_packet_cmd (char *args, int from_tty) +show_remote_protocol_Z_packet_cmd (char *args, int from_tty, + struct cmd_list_element *c) { int i; for (i = 0; i < NR_Z_PACKET_TYPES; i++) @@ -962,8 +967,8 @@ set_remote_protocol_binary_download_cmd (char *args, } static void -show_remote_protocol_binary_download_cmd (char *args, - int from_tty) +show_remote_protocol_binary_download_cmd (char *args, int from_tty, + struct cmd_list_element *c) { show_packet_config_cmd (&remote_protocol_binary_download); } @@ -5968,13 +5973,14 @@ set_remote_cmd (char *args, int from_tty) static void show_remote_cmd (char *args, int from_tty) { - - show_remote_protocol_Z_packet_cmd (args, from_tty); - show_remote_protocol_e_packet_cmd (args, from_tty); - show_remote_protocol_E_packet_cmd (args, from_tty); - show_remote_protocol_P_packet_cmd (args, from_tty); - show_remote_protocol_qSymbol_packet_cmd (args, from_tty); - show_remote_protocol_binary_download_cmd (args, from_tty); + /* FIXME: cagney/2002-06-15: This function should iterate over + remote_show_cmdlist for a list of sub commands to show. */ + show_remote_protocol_Z_packet_cmd (args, from_tty, NULL); + show_remote_protocol_e_packet_cmd (args, from_tty, NULL); + show_remote_protocol_E_packet_cmd (args, from_tty, NULL); + show_remote_protocol_P_packet_cmd (args, from_tty, NULL); + show_remote_protocol_qSymbol_packet_cmd (args, from_tty, NULL); + show_remote_protocol_binary_download_cmd (args, from_tty, NULL); } static void @@ -6069,11 +6075,11 @@ response packet. GDB supplies the initial `$' character, and the\n\ terminating `#' character and checksum.", &maintenancelist); - add_show_from_set - (add_set_boolean_cmd ("remotebreak", no_class, &remote_break, - "Set whether to send break if interrupted.\n", - &setlist), - &showlist); + add_setshow_boolean_cmd ("remotebreak", no_class, &remote_break, + "Set whether to send break if interrupted.\n", + "Show whether to send break if interrupted.\n", + NULL, NULL, + &setlist, &showlist); /* Install commands for configuring memory read/write packets. */ @@ -6150,7 +6156,7 @@ in a memory packet.\n", 0); /* Disable by default. The ``e'' packet has nasty interactions with the threading code - it relies on global state. */ - remote_protocol_e.detect = CMD_AUTO_BOOLEAN_FALSE; + remote_protocol_e.detect = AUTO_BOOLEAN_FALSE; update_packet_config (&remote_protocol_e); add_packet_config_cmd (&remote_protocol_E, @@ -6161,7 +6167,7 @@ in a memory packet.\n", 0); /* Disable by default. The ``e'' packet has nasty interactions with the threading code - it relies on global state. */ - remote_protocol_E.detect = CMD_AUTO_BOOLEAN_FALSE; + remote_protocol_E.detect = AUTO_BOOLEAN_FALSE; update_packet_config (&remote_protocol_E); add_packet_config_cmd (&remote_protocol_P, @@ -6207,12 +6213,11 @@ in a memory packet.\n", 0); /* Keep the old ``set remote Z-packet ...'' working. */ - tmpcmd = add_set_auto_boolean_cmd ("Z-packet", class_obscure, - &remote_Z_packet_detect, - "\ -Set use of remote protocol `Z' packets", &remote_set_cmdlist); - set_cmd_sfunc (tmpcmd, set_remote_protocol_Z_packet_cmd); - add_cmd ("Z-packet", class_obscure, show_remote_protocol_Z_packet_cmd, - "Show use of remote protocol `Z' packets ", - &remote_show_cmdlist); + add_setshow_auto_boolean_cmd ("Z-packet", class_obscure, + &remote_Z_packet_detect, "\ +Set use of remote protocol `Z' packets", + "Show use of remote protocol `Z' packets ", + set_remote_protocol_Z_packet_cmd, + show_remote_protocol_Z_packet_cmd, + &remote_set_cmdlist, &remote_show_cmdlist); } diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c index db38203b5e0..5a09361a53e 100644 --- a/gdb/rs6000-tdep.c +++ b/gdb/rs6000-tdep.c @@ -1579,7 +1579,7 @@ regsize (const struct reg *reg, int wordsize) /* Return the name of register number N, or null if no such register exists in the current architecture. */ -static char * +static const char * rs6000_register_name (int n) { struct gdbarch_tdep *tdep = TDEP; @@ -2624,7 +2624,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) set_gdbarch_register_convert_to_raw (gdbarch, rs6000_register_convert_to_raw); set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum); - set_gdbarch_extract_return_value (gdbarch, rs6000_extract_return_value); + set_gdbarch_deprecated_extract_return_value (gdbarch, rs6000_extract_return_value); /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments() is correct for the SysV ABI when the wordsize is 8, but I'm also @@ -2640,7 +2640,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) set_gdbarch_store_struct_return (gdbarch, rs6000_store_struct_return); set_gdbarch_store_return_value (gdbarch, rs6000_store_return_value); - set_gdbarch_extract_struct_value_address (gdbarch, rs6000_extract_struct_value_address); + set_gdbarch_deprecated_extract_struct_value_address (gdbarch, rs6000_extract_struct_value_address); set_gdbarch_pop_frame (gdbarch, rs6000_pop_frame); set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue); diff --git a/gdb/s390-tdep.c b/gdb/s390-tdep.c index 8add4952f19..cb3b81de05a 100644 --- a/gdb/s390-tdep.c +++ b/gdb/s390-tdep.c @@ -150,7 +150,7 @@ s390_memset_extra_info (struct frame_extra_info *fextra_info) -char * +const char * s390_register_name (int reg_nr) { static char *register_names[] = { diff --git a/gdb/sh-tdep.c b/gdb/sh-tdep.c index 375b55a6b66..2ef89faadf1 100644 --- a/gdb/sh-tdep.c +++ b/gdb/sh-tdep.c @@ -68,7 +68,7 @@ struct frame_extra_info int f_offset; }; -static char * +static const char * sh_generic_register_name (int reg_nr) { static char *register_names[] = @@ -90,7 +90,7 @@ sh_generic_register_name (int reg_nr) return register_names[reg_nr]; } -static char * +static const char * sh_sh_register_name (int reg_nr) { static char *register_names[] = @@ -112,7 +112,7 @@ sh_sh_register_name (int reg_nr) return register_names[reg_nr]; } -static char * +static const char * sh_sh3_register_name (int reg_nr) { static char *register_names[] = @@ -134,7 +134,7 @@ sh_sh3_register_name (int reg_nr) return register_names[reg_nr]; } -static char * +static const char * sh_sh3e_register_name (int reg_nr) { static char *register_names[] = @@ -156,7 +156,7 @@ sh_sh3e_register_name (int reg_nr) return register_names[reg_nr]; } -static char * +static const char * sh_sh_dsp_register_name (int reg_nr) { static char *register_names[] = @@ -178,7 +178,7 @@ sh_sh_dsp_register_name (int reg_nr) return register_names[reg_nr]; } -static char * +static const char * sh_sh3_dsp_register_name (int reg_nr) { static char *register_names[] = @@ -201,7 +201,7 @@ sh_sh3_dsp_register_name (int reg_nr) return register_names[reg_nr]; } -static char * +static const char * sh_sh4_register_name (int reg_nr) { static char *register_names[] = @@ -236,7 +236,7 @@ sh_sh4_register_name (int reg_nr) return register_names[reg_nr]; } -static char * +static const char * sh_sh64_register_name (int reg_nr) { static char *register_names[] = @@ -3385,9 +3385,9 @@ sh_pseudo_register_read (int reg_nr, char *buffer) /* Build the value in the provided buffer. */ /* Read the real regs for which this one is an alias. */ for (portion = 0; portion < 2; portion++) - regcache_read (base_regnum + portion, - temp_buffer - + REGISTER_RAW_SIZE (base_regnum) * portion); + regcache_read (current_regcache, base_regnum + portion, + (temp_buffer + + REGISTER_RAW_SIZE (base_regnum) * portion)); /* We must pay attention to the endiannes. */ sh_sh4_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr), @@ -3400,7 +3400,7 @@ sh_pseudo_register_read (int reg_nr, char *buffer) /* Read the real regs for which this one is an alias. */ for (portion = 0; portion < 4; portion++) - regcache_read (base_regnum + portion, + regcache_read (current_regcache, base_regnum + portion, buffer + REGISTER_RAW_SIZE (base_regnum) * portion); } } @@ -3410,7 +3410,7 @@ sh4_register_read (struct gdbarch *gdbarch, int reg_nr, char *buffer) { if (reg_nr >= 0 && reg_nr < gdbarch_tdep (current_gdbarch)->DR0_REGNUM) /* It is a regular register. */ - regcache_read (reg_nr, buffer); + regcache_read (current_regcache, reg_nr, buffer); else /* It is a pseudo register and we need to construct its value */ sh_pseudo_register_read (reg_nr, buffer); @@ -3434,9 +3434,9 @@ sh64_pseudo_register_read (int reg_nr, char *buffer) /* DR regs are double precision registers obtained by concatenating 2 single precision floating point registers. */ for (portion = 0; portion < 2; portion++) - regcache_read (base_regnum + portion, - temp_buffer - + REGISTER_RAW_SIZE (base_regnum) * portion); + regcache_read (current_regcache, base_regnum + portion, + (temp_buffer + + REGISTER_RAW_SIZE (base_regnum) * portion)); /* We must pay attention to the endiannes. */ sh_sh64_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr), @@ -3453,8 +3453,8 @@ sh64_pseudo_register_read (int reg_nr, char *buffer) /* FPP regs are pairs of single precision registers obtained by concatenating 2 single precision floating point registers. */ for (portion = 0; portion < 2; portion++) - regcache_read (base_regnum + portion, - buffer + REGISTER_RAW_SIZE (base_regnum) * portion); + regcache_read (current_regcache, base_regnum + portion, + buffer + REGISTER_RAW_SIZE (base_regnum) * portion); } else if (reg_nr >= tdep->FV0_REGNUM @@ -3466,8 +3466,8 @@ sh64_pseudo_register_read (int reg_nr, char *buffer) /* FV regs are vectors of single precision registers obtained by concatenating 4 single precision floating point registers. */ for (portion = 0; portion < 4; portion++) - regcache_read (base_regnum + portion, - buffer + REGISTER_RAW_SIZE (base_regnum) * portion); + regcache_read (current_regcache, base_regnum + portion, + buffer + REGISTER_RAW_SIZE (base_regnum) * portion); } /* sh compact pseudo registers. 1-to-1 with a shmedia register */ @@ -3477,7 +3477,7 @@ sh64_pseudo_register_read (int reg_nr, char *buffer) base_regnum = sh64_compact_reg_base_num (reg_nr); /* Build the value in the provided buffer. */ - regcache_read (base_regnum, temp_buffer); + regcache_read (current_regcache, base_regnum, temp_buffer); if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) offset = 4; memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/ @@ -3491,7 +3491,7 @@ sh64_pseudo_register_read (int reg_nr, char *buffer) /* Build the value in the provided buffer. */ /* Floating point registers map 1-1 to the media fp regs, they have the same size and endienness. */ - regcache_read (base_regnum, buffer); + regcache_read (current_regcache, base_regnum, buffer); } else if (reg_nr >= tdep->DR0_C_REGNUM @@ -3502,9 +3502,9 @@ sh64_pseudo_register_read (int reg_nr, char *buffer) /* DR_C regs are double precision registers obtained by concatenating 2 single precision floating point registers. */ for (portion = 0; portion < 2; portion++) - regcache_read (base_regnum + portion, - temp_buffer - + REGISTER_RAW_SIZE (base_regnum) * portion); + regcache_read (current_regcache, base_regnum + portion, + (temp_buffer + + REGISTER_RAW_SIZE (base_regnum) * portion)); /* We must pay attention to the endiannes. */ sh_sh64_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr), @@ -3520,8 +3520,8 @@ sh64_pseudo_register_read (int reg_nr, char *buffer) /* FV_C regs are vectors of single precision registers obtained by concatenating 4 single precision floating point registers. */ for (portion = 0; portion < 4; portion++) - regcache_read (base_regnum + portion, - buffer + REGISTER_RAW_SIZE (base_regnum) * portion); + regcache_read (current_regcache, base_regnum + portion, + buffer + REGISTER_RAW_SIZE (base_regnum) * portion); } else if (reg_nr == tdep->FPSCR_C_REGNUM) @@ -3552,11 +3552,11 @@ sh64_pseudo_register_read (int reg_nr, char *buffer) */ /* *INDENT-ON* */ /* Get FPSCR into a local buffer */ - regcache_read (fpscr_base_regnum, temp_buffer); + regcache_read (current_regcache, fpscr_base_regnum, temp_buffer); /* Get value as an int. */ fpscr_value = extract_unsigned_integer (temp_buffer, 4); /* Get SR into a local buffer */ - regcache_read (sr_base_regnum, temp_buffer); + regcache_read (current_regcache, sr_base_regnum, temp_buffer); /* Get value as an int. */ sr_value = extract_unsigned_integer (temp_buffer, 4); /* Build the new value. */ @@ -3574,7 +3574,7 @@ sh64_pseudo_register_read (int reg_nr, char *buffer) /* FPUL_C register is floating point register 32, same size, same endianness. */ - regcache_read (base_regnum, buffer); + regcache_read (current_regcache, base_regnum, buffer); } } @@ -3584,7 +3584,7 @@ sh64_register_read (struct gdbarch *gdbarch, int reg_nr, char *buffer) if (reg_nr >= 0 && reg_nr < gdbarch_tdep (current_gdbarch)->DR0_REGNUM) /* It is a regular register. */ - regcache_read (reg_nr, buffer); + regcache_read (current_regcache, reg_nr, buffer); else /* It is a pseudo register and we need to construct its value */ sh64_pseudo_register_read (reg_nr, buffer); @@ -3608,8 +3608,9 @@ sh_pseudo_register_write (int reg_nr, char *buffer) /* Write the real regs for which this one is an alias. */ for (portion = 0; portion < 2; portion++) - regcache_write (base_regnum + portion, - temp_buffer + REGISTER_RAW_SIZE (base_regnum) * portion); + regcache_write (current_regcache, base_regnum + portion, + (temp_buffer + + REGISTER_RAW_SIZE (base_regnum) * portion)); } else if (reg_nr >= tdep->FV0_REGNUM && reg_nr <= tdep->FV_LAST_REGNUM) @@ -3618,7 +3619,7 @@ sh_pseudo_register_write (int reg_nr, char *buffer) /* Write the real regs for which this one is an alias. */ for (portion = 0; portion < 4; portion++) - regcache_write (base_regnum + portion, + regcache_write (current_regcache, base_regnum + portion, buffer + REGISTER_RAW_SIZE (base_regnum) * portion); } } @@ -3628,7 +3629,7 @@ sh4_register_write (struct gdbarch *gdbarch, int reg_nr, char *buffer) { if (reg_nr >= 0 && reg_nr < gdbarch_tdep (current_gdbarch)->DR0_REGNUM) /* It is a regular register. */ - regcache_write (reg_nr, buffer); + regcache_write (current_regcache, reg_nr, buffer); else /* It is a pseudo register and we need to construct its value */ sh_pseudo_register_write (reg_nr, buffer); @@ -3653,8 +3654,9 @@ sh64_pseudo_register_write (int reg_nr, char *buffer) /* Write the real regs for which this one is an alias. */ for (portion = 0; portion < 2; portion++) - regcache_write (base_regnum + portion, - temp_buffer + REGISTER_RAW_SIZE (base_regnum) * portion); + regcache_write (current_regcache, base_regnum + portion, + (temp_buffer + + REGISTER_RAW_SIZE (base_regnum) * portion)); } else if (reg_nr >= tdep->FPP0_REGNUM @@ -3664,7 +3666,7 @@ sh64_pseudo_register_write (int reg_nr, char *buffer) /* Write the real regs for which this one is an alias. */ for (portion = 0; portion < 2; portion++) - regcache_write (base_regnum + portion, + regcache_write (current_regcache, base_regnum + portion, buffer + REGISTER_RAW_SIZE (base_regnum) * portion); } @@ -3675,7 +3677,7 @@ sh64_pseudo_register_write (int reg_nr, char *buffer) /* Write the real regs for which this one is an alias. */ for (portion = 0; portion < 4; portion++) - regcache_write (base_regnum + portion, + regcache_write (current_regcache, base_regnum + portion, buffer + REGISTER_RAW_SIZE (base_regnum) * portion); } @@ -3693,10 +3695,10 @@ sh64_pseudo_register_write (int reg_nr, char *buffer) /* Let's read the value of the base register into a temporary buffer, so that overwriting the last four bytes with the new value of the pseudo will leave the upper 4 bytes unchanged. */ - regcache_read (base_regnum, temp_buffer); + regcache_read (current_regcache, base_regnum, temp_buffer); /* Write as an 8 byte quantity */ memcpy (temp_buffer + offset, buffer, 4); - regcache_write (base_regnum, temp_buffer); + regcache_write (current_regcache, base_regnum, temp_buffer); } /* sh floating point compact pseudo registers. 1-to-1 with a shmedia @@ -3705,7 +3707,7 @@ sh64_pseudo_register_write (int reg_nr, char *buffer) && reg_nr <= tdep->FP_LAST_C_REGNUM) { base_regnum = sh64_compact_reg_base_num (reg_nr); - regcache_write (base_regnum, buffer); + regcache_write (current_regcache, base_regnum, buffer); } else if (reg_nr >= tdep->DR0_C_REGNUM @@ -3718,8 +3720,9 @@ sh64_pseudo_register_write (int reg_nr, char *buffer) sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr, buffer, temp_buffer); - regcache_write (base_regnum + portion, - temp_buffer + REGISTER_RAW_SIZE (base_regnum) * portion); + regcache_write (current_regcache, base_regnum + portion, + (temp_buffer + + REGISTER_RAW_SIZE (base_regnum) * portion)); } } @@ -3730,7 +3733,7 @@ sh64_pseudo_register_write (int reg_nr, char *buffer) for (portion = 0; portion < 4; portion++) { - regcache_write (base_regnum + portion, + regcache_write (current_regcache, base_regnum + portion, buffer + REGISTER_RAW_SIZE (base_regnum) * portion); } } @@ -3773,25 +3776,25 @@ sh64_pseudo_register_write (int reg_nr, char *buffer) fpscr_value = fpscr_c_value & fpscr_mask; sr_value = (fpscr_value & sr_mask) >> 6; - regcache_read (fpscr_base_regnum, temp_buffer); + regcache_read (current_regcache, fpscr_base_regnum, temp_buffer); old_fpscr_value = extract_unsigned_integer (temp_buffer, 4); old_fpscr_value &= 0xfffc0002; fpscr_value |= old_fpscr_value; store_unsigned_integer (temp_buffer, 4, fpscr_value); - regcache_write (fpscr_base_regnum, temp_buffer); + regcache_write (current_regcache, fpscr_base_regnum, temp_buffer); - regcache_read (sr_base_regnum, temp_buffer); + regcache_read (current_regcache, sr_base_regnum, temp_buffer); old_sr_value = extract_unsigned_integer (temp_buffer, 4); old_sr_value &= 0xffff8fff; sr_value |= old_sr_value; store_unsigned_integer (temp_buffer, 4, sr_value); - regcache_write (sr_base_regnum, temp_buffer); + regcache_write (current_regcache, sr_base_regnum, temp_buffer); } else if (reg_nr == tdep->FPUL_C_REGNUM) { base_regnum = sh64_compact_reg_base_num (reg_nr); - regcache_write (base_regnum, buffer); + regcache_write (current_regcache, base_regnum, buffer); } } @@ -3800,7 +3803,7 @@ sh64_register_write (struct gdbarch *gdbarch, int reg_nr, char *buffer) { if (reg_nr >= 0 && reg_nr < gdbarch_tdep (current_gdbarch)->DR0_REGNUM) /* It is a regular register. */ - regcache_write (reg_nr, buffer); + regcache_write (current_regcache, reg_nr, buffer); else /* It is a pseudo register and we need to construct its value */ sh64_pseudo_register_write (reg_nr, buffer); diff --git a/gdb/sparc-tdep.c b/gdb/sparc-tdep.c index 6ad95c48dc8..2ca35b1910c 100644 --- a/gdb/sparc-tdep.c +++ b/gdb/sparc-tdep.c @@ -2551,7 +2551,7 @@ sparc_print_extra_frame_info (struct frame_info *fi) /* MULTI_ARCH support */ -static char * +static const char * sparc32_register_name (int regno) { static char *register_names[] = @@ -2575,7 +2575,7 @@ sparc32_register_name (int regno) return register_names[regno]; } -static char * +static const char * sparc64_register_name (int regno) { static char *register_names[] = @@ -2607,7 +2607,7 @@ sparc64_register_name (int regno) return register_names[regno]; } -static char * +static const char * sparclite_register_name (int regno) { static char *register_names[] = @@ -2632,7 +2632,7 @@ sparclite_register_name (int regno) return register_names[regno]; } -static char * +static const char * sparclet_register_name (int regno) { static char *register_names[] = diff --git a/gdb/target.c b/gdb/target.c index 2cd492809f4..69f034513e4 100644 --- a/gdb/target.c +++ b/gdb/target.c @@ -2299,16 +2299,15 @@ initialize_targets (void) When non-zero, target debugging is enabled.", &setdebuglist), &showdebuglist); - add_show_from_set - (add_set_boolean_cmd - ("trust-readonly-sections", class_support, - &trust_readonly, - "Set mode for reading from readonly sections.\n\ + add_setshow_boolean_cmd ("trust-readonly-sections", class_support, + &trust_readonly, "\ +Set mode for reading from readonly sections.\n\ When this mode is on, memory reads from readonly sections (such as .text)\n\ will be read from the object file instead of from the target. This will\n\ -result in significant performance improvement for remote targets.", - &setlist), - &showlist); +result in significant performance improvement for remote targets.", "\ +Set mode for reading from readonly sections.\n", + NULL, NULL, + &setlist, &showlist); add_com ("monitor", class_obscure, do_monitor_command, "Send a command to the remote monitor (remote targets only)."); diff --git a/gdb/v850-tdep.c b/gdb/v850-tdep.c index dc3bc6ba9e0..c4f6bd908b5 100644 --- a/gdb/v850-tdep.c +++ b/gdb/v850-tdep.c @@ -205,7 +205,7 @@ static CORE_ADDR v850_scan_prologue (CORE_ADDR pc, struct prologue_info *fs); /* Function: v850_register_name Returns the name of the v850/v850e register N. */ -static char * +static const char * v850_register_name (int regnum) { if (regnum < 0 || regnum >= E_NUM_REGS) diff --git a/gdb/valops.c b/gdb/valops.c index 691c1c4461f..22c744d7608 100644 --- a/gdb/valops.c +++ b/gdb/valops.c @@ -961,9 +961,9 @@ value_ind (struct value *arg1) to do. "long long" variables are rare enough that BUILTIN_TYPE_LONGEST would seem to be a mistake. */ if (TYPE_CODE (base_type) == TYPE_CODE_INT) - return value_at (builtin_type_int, - (CORE_ADDR) value_as_long (arg1), - VALUE_BFD_SECTION (arg1)); + return value_at_lazy (builtin_type_int, + (CORE_ADDR) value_as_long (arg1), + VALUE_BFD_SECTION (arg1)); else if (TYPE_CODE (base_type) == TYPE_CODE_PTR) { struct type *enc_type; diff --git a/gdb/values.c b/gdb/values.c index 69e1dfa5ac2..a72b7fa3ccd 100644 --- a/gdb/values.c +++ b/gdb/values.c @@ -1231,6 +1231,7 @@ value_being_returned (struct type *valtype, struct regcache *retbuf, struct value *val; CORE_ADDR addr; +#if 0 /* If this is not defined, just use EXTRACT_RETURN_VALUE instead. */ if (EXTRACT_STRUCT_VALUE_ADDRESS_P ()) if (struct_return) @@ -1240,6 +1241,17 @@ value_being_returned (struct type *valtype, struct regcache *retbuf, error ("Function return value unknown."); return value_at (valtype, addr, NULL); } +#endif + + /* If this is not defined, just use EXTRACT_RETURN_VALUE instead. */ + if (DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS_P ()) + if (struct_return) + { + addr = DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS (retbuf); + if (!addr) + error ("Function return value unknown."); + return value_at (valtype, addr, NULL); + } /* If this is not defined, just use EXTRACT_RETURN_VALUE instead. */ if (DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS_P ()) @@ -1254,6 +1266,7 @@ value_being_returned (struct type *valtype, struct regcache *retbuf, val = allocate_value (valtype); CHECK_TYPEDEF (valtype); +#define EXTRACT_RETURN_VALUE DEPRECATED_EXTRACT_RETURN_VALUE EXTRACT_RETURN_VALUE (valtype, retbuf, VALUE_CONTENTS_RAW (val)); return val; diff --git a/gdb/varobj.c b/gdb/varobj.c index 9ae145e2170..09b5a7cb888 100644 --- a/gdb/varobj.c +++ b/gdb/varobj.c @@ -1210,7 +1210,7 @@ create_child (struct varobj *parent, int index, char *name) child->name = name; child->index = index; child->value = value_of_child (parent, index); - if ((!CPLUS_FAKE_CHILD(child) && child->value == NULL) || parent->error) + if ((!CPLUS_FAKE_CHILD (child) && child->value == NULL) || parent->error) child->error = 1; child->parent = parent; child->root = parent->root; @@ -1645,8 +1645,8 @@ value_of_child (struct varobj *parent, int index) if (value != NULL && VALUE_LAZY (value)) { /* If we fail to fetch the value of the child, return - NULL so that callers notice that we're leaving an - error message. */ + NULL so that callers notice that we're leaving an + error message. */ if (!gdb_value_fetch_lazy (value)) value = NULL; } @@ -1929,7 +1929,8 @@ c_value_of_child (struct varobj *parent, int index) case TYPE_CODE_STRUCT: case TYPE_CODE_UNION: - gdb_value_struct_elt (NULL, &value, &temp, NULL, name, NULL, "vstructure"); + gdb_value_struct_elt (NULL, &value, &temp, NULL, name, NULL, + "vstructure"); break; case TYPE_CODE_PTR: @@ -1937,7 +1938,8 @@ c_value_of_child (struct varobj *parent, int index) { case TYPE_CODE_STRUCT: case TYPE_CODE_UNION: - gdb_value_struct_elt (NULL, &value, &temp, NULL, name, NULL, "vstructure"); + gdb_value_struct_elt (NULL, &value, &temp, NULL, name, NULL, + "vstructure"); break; default: @@ -2062,9 +2064,10 @@ c_value_of_variable (struct varobj *var) { if (VALUE_LAZY (var->value)) gdb_value_fetch_lazy (var->value); - val_print (VALUE_TYPE (var->value), VALUE_CONTENTS_RAW (var->value), 0, - VALUE_ADDRESS (var->value), - stb, format_code[(int) var->format], 1, 0, 0); + val_print (VALUE_TYPE (var->value), + VALUE_CONTENTS_RAW (var->value), 0, + VALUE_ADDRESS (var->value), stb, + format_code[(int) var->format], 1, 0, 0); thevalue = ui_file_xstrdup (stb, &dummy); do_cleanups (old_chain); } @@ -2200,7 +2203,8 @@ cplus_name_of_child (struct varobj *parent, int index) /* FIXME: This assumes that type orders inherited, public, private, protected */ i = index + TYPE_N_BASECLASSES (type); - if (STREQ (parent->name, "private") || STREQ (parent->name, "protected")) + if (STREQ (parent->name, "private") + || STREQ (parent->name, "protected")) i += children[v_public]; if (STREQ (parent->name, "protected")) i += children[v_private]; diff --git a/gdb/vax-tdep.c b/gdb/vax-tdep.c index 2e82d927e10..a723a6d0306 100644 --- a/gdb/vax-tdep.c +++ b/gdb/vax-tdep.c @@ -83,7 +83,7 @@ static gdbarch_fix_call_dummy_ftype vax_fix_call_dummy; static unsigned char *print_insn_arg (); -static char * +static const char * vax_register_name (int regno) { static char *register_names[] = diff --git a/gdb/version.in b/gdb/version.in index ff62cb84c8f..d89eb22266c 100644 --- a/gdb/version.in +++ b/gdb/version.in @@ -1 +1 @@ -2002-06-15-cvs +2002-06-20-cvs diff --git a/gdb/xstormy16-tdep.c b/gdb/xstormy16-tdep.c index 9be59718918..8e283b861ea 100644 --- a/gdb/xstormy16-tdep.c +++ b/gdb/xstormy16-tdep.c @@ -97,7 +97,7 @@ enum /* Function: xstormy16_register_name Returns the name of the standard Xstormy16 register N. */ -static char * +static const char * xstormy16_register_name (int regnum) { static char *register_names[] = { diff --git a/libiberty/ChangeLog b/libiberty/ChangeLog index 916995e5b12..06cb89f4b0e 100644 --- a/libiberty/ChangeLog +++ b/libiberty/ChangeLog @@ -1,3 +1,8 @@ +2002-06-17 Douglas Rupp <rupp@gnat.com> + + * lbasename.c: Add 2002 to copyright. + (IS_DIR_SEPARATOR): Remove VMS junk. + 2002-06-05 Geoffrey Keating <geoffk@redhat.com> * hashtab.c (htab_create): New stub function for backward diff --git a/libiberty/lbasename.c b/libiberty/lbasename.c index cea0253887b..43cb73f0a1d 100644 --- a/libiberty/lbasename.c +++ b/libiberty/lbasename.c @@ -1,6 +1,6 @@ /* Libiberty basename. Like basename, but is not overridden by the system C library. - Copyright (C) 2001 Free Software Foundation, Inc. + Copyright (C) 2001, 2002 Free Software Foundation, Inc. This file is part of the libiberty library. Libiberty is free software; you can redistribute it and/or @@ -53,19 +53,11 @@ and a path ending in @code{/} returns the empty string after it. # endif #endif -/* Define IS_DIR_SEPARATOR. VMS uses '::', ':', '[...]' and '<...>' to - separate the different components of a file specification. It's a - bit of a stretch to call ':', ']' and '>' directory separators, so - just define the test to find the file name component. */ -#ifdef VMS -# define IS_DIR_SEPARATOR(ch) ((ch) == ':' || (ch) == ']' || (ch) == '>') +#ifndef DIR_SEPARATOR_2 +# define IS_DIR_SEPARATOR(ch) ((ch) == DIR_SEPARATOR) #else -# ifndef DIR_SEPARATOR_2 -# define IS_DIR_SEPARATOR(ch) ((ch) == DIR_SEPARATOR) -# else -# define IS_DIR_SEPARATOR(ch) \ +# define IS_DIR_SEPARATOR(ch) \ (((ch) == DIR_SEPARATOR) || ((ch) == DIR_SEPARATOR_2)) -# endif #endif const char * diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 542313e9445..0b8925b25a1 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,27 @@ +2002-06-18 Dave Brolley <brolley@redhat.com> + + * po/POTFILES.in: Add frv-*.[ch]. + * disassemble.c (ARCH_frv): New macro. + (disassembler): Handle bfd_arch_frv. + * configure.in: Support frv_bfd_arch. + * Makefile.am (HFILES): Add frv-*.h. + (CFILES): Add frv-*.c + (ALL_MACHINES): Add frv-*.lo. + (CLEANFILES): Add stamp-frv. + (FRV_DEPS): New variable. + (stamp-frv): New target. + (frv-asm.lo): New target. + (frv-desc.lo): New target. + (frv-dis.lo): New target. + (frv-ibld.lo): New target. + (frv-opc.lo): New target. + (frv-*.[ch]): New files. + +2002-06-18 Ben Elliston <bje@redhat.com> + + * Makefile.am (CGENDEPS): Remove unnecessary stamp-cgen. + * Makefile.in: Regenerate. + 2002-06-08 Alan Modra <amodra@bigpond.net.au> * a29k-dis.c: Replace CONST with const. diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am index 7ee8c32b944..bafdb5753dd 100644 --- a/opcodes/Makefile.am +++ b/opcodes/Makefile.am @@ -26,6 +26,7 @@ LIBIBERTY = ../libiberty/libiberty.a HFILES = \ arm-opc.h \ fr30-desc.h fr30-opc.h \ + frv-desc.h frv-opc.h \ h8500-opc.h \ ia64-asmtab.h \ ia64-opc.h \ @@ -66,6 +67,11 @@ CFILES = \ fr30-dis.c \ fr30-ibld.c \ fr30-opc.c \ + frv-asm.c \ + frv-desc.c \ + frv-dis.c \ + frv-ibld.c \ + frv-opc.c \ h8300-dis.c \ h8500-dis.c \ hppa-dis.c \ @@ -168,6 +174,11 @@ ALL_MACHINES = \ fr30-dis.lo \ fr30-ibld.lo \ fr30-opc.lo \ + frv-asm.lo \ + frv-desc.lo \ + frv-dis.lo \ + frv-ibld.lo \ + frv-opc.lo \ h8300-dis.lo \ h8500-dis.lo \ hppa-dis.lo \ @@ -301,7 +312,7 @@ uninstall_libopcodes: rm -f $(DESTDIR)$(bfdincludedir)/dis-asm.h CLEANFILES = \ - stamp-m32r stamp-fr30 stamp-openrisc \ + stamp-m32r stamp-fr30 stamp-frv stamp-openrisc \ stamp-xstormy16 \ libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2 @@ -311,7 +322,7 @@ CPUDIR = $(CGENDIR)/cpu CGEN = `if test -f ../guile/libguile/guile ; then echo ../guile/libguile/guile; else echo guile ; fi` CGENFLAGS = -v -CGENDEPS = ../cgen/stamp-cgen \ +CGENDEPS = \ $(CGENDIR)/desc.scm $(CGENDIR)/desc-cpu.scm \ $(CGENDIR)/opcodes.scm $(CGENDIR)/opc-asmdis.scm \ $(CGENDIR)/opc-ibld.scm $(CGENDIR)/opc-itab.scm \ @@ -321,11 +332,13 @@ CGENDEPS = ../cgen/stamp-cgen \ if CGEN_MAINT M32R_DEPS = stamp-m32r FR30_DEPS = stamp-fr30 +FRV_DEPS = stamp-frv OPENRISC_DEPS = stamp-openrisc XSTORMY16_DEPS = stamp-xstormy16 else M32R_DEPS = FR30_DEPS = +FRV_DEPS = OPENRISC_DEPS = XSTORMY16_DEPS = endif @@ -348,6 +361,11 @@ $(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30- stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc $(MAKE) run-cgen arch=fr30 prefix=fr30 options= extrafiles= +$(srcdir)/frv-desc.h $(srcdir)/frv-desc.c $(srcdir)/frv-opc.h $(srcdir)/frv-opc.c $(srcdir)/frv-ibld.c $(srcdir)/frv-asm.c $(srcdir)/frv-dis.c: $(FRV_DEPS) + @true +stamp-frv: $(CGENDEPS) $(CPUDIR)/frv.cpu $(CPUDIR)/frv.opc + $(MAKE) run-cgen arch=frv prefix=frv options= extrafiles= + $(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS) @true stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc @@ -495,6 +513,23 @@ fr30-ibld.lo: fr30-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ fr30-opc.lo: fr30-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \ fr30-opc.h $(INCDIR)/libiberty.h +frv-asm.lo: frv-asm.c sysdep.h config.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h frv-desc.h \ + $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h +frv-desc.lo: frv-desc.c sysdep.h config.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h frv-desc.h \ + $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h +frv-dis.lo: frv-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \ + $(BFD_H) $(INCDIR)/ansidecl.h \ + $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen.h \ + frv-opc.h opintl.h +frv-ibld.lo: frv-ibld.c sysdep.h config.h $(INCDIR)/dis-asm.h \ + $(BFD_H) $(INCDIR)/ansidecl.h \ + $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen.h \ + frv-opc.h opintl.h +frv-opc.lo: frv-opc.c sysdep.h config.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h frv-desc.h \ + $(INCDIR)/opcode/cgen.h frv-opc.h h8300-dis.lo: h8300-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/h8300.h $(INCDIR)/dis-asm.h $(BFD_H) \ $(INCDIR)/symcat.h opintl.h diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in index f7147e14bb8..b1b7ae102ad 100644 --- a/opcodes/Makefile.in +++ b/opcodes/Makefile.in @@ -136,6 +136,7 @@ LIBIBERTY = ../libiberty/libiberty.a HFILES = \ arm-opc.h \ fr30-desc.h fr30-opc.h \ + frv-desc.h frv-opc.h \ h8500-opc.h \ ia64-asmtab.h \ ia64-opc.h \ @@ -177,6 +178,11 @@ CFILES = \ fr30-dis.c \ fr30-ibld.c \ fr30-opc.c \ + frv-asm.c \ + frv-desc.c \ + frv-dis.c \ + frv-ibld.c \ + frv-opc.c \ h8300-dis.c \ h8500-dis.c \ hppa-dis.c \ @@ -280,6 +286,11 @@ ALL_MACHINES = \ fr30-dis.lo \ fr30-ibld.lo \ fr30-opc.lo \ + frv-asm.lo \ + frv-desc.lo \ + frv-dis.lo \ + frv-ibld.lo \ + frv-opc.lo \ h8300-dis.lo \ h8500-dis.lo \ hppa-dis.lo \ @@ -368,7 +379,7 @@ noinst_LIBRARIES = libopcodes.a POTFILES = $(HFILES) $(CFILES) CLEANFILES = \ - stamp-m32r stamp-fr30 stamp-openrisc \ + stamp-m32r stamp-fr30 stamp-frv stamp-openrisc \ stamp-xstormy16 \ libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2 @@ -378,7 +389,7 @@ CPUDIR = $(CGENDIR)/cpu CGEN = `if test -f ../guile/libguile/guile ; then echo ../guile/libguile/guile; else echo guile ; fi` CGENFLAGS = -v -CGENDEPS = ../cgen/stamp-cgen \ +CGENDEPS = \ $(CGENDIR)/desc.scm $(CGENDIR)/desc-cpu.scm \ $(CGENDIR)/opcodes.scm $(CGENDIR)/opc-asmdis.scm \ $(CGENDIR)/opc-ibld.scm $(CGENDIR)/opc-itab.scm \ @@ -389,6 +400,8 @@ CGENDEPS = ../cgen/stamp-cgen \ @CGEN_MAINT_FALSE@M32R_DEPS = @CGEN_MAINT_TRUE@FR30_DEPS = @CGEN_MAINT_TRUE@stamp-fr30 @CGEN_MAINT_FALSE@FR30_DEPS = +@CGEN_MAINT_TRUE@FRV_DEPS = @CGEN_MAINT_TRUE@stamp-frv +@CGEN_MAINT_FALSE@FRV_DEPS = @CGEN_MAINT_TRUE@OPENRISC_DEPS = @CGEN_MAINT_TRUE@stamp-openrisc @CGEN_MAINT_FALSE@OPENRISC_DEPS = @CGEN_MAINT_TRUE@XSTORMY16_DEPS = @CGEN_MAINT_TRUE@stamp-xstormy16 @@ -844,6 +857,11 @@ $(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30- stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc $(MAKE) run-cgen arch=fr30 prefix=fr30 options= extrafiles= +$(srcdir)/frv-desc.h $(srcdir)/frv-desc.c $(srcdir)/frv-opc.h $(srcdir)/frv-opc.c $(srcdir)/frv-ibld.c $(srcdir)/frv-asm.c $(srcdir)/frv-dis.c: $(FRV_DEPS) + @true +stamp-frv: $(CGENDEPS) $(CPUDIR)/frv.cpu $(CPUDIR)/frv.opc + $(MAKE) run-cgen arch=frv prefix=frv options= extrafiles= + $(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS) @true stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc @@ -991,6 +1009,23 @@ fr30-ibld.lo: fr30-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ fr30-opc.lo: fr30-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \ fr30-opc.h $(INCDIR)/libiberty.h +frv-asm.lo: frv-asm.c sysdep.h config.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h frv-desc.h \ + $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h +frv-desc.lo: frv-desc.c sysdep.h config.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h frv-desc.h \ + $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h +frv-dis.lo: frv-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \ + $(BFD_H) $(INCDIR)/ansidecl.h \ + $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen.h \ + frv-opc.h opintl.h +frv-ibld.lo: frv-ibld.c sysdep.h config.h $(INCDIR)/dis-asm.h \ + $(BFD_H) $(INCDIR)/ansidecl.h \ + $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen.h \ + frv-opc.h opintl.h +frv-opc.lo: frv-opc.c sysdep.h config.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h frv-desc.h \ + $(INCDIR)/opcode/cgen.h frv-opc.h h8300-dis.lo: h8300-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/h8300.h $(INCDIR)/dis-asm.h $(BFD_H) \ $(INCDIR)/symcat.h opintl.h diff --git a/opcodes/configure b/opcodes/configure index 4d0b55f891f..3bc0513ffe8 100755 --- a/opcodes/configure +++ b/opcodes/configure @@ -4650,6 +4650,7 @@ if test x${all_targets} = xfalse ; then bfd_we32k_arch) ;; bfd_xstormy16_arch) ta="$ta xstormy16-asm.lo xstormy16-desc.lo xstormy16-dis.lo xstormy16-ibld.lo xstormy16-opc.lo" using_cgen=yes ;; bfd_z8k_arch) ta="$ta z8k-dis.lo" ;; + bfd_frv_arch) ta="$ta frv-asm.lo frv-desc.lo frv-dis.lo frv-ibld.lo frv-opc.lo" using_cgen=yes ;; "") ;; *) { echo "configure: error: *** unknown target architecture $arch" 1>&2; exit 1; } ;; diff --git a/opcodes/configure.in b/opcodes/configure.in index c09fad0600e..9d116a8d1a3 100644 --- a/opcodes/configure.in +++ b/opcodes/configure.in @@ -238,6 +238,7 @@ if test x${all_targets} = xfalse ; then bfd_we32k_arch) ;; bfd_xstormy16_arch) ta="$ta xstormy16-asm.lo xstormy16-desc.lo xstormy16-dis.lo xstormy16-ibld.lo xstormy16-opc.lo" using_cgen=yes ;; bfd_z8k_arch) ta="$ta z8k-dis.lo" ;; + bfd_frv_arch) ta="$ta frv-asm.lo frv-desc.lo frv-dis.lo frv-ibld.lo frv-opc.lo" using_cgen=yes ;; "") ;; *) AC_MSG_ERROR(*** unknown target architecture $arch) ;; diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index bfb22c2c188..b39114de93d 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -66,6 +66,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define ARCH_w65 #define ARCH_xstormy16 #define ARCH_z8k +#define ARCH_frv #define INCLUDE_SHMEDIA #endif @@ -336,6 +337,11 @@ disassembler (abfd) disassemble = print_insn_vax; break; #endif +#ifdef ARCH_frv + case bfd_arch_frv: + disassemble = print_insn_frv; + break; +#endif default: return 0; } diff --git a/opcodes/frv-asm.c b/opcodes/frv-asm.c new file mode 100644 index 00000000000..538ed2dc8f1 --- /dev/null +++ b/opcodes/frv-asm.c @@ -0,0 +1,1023 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +THIS FILE IS MACHINE GENERATED WITH CGEN. +- the resultant file is machine generated, cgen-asm.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include <stdio.h> +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "frv-desc.h" +#include "frv-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); + +/* -- assembler routines inserted here. */ + +/* -- asm.c */ +static const char * parse_ulo16 + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static const char * parse_uslo16 + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static const char * parse_uhi16 + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static long parse_register_number + PARAMS ((const char **)); +static const char * parse_spr + PARAMS ((CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *)); +static const char * parse_d12 + PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); +static const char * parse_s12 + PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); +static const char * parse_u12 + PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); + +static const char * +parse_ulo16 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + unsigned long *valuep; +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#' || **strp == '%') + { + if (strncasecmp (*strp + 1, "lo(", 3) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_LO16, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value &= 0xffff; + *valuep = value; + return errmsg; + } + if (strncasecmp (*strp + 1, "gprello(", 8) == 0) + { + *strp += 9; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GPRELLO, + &result_type, &value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value >>= 16; + *valuep = value; + return errmsg; + } + } + return cgen_parse_signed_integer (cd, strp, opindex, valuep); +} + +static const char * +parse_uslo16 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + unsigned long *valuep; +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#' || **strp == '%') + { + if (strncasecmp (*strp + 1, "lo(", 3) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_LO16, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value &= 0xffff; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gprello(", 8) == 0) + { + *strp += 9; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GPRELLO, + &result_type, &value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value &= 0xffff; + *valuep = value; + return errmsg; + } + } + return cgen_parse_unsigned_integer (cd, strp, opindex, valuep); +} + +static const char * +parse_uhi16 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + unsigned long *valuep; +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#' || **strp == '%') + { + if (strncasecmp (*strp + 1, "hi(", 3) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_HI16, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value >>= 16; + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp + 1, "gprelhi(", 8) == 0) + { + *strp += 9; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GPRELHI, + &result_type, &value); + if (**strp != ')') + return "missing ')'"; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value >>= 16; + *valuep = value; + return errmsg; + } + } + return cgen_parse_unsigned_integer (cd, strp, opindex, valuep); +} + +static long +parse_register_number (strp) + const char **strp; +{ + int regno; + if (**strp < '0' || **strp > '9') + return -1; /* error */ + + regno = **strp - '0'; + for (++*strp; **strp >= '0' && **strp <= '9'; ++*strp) + regno = regno * 10 + (**strp - '0'); + + return regno; +} + +static const char * +parse_spr (cd, strp, table, valuep) + CGEN_CPU_DESC cd; + const char **strp; + CGEN_KEYWORD * table; + long *valuep; +{ + const char *save_strp; + long regno; + + /* Check for spr index notation. */ + if (strncasecmp (*strp, "spr[", 4) == 0) + { + *strp += 4; + regno = parse_register_number (strp); + if (**strp != ']') + return "missing `]'"; + ++*strp; + if (! spr_valid (regno)) + return "Special purpose register number is out of range"; + *valuep = regno; + return NULL; + } + + save_strp = *strp; + regno = parse_register_number (strp); + if (regno != -1) + { + if (! spr_valid (regno)) + return "Special purpose register number is out of range"; + *valuep = regno; + return NULL; + } + + *strp = save_strp; + return cgen_parse_keyword (cd, strp, table, valuep); +} + +static const char * +parse_d12 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + /* Check for small data reference. */ + if (**strp == '#' || **strp == '%') + { + if (strncasecmp (*strp + 1, "gprel12(", 8) == 0) + { + *strp += 9; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GPREL12, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + *valuep = value; + return errmsg; + } + } + return cgen_parse_signed_integer (cd, strp, opindex, valuep); +} + +static const char * +parse_s12 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + /* Check for small data reference. */ + if ((**strp == '#' || **strp == '%') + && strncasecmp (*strp + 1, "gprel12(", 8) == 0) + { + *strp += 9; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GPREL12, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + *valuep = value; + return errmsg; + } + else + { + if (**strp == '#') + ++*strp; + return cgen_parse_signed_integer (cd, strp, opindex, valuep); + } +} + +static const char * +parse_u12 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + /* Check for small data reference. */ + if ((**strp == '#' || **strp == '%') + && strncasecmp (*strp + 1, "gprel12(", 8) == 0) + { + *strp += 9; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_GPRELU12, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + *valuep = value; + return errmsg; + } + else + { + if (**strp == '#') + ++*strp; + return cgen_parse_signed_integer (cd, strp, opindex, valuep); + } +} + +/* -- */ + +const char * frv_cgen_parse_operand + PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *)); + +/* Main entry point for operand parsing. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. */ + +const char * +frv_cgen_parse_operand (cd, opindex, strp, fields) + CGEN_CPU_DESC cd; + int opindex; + const char ** strp; + CGEN_FIELDS * fields; +{ + const char * errmsg = NULL; + /* Used by scalar operands that still need to be parsed. */ + long junk ATTRIBUTE_UNUSED; + + switch (opindex) + { + case FRV_OPERAND_A : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_A, &fields->f_A); + break; + case FRV_OPERAND_ACC40SI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_acc_names, & fields->f_ACC40Si); + break; + case FRV_OPERAND_ACC40SK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_acc_names, & fields->f_ACC40Sk); + break; + case FRV_OPERAND_ACC40UI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_acc_names, & fields->f_ACC40Ui); + break; + case FRV_OPERAND_ACC40UK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_acc_names, & fields->f_ACC40Uk); + break; + case FRV_OPERAND_ACCGI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_accg_names, & fields->f_ACCGi); + break; + case FRV_OPERAND_ACCGK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_accg_names, & fields->f_ACCGk); + break; + case FRV_OPERAND_CCI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cccr_names, & fields->f_CCi); + break; + case FRV_OPERAND_CPRDOUBLEK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cpr_names, & fields->f_CPRk); + break; + case FRV_OPERAND_CPRI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cpr_names, & fields->f_CPRi); + break; + case FRV_OPERAND_CPRJ : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cpr_names, & fields->f_CPRj); + break; + case FRV_OPERAND_CPRK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cpr_names, & fields->f_CPRk); + break; + case FRV_OPERAND_CRI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cccr_names, & fields->f_CRi); + break; + case FRV_OPERAND_CRJ : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cccr_names, & fields->f_CRj); + break; + case FRV_OPERAND_CRJ_FLOAT : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cccr_names, & fields->f_CRj_float); + break; + case FRV_OPERAND_CRJ_INT : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cccr_names, & fields->f_CRj_int); + break; + case FRV_OPERAND_CRK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_cccr_names, & fields->f_CRk); + break; + case FRV_OPERAND_FCCI_1 : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fccr_names, & fields->f_FCCi_1); + break; + case FRV_OPERAND_FCCI_2 : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fccr_names, & fields->f_FCCi_2); + break; + case FRV_OPERAND_FCCI_3 : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fccr_names, & fields->f_FCCi_3); + break; + case FRV_OPERAND_FCCK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fccr_names, & fields->f_FCCk); + break; + case FRV_OPERAND_FRDOUBLEI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRi); + break; + case FRV_OPERAND_FRDOUBLEJ : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRj); + break; + case FRV_OPERAND_FRDOUBLEK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk); + break; + case FRV_OPERAND_FRI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRi); + break; + case FRV_OPERAND_FRINTI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRi); + break; + case FRV_OPERAND_FRINTJ : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRj); + break; + case FRV_OPERAND_FRINTK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk); + break; + case FRV_OPERAND_FRJ : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRj); + break; + case FRV_OPERAND_FRK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk); + break; + case FRV_OPERAND_FRKHI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk); + break; + case FRV_OPERAND_FRKLO : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk); + break; + case FRV_OPERAND_GRDOUBLEK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_gr_names, & fields->f_GRk); + break; + case FRV_OPERAND_GRI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_gr_names, & fields->f_GRi); + break; + case FRV_OPERAND_GRJ : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_gr_names, & fields->f_GRj); + break; + case FRV_OPERAND_GRK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_gr_names, & fields->f_GRk); + break; + case FRV_OPERAND_GRKHI : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_gr_names, & fields->f_GRk); + break; + case FRV_OPERAND_GRKLO : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_gr_names, & fields->f_GRk); + break; + case FRV_OPERAND_ICCI_1 : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_iccr_names, & fields->f_ICCi_1); + break; + case FRV_OPERAND_ICCI_2 : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_iccr_names, & fields->f_ICCi_2); + break; + case FRV_OPERAND_ICCI_3 : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_iccr_names, & fields->f_ICCi_3); + break; + case FRV_OPERAND_LI : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_LI, &fields->f_LI); + break; + case FRV_OPERAND_AE : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_AE, &fields->f_ae); + break; + case FRV_OPERAND_CCOND : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_CCOND, &fields->f_ccond); + break; + case FRV_OPERAND_COND : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_COND, &fields->f_cond); + break; + case FRV_OPERAND_D12 : + errmsg = parse_d12 (cd, strp, FRV_OPERAND_D12, &fields->f_d12); + break; + case FRV_OPERAND_DEBUG : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_DEBUG, &fields->f_debug); + break; + case FRV_OPERAND_EIR : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_EIR, &fields->f_eir); + break; + case FRV_OPERAND_HINT : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_HINT, &fields->f_hint); + break; + case FRV_OPERAND_HINT_NOT_TAKEN : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_h_hint_not_taken, & fields->f_hint); + break; + case FRV_OPERAND_HINT_TAKEN : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_h_hint_taken, & fields->f_hint); + break; + case FRV_OPERAND_LABEL16 : + { + bfd_vma value; + errmsg = cgen_parse_address (cd, strp, FRV_OPERAND_LABEL16, 0, NULL, & value); + fields->f_label16 = value; + } + break; + case FRV_OPERAND_LABEL24 : + { + bfd_vma value; + errmsg = cgen_parse_address (cd, strp, FRV_OPERAND_LABEL24, 0, NULL, & value); + fields->f_label24 = value; + } + break; + case FRV_OPERAND_LOCK : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_LOCK, &fields->f_lock); + break; + case FRV_OPERAND_PACK : + errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_h_pack, & fields->f_pack); + break; + case FRV_OPERAND_S10 : + errmsg = cgen_parse_signed_integer (cd, strp, FRV_OPERAND_S10, &fields->f_s10); + break; + case FRV_OPERAND_S12 : + errmsg = parse_s12 (cd, strp, FRV_OPERAND_S12, &fields->f_d12); + break; + case FRV_OPERAND_S16 : + errmsg = cgen_parse_signed_integer (cd, strp, FRV_OPERAND_S16, &fields->f_s16); + break; + case FRV_OPERAND_S5 : + errmsg = cgen_parse_signed_integer (cd, strp, FRV_OPERAND_S5, &fields->f_s5); + break; + case FRV_OPERAND_S6 : + errmsg = cgen_parse_signed_integer (cd, strp, FRV_OPERAND_S6, &fields->f_s6); + break; + case FRV_OPERAND_S6_1 : + errmsg = cgen_parse_signed_integer (cd, strp, FRV_OPERAND_S6_1, &fields->f_s6_1); + break; + case FRV_OPERAND_SLO16 : + errmsg = parse_uslo16 (cd, strp, FRV_OPERAND_SLO16, &fields->f_s16); + break; + case FRV_OPERAND_SPR : + errmsg = parse_spr (cd, strp, & frv_cgen_opval_spr_names, & fields->f_spr); + break; + case FRV_OPERAND_U12 : + errmsg = parse_u12 (cd, strp, FRV_OPERAND_U12, &fields->f_u12); + break; + case FRV_OPERAND_U16 : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_U16, &fields->f_u16); + break; + case FRV_OPERAND_U6 : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_U6, &fields->f_u6); + break; + case FRV_OPERAND_UHI16 : + errmsg = parse_uhi16 (cd, strp, FRV_OPERAND_UHI16, &fields->f_u16); + break; + case FRV_OPERAND_ULO16 : + errmsg = parse_ulo16 (cd, strp, FRV_OPERAND_ULO16, &fields->f_u16); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); + abort (); + } + + return errmsg; +} + +cgen_parse_fn * const frv_cgen_parse_handlers[] = +{ + parse_insn_normal, +}; + +void +frv_cgen_init_asm (cd) + CGEN_CPU_DESC cd; +{ + frv_cgen_init_opcode_table (cd); + frv_cgen_init_ibld_table (cd); + cd->parse_handlers = & frv_cgen_parse_handlers[0]; + cd->parse_operand = frv_cgen_parse_operand; +} + + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by frv_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +frv_cgen_build_insn_regex (insn) + CGEN_INSN *insn; +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. */ + +static const char * +parse_insn_normal (cd, insn, strp, fields) + CGEN_CPU_DESC cd; + const CGEN_INSN *insn; + const char **strp; + CGEN_FIELDS *fields; +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && TOLOWER (*p) == TOLOWER (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + + /* We have an operand of some sort. */ + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), + &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (ISSPACE (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +frv_cgen_assemble_insn (cd, str, fields, buf, errmsg) + CGEN_CPU_DESC cd; + const char *str; + CGEN_FIELDS *fields; + CGEN_INSN_BYTES_PTR buf; + char **errmsg; +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; + + /* Skip leading white space. */ + while (ISSPACE (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ + /* Is this insn supported by the selected cpu? */ + if (! frv_cgen_insn_supported (cd, insn)) + continue; +#endif + /* If the RELAX attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0) + continue; + + str = start; + + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS + const char *tmp_errmsg; + + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); +#else + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); +#endif + + *errmsg = errbuf; + return NULL; + } +} + +#if 0 /* This calls back to GAS which we can't do without care. */ + +/* Record each member of OPVALS in the assembler's symbol table. + This lets GAS parse registers for us. + ??? Interesting idea but not currently used. */ + +/* Record each member of OPVALS in the assembler's symbol table. + FIXME: Not currently used. */ + +void +frv_cgen_asm_hash_keywords (cd, opvals) + CGEN_CPU_DESC cd; + CGEN_KEYWORD *opvals; +{ + CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); + const CGEN_KEYWORD_ENTRY * ke; + + while ((ke = cgen_keyword_search_next (& search)) != NULL) + { +#if 0 /* Unnecessary, should be done in the search routine. */ + if (! frv_cgen_opval_supported (ke)) + continue; +#endif + cgen_asm_record_register (cd, ke->name, ke->value); + } +} + +#endif /* 0 */ diff --git a/opcodes/frv-desc.c b/opcodes/frv-desc.c new file mode 100644 index 00000000000..8b8274c99ec --- /dev/null +++ b/opcodes/frv-desc.c @@ -0,0 +1,6311 @@ +/* CPU data for frv. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#include "sysdep.h" +#include <stdio.h> +#include <stdarg.h> +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "frv-desc.h" +#include "frv-opc.h" +#include "opintl.h" +#include "libiberty.h" + +/* Attributes. */ + +static const CGEN_ATTR_ENTRY bool_attr[] = +{ + { "#f", 0 }, + { "#t", 1 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY MACH_attr[] = +{ + { "base", MACH_BASE }, + { "frv", MACH_FRV }, + { "fr500", MACH_FR500 }, + { "fr400", MACH_FR400 }, + { "tomcat", MACH_TOMCAT }, + { "simple", MACH_SIMPLE }, + { "max", MACH_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ISA_attr[] = +{ + { "frv", ISA_FRV }, + { "max", ISA_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY UNIT_attr[] = +{ + { "NIL", UNIT_NIL }, + { "I0", UNIT_I0 }, + { "I1", UNIT_I1 }, + { "I01", UNIT_I01 }, + { "FM0", UNIT_FM0 }, + { "FM1", UNIT_FM1 }, + { "FM01", UNIT_FM01 }, + { "B0", UNIT_B0 }, + { "B1", UNIT_B1 }, + { "B01", UNIT_B01 }, + { "C", UNIT_C }, + { "MULT_DIV", UNIT_MULT_DIV }, + { "LOAD", UNIT_LOAD }, + { "NUM_UNITS", UNIT_NUM_UNITS }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY FR400_MAJOR_attr[] = +{ + { "NONE", FR400_MAJOR_NONE }, + { "I_1", FR400_MAJOR_I_1 }, + { "I_2", FR400_MAJOR_I_2 }, + { "I_3", FR400_MAJOR_I_3 }, + { "I_4", FR400_MAJOR_I_4 }, + { "I_5", FR400_MAJOR_I_5 }, + { "B_1", FR400_MAJOR_B_1 }, + { "B_2", FR400_MAJOR_B_2 }, + { "B_3", FR400_MAJOR_B_3 }, + { "B_4", FR400_MAJOR_B_4 }, + { "B_5", FR400_MAJOR_B_5 }, + { "B_6", FR400_MAJOR_B_6 }, + { "C_1", FR400_MAJOR_C_1 }, + { "C_2", FR400_MAJOR_C_2 }, + { "M_1", FR400_MAJOR_M_1 }, + { "M_2", FR400_MAJOR_M_2 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY FR500_MAJOR_attr[] = +{ + { "NONE", FR500_MAJOR_NONE }, + { "I_1", FR500_MAJOR_I_1 }, + { "I_2", FR500_MAJOR_I_2 }, + { "I_3", FR500_MAJOR_I_3 }, + { "I_4", FR500_MAJOR_I_4 }, + { "I_5", FR500_MAJOR_I_5 }, + { "I_6", FR500_MAJOR_I_6 }, + { "B_1", FR500_MAJOR_B_1 }, + { "B_2", FR500_MAJOR_B_2 }, + { "B_3", FR500_MAJOR_B_3 }, + { "B_4", FR500_MAJOR_B_4 }, + { "B_5", FR500_MAJOR_B_5 }, + { "B_6", FR500_MAJOR_B_6 }, + { "C_1", FR500_MAJOR_C_1 }, + { "C_2", FR500_MAJOR_C_2 }, + { "F_1", FR500_MAJOR_F_1 }, + { "F_2", FR500_MAJOR_F_2 }, + { "F_3", FR500_MAJOR_F_3 }, + { "F_4", FR500_MAJOR_F_4 }, + { "F_5", FR500_MAJOR_F_5 }, + { "F_6", FR500_MAJOR_F_6 }, + { "F_7", FR500_MAJOR_F_7 }, + { "F_8", FR500_MAJOR_F_8 }, + { "M_1", FR500_MAJOR_M_1 }, + { "M_2", FR500_MAJOR_M_2 }, + { "M_3", FR500_MAJOR_M_3 }, + { "M_4", FR500_MAJOR_M_4 }, + { "M_5", FR500_MAJOR_M_5 }, + { "M_6", FR500_MAJOR_M_6 }, + { "M_7", FR500_MAJOR_M_7 }, + { "M_8", FR500_MAJOR_M_8 }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE frv_cgen_ifield_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "RESERVED", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE frv_cgen_hardware_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, + { "PC", &bool_attr[0], &bool_attr[0] }, + { "PROFILE", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE frv_cgen_operand_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, + { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE frv_cgen_insn_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "UNIT", & UNIT_attr[0], & UNIT_attr[0] }, + { "FR400-MAJOR", & FR400_MAJOR_attr[0], & FR400_MAJOR_attr[0] }, + { "FR500-MAJOR", & FR500_MAJOR_attr[0], & FR500_MAJOR_attr[0] }, + { "ALIAS", &bool_attr[0], &bool_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, + { "COND-CTI", &bool_attr[0], &bool_attr[0] }, + { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, + { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "NO-DIS", &bool_attr[0], &bool_attr[0] }, + { "PBB", &bool_attr[0], &bool_attr[0] }, + { "PRIVILEGED", &bool_attr[0], &bool_attr[0] }, + { "NON-EXCEPTING", &bool_attr[0], &bool_attr[0] }, + { "CONDITIONAL", &bool_attr[0], &bool_attr[0] }, + { "FR-ACCESS", &bool_attr[0], &bool_attr[0] }, + { "PRESERVE-OVF", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +/* Instruction set variants. */ + +static const CGEN_ISA frv_cgen_isa_table[] = { + { "frv", 32, 32, 32, 32 }, + { 0, 0, 0, 0, 0 } +}; + +/* Machine variants. */ + +static const CGEN_MACH frv_cgen_mach_table[] = { + { "frv", "frv", MACH_FRV, 0 }, + { "fr500", "fr500", MACH_FR500, 0 }, + { "tomcat", "tomcat", MACH_TOMCAT, 0 }, + { "fr400", "fr400", MACH_FR400, 0 }, + { "simple", "simple", MACH_SIMPLE, 0 }, + { 0, 0, 0, 0 } +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_gr_names_entries[] = +{ + { "sp", 1, {0, {0}}, 0, 0 }, + { "fp", 2, {0, {0}}, 0, 0 }, + { "gr0", 0, {0, {0}}, 0, 0 }, + { "gr1", 1, {0, {0}}, 0, 0 }, + { "gr2", 2, {0, {0}}, 0, 0 }, + { "gr3", 3, {0, {0}}, 0, 0 }, + { "gr4", 4, {0, {0}}, 0, 0 }, + { "gr5", 5, {0, {0}}, 0, 0 }, + { "gr6", 6, {0, {0}}, 0, 0 }, + { "gr7", 7, {0, {0}}, 0, 0 }, + { "gr8", 8, {0, {0}}, 0, 0 }, + { "gr9", 9, {0, {0}}, 0, 0 }, + { "gr10", 10, {0, {0}}, 0, 0 }, + { "gr11", 11, {0, {0}}, 0, 0 }, + { "gr12", 12, {0, {0}}, 0, 0 }, + { "gr13", 13, {0, {0}}, 0, 0 }, + { "gr14", 14, {0, {0}}, 0, 0 }, + { "gr15", 15, {0, {0}}, 0, 0 }, + { "gr16", 16, {0, {0}}, 0, 0 }, + { "gr17", 17, {0, {0}}, 0, 0 }, + { "gr18", 18, {0, {0}}, 0, 0 }, + { "gr19", 19, {0, {0}}, 0, 0 }, + { "gr20", 20, {0, {0}}, 0, 0 }, + { "gr21", 21, {0, {0}}, 0, 0 }, + { "gr22", 22, {0, {0}}, 0, 0 }, + { "gr23", 23, {0, {0}}, 0, 0 }, + { "gr24", 24, {0, {0}}, 0, 0 }, + { "gr25", 25, {0, {0}}, 0, 0 }, + { "gr26", 26, {0, {0}}, 0, 0 }, + { "gr27", 27, {0, {0}}, 0, 0 }, + { "gr28", 28, {0, {0}}, 0, 0 }, + { "gr29", 29, {0, {0}}, 0, 0 }, + { "gr30", 30, {0, {0}}, 0, 0 }, + { "gr31", 31, {0, {0}}, 0, 0 }, + { "gr32", 32, {0, {0}}, 0, 0 }, + { "gr33", 33, {0, {0}}, 0, 0 }, + { "gr34", 34, {0, {0}}, 0, 0 }, + { "gr35", 35, {0, {0}}, 0, 0 }, + { "gr36", 36, {0, {0}}, 0, 0 }, + { "gr37", 37, {0, {0}}, 0, 0 }, + { "gr38", 38, {0, {0}}, 0, 0 }, + { "gr39", 39, {0, {0}}, 0, 0 }, + { "gr40", 40, {0, {0}}, 0, 0 }, + { "gr41", 41, {0, {0}}, 0, 0 }, + { "gr42", 42, {0, {0}}, 0, 0 }, + { "gr43", 43, {0, {0}}, 0, 0 }, + { "gr44", 44, {0, {0}}, 0, 0 }, + { "gr45", 45, {0, {0}}, 0, 0 }, + { "gr46", 46, {0, {0}}, 0, 0 }, + { "gr47", 47, {0, {0}}, 0, 0 }, + { "gr48", 48, {0, {0}}, 0, 0 }, + { "gr49", 49, {0, {0}}, 0, 0 }, + { "gr50", 50, {0, {0}}, 0, 0 }, + { "gr51", 51, {0, {0}}, 0, 0 }, + { "gr52", 52, {0, {0}}, 0, 0 }, + { "gr53", 53, {0, {0}}, 0, 0 }, + { "gr54", 54, {0, {0}}, 0, 0 }, + { "gr55", 55, {0, {0}}, 0, 0 }, + { "gr56", 56, {0, {0}}, 0, 0 }, + { "gr57", 57, {0, {0}}, 0, 0 }, + { "gr58", 58, {0, {0}}, 0, 0 }, + { "gr59", 59, {0, {0}}, 0, 0 }, + { "gr60", 60, {0, {0}}, 0, 0 }, + { "gr61", 61, {0, {0}}, 0, 0 }, + { "gr62", 62, {0, {0}}, 0, 0 }, + { "gr63", 63, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_gr_names = +{ + & frv_cgen_opval_gr_names_entries[0], + 66, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_fr_names_entries[] = +{ + { "fr0", 0, {0, {0}}, 0, 0 }, + { "fr1", 1, {0, {0}}, 0, 0 }, + { "fr2", 2, {0, {0}}, 0, 0 }, + { "fr3", 3, {0, {0}}, 0, 0 }, + { "fr4", 4, {0, {0}}, 0, 0 }, + { "fr5", 5, {0, {0}}, 0, 0 }, + { "fr6", 6, {0, {0}}, 0, 0 }, + { "fr7", 7, {0, {0}}, 0, 0 }, + { "fr8", 8, {0, {0}}, 0, 0 }, + { "fr9", 9, {0, {0}}, 0, 0 }, + { "fr10", 10, {0, {0}}, 0, 0 }, + { "fr11", 11, {0, {0}}, 0, 0 }, + { "fr12", 12, {0, {0}}, 0, 0 }, + { "fr13", 13, {0, {0}}, 0, 0 }, + { "fr14", 14, {0, {0}}, 0, 0 }, + { "fr15", 15, {0, {0}}, 0, 0 }, + { "fr16", 16, {0, {0}}, 0, 0 }, + { "fr17", 17, {0, {0}}, 0, 0 }, + { "fr18", 18, {0, {0}}, 0, 0 }, + { "fr19", 19, {0, {0}}, 0, 0 }, + { "fr20", 20, {0, {0}}, 0, 0 }, + { "fr21", 21, {0, {0}}, 0, 0 }, + { "fr22", 22, {0, {0}}, 0, 0 }, + { "fr23", 23, {0, {0}}, 0, 0 }, + { "fr24", 24, {0, {0}}, 0, 0 }, + { "fr25", 25, {0, {0}}, 0, 0 }, + { "fr26", 26, {0, {0}}, 0, 0 }, + { "fr27", 27, {0, {0}}, 0, 0 }, + { "fr28", 28, {0, {0}}, 0, 0 }, + { "fr29", 29, {0, {0}}, 0, 0 }, + { "fr30", 30, {0, {0}}, 0, 0 }, + { "fr31", 31, {0, {0}}, 0, 0 }, + { "fr32", 32, {0, {0}}, 0, 0 }, + { "fr33", 33, {0, {0}}, 0, 0 }, + { "fr34", 34, {0, {0}}, 0, 0 }, + { "fr35", 35, {0, {0}}, 0, 0 }, + { "fr36", 36, {0, {0}}, 0, 0 }, + { "fr37", 37, {0, {0}}, 0, 0 }, + { "fr38", 38, {0, {0}}, 0, 0 }, + { "fr39", 39, {0, {0}}, 0, 0 }, + { "fr40", 40, {0, {0}}, 0, 0 }, + { "fr41", 41, {0, {0}}, 0, 0 }, + { "fr42", 42, {0, {0}}, 0, 0 }, + { "fr43", 43, {0, {0}}, 0, 0 }, + { "fr44", 44, {0, {0}}, 0, 0 }, + { "fr45", 45, {0, {0}}, 0, 0 }, + { "fr46", 46, {0, {0}}, 0, 0 }, + { "fr47", 47, {0, {0}}, 0, 0 }, + { "fr48", 48, {0, {0}}, 0, 0 }, + { "fr49", 49, {0, {0}}, 0, 0 }, + { "fr50", 50, {0, {0}}, 0, 0 }, + { "fr51", 51, {0, {0}}, 0, 0 }, + { "fr52", 52, {0, {0}}, 0, 0 }, + { "fr53", 53, {0, {0}}, 0, 0 }, + { "fr54", 54, {0, {0}}, 0, 0 }, + { "fr55", 55, {0, {0}}, 0, 0 }, + { "fr56", 56, {0, {0}}, 0, 0 }, + { "fr57", 57, {0, {0}}, 0, 0 }, + { "fr58", 58, {0, {0}}, 0, 0 }, + { "fr59", 59, {0, {0}}, 0, 0 }, + { "fr60", 60, {0, {0}}, 0, 0 }, + { "fr61", 61, {0, {0}}, 0, 0 }, + { "fr62", 62, {0, {0}}, 0, 0 }, + { "fr63", 63, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_fr_names = +{ + & frv_cgen_opval_fr_names_entries[0], + 64, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_cpr_names_entries[] = +{ + { "cpr0", 0, {0, {0}}, 0, 0 }, + { "cpr1", 1, {0, {0}}, 0, 0 }, + { "cpr2", 2, {0, {0}}, 0, 0 }, + { "cpr3", 3, {0, {0}}, 0, 0 }, + { "cpr4", 4, {0, {0}}, 0, 0 }, + { "cpr5", 5, {0, {0}}, 0, 0 }, + { "cpr6", 6, {0, {0}}, 0, 0 }, + { "cpr7", 7, {0, {0}}, 0, 0 }, + { "cpr8", 8, {0, {0}}, 0, 0 }, + { "cpr9", 9, {0, {0}}, 0, 0 }, + { "cpr10", 10, {0, {0}}, 0, 0 }, + { "cpr11", 11, {0, {0}}, 0, 0 }, + { "cpr12", 12, {0, {0}}, 0, 0 }, + { "cpr13", 13, {0, {0}}, 0, 0 }, + { "cpr14", 14, {0, {0}}, 0, 0 }, + { "cpr15", 15, {0, {0}}, 0, 0 }, + { "cpr16", 16, {0, {0}}, 0, 0 }, + { "cpr17", 17, {0, {0}}, 0, 0 }, + { "cpr18", 18, {0, {0}}, 0, 0 }, + { "cpr19", 19, {0, {0}}, 0, 0 }, + { "cpr20", 20, {0, {0}}, 0, 0 }, + { "cpr21", 21, {0, {0}}, 0, 0 }, + { "cpr22", 22, {0, {0}}, 0, 0 }, + { "cpr23", 23, {0, {0}}, 0, 0 }, + { "cpr24", 24, {0, {0}}, 0, 0 }, + { "cpr25", 25, {0, {0}}, 0, 0 }, + { "cpr26", 26, {0, {0}}, 0, 0 }, + { "cpr27", 27, {0, {0}}, 0, 0 }, + { "cpr28", 28, {0, {0}}, 0, 0 }, + { "cpr29", 29, {0, {0}}, 0, 0 }, + { "cpr30", 30, {0, {0}}, 0, 0 }, + { "cpr31", 31, {0, {0}}, 0, 0 }, + { "cpr32", 32, {0, {0}}, 0, 0 }, + { "cpr33", 33, {0, {0}}, 0, 0 }, + { "cpr34", 34, {0, {0}}, 0, 0 }, + { "cpr35", 35, {0, {0}}, 0, 0 }, + { "cpr36", 36, {0, {0}}, 0, 0 }, + { "cpr37", 37, {0, {0}}, 0, 0 }, + { "cpr38", 38, {0, {0}}, 0, 0 }, + { "cpr39", 39, {0, {0}}, 0, 0 }, + { "cpr40", 40, {0, {0}}, 0, 0 }, + { "cpr41", 41, {0, {0}}, 0, 0 }, + { "cpr42", 42, {0, {0}}, 0, 0 }, + { "cpr43", 43, {0, {0}}, 0, 0 }, + { "cpr44", 44, {0, {0}}, 0, 0 }, + { "cpr45", 45, {0, {0}}, 0, 0 }, + { "cpr46", 46, {0, {0}}, 0, 0 }, + { "cpr47", 47, {0, {0}}, 0, 0 }, + { "cpr48", 48, {0, {0}}, 0, 0 }, + { "cpr49", 49, {0, {0}}, 0, 0 }, + { "cpr50", 50, {0, {0}}, 0, 0 }, + { "cpr51", 51, {0, {0}}, 0, 0 }, + { "cpr52", 52, {0, {0}}, 0, 0 }, + { "cpr53", 53, {0, {0}}, 0, 0 }, + { "cpr54", 54, {0, {0}}, 0, 0 }, + { "cpr55", 55, {0, {0}}, 0, 0 }, + { "cpr56", 56, {0, {0}}, 0, 0 }, + { "cpr57", 57, {0, {0}}, 0, 0 }, + { "cpr58", 58, {0, {0}}, 0, 0 }, + { "cpr59", 59, {0, {0}}, 0, 0 }, + { "cpr60", 60, {0, {0}}, 0, 0 }, + { "cpr61", 61, {0, {0}}, 0, 0 }, + { "cpr62", 62, {0, {0}}, 0, 0 }, + { "cpr63", 63, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_cpr_names = +{ + & frv_cgen_opval_cpr_names_entries[0], + 64, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_spr_names_entries[] = +{ + { "psr", 0, {0, {0}}, 0, 0 }, + { "pcsr", 1, {0, {0}}, 0, 0 }, + { "bpcsr", 2, {0, {0}}, 0, 0 }, + { "tbr", 3, {0, {0}}, 0, 0 }, + { "bpsr", 4, {0, {0}}, 0, 0 }, + { "hsr0", 16, {0, {0}}, 0, 0 }, + { "hsr1", 17, {0, {0}}, 0, 0 }, + { "hsr2", 18, {0, {0}}, 0, 0 }, + { "hsr3", 19, {0, {0}}, 0, 0 }, + { "hsr4", 20, {0, {0}}, 0, 0 }, + { "hsr5", 21, {0, {0}}, 0, 0 }, + { "hsr6", 22, {0, {0}}, 0, 0 }, + { "hsr7", 23, {0, {0}}, 0, 0 }, + { "hsr8", 24, {0, {0}}, 0, 0 }, + { "hsr9", 25, {0, {0}}, 0, 0 }, + { "hsr10", 26, {0, {0}}, 0, 0 }, + { "hsr11", 27, {0, {0}}, 0, 0 }, + { "hsr12", 28, {0, {0}}, 0, 0 }, + { "hsr13", 29, {0, {0}}, 0, 0 }, + { "hsr14", 30, {0, {0}}, 0, 0 }, + { "hsr15", 31, {0, {0}}, 0, 0 }, + { "hsr16", 32, {0, {0}}, 0, 0 }, + { "hsr17", 33, {0, {0}}, 0, 0 }, + { "hsr18", 34, {0, {0}}, 0, 0 }, + { "hsr19", 35, {0, {0}}, 0, 0 }, + { "hsr20", 36, {0, {0}}, 0, 0 }, + { "hsr21", 37, {0, {0}}, 0, 0 }, + { "hsr22", 38, {0, {0}}, 0, 0 }, + { "hsr23", 39, {0, {0}}, 0, 0 }, + { "hsr24", 40, {0, {0}}, 0, 0 }, + { "hsr25", 41, {0, {0}}, 0, 0 }, + { "hsr26", 42, {0, {0}}, 0, 0 }, + { "hsr27", 43, {0, {0}}, 0, 0 }, + { "hsr28", 44, {0, {0}}, 0, 0 }, + { "hsr29", 45, {0, {0}}, 0, 0 }, + { "hsr30", 46, {0, {0}}, 0, 0 }, + { "hsr31", 47, {0, {0}}, 0, 0 }, + { "hsr32", 48, {0, {0}}, 0, 0 }, + { "hsr33", 49, {0, {0}}, 0, 0 }, + { "hsr34", 50, {0, {0}}, 0, 0 }, + { "hsr35", 51, {0, {0}}, 0, 0 }, + { "hsr36", 52, {0, {0}}, 0, 0 }, + { "hsr37", 53, {0, {0}}, 0, 0 }, + { "hsr38", 54, {0, {0}}, 0, 0 }, + { "hsr39", 55, {0, {0}}, 0, 0 }, + { "hsr40", 56, {0, {0}}, 0, 0 }, + { "hsr41", 57, {0, {0}}, 0, 0 }, + { "hsr42", 58, {0, {0}}, 0, 0 }, + { "hsr43", 59, {0, {0}}, 0, 0 }, + { "hsr44", 60, {0, {0}}, 0, 0 }, + { "hsr45", 61, {0, {0}}, 0, 0 }, + { "hsr46", 62, {0, {0}}, 0, 0 }, + { "hsr47", 63, {0, {0}}, 0, 0 }, + { "hsr48", 64, {0, {0}}, 0, 0 }, + { "hsr49", 65, {0, {0}}, 0, 0 }, + { "hsr50", 66, {0, {0}}, 0, 0 }, + { "hsr51", 67, {0, {0}}, 0, 0 }, + { "hsr52", 68, {0, {0}}, 0, 0 }, + { "hsr53", 69, {0, {0}}, 0, 0 }, + { "hsr54", 70, {0, {0}}, 0, 0 }, + { "hsr55", 71, {0, {0}}, 0, 0 }, + { "hsr56", 72, {0, {0}}, 0, 0 }, + { "hsr57", 73, {0, {0}}, 0, 0 }, + { "hsr58", 74, {0, {0}}, 0, 0 }, + { "hsr59", 75, {0, {0}}, 0, 0 }, + { "hsr60", 76, {0, {0}}, 0, 0 }, + { "hsr61", 77, {0, {0}}, 0, 0 }, + { "hsr62", 78, {0, {0}}, 0, 0 }, + { "hsr63", 79, {0, {0}}, 0, 0 }, + { "ccr", 256, {0, {0}}, 0, 0 }, + { "cccr", 263, {0, {0}}, 0, 0 }, + { "lr", 272, {0, {0}}, 0, 0 }, + { "lcr", 273, {0, {0}}, 0, 0 }, + { "isr", 288, {0, {0}}, 0, 0 }, + { "neear0", 352, {0, {0}}, 0, 0 }, + { "neear1", 353, {0, {0}}, 0, 0 }, + { "neear2", 354, {0, {0}}, 0, 0 }, + { "neear3", 355, {0, {0}}, 0, 0 }, + { "neear4", 356, {0, {0}}, 0, 0 }, + { "neear5", 357, {0, {0}}, 0, 0 }, + { "neear6", 358, {0, {0}}, 0, 0 }, + { "neear7", 359, {0, {0}}, 0, 0 }, + { "neear8", 360, {0, {0}}, 0, 0 }, + { "neear9", 361, {0, {0}}, 0, 0 }, + { "neear10", 362, {0, {0}}, 0, 0 }, + { "neear11", 363, {0, {0}}, 0, 0 }, + { "neear12", 364, {0, {0}}, 0, 0 }, + { "neear13", 365, {0, {0}}, 0, 0 }, + { "neear14", 366, {0, {0}}, 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"dampr30", 1886, {0, {0}}, 0, 0 }, + { "dampr31", 1887, {0, {0}}, 0, 0 }, + { "dampr32", 1888, {0, {0}}, 0, 0 }, + { "dampr33", 1889, {0, {0}}, 0, 0 }, + { "dampr34", 1890, {0, {0}}, 0, 0 }, + { "dampr35", 1891, {0, {0}}, 0, 0 }, + { "dampr36", 1892, {0, {0}}, 0, 0 }, + { "dampr37", 1893, {0, {0}}, 0, 0 }, + { "dampr38", 1894, {0, {0}}, 0, 0 }, + { "dampr39", 1895, {0, {0}}, 0, 0 }, + { "dampr40", 1896, {0, {0}}, 0, 0 }, + { "dampr41", 1897, {0, {0}}, 0, 0 }, + { "dampr42", 1898, {0, {0}}, 0, 0 }, + { "dampr43", 1899, {0, {0}}, 0, 0 }, + { "dampr44", 1900, {0, {0}}, 0, 0 }, + { "dampr45", 1901, {0, {0}}, 0, 0 }, + { "dampr46", 1902, {0, {0}}, 0, 0 }, + { "dampr47", 1903, {0, {0}}, 0, 0 }, + { "dampr48", 1904, {0, {0}}, 0, 0 }, + { "dampr49", 1905, {0, {0}}, 0, 0 }, + { "dampr50", 1906, {0, {0}}, 0, 0 }, + { "dampr51", 1907, {0, {0}}, 0, 0 }, + { "dampr52", 1908, {0, {0}}, 0, 0 }, + { "dampr53", 1909, {0, {0}}, 0, 0 }, + { "dampr54", 1910, {0, {0}}, 0, 0 }, + { "dampr55", 1911, {0, {0}}, 0, 0 }, + { "dampr56", 1912, {0, {0}}, 0, 0 }, + { "dampr57", 1913, {0, {0}}, 0, 0 }, + { "dampr58", 1914, {0, {0}}, 0, 0 }, + { "dampr59", 1915, {0, {0}}, 0, 0 }, + { "dampr60", 1916, {0, {0}}, 0, 0 }, + { "dampr61", 1917, {0, {0}}, 0, 0 }, + { "dampr62", 1918, {0, {0}}, 0, 0 }, + { "dampr63", 1919, {0, {0}}, 0, 0 }, + { "amcr", 1920, {0, {0}}, 0, 0 }, + { "stbar", 1921, {0, {0}}, 0, 0 }, + { "mmcr", 1922, {0, {0}}, 0, 0 }, + { "dcr", 2048, {0, {0}}, 0, 0 }, + { "brr", 2049, {0, {0}}, 0, 0 }, + { "nmar", 2050, {0, {0}}, 0, 0 }, + { "ibar0", 2052, {0, {0}}, 0, 0 }, + { "ibar1", 2053, {0, {0}}, 0, 0 }, + { "ibar2", 2054, {0, {0}}, 0, 0 }, + { "ibar3", 2055, {0, {0}}, 0, 0 }, + { "dbar0", 2056, {0, {0}}, 0, 0 }, + { "dbar1", 2057, {0, {0}}, 0, 0 }, + { "dbar2", 2058, {0, {0}}, 0, 0 }, + { "dbar3", 2059, {0, {0}}, 0, 0 }, + { "dbdr00", 2060, {0, {0}}, 0, 0 }, + { "dbdr01", 2061, {0, {0}}, 0, 0 }, + { "dbdr02", 2062, {0, {0}}, 0, 0 }, + { "dbdr03", 2063, {0, {0}}, 0, 0 }, + { "dbdr10", 2064, {0, {0}}, 0, 0 }, + { "dbdr11", 2065, {0, {0}}, 0, 0 }, + { "dbdr12", 2066, {0, {0}}, 0, 0 }, + { "dbdr13", 2067, {0, {0}}, 0, 0 }, + { "dbdr20", 2068, {0, {0}}, 0, 0 }, + { "dbdr21", 2069, {0, {0}}, 0, 0 }, + { "dbdr22", 2070, {0, {0}}, 0, 0 }, + { "dbdr23", 2071, {0, {0}}, 0, 0 }, + { "dbdr30", 2072, {0, {0}}, 0, 0 }, + { "dbdr31", 2073, {0, {0}}, 0, 0 }, + { "dbdr32", 2074, {0, {0}}, 0, 0 }, + { "dbdr33", 2075, {0, {0}}, 0, 0 }, + { "dbmr00", 2076, {0, {0}}, 0, 0 }, + { "dbmr01", 2077, {0, {0}}, 0, 0 }, + { "dbmr02", 2078, {0, {0}}, 0, 0 }, + { "dbmr03", 2079, {0, {0}}, 0, 0 }, + { "dbmr10", 2080, {0, {0}}, 0, 0 }, + { "dbmr11", 2081, {0, {0}}, 0, 0 }, + { "dbmr12", 2082, {0, {0}}, 0, 0 }, + { "dbmr13", 2083, {0, {0}}, 0, 0 }, + { "dbmr20", 2084, {0, {0}}, 0, 0 }, + { "dbmr21", 2085, {0, {0}}, 0, 0 }, + { "dbmr22", 2086, {0, {0}}, 0, 0 }, + { "dbmr23", 2087, {0, {0}}, 0, 0 }, + { "dbmr30", 2088, {0, {0}}, 0, 0 }, + { "dbmr31", 2089, {0, {0}}, 0, 0 }, + { "dbmr32", 2090, {0, {0}}, 0, 0 }, + { "dbmr33", 2091, {0, {0}}, 0, 0 }, + { "cpcfr", 2092, {0, {0}}, 0, 0 }, + { "cpcr", 2093, {0, {0}}, 0, 0 }, + { "cpsr", 2094, {0, {0}}, 0, 0 }, + { "cpesr0", 2096, {0, {0}}, 0, 0 }, + { "cpesr1", 2097, {0, {0}}, 0, 0 }, + { "cpemr0", 2098, {0, {0}}, 0, 0 }, + { "cpemr1", 2099, {0, {0}}, 0, 0 }, + { "ihsr8", 3848, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_spr_names = +{ + & frv_cgen_opval_spr_names_entries[0], + 1005, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_accg_names_entries[] = +{ + { "accg0", 0, {0, {0}}, 0, 0 }, + { "accg1", 1, {0, {0}}, 0, 0 }, + { "accg2", 2, {0, {0}}, 0, 0 }, + { "accg3", 3, {0, {0}}, 0, 0 }, + { "accg4", 4, {0, {0}}, 0, 0 }, + { "accg5", 5, {0, {0}}, 0, 0 }, + { "accg6", 6, {0, {0}}, 0, 0 }, + { "accg7", 7, {0, {0}}, 0, 0 }, + { "accg8", 8, {0, {0}}, 0, 0 }, + { "accg9", 9, {0, {0}}, 0, 0 }, + { "accg10", 10, {0, {0}}, 0, 0 }, + { "accg11", 11, {0, {0}}, 0, 0 }, + { "accg12", 12, {0, {0}}, 0, 0 }, + { "accg13", 13, {0, {0}}, 0, 0 }, + { "accg14", 14, {0, {0}}, 0, 0 }, + { "accg15", 15, {0, {0}}, 0, 0 }, + { "accg16", 16, {0, {0}}, 0, 0 }, + { "accg17", 17, {0, {0}}, 0, 0 }, + { "accg18", 18, {0, {0}}, 0, 0 }, + { "accg19", 19, {0, {0}}, 0, 0 }, + { "accg20", 20, {0, {0}}, 0, 0 }, + { "accg21", 21, {0, {0}}, 0, 0 }, + { "accg22", 22, {0, {0}}, 0, 0 }, + { "accg23", 23, {0, {0}}, 0, 0 }, + { "accg24", 24, {0, {0}}, 0, 0 }, + { "accg25", 25, {0, {0}}, 0, 0 }, + { "accg26", 26, {0, {0}}, 0, 0 }, + { "accg27", 27, {0, {0}}, 0, 0 }, + { "accg28", 28, {0, {0}}, 0, 0 }, + { "accg29", 29, {0, {0}}, 0, 0 }, + { "accg30", 30, {0, {0}}, 0, 0 }, + { "accg31", 31, {0, {0}}, 0, 0 }, + { "accg32", 32, {0, {0}}, 0, 0 }, + { "accg33", 33, {0, {0}}, 0, 0 }, + { "accg34", 34, {0, {0}}, 0, 0 }, + { "accg35", 35, {0, {0}}, 0, 0 }, + { "accg36", 36, {0, {0}}, 0, 0 }, + { "accg37", 37, {0, {0}}, 0, 0 }, + { "accg38", 38, {0, {0}}, 0, 0 }, + { "accg39", 39, {0, {0}}, 0, 0 }, + { "accg40", 40, {0, {0}}, 0, 0 }, + { "accg41", 41, {0, {0}}, 0, 0 }, + { "accg42", 42, {0, {0}}, 0, 0 }, + { "accg43", 43, {0, {0}}, 0, 0 }, + { "accg44", 44, {0, {0}}, 0, 0 }, + { "accg45", 45, {0, {0}}, 0, 0 }, + { "accg46", 46, {0, {0}}, 0, 0 }, + { "accg47", 47, {0, {0}}, 0, 0 }, + { "accg48", 48, {0, {0}}, 0, 0 }, + { "accg49", 49, {0, {0}}, 0, 0 }, + { "accg50", 50, {0, {0}}, 0, 0 }, + { "accg51", 51, {0, {0}}, 0, 0 }, + { "accg52", 52, {0, {0}}, 0, 0 }, + { "accg53", 53, {0, {0}}, 0, 0 }, + { "accg54", 54, {0, {0}}, 0, 0 }, + { "accg55", 55, {0, {0}}, 0, 0 }, + { "accg56", 56, {0, {0}}, 0, 0 }, + { "accg57", 57, {0, {0}}, 0, 0 }, + { "accg58", 58, {0, {0}}, 0, 0 }, + { "accg59", 59, {0, {0}}, 0, 0 }, + { "accg60", 60, {0, {0}}, 0, 0 }, + { "accg61", 61, {0, {0}}, 0, 0 }, + { "accg62", 62, {0, {0}}, 0, 0 }, + { "accg63", 63, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_accg_names = +{ + & frv_cgen_opval_accg_names_entries[0], + 64, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_acc_names_entries[] = +{ + { "acc0", 0, {0, {0}}, 0, 0 }, + { "acc1", 1, {0, {0}}, 0, 0 }, + { "acc2", 2, {0, {0}}, 0, 0 }, + { "acc3", 3, {0, {0}}, 0, 0 }, + { "acc4", 4, {0, {0}}, 0, 0 }, + { "acc5", 5, {0, {0}}, 0, 0 }, + { "acc6", 6, {0, {0}}, 0, 0 }, + { "acc7", 7, {0, {0}}, 0, 0 }, + { "acc8", 8, {0, {0}}, 0, 0 }, + { "acc9", 9, {0, {0}}, 0, 0 }, + { "acc10", 10, {0, {0}}, 0, 0 }, + { "acc11", 11, {0, {0}}, 0, 0 }, + { "acc12", 12, {0, {0}}, 0, 0 }, + { "acc13", 13, {0, {0}}, 0, 0 }, + { "acc14", 14, {0, {0}}, 0, 0 }, + { "acc15", 15, {0, {0}}, 0, 0 }, + { "acc16", 16, {0, {0}}, 0, 0 }, + { "acc17", 17, {0, {0}}, 0, 0 }, + { "acc18", 18, {0, {0}}, 0, 0 }, + { "acc19", 19, {0, {0}}, 0, 0 }, + { "acc20", 20, {0, {0}}, 0, 0 }, + { "acc21", 21, {0, {0}}, 0, 0 }, + { "acc22", 22, {0, {0}}, 0, 0 }, + { "acc23", 23, {0, {0}}, 0, 0 }, + { "acc24", 24, {0, {0}}, 0, 0 }, + { "acc25", 25, {0, {0}}, 0, 0 }, + { "acc26", 26, {0, {0}}, 0, 0 }, + { "acc27", 27, {0, {0}}, 0, 0 }, + { "acc28", 28, {0, {0}}, 0, 0 }, + { "acc29", 29, {0, {0}}, 0, 0 }, + { "acc30", 30, {0, {0}}, 0, 0 }, + { "acc31", 31, {0, {0}}, 0, 0 }, + { "acc32", 32, {0, {0}}, 0, 0 }, + { "acc33", 33, {0, {0}}, 0, 0 }, + { "acc34", 34, {0, {0}}, 0, 0 }, + { "acc35", 35, {0, {0}}, 0, 0 }, + { "acc36", 36, {0, {0}}, 0, 0 }, + { "acc37", 37, {0, {0}}, 0, 0 }, + { "acc38", 38, {0, {0}}, 0, 0 }, + { "acc39", 39, {0, {0}}, 0, 0 }, + { "acc40", 40, {0, {0}}, 0, 0 }, + { "acc41", 41, {0, {0}}, 0, 0 }, + { "acc42", 42, {0, {0}}, 0, 0 }, + { "acc43", 43, {0, {0}}, 0, 0 }, + { "acc44", 44, {0, {0}}, 0, 0 }, + { "acc45", 45, {0, {0}}, 0, 0 }, + { "acc46", 46, {0, {0}}, 0, 0 }, + { "acc47", 47, {0, {0}}, 0, 0 }, + { "acc48", 48, {0, {0}}, 0, 0 }, + { "acc49", 49, {0, {0}}, 0, 0 }, + { "acc50", 50, {0, {0}}, 0, 0 }, + { "acc51", 51, {0, {0}}, 0, 0 }, + { "acc52", 52, {0, {0}}, 0, 0 }, + { "acc53", 53, {0, {0}}, 0, 0 }, + { "acc54", 54, {0, {0}}, 0, 0 }, + { "acc55", 55, {0, {0}}, 0, 0 }, + { "acc56", 56, {0, {0}}, 0, 0 }, + { "acc57", 57, {0, {0}}, 0, 0 }, + { "acc58", 58, {0, {0}}, 0, 0 }, + { "acc59", 59, {0, {0}}, 0, 0 }, + { "acc60", 60, {0, {0}}, 0, 0 }, + { "acc61", 61, {0, {0}}, 0, 0 }, + { "acc62", 62, {0, {0}}, 0, 0 }, + { "acc63", 63, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_acc_names = +{ + & frv_cgen_opval_acc_names_entries[0], + 64, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_iccr_names_entries[] = +{ + { "icc0", 0, {0, {0}}, 0, 0 }, + { "icc1", 1, {0, {0}}, 0, 0 }, + { "icc2", 2, {0, {0}}, 0, 0 }, + { "icc3", 3, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_iccr_names = +{ + & frv_cgen_opval_iccr_names_entries[0], + 4, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_fccr_names_entries[] = +{ + { "fcc0", 0, {0, {0}}, 0, 0 }, + { "fcc1", 1, {0, {0}}, 0, 0 }, + { "fcc2", 2, {0, {0}}, 0, 0 }, + { "fcc3", 3, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_fccr_names = +{ + & frv_cgen_opval_fccr_names_entries[0], + 4, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_cccr_names_entries[] = +{ + { "cc0", 0, {0, {0}}, 0, 0 }, + { "cc1", 1, {0, {0}}, 0, 0 }, + { "cc2", 2, {0, {0}}, 0, 0 }, + { "cc3", 3, {0, {0}}, 0, 0 }, + { "cc4", 4, {0, {0}}, 0, 0 }, + { "cc5", 5, {0, {0}}, 0, 0 }, + { "cc6", 6, {0, {0}}, 0, 0 }, + { "cc7", 7, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_cccr_names = +{ + & frv_cgen_opval_cccr_names_entries[0], + 8, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_pack_entries[] = +{ + { "", 1, {0, {0}}, 0, 0 }, + { ".p", 0, {0, {0}}, 0, 0 }, + { ".P", 0, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_h_pack = +{ + & frv_cgen_opval_h_pack_entries[0], + 3, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_hint_taken_entries[] = +{ + { "", 2, {0, {0}}, 0, 0 }, + { "", 0, {0, {0}}, 0, 0 }, + { "", 1, {0, {0}}, 0, 0 }, + { "", 3, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_h_hint_taken = +{ + & frv_cgen_opval_h_hint_taken_entries[0], + 4, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_hint_not_taken_entries[] = +{ + { "", 0, {0, {0}}, 0, 0 }, + { "", 1, {0, {0}}, 0, 0 }, + { "", 2, {0, {0}}, 0, 0 }, + { "", 3, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD frv_cgen_opval_h_hint_not_taken = +{ + & frv_cgen_opval_h_hint_not_taken_entries[0], + 4, + 0, 0, 0, 0, "" +}; + + +/* The hardware table. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_HW_##a) +#else +#define A(a) (1 << CGEN_HW_/**/a) +#endif + +const CGEN_HW_ENTRY frv_cgen_hw_table[] = +{ + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } }, + { "h-psr_imple", HW_H_PSR_IMPLE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-psr_ver", HW_H_PSR_VER, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-psr_ice", HW_H_PSR_ICE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-psr_nem", HW_H_PSR_NEM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-psr_cm", HW_H_PSR_CM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-psr_be", HW_H_PSR_BE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-psr_esr", HW_H_PSR_ESR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-psr_ef", HW_H_PSR_EF, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-psr_em", HW_H_PSR_EM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-psr_pil", HW_H_PSR_PIL, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-psr_ps", HW_H_PSR_PS, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-psr_et", HW_H_PSR_ET, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-psr_s", HW_H_PSR_S, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-tbr_tba", HW_H_TBR_TBA, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-tbr_tt", HW_H_TBR_TT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-bpsr_bs", HW_H_BPSR_BS, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-bpsr_bet", HW_H_BPSR_BET, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } }, + { "h-gr_double", HW_H_GR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, + { "h-gr_hi", HW_H_GR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, + { "h-gr_lo", HW_H_GR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, + { "h-fr", HW_H_FR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } }, + { "h-fr_double", HW_H_FR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, + { "h-fr_int", HW_H_FR_INT, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, + { "h-fr_hi", HW_H_FR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, + { "h-fr_lo", HW_H_FR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, + { "h-fr_0", HW_H_FR_0, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, + { "h-fr_1", HW_H_FR_1, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, + { "h-fr_2", HW_H_FR_2, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, + { "h-fr_3", HW_H_FR_3, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, + { "h-cpr", HW_H_CPR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cpr_names, { 0|A(PROFILE), { (1<<MACH_FRV) } } }, + { "h-cpr_double", HW_H_CPR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cpr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_FRV) } } }, + { "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_spr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } }, + { "h-accg", HW_H_ACCG, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_accg_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, + { "h-acc40S", HW_H_ACC40S, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, + { "h-acc40U", HW_H_ACC40U, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, + { "h-iccr", HW_H_ICCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } }, + { "h-fccr", HW_H_FCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } }, + { "h-cccr", HW_H_CCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } }, + { "h-pack", HW_H_PACK, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_pack, { 0, { (1<<MACH_BASE) } } }, + { "h-hint-taken", HW_H_HINT_TAKEN, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_hint_taken, { 0, { (1<<MACH_BASE) } } }, + { "h-hint-not-taken", HW_H_HINT_NOT_TAKEN, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_hint_not_taken, { 0, { (1<<MACH_BASE) } } }, + { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} } +}; + +#undef A + + +/* The instruction field table. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_IFLD_##a) +#else +#define A(a) (1 << CGEN_IFLD_/**/a) +#endif + +const CGEN_IFLD frv_cgen_ifld_table[] = +{ + { FRV_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_PACK, "f-pack", 0, 32, 31, 1, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_OP, "f-op", 0, 32, 24, 7, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_OPE1, "f-ope1", 0, 32, 11, 6, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_OPE2, "f-ope2", 0, 32, 9, 4, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_OPE3, "f-ope3", 0, 32, 15, 3, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_OPE4, "f-ope4", 0, 32, 7, 2, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_GRI, "f-GRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_GRJ, "f-GRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_GRK, "f-GRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_FRI, "f-FRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_FRJ, "f-FRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_FRK, "f-FRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_CPRI, "f-CPRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_CPRJ, "f-CPRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_CPRK, "f-CPRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_ACCGI, "f-ACCGi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_ACCGK, "f-ACCGk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_ACC40SI, "f-ACC40Si", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_ACC40UI, "f-ACC40Ui", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_ACC40SK, "f-ACC40Sk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_ACC40UK, "f-ACC40Uk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_CRI, "f-CRi", 0, 32, 14, 3, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_CRJ, "f-CRj", 0, 32, 2, 3, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_CRK, "f-CRk", 0, 32, 27, 3, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_CCI, "f-CCi", 0, 32, 11, 3, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_CRJ_INT, "f-CRj_int", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_CRJ_FLOAT, "f-CRj_float", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_ICCI_1, "f-ICCi_1", 0, 32, 11, 2, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_ICCI_2, "f-ICCi_2", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_ICCI_3, "f-ICCi_3", 0, 32, 1, 2, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_FCCI_1, "f-FCCi_1", 0, 32, 11, 2, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_FCCI_2, "f-FCCi_2", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_FCCI_3, "f-FCCi_3", 0, 32, 1, 2, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_FCCK, "f-FCCk", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_EIR, "f-eir", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_S10, "f-s10", 0, 32, 9, 10, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_S12, "f-s12", 0, 32, 11, 12, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_D12, "f-d12", 0, 32, 11, 12, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_U16, "f-u16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_S16, "f-s16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_S6, "f-s6", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_S6_1, "f-s6_1", 0, 32, 11, 6, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_U6, "f-u6", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_S5, "f-s5", 0, 32, 4, 5, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_U12_H, "f-u12-h", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_U12_L, "f-u12-l", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_INT_CC, "f-int-cc", 0, 32, 30, 4, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_FLT_CC, "f-flt-cc", 0, 32, 30, 4, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_COND, "f-cond", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_CCOND, "f-ccond", 0, 32, 12, 1, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_HINT, "f-hint", 0, 32, 17, 2, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_LI, "f-LI", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_LOCK, "f-lock", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_DEBUG, "f-debug", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_A, "f-A", 0, 32, 17, 1, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_AE, "f-ae", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_SPR_H, "f-spr-h", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_SPR_L, "f-spr-l", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_LABEL16, "f-label16", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, + { FRV_F_LABELH6, "f-labelH6", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_LABELL18, "f-labelL18", 0, 32, 17, 18, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_ICCI_1_NULL, "f-ICCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_ICCI_2_NULL, "f-ICCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_ICCI_3_NULL, "f-ICCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_FCCI_1_NULL, "f-FCCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_FCCI_2_NULL, "f-FCCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_FCCI_3_NULL, "f-FCCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_RS_NULL, "f-rs-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_GRI_NULL, "f-GRi-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_GRJ_NULL, "f-GRj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_GRK_NULL, "f-GRk-null", 0, 32, 30, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_FRI_NULL, "f-FRi-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_FRJ_NULL, "f-FRj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_ACCJ_NULL, "f-ACCj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_RD_NULL, "f-rd-null", 0, 32, 30, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_COND_NULL, "f-cond-null", 0, 32, 30, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_CCOND_NULL, "f-ccond-null", 0, 32, 12, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_S12_NULL, "f-s12-null", 0, 32, 11, 12, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_LABEL16_NULL, "f-label16-null", 0, 32, 15, 16, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_MISC_NULL_1, "f-misc-null-1", 0, 32, 30, 5, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_MISC_NULL_2, "f-misc-null-2", 0, 32, 11, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_MISC_NULL_3, "f-misc-null-3", 0, 32, 11, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_MISC_NULL_4, "f-misc-null-4", 0, 32, 17, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_MISC_NULL_5, "f-misc-null-5", 0, 32, 17, 16, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_MISC_NULL_6, "f-misc-null-6", 0, 32, 30, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_MISC_NULL_7, "f-misc-null-7", 0, 32, 17, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_MISC_NULL_8, "f-misc-null-8", 0, 32, 5, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_MISC_NULL_9, "f-misc-null-9", 0, 32, 5, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_MISC_NULL_10, "f-misc-null-10", 0, 32, 16, 5, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_MISC_NULL_11, "f-misc-null-11", 0, 32, 5, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_LI_OFF, "f-LI-off", 0, 32, 25, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { FRV_F_LI_ON, "f-LI-on", 0, 32, 25, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, + { 0, 0, 0, 0, 0, 0, {0, {0}} } +}; + +#undef A + + + +/* multi ifield declarations */ + +const CGEN_MAYBE_MULTI_IFLD FRV_F_U12_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD FRV_F_SPR_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD FRV_F_LABEL24_MULTI_IFIELD []; + + +/* multi ifield definitions */ + +const CGEN_MAYBE_MULTI_IFLD FRV_F_U12_MULTI_IFIELD [] = +{ + { 0, &(frv_cgen_ifld_table[46]) }, + { 0, &(frv_cgen_ifld_table[47]) }, + {0,0} +}; +const CGEN_MAYBE_MULTI_IFLD FRV_F_SPR_MULTI_IFIELD [] = +{ + { 0, &(frv_cgen_ifld_table[58]) }, + { 0, &(frv_cgen_ifld_table[59]) }, + {0,0} +}; +const CGEN_MAYBE_MULTI_IFLD FRV_F_LABEL24_MULTI_IFIELD [] = +{ + { 0, &(frv_cgen_ifld_table[61]) }, + { 0, &(frv_cgen_ifld_table[62]) }, + {0,0} +}; + +/* The operand table. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_OPERAND_##a) +#else +#define A(a) (1 << CGEN_OPERAND_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) FRV_OPERAND_##op +#else +#define OPERAND(op) FRV_OPERAND_/**/op +#endif + +const CGEN_OPERAND frv_cgen_operand_table[] = +{ +/* pc: program counter */ + { "pc", FRV_OPERAND_PC, HW_H_PC, 0, 0, + { 0, &(frv_cgen_ifld_table[0]) }, + { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, +/* pack: packing bit */ + { "pack", FRV_OPERAND_PACK, HW_H_PACK, 31, 1, + { 0, &(frv_cgen_ifld_table[2]) }, + { 0, { (1<<MACH_BASE) } } }, +/* GRi: source register 1 */ + { "GRi", FRV_OPERAND_GRI, HW_H_GR, 17, 6, + { 0, &(frv_cgen_ifld_table[8]) }, + { 0, { (1<<MACH_BASE) } } }, +/* GRj: source register 2 */ + { "GRj", FRV_OPERAND_GRJ, HW_H_GR, 5, 6, + { 0, &(frv_cgen_ifld_table[9]) }, + { 0, { (1<<MACH_BASE) } } }, +/* GRk: destination register */ + { "GRk", FRV_OPERAND_GRK, HW_H_GR, 30, 6, + { 0, &(frv_cgen_ifld_table[10]) }, + { 0, { (1<<MACH_BASE) } } }, +/* GRkhi: destination register */ + { "GRkhi", FRV_OPERAND_GRKHI, HW_H_GR_HI, 30, 6, + { 0, &(frv_cgen_ifld_table[10]) }, + { 0, { (1<<MACH_BASE) } } }, +/* GRklo: destination register */ + { "GRklo", FRV_OPERAND_GRKLO, HW_H_GR_LO, 30, 6, + { 0, &(frv_cgen_ifld_table[10]) }, + { 0, { (1<<MACH_BASE) } } }, +/* GRdoublek: destination register */ + { "GRdoublek", FRV_OPERAND_GRDOUBLEK, HW_H_GR_DOUBLE, 30, 6, + { 0, &(frv_cgen_ifld_table[10]) }, + { 0, { (1<<MACH_BASE) } } }, +/* ACC40Si: signed accumulator */ + { "ACC40Si", FRV_OPERAND_ACC40SI, HW_H_ACC40S, 17, 6, + { 0, &(frv_cgen_ifld_table[19]) }, + { 0, { (1<<MACH_BASE) } } }, +/* ACC40Ui: unsigned accumulator */ + { "ACC40Ui", FRV_OPERAND_ACC40UI, HW_H_ACC40U, 17, 6, + { 0, &(frv_cgen_ifld_table[20]) }, + { 0, { (1<<MACH_BASE) } } }, +/* ACC40Sk: target accumulator */ + { "ACC40Sk", FRV_OPERAND_ACC40SK, HW_H_ACC40S, 30, 6, + { 0, &(frv_cgen_ifld_table[21]) }, + { 0, { (1<<MACH_BASE) } } }, +/* ACC40Uk: target accumulator */ + { "ACC40Uk", FRV_OPERAND_ACC40UK, HW_H_ACC40U, 30, 6, + { 0, &(frv_cgen_ifld_table[22]) }, + { 0, { (1<<MACH_BASE) } } }, +/* ACCGi: source register */ + { "ACCGi", FRV_OPERAND_ACCGI, HW_H_ACCG, 17, 6, + { 0, &(frv_cgen_ifld_table[17]) }, + { 0, { (1<<MACH_BASE) } } }, +/* ACCGk: target register */ + { "ACCGk", FRV_OPERAND_ACCGK, HW_H_ACCG, 30, 6, + { 0, &(frv_cgen_ifld_table[18]) }, + { 0, { (1<<MACH_BASE) } } }, +/* CPRi: source register */ + { "CPRi", FRV_OPERAND_CPRI, HW_H_CPR, 17, 6, + { 0, &(frv_cgen_ifld_table[14]) }, + { 0, { (1<<MACH_FRV) } } }, +/* CPRj: source register */ + { "CPRj", FRV_OPERAND_CPRJ, HW_H_CPR, 5, 6, + { 0, &(frv_cgen_ifld_table[15]) }, + { 0, { (1<<MACH_FRV) } } }, +/* CPRk: destination register */ + { "CPRk", FRV_OPERAND_CPRK, HW_H_CPR, 30, 6, + { 0, &(frv_cgen_ifld_table[16]) }, + { 0, { (1<<MACH_FRV) } } }, +/* CPRdoublek: destination register */ + { "CPRdoublek", FRV_OPERAND_CPRDOUBLEK, HW_H_CPR_DOUBLE, 30, 6, + { 0, &(frv_cgen_ifld_table[16]) }, + { 0, { (1<<MACH_FRV) } } }, +/* FRinti: source register 1 */ + { "FRinti", FRV_OPERAND_FRINTI, HW_H_FR_INT, 17, 6, + { 0, &(frv_cgen_ifld_table[11]) }, + { 0, { (1<<MACH_BASE) } } }, +/* FRintj: source register 2 */ + { "FRintj", FRV_OPERAND_FRINTJ, HW_H_FR_INT, 5, 6, + { 0, &(frv_cgen_ifld_table[12]) }, + { 0, { (1<<MACH_BASE) } } }, +/* FRintk: target register */ + { "FRintk", FRV_OPERAND_FRINTK, HW_H_FR_INT, 30, 6, + { 0, &(frv_cgen_ifld_table[13]) }, + { 0, { (1<<MACH_BASE) } } }, +/* FRi: source register 1 */ + { "FRi", FRV_OPERAND_FRI, HW_H_FR, 17, 6, + { 0, &(frv_cgen_ifld_table[11]) }, + { 0, { (1<<MACH_BASE) } } }, +/* FRj: source register 2 */ + { "FRj", FRV_OPERAND_FRJ, HW_H_FR, 5, 6, + { 0, &(frv_cgen_ifld_table[12]) }, + { 0, { (1<<MACH_BASE) } } }, +/* FRk: destination register */ + { "FRk", FRV_OPERAND_FRK, HW_H_FR, 30, 6, + { 0, &(frv_cgen_ifld_table[13]) }, + { 0, { (1<<MACH_BASE) } } }, +/* FRkhi: destination register */ + { "FRkhi", FRV_OPERAND_FRKHI, HW_H_FR_HI, 30, 6, + { 0, &(frv_cgen_ifld_table[13]) }, + { 0, { (1<<MACH_BASE) } } }, +/* FRklo: destination register */ + { "FRklo", FRV_OPERAND_FRKLO, HW_H_FR_LO, 30, 6, + { 0, &(frv_cgen_ifld_table[13]) }, + { 0, { (1<<MACH_BASE) } } }, +/* FRdoublei: source register 1 */ + { "FRdoublei", FRV_OPERAND_FRDOUBLEI, HW_H_FR_DOUBLE, 17, 6, + { 0, &(frv_cgen_ifld_table[11]) }, + { 0, { (1<<MACH_BASE) } } }, +/* FRdoublej: source register 2 */ + { "FRdoublej", FRV_OPERAND_FRDOUBLEJ, HW_H_FR_DOUBLE, 5, 6, + { 0, &(frv_cgen_ifld_table[12]) }, + { 0, { (1<<MACH_BASE) } } }, +/* FRdoublek: target register */ + { "FRdoublek", FRV_OPERAND_FRDOUBLEK, HW_H_FR_DOUBLE, 30, 6, + { 0, &(frv_cgen_ifld_table[13]) }, + { 0, { (1<<MACH_BASE) } } }, +/* CRi: source register 1 */ + { "CRi", FRV_OPERAND_CRI, HW_H_CCCR, 14, 3, + { 0, &(frv_cgen_ifld_table[23]) }, + { 0, { (1<<MACH_BASE) } } }, +/* CRj: source register 2 */ + { "CRj", FRV_OPERAND_CRJ, HW_H_CCCR, 2, 3, + { 0, &(frv_cgen_ifld_table[24]) }, + { 0, { (1<<MACH_BASE) } } }, +/* CRj_int: destination register */ + { "CRj_int", FRV_OPERAND_CRJ_INT, HW_H_CCCR, 26, 2, + { 0, &(frv_cgen_ifld_table[27]) }, + { 0, { (1<<MACH_BASE) } } }, +/* CRj_float: destination register */ + { "CRj_float", FRV_OPERAND_CRJ_FLOAT, HW_H_CCCR, 26, 2, + { 0, &(frv_cgen_ifld_table[28]) }, + { 0, { (1<<MACH_BASE) } } }, +/* CRk: destination register */ + { "CRk", FRV_OPERAND_CRK, HW_H_CCCR, 27, 3, + { 0, &(frv_cgen_ifld_table[25]) }, + { 0, { (1<<MACH_BASE) } } }, +/* CCi: condition register */ + { "CCi", FRV_OPERAND_CCI, HW_H_CCCR, 11, 3, + { 0, &(frv_cgen_ifld_table[26]) }, + { 0, { (1<<MACH_BASE) } } }, +/* ICCi_1: condition register */ + { "ICCi_1", FRV_OPERAND_ICCI_1, HW_H_ICCR, 11, 2, + { 0, &(frv_cgen_ifld_table[29]) }, + { 0, { (1<<MACH_BASE) } } }, +/* ICCi_2: condition register */ + { "ICCi_2", FRV_OPERAND_ICCI_2, HW_H_ICCR, 26, 2, + { 0, &(frv_cgen_ifld_table[30]) }, + { 0, { (1<<MACH_BASE) } } }, +/* ICCi_3: condition register */ + { "ICCi_3", FRV_OPERAND_ICCI_3, HW_H_ICCR, 1, 2, + { 0, &(frv_cgen_ifld_table[31]) }, + { 0, { (1<<MACH_BASE) } } }, +/* FCCi_1: condition register */ + { "FCCi_1", FRV_OPERAND_FCCI_1, HW_H_FCCR, 11, 2, + { 0, &(frv_cgen_ifld_table[32]) }, + { 0, { (1<<MACH_BASE) } } }, +/* FCCi_2: condition register */ + { "FCCi_2", FRV_OPERAND_FCCI_2, HW_H_FCCR, 26, 2, + { 0, &(frv_cgen_ifld_table[33]) }, + { 0, { (1<<MACH_BASE) } } }, +/* FCCi_3: condition register */ + { "FCCi_3", FRV_OPERAND_FCCI_3, HW_H_FCCR, 1, 2, + { 0, &(frv_cgen_ifld_table[34]) }, + { 0, { (1<<MACH_BASE) } } }, +/* FCCk: condition register */ + { "FCCk", FRV_OPERAND_FCCK, HW_H_FCCR, 26, 2, + { 0, &(frv_cgen_ifld_table[35]) }, + { 0, { (1<<MACH_BASE) } } }, +/* eir: exception insn reg */ + { "eir", FRV_OPERAND_EIR, HW_H_UINT, 17, 6, + { 0, &(frv_cgen_ifld_table[36]) }, + { 0, { (1<<MACH_BASE) } } }, +/* s10: 10 bit signed immediate */ + { "s10", FRV_OPERAND_S10, HW_H_SINT, 9, 10, + { 0, &(frv_cgen_ifld_table[37]) }, + { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, +/* u16: 16 bit unsigned immediate */ + { "u16", FRV_OPERAND_U16, HW_H_UINT, 15, 16, + { 0, &(frv_cgen_ifld_table[40]) }, + { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, +/* s16: 16 bit signed immediate */ + { "s16", FRV_OPERAND_S16, HW_H_SINT, 15, 16, + { 0, &(frv_cgen_ifld_table[41]) }, + { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, +/* s6: 6 bit signed immediate */ + { "s6", FRV_OPERAND_S6, HW_H_SINT, 5, 6, + { 0, &(frv_cgen_ifld_table[42]) }, + { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, +/* s6_1: 6 bit signed immediate */ + { "s6_1", FRV_OPERAND_S6_1, HW_H_SINT, 11, 6, + { 0, &(frv_cgen_ifld_table[43]) }, + { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, +/* u6: 6 bit unsigned immediate */ + { "u6", FRV_OPERAND_U6, HW_H_UINT, 5, 6, + { 0, &(frv_cgen_ifld_table[44]) }, + { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, +/* s5: 5 bit signed immediate */ + { "s5", FRV_OPERAND_S5, HW_H_SINT, 4, 5, + { 0, &(frv_cgen_ifld_table[45]) }, + { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, +/* cond: conditional arithmetic */ + { "cond", FRV_OPERAND_COND, HW_H_UINT, 8, 1, + { 0, &(frv_cgen_ifld_table[50]) }, + { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, +/* ccond: lr branch condition */ + { "ccond", FRV_OPERAND_CCOND, HW_H_UINT, 12, 1, + { 0, &(frv_cgen_ifld_table[51]) }, + { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, +/* hint: 2 bit branch predictor */ + { "hint", FRV_OPERAND_HINT, HW_H_UINT, 17, 2, + { 0, &(frv_cgen_ifld_table[52]) }, + { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, +/* hint_taken: 2 bit branch predictor */ + { "hint_taken", FRV_OPERAND_HINT_TAKEN, HW_H_HINT_TAKEN, 17, 2, + { 0, &(frv_cgen_ifld_table[52]) }, + { 0, { (1<<MACH_BASE) } } }, +/* hint_not_taken: 2 bit branch predictor */ + { "hint_not_taken", FRV_OPERAND_HINT_NOT_TAKEN, HW_H_HINT_NOT_TAKEN, 17, 2, + { 0, &(frv_cgen_ifld_table[52]) }, + { 0, { (1<<MACH_BASE) } } }, +/* LI: link indicator */ + { "LI", FRV_OPERAND_LI, HW_H_UINT, 25, 1, + { 0, &(frv_cgen_ifld_table[53]) }, + { 0, { (1<<MACH_BASE) } } }, +/* lock: cache lock indicator */ + { "lock", FRV_OPERAND_LOCK, HW_H_UINT, 25, 1, + { 0, &(frv_cgen_ifld_table[54]) }, + { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, +/* debug: debug mode indicator */ + { "debug", FRV_OPERAND_DEBUG, HW_H_UINT, 25, 1, + { 0, &(frv_cgen_ifld_table[55]) }, + { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, +/* A: all accumulator indicator */ + { "A", FRV_OPERAND_A, HW_H_UINT, 17, 1, + { 0, &(frv_cgen_ifld_table[56]) }, + { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, +/* ae: all entries indicator */ + { "ae", FRV_OPERAND_AE, HW_H_UINT, 25, 1, + { 0, &(frv_cgen_ifld_table[57]) }, + { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, +/* label16: 18 bit pc relative address */ + { "label16", FRV_OPERAND_LABEL16, HW_H_IADDR, 15, 16, + { 0, &(frv_cgen_ifld_table[60]) }, + { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, +/* label24: 26 bit pc relative address */ + { "label24", FRV_OPERAND_LABEL24, HW_H_IADDR, 17, 24, + { 2, &(FRV_F_LABEL24_MULTI_IFIELD[0]) }, + { 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } }, +/* d12: 12 bit signed immediate */ + { "d12", FRV_OPERAND_D12, HW_H_SINT, 11, 12, + { 0, &(frv_cgen_ifld_table[39]) }, + { 0, { (1<<MACH_BASE) } } }, +/* s12: 12 bit signed immediate */ + { "s12", FRV_OPERAND_S12, HW_H_SINT, 11, 12, + { 0, &(frv_cgen_ifld_table[39]) }, + { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, +/* u12: 12 bit signed immediate */ + { "u12", FRV_OPERAND_U12, HW_H_SINT, 5, 12, + { 2, &(FRV_F_U12_MULTI_IFIELD[0]) }, + { 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } } }, +/* spr: special purpose register */ + { "spr", FRV_OPERAND_SPR, HW_H_SPR, 17, 12, + { 2, &(FRV_F_SPR_MULTI_IFIELD[0]) }, + { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, +/* ulo16: 16 bit unsigned immediate, for #lo() */ + { "ulo16", FRV_OPERAND_ULO16, HW_H_UINT, 15, 16, + { 0, &(frv_cgen_ifld_table[40]) }, + { 0, { (1<<MACH_BASE) } } }, +/* slo16: 16 bit unsigned immediate, for #lo() */ + { "slo16", FRV_OPERAND_SLO16, HW_H_SINT, 15, 16, + { 0, &(frv_cgen_ifld_table[41]) }, + { 0, { (1<<MACH_BASE) } } }, +/* uhi16: 16 bit unsigned immediate, for #hi() */ + { "uhi16", FRV_OPERAND_UHI16, HW_H_UINT, 15, 16, + { 0, &(frv_cgen_ifld_table[40]) }, + { 0, { (1<<MACH_BASE) } } }, +/* psr_esr: PSR.ESR bit */ + { "psr_esr", FRV_OPERAND_PSR_ESR, HW_H_PSR_ESR, 0, 0, + { 0, 0 }, + { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, +/* psr_s: PSR.S bit */ + { "psr_s", FRV_OPERAND_PSR_S, HW_H_PSR_S, 0, 0, + { 0, 0 }, + { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, +/* psr_ps: PSR.PS bit */ + { "psr_ps", FRV_OPERAND_PSR_PS, HW_H_PSR_PS, 0, 0, + { 0, 0 }, + { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, +/* psr_et: PSR.ET bit */ + { "psr_et", FRV_OPERAND_PSR_ET, HW_H_PSR_ET, 0, 0, + { 0, 0 }, + { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, +/* bpsr_bs: BPSR.BS bit */ + { "bpsr_bs", FRV_OPERAND_BPSR_BS, HW_H_BPSR_BS, 0, 0, + { 0, 0 }, + { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, +/* bpsr_bet: BPSR.BET bit */ + { "bpsr_bet", FRV_OPERAND_BPSR_BET, HW_H_BPSR_BET, 0, 0, + { 0, 0 }, + { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, +/* tbr_tba: TBR.TBA */ + { "tbr_tba", FRV_OPERAND_TBR_TBA, HW_H_TBR_TBA, 0, 0, + { 0, 0 }, + { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, +/* tbr_tt: TBR.TT */ + { "tbr_tt", FRV_OPERAND_TBR_TT, HW_H_TBR_TT, 0, 0, + { 0, 0 }, + { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, + { 0, 0, 0, 0, 0, {0, {0}} } +}; + +#undef A + + +/* The instruction table. */ + +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif + +static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { 0, 0, 0, 0, {0, {0}} }, +/* add$pack $GRi,$GRj,$GRk */ + { + FRV_INSN_ADD, "add", "add", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* sub$pack $GRi,$GRj,$GRk */ + { + FRV_INSN_SUB, "sub", "sub", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* and$pack $GRi,$GRj,$GRk */ + { + FRV_INSN_AND, "and", "and", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* or$pack $GRi,$GRj,$GRk */ + { + FRV_INSN_OR, "or", "or", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* xor$pack $GRi,$GRj,$GRk */ + { + FRV_INSN_XOR, "xor", "xor", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* not$pack $GRj,$GRk */ + { + FRV_INSN_NOT, "not", "not", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* sdiv$pack $GRi,$GRj,$GRk */ + { + FRV_INSN_SDIV, "sdiv", "sdiv", 32, + { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* nsdiv$pack $GRi,$GRj,$GRk */ + { + FRV_INSN_NSDIV, "nsdiv", "nsdiv", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } } + }, +/* udiv$pack $GRi,$GRj,$GRk */ + { + FRV_INSN_UDIV, "udiv", "udiv", 32, + { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* nudiv$pack $GRi,$GRj,$GRk */ + { + FRV_INSN_NUDIV, "nudiv", "nudiv", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } } + }, +/* smul$pack $GRi,$GRj,$GRdoublek */ + { + FRV_INSN_SMUL, "smul", "smul", 32, + { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* umul$pack $GRi,$GRj,$GRdoublek */ + { + FRV_INSN_UMUL, "umul", "umul", 32, + { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* sll$pack $GRi,$GRj,$GRk */ + { + FRV_INSN_SLL, "sll", "sll", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* srl$pack $GRi,$GRj,$GRk */ + { + FRV_INSN_SRL, "srl", "srl", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* sra$pack $GRi,$GRj,$GRk */ + { + FRV_INSN_SRA, "sra", "sra", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* scan$pack $GRi,$GRj,$GRk */ + { + FRV_INSN_SCAN, "scan", "scan", 32, + { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* cadd$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + FRV_INSN_CADD, "cadd", "cadd", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* csub$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + FRV_INSN_CSUB, "csub", "csub", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* cand$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + FRV_INSN_CAND, "cand", "cand", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* cor$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + FRV_INSN_COR, "cor", "cor", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* cxor$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + FRV_INSN_CXOR, "cxor", "cxor", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* cnot$pack $GRj,$GRk,$CCi,$cond */ + { + FRV_INSN_CNOT, "cnot", "cnot", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */ + { + FRV_INSN_CSMUL, "csmul", "csmul", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* csdiv$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + FRV_INSN_CSDIV, "csdiv", "csdiv", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* cudiv$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + FRV_INSN_CUDIV, "cudiv", "cudiv", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* csll$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + FRV_INSN_CSLL, "csll", "csll", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* csrl$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + FRV_INSN_CSRL, "csrl", "csrl", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* csra$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + FRV_INSN_CSRA, "csra", "csra", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* cscan$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + FRV_INSN_CSCAN, "cscan", "cscan", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* addcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + FRV_INSN_ADDCC, "addcc", "addcc", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* subcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + FRV_INSN_SUBCC, "subcc", "subcc", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* andcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + FRV_INSN_ANDCC, "andcc", "andcc", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* orcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + FRV_INSN_ORCC, "orcc", "orcc", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* xorcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + FRV_INSN_XORCC, "xorcc", "xorcc", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* sllcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + FRV_INSN_SLLCC, "sllcc", "sllcc", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* srlcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + FRV_INSN_SRLCC, "srlcc", "srlcc", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* sracc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + FRV_INSN_SRACC, "sracc", "sracc", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* smulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */ + { + FRV_INSN_SMULCC, "smulcc", "smulcc", 32, + { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* umulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */ + { + FRV_INSN_UMULCC, "umulcc", "umulcc", 32, + { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* caddcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + FRV_INSN_CADDCC, "caddcc", "caddcc", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* csubcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + FRV_INSN_CSUBCC, "csubcc", "csubcc", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */ + { + FRV_INSN_CSMULCC, "csmulcc", "csmulcc", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* candcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + FRV_INSN_CANDCC, "candcc", "candcc", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* corcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + FRV_INSN_CORCC, "corcc", "corcc", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* cxorcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + FRV_INSN_CXORCC, "cxorcc", "cxorcc", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* csllcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + FRV_INSN_CSLLCC, "csllcc", "csllcc", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* csrlcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + FRV_INSN_CSRLCC, "csrlcc", "csrlcc", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* csracc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + FRV_INSN_CSRACC, "csracc", "csracc", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* addx$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + FRV_INSN_ADDX, "addx", "addx", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* subx$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + FRV_INSN_SUBX, "subx", "subx", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* addxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + FRV_INSN_ADDXCC, "addxcc", "addxcc", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* subxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + FRV_INSN_SUBXCC, "subxcc", "subxcc", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* addi$pack $GRi,$s12,$GRk */ + { + FRV_INSN_ADDI, "addi", "addi", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* subi$pack $GRi,$s12,$GRk */ + { + FRV_INSN_SUBI, "subi", "subi", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* andi$pack $GRi,$s12,$GRk */ + { + FRV_INSN_ANDI, "andi", "andi", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* ori$pack $GRi,$s12,$GRk */ + { + FRV_INSN_ORI, "ori", "ori", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* xori$pack $GRi,$s12,$GRk */ + { + FRV_INSN_XORI, "xori", "xori", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* sdivi$pack $GRi,$s12,$GRk */ + { + FRV_INSN_SDIVI, "sdivi", "sdivi", 32, + { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* nsdivi$pack $GRi,$s12,$GRk */ + { + FRV_INSN_NSDIVI, "nsdivi", "nsdivi", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } } + }, +/* udivi$pack $GRi,$s12,$GRk */ + { + FRV_INSN_UDIVI, "udivi", "udivi", 32, + { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* nudivi$pack $GRi,$s12,$GRk */ + { + FRV_INSN_NUDIVI, "nudivi", "nudivi", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1 } } + }, +/* smuli$pack $GRi,$s12,$GRdoublek */ + { + FRV_INSN_SMULI, "smuli", "smuli", 32, + { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* umuli$pack $GRi,$s12,$GRdoublek */ + { + FRV_INSN_UMULI, "umuli", "umuli", 32, + { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* slli$pack $GRi,$s12,$GRk */ + { + FRV_INSN_SLLI, "slli", "slli", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* srli$pack $GRi,$s12,$GRk */ + { + FRV_INSN_SRLI, "srli", "srli", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* srai$pack $GRi,$s12,$GRk */ + { + FRV_INSN_SRAI, "srai", "srai", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* scani$pack $GRi,$s12,$GRk */ + { + FRV_INSN_SCANI, "scani", "scani", 32, + { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* addicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + FRV_INSN_ADDICC, "addicc", "addicc", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* subicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + FRV_INSN_SUBICC, "subicc", "subicc", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* andicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + FRV_INSN_ANDICC, "andicc", "andicc", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* oricc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + FRV_INSN_ORICC, "oricc", "oricc", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* xoricc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + FRV_INSN_XORICC, "xoricc", "xoricc", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* smulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */ + { + FRV_INSN_SMULICC, "smulicc", "smulicc", 32, + { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* umulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */ + { + FRV_INSN_UMULICC, "umulicc", "umulicc", 32, + { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* sllicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + FRV_INSN_SLLICC, "sllicc", "sllicc", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* srlicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + FRV_INSN_SRLICC, "srlicc", "srlicc", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* sraicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + FRV_INSN_SRAICC, "sraicc", "sraicc", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* addxi$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + FRV_INSN_ADDXI, "addxi", "addxi", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* subxi$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + FRV_INSN_SUBXI, "subxi", "subxi", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* addxicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + FRV_INSN_ADDXICC, "addxicc", "addxicc", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* subxicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + FRV_INSN_SUBXICC, "subxicc", "subxicc", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* cmpb$pack $GRi,$GRj,$ICCi_1 */ + { + FRV_INSN_CMPB, "cmpb", "cmpb", 32, + { 0, { (1<<MACH_FR400), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_NONE } } + }, +/* cmpba$pack $GRi,$GRj,$ICCi_1 */ + { + FRV_INSN_CMPBA, "cmpba", "cmpba", 32, + { 0, { (1<<MACH_FR400), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_NONE } } + }, +/* setlo$pack $ulo16,$GRklo */ + { + FRV_INSN_SETLO, "setlo", "setlo", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* sethi$pack $uhi16,$GRkhi */ + { + FRV_INSN_SETHI, "sethi", "sethi", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* setlos$pack $slo16,$GRk */ + { + FRV_INSN_SETLOS, "setlos", "setlos", 32, + { 0, { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* ldsb$pack @($GRi,$GRj),$GRk */ + { + FRV_INSN_LDSB, "ldsb", "ldsb", 32, + { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* ldub$pack @($GRi,$GRj),$GRk */ + { + FRV_INSN_LDUB, "ldub", "ldub", 32, + { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* ldsh$pack @($GRi,$GRj),$GRk */ + { + FRV_INSN_LDSH, "ldsh", "ldsh", 32, + { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* lduh$pack @($GRi,$GRj),$GRk */ + { + FRV_INSN_LDUH, "lduh", "lduh", 32, + { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* ld$pack @($GRi,$GRj),$GRk */ + { + FRV_INSN_LD, "ld", "ld", 32, + { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* ldbf$pack @($GRi,$GRj),$FRintk */ + { + FRV_INSN_LDBF, "ldbf", "ldbf", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* ldhf$pack @($GRi,$GRj),$FRintk */ + { + FRV_INSN_LDHF, "ldhf", "ldhf", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* ldf$pack @($GRi,$GRj),$FRintk */ + { + FRV_INSN_LDF, "ldf", "ldf", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* ldc$pack @($GRi,$GRj),$CPRk */ + { + FRV_INSN_LDC, "ldc", "ldc", 32, + { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nldsb$pack @($GRi,$GRj),$GRk */ + { + FRV_INSN_NLDSB, "nldsb", "nldsb", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nldub$pack @($GRi,$GRj),$GRk */ + { + FRV_INSN_NLDUB, "nldub", "nldub", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nldsh$pack @($GRi,$GRj),$GRk */ + { + FRV_INSN_NLDSH, "nldsh", "nldsh", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nlduh$pack @($GRi,$GRj),$GRk */ + { + FRV_INSN_NLDUH, "nlduh", "nlduh", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nld$pack @($GRi,$GRj),$GRk */ + { + FRV_INSN_NLD, "nld", "nld", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nldbf$pack @($GRi,$GRj),$FRintk */ + { + FRV_INSN_NLDBF, "nldbf", "nldbf", 32, + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nldhf$pack @($GRi,$GRj),$FRintk */ + { + FRV_INSN_NLDHF, "nldhf", "nldhf", 32, + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nldf$pack @($GRi,$GRj),$FRintk */ + { + FRV_INSN_NLDF, "nldf", "nldf", 32, + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* ldd$pack @($GRi,$GRj),$GRdoublek */ + { + FRV_INSN_LDD, "ldd", "ldd", 32, + { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* lddf$pack @($GRi,$GRj),$FRdoublek */ + { + FRV_INSN_LDDF, "lddf", "lddf", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* lddc$pack @($GRi,$GRj),$CPRdoublek */ + { + FRV_INSN_LDDC, "lddc", "lddc", 32, + { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* nldd$pack @($GRi,$GRj),$GRdoublek */ + { + FRV_INSN_NLDD, "nldd", "nldd", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nlddf$pack @($GRi,$GRj),$FRdoublek */ + { + FRV_INSN_NLDDF, "nlddf", "nlddf", 32, + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* ldq$pack @($GRi,$GRj),$GRk */ + { + FRV_INSN_LDQ, "ldq", "ldq", 32, + { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* ldqf$pack @($GRi,$GRj),$FRintk */ + { + FRV_INSN_LDQF, "ldqf", "ldqf", 32, + { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* ldqc$pack @($GRi,$GRj),$CPRk */ + { + FRV_INSN_LDQC, "ldqc", "ldqc", 32, + { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nldq$pack @($GRi,$GRj),$GRk */ + { + FRV_INSN_NLDQ, "nldq", "nldq", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nldqf$pack @($GRi,$GRj),$FRintk */ + { + FRV_INSN_NLDQF, "nldqf", "nldqf", 32, + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* ldsbu$pack @($GRi,$GRj),$GRk */ + { + FRV_INSN_LDSBU, "ldsbu", "ldsbu", 32, + { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* ldubu$pack @($GRi,$GRj),$GRk */ + { + FRV_INSN_LDUBU, "ldubu", "ldubu", 32, + { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* ldshu$pack @($GRi,$GRj),$GRk */ + { + FRV_INSN_LDSHU, "ldshu", "ldshu", 32, + { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* lduhu$pack @($GRi,$GRj),$GRk */ + { + FRV_INSN_LDUHU, "lduhu", "lduhu", 32, + { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* ldu$pack @($GRi,$GRj),$GRk */ + { + FRV_INSN_LDU, "ldu", "ldu", 32, + { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* nldsbu$pack @($GRi,$GRj),$GRk */ + { + FRV_INSN_NLDSBU, "nldsbu", "nldsbu", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nldubu$pack @($GRi,$GRj),$GRk */ + { + FRV_INSN_NLDUBU, "nldubu", "nldubu", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nldshu$pack @($GRi,$GRj),$GRk */ + { + FRV_INSN_NLDSHU, "nldshu", "nldshu", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nlduhu$pack @($GRi,$GRj),$GRk */ + { + FRV_INSN_NLDUHU, "nlduhu", "nlduhu", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nldu$pack @($GRi,$GRj),$GRk */ + { + FRV_INSN_NLDU, "nldu", "nldu", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* ldbfu$pack @($GRi,$GRj),$FRintk */ + { + FRV_INSN_LDBFU, "ldbfu", "ldbfu", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* ldhfu$pack @($GRi,$GRj),$FRintk */ + { + FRV_INSN_LDHFU, "ldhfu", "ldhfu", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* ldfu$pack @($GRi,$GRj),$FRintk */ + { + FRV_INSN_LDFU, "ldfu", "ldfu", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* ldcu$pack @($GRi,$GRj),$CPRk */ + { + FRV_INSN_LDCU, "ldcu", "ldcu", 32, + { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nldbfu$pack @($GRi,$GRj),$FRintk */ + { + FRV_INSN_NLDBFU, "nldbfu", "nldbfu", 32, + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nldhfu$pack @($GRi,$GRj),$FRintk */ + { + FRV_INSN_NLDHFU, "nldhfu", "nldhfu", 32, + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nldfu$pack @($GRi,$GRj),$FRintk */ + { + FRV_INSN_NLDFU, "nldfu", "nldfu", 32, + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* lddu$pack @($GRi,$GRj),$GRdoublek */ + { + FRV_INSN_LDDU, "lddu", "lddu", 32, + { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* nlddu$pack @($GRi,$GRj),$GRdoublek */ + { + FRV_INSN_NLDDU, "nlddu", "nlddu", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* lddfu$pack @($GRi,$GRj),$FRdoublek */ + { + FRV_INSN_LDDFU, "lddfu", "lddfu", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* lddcu$pack @($GRi,$GRj),$CPRdoublek */ + { + FRV_INSN_LDDCU, "lddcu", "lddcu", 32, + { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* nlddfu$pack @($GRi,$GRj),$FRdoublek */ + { + FRV_INSN_NLDDFU, "nlddfu", "nlddfu", 32, + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* ldqu$pack @($GRi,$GRj),$GRk */ + { + FRV_INSN_LDQU, "ldqu", "ldqu", 32, + { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nldqu$pack @($GRi,$GRj),$GRk */ + { + FRV_INSN_NLDQU, "nldqu", "nldqu", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* ldqfu$pack @($GRi,$GRj),$FRintk */ + { + FRV_INSN_LDQFU, "ldqfu", "ldqfu", 32, + { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* ldqcu$pack @($GRi,$GRj),$CPRk */ + { + FRV_INSN_LDQCU, "ldqcu", "ldqcu", 32, + { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nldqfu$pack @($GRi,$GRj),$FRintk */ + { + FRV_INSN_NLDQFU, "nldqfu", "nldqfu", 32, + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* ldsbi$pack @($GRi,$d12),$GRk */ + { + FRV_INSN_LDSBI, "ldsbi", "ldsbi", 32, + { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* ldshi$pack @($GRi,$d12),$GRk */ + { + FRV_INSN_LDSHI, "ldshi", "ldshi", 32, + { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* ldi$pack @($GRi,$d12),$GRk */ + { + FRV_INSN_LDI, "ldi", "ldi", 32, + { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* ldubi$pack @($GRi,$d12),$GRk */ + { + FRV_INSN_LDUBI, "ldubi", "ldubi", 32, + { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* lduhi$pack @($GRi,$d12),$GRk */ + { + FRV_INSN_LDUHI, "lduhi", "lduhi", 32, + { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* ldbfi$pack @($GRi,$d12),$FRintk */ + { + FRV_INSN_LDBFI, "ldbfi", "ldbfi", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* ldhfi$pack @($GRi,$d12),$FRintk */ + { + FRV_INSN_LDHFI, "ldhfi", "ldhfi", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* ldfi$pack @($GRi,$d12),$FRintk */ + { + FRV_INSN_LDFI, "ldfi", "ldfi", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* nldsbi$pack @($GRi,$d12),$GRk */ + { + FRV_INSN_NLDSBI, "nldsbi", "nldsbi", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nldubi$pack @($GRi,$d12),$GRk */ + { + FRV_INSN_NLDUBI, "nldubi", "nldubi", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nldshi$pack @($GRi,$d12),$GRk */ + { + FRV_INSN_NLDSHI, "nldshi", "nldshi", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nlduhi$pack @($GRi,$d12),$GRk */ + { + FRV_INSN_NLDUHI, "nlduhi", "nlduhi", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nldi$pack @($GRi,$d12),$GRk */ + { + FRV_INSN_NLDI, "nldi", "nldi", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nldbfi$pack @($GRi,$d12),$FRintk */ + { + FRV_INSN_NLDBFI, "nldbfi", "nldbfi", 32, + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nldhfi$pack @($GRi,$d12),$FRintk */ + { + FRV_INSN_NLDHFI, "nldhfi", "nldhfi", 32, + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nldfi$pack @($GRi,$d12),$FRintk */ + { + FRV_INSN_NLDFI, "nldfi", "nldfi", 32, + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* lddi$pack @($GRi,$d12),$GRdoublek */ + { + FRV_INSN_LDDI, "lddi", "lddi", 32, + { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* lddfi$pack @($GRi,$d12),$FRdoublek */ + { + FRV_INSN_LDDFI, "lddfi", "lddfi", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* nlddi$pack @($GRi,$d12),$GRdoublek */ + { + FRV_INSN_NLDDI, "nlddi", "nlddi", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nlddfi$pack @($GRi,$d12),$FRdoublek */ + { + FRV_INSN_NLDDFI, "nlddfi", "nlddfi", 32, + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* ldqi$pack @($GRi,$d12),$GRk */ + { + FRV_INSN_LDQI, "ldqi", "ldqi", 32, + { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* ldqfi$pack @($GRi,$d12),$FRintk */ + { + FRV_INSN_LDQFI, "ldqfi", "ldqfi", 32, + { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nldqi$pack @($GRi,$d12),$GRk */ + { + FRV_INSN_NLDQI, "nldqi", "nldqi", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* nldqfi$pack @($GRi,$d12),$FRintk */ + { + FRV_INSN_NLDQFI, "nldqfi", "nldqfi", 32, + { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* stb$pack $GRk,@($GRi,$GRj) */ + { + FRV_INSN_STB, "stb", "stb", 32, + { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* sth$pack $GRk,@($GRi,$GRj) */ + { + FRV_INSN_STH, "sth", "sth", 32, + { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* st$pack $GRk,@($GRi,$GRj) */ + { + FRV_INSN_ST, "st", "st", 32, + { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* stbf$pack $FRintk,@($GRi,$GRj) */ + { + FRV_INSN_STBF, "stbf", "stbf", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* sthf$pack $FRintk,@($GRi,$GRj) */ + { + FRV_INSN_STHF, "sthf", "sthf", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* stf$pack $FRintk,@($GRi,$GRj) */ + { + FRV_INSN_STF, "stf", "stf", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* stc$pack $CPRk,@($GRi,$GRj) */ + { + FRV_INSN_STC, "stc", "stc", 32, + { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* rstb$pack $GRk,@($GRi,$GRj) */ + { + FRV_INSN_RSTB, "rstb", "rstb", 32, + { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + }, +/* rsth$pack $GRk,@($GRi,$GRj) */ + { + FRV_INSN_RSTH, "rsth", "rsth", 32, + { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + }, +/* rst$pack $GRk,@($GRi,$GRj) */ + { + FRV_INSN_RST, "rst", "rst", 32, + { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + }, +/* rstbf$pack $FRintk,@($GRi,$GRj) */ + { + FRV_INSN_RSTBF, "rstbf", "rstbf", 32, + { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + }, +/* rsthf$pack $FRintk,@($GRi,$GRj) */ + { + FRV_INSN_RSTHF, "rsthf", "rsthf", 32, + { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + }, +/* rstf$pack $FRintk,@($GRi,$GRj) */ + { + FRV_INSN_RSTF, "rstf", "rstf", 32, + { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + }, +/* std$pack $GRk,@($GRi,$GRj) */ + { + FRV_INSN_STD, "std", "std", 32, + { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* stdf$pack $FRk,@($GRi,$GRj) */ + { + FRV_INSN_STDF, "stdf", "stdf", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* stdc$pack $CPRk,@($GRi,$GRj) */ + { + FRV_INSN_STDC, "stdc", "stdc", 32, + { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* rstd$pack $GRk,@($GRi,$GRj) */ + { + FRV_INSN_RSTD, "rstd", "rstd", 32, + { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + }, +/* rstdf$pack $FRk,@($GRi,$GRj) */ + { + FRV_INSN_RSTDF, "rstdf", "rstdf", 32, + { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + }, +/* stq$pack $GRk,@($GRi,$GRj) */ + { + FRV_INSN_STQ, "stq", "stq", 32, + { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + }, +/* stqf$pack $FRintk,@($GRi,$GRj) */ + { + FRV_INSN_STQF, "stqf", "stqf", 32, + { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + }, +/* stqc$pack $CPRk,@($GRi,$GRj) */ + { + FRV_INSN_STQC, "stqc", "stqc", 32, + { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + }, +/* rstq$pack $GRk,@($GRi,$GRj) */ + { + FRV_INSN_RSTQ, "rstq", "rstq", 32, + { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + }, +/* rstqf$pack $FRintk,@($GRi,$GRj) */ + { + FRV_INSN_RSTQF, "rstqf", "rstqf", 32, + { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + }, +/* stbu$pack $GRk,@($GRi,$GRj) */ + { + FRV_INSN_STBU, "stbu", "stbu", 32, + { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* sthu$pack $GRk,@($GRi,$GRj) */ + { + FRV_INSN_STHU, "sthu", "sthu", 32, + { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* stu$pack $GRk,@($GRi,$GRj) */ + { + FRV_INSN_STU, "stu", "stu", 32, + { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* stbfu$pack $FRintk,@($GRi,$GRj) */ + { + FRV_INSN_STBFU, "stbfu", "stbfu", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* sthfu$pack $FRintk,@($GRi,$GRj) */ + { + FRV_INSN_STHFU, "sthfu", "sthfu", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* stfu$pack $FRintk,@($GRi,$GRj) */ + { + FRV_INSN_STFU, "stfu", "stfu", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* stcu$pack $CPRk,@($GRi,$GRj) */ + { + FRV_INSN_STCU, "stcu", "stcu", 32, + { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* stdu$pack $GRk,@($GRi,$GRj) */ + { + FRV_INSN_STDU, "stdu", "stdu", 32, + { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* stdfu$pack $FRk,@($GRi,$GRj) */ + { + FRV_INSN_STDFU, "stdfu", "stdfu", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* stdcu$pack $CPRk,@($GRi,$GRj) */ + { + FRV_INSN_STDCU, "stdcu", "stdcu", 32, + { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* stqu$pack $GRk,@($GRi,$GRj) */ + { + FRV_INSN_STQU, "stqu", "stqu", 32, + { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + }, +/* stqfu$pack $FRintk,@($GRi,$GRj) */ + { + FRV_INSN_STQFU, "stqfu", "stqfu", 32, + { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + }, +/* stqcu$pack $CPRk,@($GRi,$GRj) */ + { + FRV_INSN_STQCU, "stqcu", "stqcu", 32, + { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + }, +/* cldsb$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + FRV_INSN_CLDSB, "cldsb", "cldsb", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* cldub$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + FRV_INSN_CLDUB, "cldub", "cldub", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* cldsh$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + FRV_INSN_CLDSH, "cldsh", "cldsh", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* clduh$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + FRV_INSN_CLDUH, "clduh", "clduh", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* cld$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + FRV_INSN_CLD, "cld", "cld", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* cldbf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + { + FRV_INSN_CLDBF, "cldbf", "cldbf", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* cldhf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + { + FRV_INSN_CLDHF, "cldhf", "cldhf", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* cldf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + { + FRV_INSN_CLDF, "cldf", "cldf", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* cldd$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */ + { + FRV_INSN_CLDD, "cldd", "cldd", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* clddf$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */ + { + FRV_INSN_CLDDF, "clddf", "clddf", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* cldq$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + FRV_INSN_CLDQ, "cldq", "cldq", 32, + { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* cldsbu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + FRV_INSN_CLDSBU, "cldsbu", "cldsbu", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* cldubu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + FRV_INSN_CLDUBU, "cldubu", "cldubu", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* cldshu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + FRV_INSN_CLDSHU, "cldshu", "cldshu", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* clduhu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + FRV_INSN_CLDUHU, "clduhu", "clduhu", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* cldu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + FRV_INSN_CLDU, "cldu", "cldu", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* cldbfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + { + FRV_INSN_CLDBFU, "cldbfu", "cldbfu", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* cldhfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + { + FRV_INSN_CLDHFU, "cldhfu", "cldhfu", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* cldfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + { + FRV_INSN_CLDFU, "cldfu", "cldfu", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* clddu$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */ + { + FRV_INSN_CLDDU, "clddu", "clddu", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* clddfu$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */ + { + FRV_INSN_CLDDFU, "clddfu", "clddfu", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2 } } + }, +/* cldqu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + FRV_INSN_CLDQU, "cldqu", "cldqu", 32, + { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2 } } + }, +/* cstb$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + FRV_INSN_CSTB, "cstb", "cstb", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* csth$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + FRV_INSN_CSTH, "csth", "csth", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* cst$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + FRV_INSN_CST, "cst", "cst", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* cstbf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + { + FRV_INSN_CSTBF, "cstbf", "cstbf", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* csthf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + { + FRV_INSN_CSTHF, "csthf", "csthf", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* cstf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + { + FRV_INSN_CSTF, "cstf", "cstf", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* cstd$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + FRV_INSN_CSTD, "cstd", "cstd", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* cstdf$pack $FRk,@($GRi,$GRj),$CCi,$cond */ + { + FRV_INSN_CSTDF, "cstdf", "cstdf", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* cstq$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + FRV_INSN_CSTQ, "cstq", "cstq", 32, + { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + }, +/* cstbu$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + FRV_INSN_CSTBU, "cstbu", "cstbu", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* csthu$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + FRV_INSN_CSTHU, "csthu", "csthu", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* cstu$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + FRV_INSN_CSTU, "cstu", "cstu", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* cstbfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + { + FRV_INSN_CSTBFU, "cstbfu", "cstbfu", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* csthfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + { + FRV_INSN_CSTHFU, "csthfu", "csthfu", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* cstfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + { + FRV_INSN_CSTFU, "cstfu", "cstfu", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* cstdu$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + FRV_INSN_CSTDU, "cstdu", "cstdu", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* cstdfu$pack $FRk,@($GRi,$GRj),$CCi,$cond */ + { + FRV_INSN_CSTDFU, "cstdfu", "cstdfu", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* stbi$pack $GRk,@($GRi,$d12) */ + { + FRV_INSN_STBI, "stbi", "stbi", 32, + { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* sthi$pack $GRk,@($GRi,$d12) */ + { + FRV_INSN_STHI, "sthi", "sthi", 32, + { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* sti$pack $GRk,@($GRi,$d12) */ + { + FRV_INSN_STI, "sti", "sti", 32, + { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* stbfi$pack $FRintk,@($GRi,$d12) */ + { + FRV_INSN_STBFI, "stbfi", "stbfi", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* sthfi$pack $FRintk,@($GRi,$d12) */ + { + FRV_INSN_STHFI, "sthfi", "sthfi", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* stfi$pack $FRintk,@($GRi,$d12) */ + { + FRV_INSN_STFI, "stfi", "stfi", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* stdi$pack $GRk,@($GRi,$d12) */ + { + FRV_INSN_STDI, "stdi", "stdi", 32, + { 0, { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* stdfi$pack $FRk,@($GRi,$d12) */ + { + FRV_INSN_STDFI, "stdfi", "stdfi", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_3, FR500_MAJOR_I_3 } } + }, +/* stqi$pack $GRk,@($GRi,$d12) */ + { + FRV_INSN_STQI, "stqi", "stqi", 32, + { 0, { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + }, +/* stqfi$pack $FRintk,@($GRi,$d12) */ + { + FRV_INSN_STQFI, "stqfi", "stqfi", 32, + { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_3 } } + }, +/* swap$pack @($GRi,$GRj),$GRk */ + { + FRV_INSN_SWAP, "swap", "swap", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } } + }, +/* swapi$pack @($GRi,$d12),$GRk */ + { + FRV_INSN_SWAPI, "swapi", "swapi", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } } + }, +/* cswap$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + FRV_INSN_CSWAP, "cswap", "cswap", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } } + }, +/* movgf$pack $GRj,$FRintk */ + { + FRV_INSN_MOVGF, "movgf", "movgf", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } } + }, +/* movfg$pack $FRintk,$GRj */ + { + FRV_INSN_MOVFG, "movfg", "movfg", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } } + }, +/* movgfd$pack $GRj,$FRintk */ + { + FRV_INSN_MOVGFD, "movgfd", "movgfd", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } } + }, +/* movfgd$pack $FRintk,$GRj */ + { + FRV_INSN_MOVFGD, "movfgd", "movfgd", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } } + }, +/* movgfq$pack $GRj,$FRintk */ + { + FRV_INSN_MOVGFQ, "movgfq", "movgfq", 32, + { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_4 } } + }, +/* movfgq$pack $FRintk,$GRj */ + { + FRV_INSN_MOVFGQ, "movfgq", "movfgq", 32, + { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_4 } } + }, +/* cmovgf$pack $GRj,$FRintk,$CCi,$cond */ + { + FRV_INSN_CMOVGF, "cmovgf", "cmovgf", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } } + }, +/* cmovfg$pack $FRintk,$GRj,$CCi,$cond */ + { + FRV_INSN_CMOVFG, "cmovfg", "cmovfg", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } } + }, +/* cmovgfd$pack $GRj,$FRintk,$CCi,$cond */ + { + FRV_INSN_CMOVGFD, "cmovgfd", "cmovgfd", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } } + }, +/* cmovfgd$pack $FRintk,$GRj,$CCi,$cond */ + { + FRV_INSN_CMOVFGD, "cmovfgd", "cmovfgd", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4 } } + }, +/* movgs$pack $GRj,$spr */ + { + FRV_INSN_MOVGS, "movgs", "movgs", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } } + }, +/* movsg$pack $spr,$GRj */ + { + FRV_INSN_MOVSG, "movsg", "movsg", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } } + }, +/* bra$pack $hint_taken$label16 */ + { + FRV_INSN_BRA, "bra", "bra", 32, + { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* bno$pack$hint_not_taken */ + { + FRV_INSN_BNO, "bno", "bno", 32, + { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* beq$pack $ICCi_2,$hint,$label16 */ + { + FRV_INSN_BEQ, "beq", "beq", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* bne$pack $ICCi_2,$hint,$label16 */ + { + FRV_INSN_BNE, "bne", "bne", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* ble$pack $ICCi_2,$hint,$label16 */ + { + FRV_INSN_BLE, "ble", "ble", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* bgt$pack $ICCi_2,$hint,$label16 */ + { + FRV_INSN_BGT, "bgt", "bgt", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* blt$pack $ICCi_2,$hint,$label16 */ + { + FRV_INSN_BLT, "blt", "blt", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* bge$pack $ICCi_2,$hint,$label16 */ + { + FRV_INSN_BGE, "bge", "bge", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* bls$pack $ICCi_2,$hint,$label16 */ + { + FRV_INSN_BLS, "bls", "bls", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* bhi$pack $ICCi_2,$hint,$label16 */ + { + FRV_INSN_BHI, "bhi", "bhi", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* bc$pack $ICCi_2,$hint,$label16 */ + { + FRV_INSN_BC, "bc", "bc", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* bnc$pack $ICCi_2,$hint,$label16 */ + { + FRV_INSN_BNC, "bnc", "bnc", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* bn$pack $ICCi_2,$hint,$label16 */ + { + FRV_INSN_BN, "bn", "bn", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* bp$pack $ICCi_2,$hint,$label16 */ + { + FRV_INSN_BP, "bp", "bp", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* bv$pack $ICCi_2,$hint,$label16 */ + { + FRV_INSN_BV, "bv", "bv", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* bnv$pack $ICCi_2,$hint,$label16 */ + { + FRV_INSN_BNV, "bnv", "bnv", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* fbra$pack $hint_taken$label16 */ + { + FRV_INSN_FBRA, "fbra", "fbra", 32, + { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* fbno$pack$hint_not_taken */ + { + FRV_INSN_FBNO, "fbno", "fbno", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* fbne$pack $FCCi_2,$hint,$label16 */ + { + FRV_INSN_FBNE, "fbne", "fbne", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* fbeq$pack $FCCi_2,$hint,$label16 */ + { + FRV_INSN_FBEQ, "fbeq", "fbeq", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* fblg$pack $FCCi_2,$hint,$label16 */ + { + FRV_INSN_FBLG, "fblg", "fblg", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* fbue$pack $FCCi_2,$hint,$label16 */ + { + FRV_INSN_FBUE, "fbue", "fbue", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* fbul$pack $FCCi_2,$hint,$label16 */ + { + FRV_INSN_FBUL, "fbul", "fbul", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* fbge$pack $FCCi_2,$hint,$label16 */ + { + FRV_INSN_FBGE, "fbge", "fbge", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* fblt$pack $FCCi_2,$hint,$label16 */ + { + FRV_INSN_FBLT, "fblt", "fblt", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* fbuge$pack $FCCi_2,$hint,$label16 */ + { + FRV_INSN_FBUGE, "fbuge", "fbuge", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* fbug$pack $FCCi_2,$hint,$label16 */ + { + FRV_INSN_FBUG, "fbug", "fbug", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* fble$pack $FCCi_2,$hint,$label16 */ + { + FRV_INSN_FBLE, "fble", "fble", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* fbgt$pack $FCCi_2,$hint,$label16 */ + { + FRV_INSN_FBGT, "fbgt", "fbgt", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* fbule$pack $FCCi_2,$hint,$label16 */ + { + FRV_INSN_FBULE, "fbule", "fbule", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* fbu$pack $FCCi_2,$hint,$label16 */ + { + FRV_INSN_FBU, "fbu", "fbu", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* fbo$pack $FCCi_2,$hint,$label16 */ + { + FRV_INSN_FBO, "fbo", "fbo", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1 } } + }, +/* bctrlr$pack $ccond,$hint */ + { + FRV_INSN_BCTRLR, "bctrlr", "bctrlr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* bralr$pack$hint_taken */ + { + FRV_INSN_BRALR, "bralr", "bralr", 32, + { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* bnolr$pack$hint_not_taken */ + { + FRV_INSN_BNOLR, "bnolr", "bnolr", 32, + { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* beqlr$pack $ICCi_2,$hint */ + { + FRV_INSN_BEQLR, "beqlr", "beqlr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* bnelr$pack $ICCi_2,$hint */ + { + FRV_INSN_BNELR, "bnelr", "bnelr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* blelr$pack $ICCi_2,$hint */ + { + FRV_INSN_BLELR, "blelr", "blelr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* bgtlr$pack $ICCi_2,$hint */ + { + FRV_INSN_BGTLR, "bgtlr", "bgtlr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* bltlr$pack $ICCi_2,$hint */ + { + FRV_INSN_BLTLR, "bltlr", "bltlr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* bgelr$pack $ICCi_2,$hint */ + { + FRV_INSN_BGELR, "bgelr", "bgelr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* blslr$pack $ICCi_2,$hint */ + { + FRV_INSN_BLSLR, "blslr", "blslr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* bhilr$pack $ICCi_2,$hint */ + { + FRV_INSN_BHILR, "bhilr", "bhilr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* bclr$pack $ICCi_2,$hint */ + { + FRV_INSN_BCLR, "bclr", "bclr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* bnclr$pack $ICCi_2,$hint */ + { + FRV_INSN_BNCLR, "bnclr", "bnclr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* bnlr$pack $ICCi_2,$hint */ + { + FRV_INSN_BNLR, "bnlr", "bnlr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* bplr$pack $ICCi_2,$hint */ + { + FRV_INSN_BPLR, "bplr", "bplr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* bvlr$pack $ICCi_2,$hint */ + { + FRV_INSN_BVLR, "bvlr", "bvlr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* bnvlr$pack $ICCi_2,$hint */ + { + FRV_INSN_BNVLR, "bnvlr", "bnvlr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* fbralr$pack$hint_taken */ + { + FRV_INSN_FBRALR, "fbralr", "fbralr", 32, + { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* fbnolr$pack$hint_not_taken */ + { + FRV_INSN_FBNOLR, "fbnolr", "fbnolr", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* fbeqlr$pack $FCCi_2,$hint */ + { + FRV_INSN_FBEQLR, "fbeqlr", "fbeqlr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* fbnelr$pack $FCCi_2,$hint */ + { + FRV_INSN_FBNELR, "fbnelr", "fbnelr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* fblglr$pack $FCCi_2,$hint */ + { + FRV_INSN_FBLGLR, "fblglr", "fblglr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* fbuelr$pack $FCCi_2,$hint */ + { + FRV_INSN_FBUELR, "fbuelr", "fbuelr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* fbullr$pack $FCCi_2,$hint */ + { + FRV_INSN_FBULLR, "fbullr", "fbullr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* fbgelr$pack $FCCi_2,$hint */ + { + FRV_INSN_FBGELR, "fbgelr", "fbgelr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* fbltlr$pack $FCCi_2,$hint */ + { + FRV_INSN_FBLTLR, "fbltlr", "fbltlr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* fbugelr$pack $FCCi_2,$hint */ + { + FRV_INSN_FBUGELR, "fbugelr", "fbugelr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* fbuglr$pack $FCCi_2,$hint */ + { + FRV_INSN_FBUGLR, "fbuglr", "fbuglr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* fblelr$pack $FCCi_2,$hint */ + { + FRV_INSN_FBLELR, "fblelr", "fblelr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* fbgtlr$pack $FCCi_2,$hint */ + { + FRV_INSN_FBGTLR, "fbgtlr", "fbgtlr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* fbulelr$pack $FCCi_2,$hint */ + { + FRV_INSN_FBULELR, "fbulelr", "fbulelr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* fbulr$pack $FCCi_2,$hint */ + { + FRV_INSN_FBULR, "fbulr", "fbulr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* fbolr$pack $FCCi_2,$hint */ + { + FRV_INSN_FBOLR, "fbolr", "fbolr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* bcralr$pack $ccond$hint_taken */ + { + FRV_INSN_BCRALR, "bcralr", "bcralr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* bcnolr$pack$hint_not_taken */ + { + FRV_INSN_BCNOLR, "bcnolr", "bcnolr", 32, + { 0, { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* bceqlr$pack $ICCi_2,$ccond,$hint */ + { + FRV_INSN_BCEQLR, "bceqlr", "bceqlr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* bcnelr$pack $ICCi_2,$ccond,$hint */ + { + FRV_INSN_BCNELR, "bcnelr", "bcnelr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* bclelr$pack $ICCi_2,$ccond,$hint */ + { + FRV_INSN_BCLELR, "bclelr", "bclelr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* bcgtlr$pack $ICCi_2,$ccond,$hint */ + { + FRV_INSN_BCGTLR, "bcgtlr", "bcgtlr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* bcltlr$pack $ICCi_2,$ccond,$hint */ + { + FRV_INSN_BCLTLR, "bcltlr", "bcltlr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* bcgelr$pack $ICCi_2,$ccond,$hint */ + { + FRV_INSN_BCGELR, "bcgelr", "bcgelr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* bclslr$pack $ICCi_2,$ccond,$hint */ + { + FRV_INSN_BCLSLR, "bclslr", "bclslr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* bchilr$pack $ICCi_2,$ccond,$hint */ + { + FRV_INSN_BCHILR, "bchilr", "bchilr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* bcclr$pack $ICCi_2,$ccond,$hint */ + { + FRV_INSN_BCCLR, "bcclr", "bcclr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* bcnclr$pack $ICCi_2,$ccond,$hint */ + { + FRV_INSN_BCNCLR, "bcnclr", "bcnclr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* bcnlr$pack $ICCi_2,$ccond,$hint */ + { + FRV_INSN_BCNLR, "bcnlr", "bcnlr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* bcplr$pack $ICCi_2,$ccond,$hint */ + { + FRV_INSN_BCPLR, "bcplr", "bcplr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* bcvlr$pack $ICCi_2,$ccond,$hint */ + { + FRV_INSN_BCVLR, "bcvlr", "bcvlr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* bcnvlr$pack $ICCi_2,$ccond,$hint */ + { + FRV_INSN_BCNVLR, "bcnvlr", "bcnvlr", 32, + { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* fcbralr$pack $ccond$hint_taken */ + { + FRV_INSN_FCBRALR, "fcbralr", "fcbralr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* fcbnolr$pack$hint_not_taken */ + { + FRV_INSN_FCBNOLR, "fcbnolr", "fcbnolr", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* fcbeqlr$pack $FCCi_2,$ccond,$hint */ + { + FRV_INSN_FCBEQLR, "fcbeqlr", "fcbeqlr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* fcbnelr$pack $FCCi_2,$ccond,$hint */ + { + FRV_INSN_FCBNELR, "fcbnelr", "fcbnelr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* fcblglr$pack $FCCi_2,$ccond,$hint */ + { + FRV_INSN_FCBLGLR, "fcblglr", "fcblglr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* fcbuelr$pack $FCCi_2,$ccond,$hint */ + { + FRV_INSN_FCBUELR, "fcbuelr", "fcbuelr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* fcbullr$pack $FCCi_2,$ccond,$hint */ + { + FRV_INSN_FCBULLR, "fcbullr", "fcbullr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* fcbgelr$pack $FCCi_2,$ccond,$hint */ + { + FRV_INSN_FCBGELR, "fcbgelr", "fcbgelr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* fcbltlr$pack $FCCi_2,$ccond,$hint */ + { + FRV_INSN_FCBLTLR, "fcbltlr", "fcbltlr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* fcbugelr$pack $FCCi_2,$ccond,$hint */ + { + FRV_INSN_FCBUGELR, "fcbugelr", "fcbugelr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* fcbuglr$pack $FCCi_2,$ccond,$hint */ + { + FRV_INSN_FCBUGLR, "fcbuglr", "fcbuglr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* fcblelr$pack $FCCi_2,$ccond,$hint */ + { + FRV_INSN_FCBLELR, "fcblelr", "fcblelr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* fcbgtlr$pack $FCCi_2,$ccond,$hint */ + { + FRV_INSN_FCBGTLR, "fcbgtlr", "fcbgtlr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* fcbulelr$pack $FCCi_2,$ccond,$hint */ + { + FRV_INSN_FCBULELR, "fcbulelr", "fcbulelr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* fcbulr$pack $FCCi_2,$ccond,$hint */ + { + FRV_INSN_FCBULR, "fcbulr", "fcbulr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* fcbolr$pack $FCCi_2,$ccond,$hint */ + { + FRV_INSN_FCBOLR, "fcbolr", "fcbolr", 32, + { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2 } } + }, +/* jmpl$pack @($GRi,$GRj) */ + { + FRV_INSN_JMPL, "jmpl", "jmpl", 32, + { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } } + }, +/* calll$pack @($GRi,$GRj) */ + { + FRV_INSN_CALLL, "calll", "calll", 32, + { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } } + }, +/* jmpil$pack @($GRi,$s12) */ + { + FRV_INSN_JMPIL, "jmpil", "jmpil", 32, + { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } } + }, +/* callil$pack @($GRi,$s12) */ + { + FRV_INSN_CALLIL, "callil", "callil", 32, + { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } } + }, +/* call$pack $label24 */ + { + FRV_INSN_CALL, "call", "call", 32, + { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_4, FR500_MAJOR_B_4 } } + }, +/* rett$pack $debug */ + { + FRV_INSN_RETT, "rett", "rett", 32, + { 0|A(PRIVILEGED)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } } + }, +/* rei$pack $eir */ + { + FRV_INSN_REI, "rei", "rei", 32, + { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_1 } } + }, +/* tra$pack $GRi,$GRj */ + { + FRV_INSN_TRA, "tra", "tra", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tno$pack */ + { + FRV_INSN_TNO, "tno", "tno", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* teq$pack $ICCi_2,$GRi,$GRj */ + { + FRV_INSN_TEQ, "teq", "teq", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tne$pack $ICCi_2,$GRi,$GRj */ + { + FRV_INSN_TNE, "tne", "tne", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tle$pack $ICCi_2,$GRi,$GRj */ + { + FRV_INSN_TLE, "tle", "tle", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tgt$pack $ICCi_2,$GRi,$GRj */ + { + FRV_INSN_TGT, "tgt", "tgt", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tlt$pack $ICCi_2,$GRi,$GRj */ + { + FRV_INSN_TLT, "tlt", "tlt", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tge$pack $ICCi_2,$GRi,$GRj */ + { + FRV_INSN_TGE, "tge", "tge", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tls$pack $ICCi_2,$GRi,$GRj */ + { + FRV_INSN_TLS, "tls", "tls", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* thi$pack $ICCi_2,$GRi,$GRj */ + { + FRV_INSN_THI, "thi", "thi", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tc$pack $ICCi_2,$GRi,$GRj */ + { + FRV_INSN_TC, "tc", "tc", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tnc$pack $ICCi_2,$GRi,$GRj */ + { + FRV_INSN_TNC, "tnc", "tnc", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tn$pack $ICCi_2,$GRi,$GRj */ + { + FRV_INSN_TN, "tn", "tn", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tp$pack $ICCi_2,$GRi,$GRj */ + { + FRV_INSN_TP, "tp", "tp", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tv$pack $ICCi_2,$GRi,$GRj */ + { + FRV_INSN_TV, "tv", "tv", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tnv$pack $ICCi_2,$GRi,$GRj */ + { + FRV_INSN_TNV, "tnv", "tnv", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftra$pack $GRi,$GRj */ + { + FRV_INSN_FTRA, "ftra", "ftra", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftno$pack */ + { + FRV_INSN_FTNO, "ftno", "ftno", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftne$pack $FCCi_2,$GRi,$GRj */ + { + FRV_INSN_FTNE, "ftne", "ftne", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* fteq$pack $FCCi_2,$GRi,$GRj */ + { + FRV_INSN_FTEQ, "fteq", "fteq", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftlg$pack $FCCi_2,$GRi,$GRj */ + { + FRV_INSN_FTLG, "ftlg", "ftlg", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftue$pack $FCCi_2,$GRi,$GRj */ + { + FRV_INSN_FTUE, "ftue", "ftue", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftul$pack $FCCi_2,$GRi,$GRj */ + { + FRV_INSN_FTUL, "ftul", "ftul", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftge$pack $FCCi_2,$GRi,$GRj */ + { + FRV_INSN_FTGE, "ftge", "ftge", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftlt$pack $FCCi_2,$GRi,$GRj */ + { + FRV_INSN_FTLT, "ftlt", "ftlt", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftuge$pack $FCCi_2,$GRi,$GRj */ + { + FRV_INSN_FTUGE, "ftuge", "ftuge", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftug$pack $FCCi_2,$GRi,$GRj */ + { + FRV_INSN_FTUG, "ftug", "ftug", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftle$pack $FCCi_2,$GRi,$GRj */ + { + FRV_INSN_FTLE, "ftle", "ftle", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftgt$pack $FCCi_2,$GRi,$GRj */ + { + FRV_INSN_FTGT, "ftgt", "ftgt", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftule$pack $FCCi_2,$GRi,$GRj */ + { + FRV_INSN_FTULE, "ftule", "ftule", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftu$pack $FCCi_2,$GRi,$GRj */ + { + FRV_INSN_FTU, "ftu", "ftu", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* fto$pack $FCCi_2,$GRi,$GRj */ + { + FRV_INSN_FTO, "fto", "fto", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tira$pack $GRi,$s12 */ + { + FRV_INSN_TIRA, "tira", "tira", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tino$pack */ + { + FRV_INSN_TINO, "tino", "tino", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tieq$pack $ICCi_2,$GRi,$s12 */ + { + FRV_INSN_TIEQ, "tieq", "tieq", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tine$pack $ICCi_2,$GRi,$s12 */ + { + FRV_INSN_TINE, "tine", "tine", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tile$pack $ICCi_2,$GRi,$s12 */ + { + FRV_INSN_TILE, "tile", "tile", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tigt$pack $ICCi_2,$GRi,$s12 */ + { + FRV_INSN_TIGT, "tigt", "tigt", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tilt$pack $ICCi_2,$GRi,$s12 */ + { + FRV_INSN_TILT, "tilt", "tilt", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tige$pack $ICCi_2,$GRi,$s12 */ + { + FRV_INSN_TIGE, "tige", "tige", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tils$pack $ICCi_2,$GRi,$s12 */ + { + FRV_INSN_TILS, "tils", "tils", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tihi$pack $ICCi_2,$GRi,$s12 */ + { + FRV_INSN_TIHI, "tihi", "tihi", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tic$pack $ICCi_2,$GRi,$s12 */ + { + FRV_INSN_TIC, "tic", "tic", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tinc$pack $ICCi_2,$GRi,$s12 */ + { + FRV_INSN_TINC, "tinc", "tinc", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tin$pack $ICCi_2,$GRi,$s12 */ + { + FRV_INSN_TIN, "tin", "tin", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tip$pack $ICCi_2,$GRi,$s12 */ + { + FRV_INSN_TIP, "tip", "tip", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tiv$pack $ICCi_2,$GRi,$s12 */ + { + FRV_INSN_TIV, "tiv", "tiv", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* tinv$pack $ICCi_2,$GRi,$s12 */ + { + FRV_INSN_TINV, "tinv", "tinv", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftira$pack $GRi,$s12 */ + { + FRV_INSN_FTIRA, "ftira", "ftira", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftino$pack */ + { + FRV_INSN_FTINO, "ftino", "ftino", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftine$pack $FCCi_2,$GRi,$s12 */ + { + FRV_INSN_FTINE, "ftine", "ftine", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftieq$pack $FCCi_2,$GRi,$s12 */ + { + FRV_INSN_FTIEQ, "ftieq", "ftieq", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftilg$pack $FCCi_2,$GRi,$s12 */ + { + FRV_INSN_FTILG, "ftilg", "ftilg", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftiue$pack $FCCi_2,$GRi,$s12 */ + { + FRV_INSN_FTIUE, "ftiue", "ftiue", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftiul$pack $FCCi_2,$GRi,$s12 */ + { + FRV_INSN_FTIUL, "ftiul", "ftiul", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftige$pack $FCCi_2,$GRi,$s12 */ + { + FRV_INSN_FTIGE, "ftige", "ftige", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftilt$pack $FCCi_2,$GRi,$s12 */ + { + FRV_INSN_FTILT, "ftilt", "ftilt", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftiuge$pack $FCCi_2,$GRi,$s12 */ + { + FRV_INSN_FTIUGE, "ftiuge", "ftiuge", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftiug$pack $FCCi_2,$GRi,$s12 */ + { + FRV_INSN_FTIUG, "ftiug", "ftiug", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftile$pack $FCCi_2,$GRi,$s12 */ + { + FRV_INSN_FTILE, "ftile", "ftile", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftigt$pack $FCCi_2,$GRi,$s12 */ + { + FRV_INSN_FTIGT, "ftigt", "ftigt", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftiule$pack $FCCi_2,$GRi,$s12 */ + { + FRV_INSN_FTIULE, "ftiule", "ftiule", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftiu$pack $FCCi_2,$GRi,$s12 */ + { + FRV_INSN_FTIU, "ftiu", "ftiu", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* ftio$pack $FCCi_2,$GRi,$s12 */ + { + FRV_INSN_FTIO, "ftio", "ftio", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* break$pack */ + { + FRV_INSN_BREAK, "break", "break", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* mtrap$pack */ + { + FRV_INSN_MTRAP, "mtrap", "mtrap", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1 } } + }, +/* andcr$pack $CRi,$CRj,$CRk */ + { + FRV_INSN_ANDCR, "andcr", "andcr", 32, + { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } } + }, +/* orcr$pack $CRi,$CRj,$CRk */ + { + FRV_INSN_ORCR, "orcr", "orcr", 32, + { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } } + }, +/* xorcr$pack $CRi,$CRj,$CRk */ + { + FRV_INSN_XORCR, "xorcr", "xorcr", 32, + { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } } + }, +/* nandcr$pack $CRi,$CRj,$CRk */ + { + FRV_INSN_NANDCR, "nandcr", "nandcr", 32, + { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } } + }, +/* norcr$pack $CRi,$CRj,$CRk */ + { + FRV_INSN_NORCR, "norcr", "norcr", 32, + { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } } + }, +/* andncr$pack $CRi,$CRj,$CRk */ + { + FRV_INSN_ANDNCR, "andncr", "andncr", 32, + { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } } + }, +/* orncr$pack $CRi,$CRj,$CRk */ + { + FRV_INSN_ORNCR, "orncr", "orncr", 32, + { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } } + }, +/* nandncr$pack $CRi,$CRj,$CRk */ + { + FRV_INSN_NANDNCR, "nandncr", "nandncr", 32, + { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } } + }, +/* norncr$pack $CRi,$CRj,$CRk */ + { + FRV_INSN_NORNCR, "norncr", "norncr", 32, + { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } } + }, +/* notcr$pack $CRj,$CRk */ + { + FRV_INSN_NOTCR, "notcr", "notcr", 32, + { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6 } } + }, +/* ckra$pack $CRj_int */ + { + FRV_INSN_CKRA, "ckra", "ckra", 32, + { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* ckno$pack $CRj_int */ + { + FRV_INSN_CKNO, "ckno", "ckno", 32, + { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* ckeq$pack $ICCi_3,$CRj_int */ + { + FRV_INSN_CKEQ, "ckeq", "ckeq", 32, + { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* ckne$pack $ICCi_3,$CRj_int */ + { + FRV_INSN_CKNE, "ckne", "ckne", 32, + { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* ckle$pack $ICCi_3,$CRj_int */ + { + FRV_INSN_CKLE, "ckle", "ckle", 32, + { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* ckgt$pack $ICCi_3,$CRj_int */ + { + FRV_INSN_CKGT, "ckgt", "ckgt", 32, + { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cklt$pack $ICCi_3,$CRj_int */ + { + FRV_INSN_CKLT, "cklt", "cklt", 32, + { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* ckge$pack $ICCi_3,$CRj_int */ + { + FRV_INSN_CKGE, "ckge", "ckge", 32, + { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* ckls$pack $ICCi_3,$CRj_int */ + { + FRV_INSN_CKLS, "ckls", "ckls", 32, + { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* ckhi$pack $ICCi_3,$CRj_int */ + { + FRV_INSN_CKHI, "ckhi", "ckhi", 32, + { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* ckc$pack $ICCi_3,$CRj_int */ + { + FRV_INSN_CKC, "ckc", "ckc", 32, + { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cknc$pack $ICCi_3,$CRj_int */ + { + FRV_INSN_CKNC, "cknc", "cknc", 32, + { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* ckn$pack $ICCi_3,$CRj_int */ + { + FRV_INSN_CKN, "ckn", "ckn", 32, + { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* ckp$pack $ICCi_3,$CRj_int */ + { + FRV_INSN_CKP, "ckp", "ckp", 32, + { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* ckv$pack $ICCi_3,$CRj_int */ + { + FRV_INSN_CKV, "ckv", "ckv", 32, + { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cknv$pack $ICCi_3,$CRj_int */ + { + FRV_INSN_CKNV, "cknv", "cknv", 32, + { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* fckra$pack $CRj_float */ + { + FRV_INSN_FCKRA, "fckra", "fckra", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* fckno$pack $CRj_float */ + { + FRV_INSN_FCKNO, "fckno", "fckno", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* fckne$pack $FCCi_3,$CRj_float */ + { + FRV_INSN_FCKNE, "fckne", "fckne", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* fckeq$pack $FCCi_3,$CRj_float */ + { + FRV_INSN_FCKEQ, "fckeq", "fckeq", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* fcklg$pack $FCCi_3,$CRj_float */ + { + FRV_INSN_FCKLG, "fcklg", "fcklg", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* fckue$pack $FCCi_3,$CRj_float */ + { + FRV_INSN_FCKUE, "fckue", "fckue", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* fckul$pack $FCCi_3,$CRj_float */ + { + FRV_INSN_FCKUL, "fckul", "fckul", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* fckge$pack $FCCi_3,$CRj_float */ + { + FRV_INSN_FCKGE, "fckge", "fckge", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* fcklt$pack $FCCi_3,$CRj_float */ + { + FRV_INSN_FCKLT, "fcklt", "fcklt", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* fckuge$pack $FCCi_3,$CRj_float */ + { + FRV_INSN_FCKUGE, "fckuge", "fckuge", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* fckug$pack $FCCi_3,$CRj_float */ + { + FRV_INSN_FCKUG, "fckug", "fckug", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* fckle$pack $FCCi_3,$CRj_float */ + { + FRV_INSN_FCKLE, "fckle", "fckle", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* fckgt$pack $FCCi_3,$CRj_float */ + { + FRV_INSN_FCKGT, "fckgt", "fckgt", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* fckule$pack $FCCi_3,$CRj_float */ + { + FRV_INSN_FCKULE, "fckule", "fckule", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* fcku$pack $FCCi_3,$CRj_float */ + { + FRV_INSN_FCKU, "fcku", "fcku", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* fcko$pack $FCCi_3,$CRj_float */ + { + FRV_INSN_FCKO, "fcko", "fcko", 32, + { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cckra$pack $CRj_int,$CCi,$cond */ + { + FRV_INSN_CCKRA, "cckra", "cckra", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cckno$pack $CRj_int,$CCi,$cond */ + { + FRV_INSN_CCKNO, "cckno", "cckno", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cckeq$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + FRV_INSN_CCKEQ, "cckeq", "cckeq", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cckne$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + FRV_INSN_CCKNE, "cckne", "cckne", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cckle$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + FRV_INSN_CCKLE, "cckle", "cckle", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cckgt$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + FRV_INSN_CCKGT, "cckgt", "cckgt", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* ccklt$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + FRV_INSN_CCKLT, "ccklt", "ccklt", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cckge$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + FRV_INSN_CCKGE, "cckge", "cckge", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cckls$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + FRV_INSN_CCKLS, "cckls", "cckls", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cckhi$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + FRV_INSN_CCKHI, "cckhi", "cckhi", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cckc$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + FRV_INSN_CCKC, "cckc", "cckc", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* ccknc$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + FRV_INSN_CCKNC, "ccknc", "ccknc", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cckn$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + FRV_INSN_CCKN, "cckn", "cckn", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cckp$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + FRV_INSN_CCKP, "cckp", "cckp", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cckv$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + FRV_INSN_CCKV, "cckv", "cckv", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* ccknv$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + FRV_INSN_CCKNV, "ccknv", "ccknv", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cfckra$pack $CRj_float,$CCi,$cond */ + { + FRV_INSN_CFCKRA, "cfckra", "cfckra", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cfckno$pack $CRj_float,$CCi,$cond */ + { + FRV_INSN_CFCKNO, "cfckno", "cfckno", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cfckne$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + FRV_INSN_CFCKNE, "cfckne", "cfckne", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cfckeq$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + FRV_INSN_CFCKEQ, "cfckeq", "cfckeq", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cfcklg$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + FRV_INSN_CFCKLG, "cfcklg", "cfcklg", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cfckue$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + FRV_INSN_CFCKUE, "cfckue", "cfckue", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cfckul$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + FRV_INSN_CFCKUL, "cfckul", "cfckul", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cfckge$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + FRV_INSN_CFCKGE, "cfckge", "cfckge", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cfcklt$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + FRV_INSN_CFCKLT, "cfcklt", "cfcklt", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cfckuge$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + FRV_INSN_CFCKUGE, "cfckuge", "cfckuge", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cfckug$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + FRV_INSN_CFCKUG, "cfckug", "cfckug", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cfckle$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + FRV_INSN_CFCKLE, "cfckle", "cfckle", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cfckgt$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + FRV_INSN_CFCKGT, "cfckgt", "cfckgt", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cfckule$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + FRV_INSN_CFCKULE, "cfckule", "cfckule", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cfcku$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + FRV_INSN_CFCKU, "cfcku", "cfcku", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cfcko$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + FRV_INSN_CFCKO, "cfcko", "cfcko", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5 } } + }, +/* cjmpl$pack @($GRi,$GRj),$CCi,$cond */ + { + FRV_INSN_CJMPL, "cjmpl", "cjmpl", 32, + { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } } + }, +/* ccalll$pack @($GRi,$GRj),$CCi,$cond */ + { + FRV_INSN_CCALLL, "ccalll", "ccalll", 32, + { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5 } } + }, +/* ici$pack @($GRi,$GRj) */ + { + FRV_INSN_ICI, "ici", "ici", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } } + }, +/* dci$pack @($GRi,$GRj) */ + { + FRV_INSN_DCI, "dci", "dci", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } } + }, +/* icei$pack @($GRi,$GRj),$ae */ + { + FRV_INSN_ICEI, "icei", "icei", 32, + { 0, { (1<<MACH_FR400), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE } } + }, +/* dcei$pack @($GRi,$GRj),$ae */ + { + FRV_INSN_DCEI, "dcei", "dcei", 32, + { 0, { (1<<MACH_FR400), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE } } + }, +/* dcf$pack @($GRi,$GRj) */ + { + FRV_INSN_DCF, "dcf", "dcf", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } } + }, +/* dcef$pack @($GRi,$GRj),$ae */ + { + FRV_INSN_DCEF, "dcef", "dcef", 32, + { 0, { (1<<MACH_FR400), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE } } + }, +/* witlb$pack $GRk,@($GRi,$GRj) */ + { + FRV_INSN_WITLB, "witlb", "witlb", 32, + { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } } + }, +/* wdtlb$pack $GRk,@($GRi,$GRj) */ + { + FRV_INSN_WDTLB, "wdtlb", "wdtlb", 32, + { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } } + }, +/* itlbi$pack @($GRi,$GRj) */ + { + FRV_INSN_ITLBI, "itlbi", "itlbi", 32, + { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } } + }, +/* dtlbi$pack @($GRi,$GRj) */ + { + FRV_INSN_DTLBI, "dtlbi", "dtlbi", 32, + { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } } + }, +/* icpl$pack $GRi,$GRj,$lock */ + { + FRV_INSN_ICPL, "icpl", "icpl", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } } + }, +/* dcpl$pack $GRi,$GRj,$lock */ + { + FRV_INSN_DCPL, "dcpl", "dcpl", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } } + }, +/* icul$pack $GRi */ + { + FRV_INSN_ICUL, "icul", "icul", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } } + }, +/* dcul$pack $GRi */ + { + FRV_INSN_DCUL, "dcul", "dcul", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } } + }, +/* bar$pack */ + { + FRV_INSN_BAR, "bar", "bar", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } } + }, +/* membar$pack */ + { + FRV_INSN_MEMBAR, "membar", "membar", 32, + { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2 } } + }, +/* cop1$pack $s6_1,$CPRi,$CPRj,$CPRk */ + { + FRV_INSN_COP1, "cop1", "cop1", 32, + { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } } + }, +/* cop2$pack $s6_1,$CPRi,$CPRj,$CPRk */ + { + FRV_INSN_COP2, "cop2", "cop2", 32, + { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2 } } + }, +/* clrgr$pack $GRk */ + { + FRV_INSN_CLRGR, "clrgr", "clrgr", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } } + }, +/* clrfr$pack $FRk */ + { + FRV_INSN_CLRFR, "clrfr", "clrfr", 32, + { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } } + }, +/* clrga$pack */ + { + FRV_INSN_CLRGA, "clrga", "clrga", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } } + }, +/* clrfa$pack */ + { + FRV_INSN_CLRFA, "clrfa", "clrfa", 32, + { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } } + }, +/* commitgr$pack $GRk */ + { + FRV_INSN_COMMITGR, "commitgr", "commitgr", 32, + { 0, { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } } + }, +/* commitfr$pack $FRk */ + { + FRV_INSN_COMMITFR, "commitfr", "commitfr", 32, + { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } } + }, +/* commitga$pack */ + { + FRV_INSN_COMMITGA, "commitga", "commitga", 32, + { 0, { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } } + }, +/* commitfa$pack */ + { + FRV_INSN_COMMITFA, "commitfa", "commitfa", 32, + { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6 } } + }, +/* fitos$pack $FRintj,$FRk */ + { + FRV_INSN_FITOS, "fitos", "fitos", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + }, +/* fstoi$pack $FRj,$FRintk */ + { + FRV_INSN_FSTOI, "fstoi", "fstoi", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + }, +/* fitod$pack $FRintj,$FRdoublek */ + { + FRV_INSN_FITOD, "fitod", "fitod", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + }, +/* fdtoi$pack $FRdoublej,$FRintk */ + { + FRV_INSN_FDTOI, "fdtoi", "fdtoi", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + }, +/* fditos$pack $FRintj,$FRk */ + { + FRV_INSN_FDITOS, "fditos", "fditos", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + }, +/* fdstoi$pack $FRj,$FRintk */ + { + FRV_INSN_FDSTOI, "fdstoi", "fdstoi", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + }, +/* nfditos$pack $FRintj,$FRk */ + { + FRV_INSN_NFDITOS, "nfditos", "nfditos", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + }, +/* nfdstoi$pack $FRj,$FRintk */ + { + FRV_INSN_NFDSTOI, "nfdstoi", "nfdstoi", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + }, +/* cfitos$pack $FRintj,$FRk,$CCi,$cond */ + { + FRV_INSN_CFITOS, "cfitos", "cfitos", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + }, +/* cfstoi$pack $FRj,$FRintk,$CCi,$cond */ + { + FRV_INSN_CFSTOI, "cfstoi", "cfstoi", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + }, +/* nfitos$pack $FRintj,$FRk */ + { + FRV_INSN_NFITOS, "nfitos", "nfitos", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + }, +/* nfstoi$pack $FRj,$FRintk */ + { + FRV_INSN_NFSTOI, "nfstoi", "nfstoi", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + }, +/* fmovs$pack $FRj,$FRk */ + { + FRV_INSN_FMOVS, "fmovs", "fmovs", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + }, +/* fmovd$pack $FRdoublej,$FRdoublek */ + { + FRV_INSN_FMOVD, "fmovd", "fmovd", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + }, +/* fdmovs$pack $FRj,$FRk */ + { + FRV_INSN_FDMOVS, "fdmovs", "fdmovs", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + }, +/* cfmovs$pack $FRj,$FRk,$CCi,$cond */ + { + FRV_INSN_CFMOVS, "cfmovs", "cfmovs", 32, + { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + }, +/* fnegs$pack $FRj,$FRk */ + { + FRV_INSN_FNEGS, "fnegs", "fnegs", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + }, +/* fnegd$pack $FRdoublej,$FRdoublek */ + { + FRV_INSN_FNEGD, "fnegd", "fnegd", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + }, +/* fdnegs$pack $FRj,$FRk */ + { + FRV_INSN_FDNEGS, "fdnegs", "fdnegs", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + }, +/* cfnegs$pack $FRj,$FRk,$CCi,$cond */ + { + FRV_INSN_CFNEGS, "cfnegs", "cfnegs", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + }, +/* fabss$pack $FRj,$FRk */ + { + FRV_INSN_FABSS, "fabss", "fabss", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + }, +/* fabsd$pack $FRdoublej,$FRdoublek */ + { + FRV_INSN_FABSD, "fabsd", "fabsd", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + }, +/* fdabss$pack $FRj,$FRk */ + { + FRV_INSN_FDABSS, "fdabss", "fdabss", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + }, +/* cfabss$pack $FRj,$FRk,$CCi,$cond */ + { + FRV_INSN_CFABSS, "cfabss", "cfabss", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1 } } + }, +/* fsqrts$pack $FRj,$FRk */ + { + FRV_INSN_FSQRTS, "fsqrts", "fsqrts", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } } + }, +/* fdsqrts$pack $FRj,$FRk */ + { + FRV_INSN_FDSQRTS, "fdsqrts", "fdsqrts", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } } + }, +/* nfdsqrts$pack $FRj,$FRk */ + { + FRV_INSN_NFDSQRTS, "nfdsqrts", "nfdsqrts", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } } + }, +/* fsqrtd$pack $FRdoublej,$FRdoublek */ + { + FRV_INSN_FSQRTD, "fsqrtd", "fsqrtd", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } } + }, +/* cfsqrts$pack $FRj,$FRk,$CCi,$cond */ + { + FRV_INSN_CFSQRTS, "cfsqrts", "cfsqrts", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } } + }, +/* nfsqrts$pack $FRj,$FRk */ + { + FRV_INSN_NFSQRTS, "nfsqrts", "nfsqrts", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } } + }, +/* fadds$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_FADDS, "fadds", "fadds", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } + }, +/* fsubs$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_FSUBS, "fsubs", "fsubs", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } + }, +/* fmuls$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_FMULS, "fmuls", "fmuls", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } } + }, +/* fdivs$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_FDIVS, "fdivs", "fdivs", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } } + }, +/* faddd$pack $FRdoublei,$FRdoublej,$FRdoublek */ + { + FRV_INSN_FADDD, "faddd", "faddd", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } + }, +/* fsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */ + { + FRV_INSN_FSUBD, "fsubd", "fsubd", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } + }, +/* fmuld$pack $FRdoublei,$FRdoublej,$FRdoublek */ + { + FRV_INSN_FMULD, "fmuld", "fmuld", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } } + }, +/* fdivd$pack $FRdoublei,$FRdoublej,$FRdoublek */ + { + FRV_INSN_FDIVD, "fdivd", "fdivd", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } } + }, +/* cfadds$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + FRV_INSN_CFADDS, "cfadds", "cfadds", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } + }, +/* cfsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + FRV_INSN_CFSUBS, "cfsubs", "cfsubs", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } + }, +/* cfmuls$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + FRV_INSN_CFMULS, "cfmuls", "cfmuls", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } } + }, +/* cfdivs$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + FRV_INSN_CFDIVS, "cfdivs", "cfdivs", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } } + }, +/* nfadds$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_NFADDS, "nfadds", "nfadds", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } + }, +/* nfsubs$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_NFSUBS, "nfsubs", "nfsubs", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } + }, +/* nfmuls$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_NFMULS, "nfmuls", "nfmuls", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3 } } + }, +/* nfdivs$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_NFDIVS, "nfdivs", "nfdivs", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4 } } + }, +/* fcmps$pack $FRi,$FRj,$FCCi_2 */ + { + FRV_INSN_FCMPS, "fcmps", "fcmps", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } + }, +/* fcmpd$pack $FRdoublei,$FRdoublej,$FCCi_2 */ + { + FRV_INSN_FCMPD, "fcmpd", "fcmpd", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } + }, +/* cfcmps$pack $FRi,$FRj,$FCCi_2,$CCi,$cond */ + { + FRV_INSN_CFCMPS, "cfcmps", "cfcmps", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_2 } } + }, +/* fdcmps$pack $FRi,$FRj,$FCCi_2 */ + { + FRV_INSN_FDCMPS, "fdcmps", "fdcmps", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } } + }, +/* fmadds$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_FMADDS, "fmadds", "fmadds", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + }, +/* fmsubs$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_FMSUBS, "fmsubs", "fmsubs", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + }, +/* fmaddd$pack $FRdoublei,$FRdoublej,$FRdoublek */ + { + FRV_INSN_FMADDD, "fmaddd", "fmaddd", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + }, +/* fmsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */ + { + FRV_INSN_FMSUBD, "fmsubd", "fmsubd", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + }, +/* fdmadds$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_FDMADDS, "fdmadds", "fdmadds", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + }, +/* nfdmadds$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_NFDMADDS, "nfdmadds", "nfdmadds", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + }, +/* cfmadds$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + FRV_INSN_CFMADDS, "cfmadds", "cfmadds", 32, + { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + }, +/* cfmsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + FRV_INSN_CFMSUBS, "cfmsubs", "cfmsubs", 32, + { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + }, +/* nfmadds$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_NFMADDS, "nfmadds", "nfmadds", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + }, +/* nfmsubs$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_NFMSUBS, "nfmsubs", "nfmsubs", 32, + { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + }, +/* fmas$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_FMAS, "fmas", "fmas", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + }, +/* fmss$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_FMSS, "fmss", "fmss", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + }, +/* fdmas$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_FDMAS, "fdmas", "fdmas", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + }, +/* fdmss$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_FDMSS, "fdmss", "fdmss", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + }, +/* nfdmas$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_NFDMAS, "nfdmas", "nfdmas", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + }, +/* nfdmss$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_NFDMSS, "nfdmss", "nfdmss", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + }, +/* cfmas$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + FRV_INSN_CFMAS, "cfmas", "cfmas", 32, + { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + }, +/* cfmss$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + FRV_INSN_CFMSS, "cfmss", "cfmss", 32, + { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + }, +/* fmad$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_FMAD, "fmad", "fmad", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + }, +/* fmsd$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_FMSD, "fmsd", "fmsd", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + }, +/* nfmas$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_NFMAS, "nfmas", "nfmas", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + }, +/* nfmss$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_NFMSS, "nfmss", "nfmss", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5 } } + }, +/* fdadds$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_FDADDS, "fdadds", "fdadds", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } } + }, +/* fdsubs$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_FDSUBS, "fdsubs", "fdsubs", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } } + }, +/* fdmuls$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_FDMULS, "fdmuls", "fdmuls", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } } + }, +/* fddivs$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_FDDIVS, "fddivs", "fddivs", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } } + }, +/* fdsads$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_FDSADS, "fdsads", "fdsads", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } } + }, +/* fdmulcs$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_FDMULCS, "fdmulcs", "fdmulcs", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } } + }, +/* nfdmulcs$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_NFDMULCS, "nfdmulcs", "nfdmulcs", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } } + }, +/* nfdadds$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_NFDADDS, "nfdadds", "nfdadds", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } } + }, +/* nfdsubs$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_NFDSUBS, "nfdsubs", "nfdsubs", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } } + }, +/* nfdmuls$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_NFDMULS, "nfdmuls", "nfdmuls", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } } + }, +/* nfddivs$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_NFDDIVS, "nfddivs", "nfddivs", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7 } } + }, +/* nfdsads$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_NFDSADS, "nfdsads", "nfdsads", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } } + }, +/* nfdcmps$pack $FRi,$FRj,$FCCi_2 */ + { + FRV_INSN_NFDCMPS, "nfdcmps", "nfdcmps", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6 } } + }, +/* mhsetlos$pack $u12,$FRklo */ + { + FRV_INSN_MHSETLOS, "mhsetlos", "mhsetlos", 32, + { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } + }, +/* mhsethis$pack $u12,$FRkhi */ + { + FRV_INSN_MHSETHIS, "mhsethis", "mhsethis", 32, + { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } + }, +/* mhdsets$pack $u12,$FRintk */ + { + FRV_INSN_MHDSETS, "mhdsets", "mhdsets", 32, + { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } + }, +/* mhsetloh$pack $s5,$FRklo */ + { + FRV_INSN_MHSETLOH, "mhsetloh", "mhsetloh", 32, + { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } + }, +/* mhsethih$pack $s5,$FRkhi */ + { + FRV_INSN_MHSETHIH, "mhsethih", "mhsethih", 32, + { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } + }, +/* mhdseth$pack $s5,$FRintk */ + { + FRV_INSN_MHDSETH, "mhdseth", "mhdseth", 32, + { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } + }, +/* mand$pack $FRinti,$FRintj,$FRintk */ + { + FRV_INSN_MAND, "mand", "mand", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + }, +/* mor$pack $FRinti,$FRintj,$FRintk */ + { + FRV_INSN_MOR, "mor", "mor", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + }, +/* mxor$pack $FRinti,$FRintj,$FRintk */ + { + FRV_INSN_MXOR, "mxor", "mxor", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + }, +/* cmand$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + FRV_INSN_CMAND, "cmand", "cmand", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + }, +/* cmor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + FRV_INSN_CMOR, "cmor", "cmor", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + }, +/* cmxor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + FRV_INSN_CMXOR, "cmxor", "cmxor", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + }, +/* mnot$pack $FRintj,$FRintk */ + { + FRV_INSN_MNOT, "mnot", "mnot", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + }, +/* cmnot$pack $FRintj,$FRintk,$CCi,$cond */ + { + FRV_INSN_CMNOT, "cmnot", "cmnot", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + }, +/* mrotli$pack $FRinti,$u6,$FRintk */ + { + FRV_INSN_MROTLI, "mrotli", "mrotli", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } } + }, +/* mrotri$pack $FRinti,$u6,$FRintk */ + { + FRV_INSN_MROTRI, "mrotri", "mrotri", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } } + }, +/* mwcut$pack $FRinti,$FRintj,$FRintk */ + { + FRV_INSN_MWCUT, "mwcut", "mwcut", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } } + }, +/* mwcuti$pack $FRinti,$u6,$FRintk */ + { + FRV_INSN_MWCUTI, "mwcuti", "mwcuti", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } } + }, +/* mcut$pack $ACC40Si,$FRintj,$FRintk */ + { + FRV_INSN_MCUT, "mcut", "mcut", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } } + }, +/* mcuti$pack $ACC40Si,$s6,$FRintk */ + { + FRV_INSN_MCUTI, "mcuti", "mcuti", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } } + }, +/* mcutss$pack $ACC40Si,$FRintj,$FRintk */ + { + FRV_INSN_MCUTSS, "mcutss", "mcutss", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } } + }, +/* mcutssi$pack $ACC40Si,$s6,$FRintk */ + { + FRV_INSN_MCUTSSI, "mcutssi", "mcutssi", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } } + }, +/* mdcutssi$pack $ACC40Si,$s6,$FRintk */ + { + FRV_INSN_MDCUTSSI, "mdcutssi", "mdcutssi", 32, + { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } + }, +/* maveh$pack $FRinti,$FRintj,$FRintk */ + { + FRV_INSN_MAVEH, "maveh", "maveh", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + }, +/* msllhi$pack $FRinti,$u6,$FRintk */ + { + FRV_INSN_MSLLHI, "msllhi", "msllhi", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } } + }, +/* msrlhi$pack $FRinti,$u6,$FRintk */ + { + FRV_INSN_MSRLHI, "msrlhi", "msrlhi", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } } + }, +/* msrahi$pack $FRinti,$u6,$FRintk */ + { + FRV_INSN_MSRAHI, "msrahi", "msrahi", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } } + }, +/* mdrotli$pack $FRinti,$u6,$FRintk */ + { + FRV_INSN_MDROTLI, "mdrotli", "mdrotli", 32, + { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } + }, +/* mcplhi$pack $FRinti,$u6,$FRintk */ + { + FRV_INSN_MCPLHI, "mcplhi", "mcplhi", 32, + { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } + }, +/* mcpli$pack $FRinti,$u6,$FRintk */ + { + FRV_INSN_MCPLI, "mcpli", "mcpli", 32, + { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } + }, +/* msaths$pack $FRinti,$FRintj,$FRintk */ + { + FRV_INSN_MSATHS, "msaths", "msaths", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + }, +/* mqsaths$pack $FRinti,$FRintj,$FRintk */ + { + FRV_INSN_MQSATHS, "mqsaths", "mqsaths", 32, + { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } + }, +/* msathu$pack $FRinti,$FRintj,$FRintk */ + { + FRV_INSN_MSATHU, "msathu", "msathu", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + }, +/* mcmpsh$pack $FRinti,$FRintj,$FCCk */ + { + FRV_INSN_MCMPSH, "mcmpsh", "mcmpsh", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + }, +/* mcmpuh$pack $FRinti,$FRintj,$FCCk */ + { + FRV_INSN_MCMPUH, "mcmpuh", "mcmpuh", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + }, +/* mabshs$pack $FRintj,$FRintk */ + { + FRV_INSN_MABSHS, "mabshs", "mabshs", 32, + { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } + }, +/* maddhss$pack $FRinti,$FRintj,$FRintk */ + { + FRV_INSN_MADDHSS, "maddhss", "maddhss", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + }, +/* maddhus$pack $FRinti,$FRintj,$FRintk */ + { + FRV_INSN_MADDHUS, "maddhus", "maddhus", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + }, +/* msubhss$pack $FRinti,$FRintj,$FRintk */ + { + FRV_INSN_MSUBHSS, "msubhss", "msubhss", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + }, +/* msubhus$pack $FRinti,$FRintj,$FRintk */ + { + FRV_INSN_MSUBHUS, "msubhus", "msubhus", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + }, +/* cmaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + FRV_INSN_CMADDHSS, "cmaddhss", "cmaddhss", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + }, +/* cmaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + FRV_INSN_CMADDHUS, "cmaddhus", "cmaddhus", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + }, +/* cmsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + FRV_INSN_CMSUBHSS, "cmsubhss", "cmsubhss", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + }, +/* cmsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + FRV_INSN_CMSUBHUS, "cmsubhus", "cmsubhus", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } + }, +/* mqaddhss$pack $FRinti,$FRintj,$FRintk */ + { + FRV_INSN_MQADDHSS, "mqaddhss", "mqaddhss", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } + }, +/* mqaddhus$pack $FRinti,$FRintj,$FRintk */ + { + FRV_INSN_MQADDHUS, "mqaddhus", "mqaddhus", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } + }, +/* mqsubhss$pack $FRinti,$FRintj,$FRintk */ + { + FRV_INSN_MQSUBHSS, "mqsubhss", "mqsubhss", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } + }, +/* mqsubhus$pack $FRinti,$FRintj,$FRintk */ + { + FRV_INSN_MQSUBHUS, "mqsubhus", "mqsubhus", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } + }, +/* cmqaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + FRV_INSN_CMQADDHSS, "cmqaddhss", "cmqaddhss", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } + }, +/* cmqaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + FRV_INSN_CMQADDHUS, "cmqaddhus", "cmqaddhus", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } + }, +/* cmqsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + FRV_INSN_CMQSUBHSS, "cmqsubhss", "cmqsubhss", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } + }, +/* cmqsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + FRV_INSN_CMQSUBHUS, "cmqsubhus", "cmqsubhus", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } + }, +/* maddaccs$pack $ACC40Si,$ACC40Sk */ + { + FRV_INSN_MADDACCS, "maddaccs", "maddaccs", 32, + { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } + }, +/* msubaccs$pack $ACC40Si,$ACC40Sk */ + { + FRV_INSN_MSUBACCS, "msubaccs", "msubaccs", 32, + { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } + }, +/* mdaddaccs$pack $ACC40Si,$ACC40Sk */ + { + FRV_INSN_MDADDACCS, "mdaddaccs", "mdaddaccs", 32, + { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } + }, +/* mdsubaccs$pack $ACC40Si,$ACC40Sk */ + { + FRV_INSN_MDSUBACCS, "mdsubaccs", "mdsubaccs", 32, + { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } + }, +/* masaccs$pack $ACC40Si,$ACC40Sk */ + { + FRV_INSN_MASACCS, "masaccs", "masaccs", 32, + { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } + }, +/* mdasaccs$pack $ACC40Si,$ACC40Sk */ + { + FRV_INSN_MDASACCS, "mdasaccs", "mdasaccs", 32, + { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } + }, +/* mmulhs$pack $FRinti,$FRintj,$ACC40Sk */ + { + FRV_INSN_MMULHS, "mmulhs", "mmulhs", 32, + { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + }, +/* mmulhu$pack $FRinti,$FRintj,$ACC40Sk */ + { + FRV_INSN_MMULHU, "mmulhu", "mmulhu", 32, + { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + }, +/* mmulxhs$pack $FRinti,$FRintj,$ACC40Sk */ + { + FRV_INSN_MMULXHS, "mmulxhs", "mmulxhs", 32, + { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + }, +/* mmulxhu$pack $FRinti,$FRintj,$ACC40Sk */ + { + FRV_INSN_MMULXHU, "mmulxhu", "mmulxhu", 32, + { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + }, +/* cmmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + FRV_INSN_CMMULHS, "cmmulhs", "cmmulhs", 32, + { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + }, +/* cmmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + FRV_INSN_CMMULHU, "cmmulhu", "cmmulhu", 32, + { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + }, +/* mqmulhs$pack $FRinti,$FRintj,$ACC40Sk */ + { + FRV_INSN_MQMULHS, "mqmulhs", "mqmulhs", 32, + { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } + }, +/* mqmulhu$pack $FRinti,$FRintj,$ACC40Sk */ + { + FRV_INSN_MQMULHU, "mqmulhu", "mqmulhu", 32, + { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } + }, +/* mqmulxhs$pack $FRinti,$FRintj,$ACC40Sk */ + { + FRV_INSN_MQMULXHS, "mqmulxhs", "mqmulxhs", 32, + { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } + }, +/* mqmulxhu$pack $FRinti,$FRintj,$ACC40Sk */ + { + FRV_INSN_MQMULXHU, "mqmulxhu", "mqmulxhu", 32, + { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } + }, +/* cmqmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + FRV_INSN_CMQMULHS, "cmqmulhs", "cmqmulhs", 32, + { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } + }, +/* cmqmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + FRV_INSN_CMQMULHU, "cmqmulhu", "cmqmulhu", 32, + { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } + }, +/* mmachs$pack $FRinti,$FRintj,$ACC40Sk */ + { + FRV_INSN_MMACHS, "mmachs", "mmachs", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + }, +/* mmachu$pack $FRinti,$FRintj,$ACC40Uk */ + { + FRV_INSN_MMACHU, "mmachu", "mmachu", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + }, +/* mmrdhs$pack $FRinti,$FRintj,$ACC40Sk */ + { + FRV_INSN_MMRDHS, "mmrdhs", "mmrdhs", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + }, +/* mmrdhu$pack $FRinti,$FRintj,$ACC40Uk */ + { + FRV_INSN_MMRDHU, "mmrdhu", "mmrdhu", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + }, +/* cmmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + FRV_INSN_CMMACHS, "cmmachs", "cmmachs", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + }, +/* cmmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */ + { + FRV_INSN_CMMACHU, "cmmachu", "cmmachu", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + }, +/* mqmachs$pack $FRinti,$FRintj,$ACC40Sk */ + { + FRV_INSN_MQMACHS, "mqmachs", "mqmachs", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } + }, +/* mqmachu$pack $FRinti,$FRintj,$ACC40Uk */ + { + FRV_INSN_MQMACHU, "mqmachu", "mqmachu", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } + }, +/* cmqmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + FRV_INSN_CMQMACHS, "cmqmachs", "cmqmachs", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } + }, +/* cmqmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */ + { + FRV_INSN_CMQMACHU, "cmqmachu", "cmqmachu", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } + }, +/* mqxmachs$pack $FRinti,$FRintj,$ACC40Sk */ + { + FRV_INSN_MQXMACHS, "mqxmachs", "mqxmachs", 32, + { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } + }, +/* mqxmacxhs$pack $FRinti,$FRintj,$ACC40Sk */ + { + FRV_INSN_MQXMACXHS, "mqxmacxhs", "mqxmacxhs", 32, + { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } + }, +/* mqmacxhs$pack $FRinti,$FRintj,$ACC40Sk */ + { + FRV_INSN_MQMACXHS, "mqmacxhs", "mqmacxhs", 32, + { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } + }, +/* mcpxrs$pack $FRinti,$FRintj,$ACC40Sk */ + { + FRV_INSN_MCPXRS, "mcpxrs", "mcpxrs", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + }, +/* mcpxru$pack $FRinti,$FRintj,$ACC40Sk */ + { + FRV_INSN_MCPXRU, "mcpxru", "mcpxru", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + }, +/* mcpxis$pack $FRinti,$FRintj,$ACC40Sk */ + { + FRV_INSN_MCPXIS, "mcpxis", "mcpxis", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + }, +/* mcpxiu$pack $FRinti,$FRintj,$ACC40Sk */ + { + FRV_INSN_MCPXIU, "mcpxiu", "mcpxiu", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + }, +/* cmcpxrs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + FRV_INSN_CMCPXRS, "cmcpxrs", "cmcpxrs", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + }, +/* cmcpxru$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + FRV_INSN_CMCPXRU, "cmcpxru", "cmcpxru", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + }, +/* cmcpxis$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + FRV_INSN_CMCPXIS, "cmcpxis", "cmcpxis", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + }, +/* cmcpxiu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + FRV_INSN_CMCPXIU, "cmcpxiu", "cmcpxiu", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } + }, +/* mqcpxrs$pack $FRinti,$FRintj,$ACC40Sk */ + { + FRV_INSN_MQCPXRS, "mqcpxrs", "mqcpxrs", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } + }, +/* mqcpxru$pack $FRinti,$FRintj,$ACC40Sk */ + { + FRV_INSN_MQCPXRU, "mqcpxru", "mqcpxru", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } + }, +/* mqcpxis$pack $FRinti,$FRintj,$ACC40Sk */ + { + FRV_INSN_MQCPXIS, "mqcpxis", "mqcpxis", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } + }, +/* mqcpxiu$pack $FRinti,$FRintj,$ACC40Sk */ + { + FRV_INSN_MQCPXIU, "mqcpxiu", "mqcpxiu", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } + }, +/* mexpdhw$pack $FRinti,$u6,$FRintk */ + { + FRV_INSN_MEXPDHW, "mexpdhw", "mexpdhw", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } } + }, +/* cmexpdhw$pack $FRinti,$u6,$FRintk,$CCi,$cond */ + { + FRV_INSN_CMEXPDHW, "cmexpdhw", "cmexpdhw", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } } + }, +/* mexpdhd$pack $FRinti,$u6,$FRintk */ + { + FRV_INSN_MEXPDHD, "mexpdhd", "mexpdhd", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } } + }, +/* cmexpdhd$pack $FRinti,$u6,$FRintk,$CCi,$cond */ + { + FRV_INSN_CMEXPDHD, "cmexpdhd", "cmexpdhd", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } } + }, +/* mpackh$pack $FRinti,$FRintj,$FRintk */ + { + FRV_INSN_MPACKH, "mpackh", "mpackh", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } } + }, +/* mdpackh$pack $FRinti,$FRintj,$FRintk */ + { + FRV_INSN_MDPACKH, "mdpackh", "mdpackh", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_5 } } + }, +/* munpackh$pack $FRinti,$FRintk */ + { + FRV_INSN_MUNPACKH, "munpackh", "munpackh", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } } + }, +/* mdunpackh$pack $FRinti,$FRintk */ + { + FRV_INSN_MDUNPACKH, "mdunpackh", "mdunpackh", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7 } } + }, +/* mbtoh$pack $FRintj,$FRintk */ + { + FRV_INSN_MBTOH, "mbtoh", "mbtoh", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } } + }, +/* cmbtoh$pack $FRintj,$FRintk,$CCi,$cond */ + { + FRV_INSN_CMBTOH, "cmbtoh", "cmbtoh", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } } + }, +/* mhtob$pack $FRintj,$FRintk */ + { + FRV_INSN_MHTOB, "mhtob", "mhtob", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } } + }, +/* cmhtob$pack $FRintj,$FRintk,$CCi,$cond */ + { + FRV_INSN_CMHTOB, "cmhtob", "cmhtob", 32, + { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } } + }, +/* mbtohe$pack $FRintj,$FRintk */ + { + FRV_INSN_MBTOHE, "mbtohe", "mbtohe", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7 } } + }, +/* cmbtohe$pack $FRintj,$FRintk,$CCi,$cond */ + { + FRV_INSN_CMBTOHE, "cmbtohe", "cmbtohe", 32, + { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7 } } + }, +/* mclracc$pack $ACC40Sk,$A */ + { + FRV_INSN_MCLRACC, "mclracc", "mclracc", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_3 } } + }, +/* mrdacc$pack $ACC40Si,$FRintk */ + { + FRV_INSN_MRDACC, "mrdacc", "mrdacc", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } } + }, +/* mrdaccg$pack $ACCGi,$FRintk */ + { + FRV_INSN_MRDACCG, "mrdaccg", "mrdaccg", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } } + }, +/* mwtacc$pack $FRinti,$ACC40Sk */ + { + FRV_INSN_MWTACC, "mwtacc", "mwtacc", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_3 } } + }, +/* mwtaccg$pack $FRinti,$ACCGk */ + { + FRV_INSN_MWTACCG, "mwtaccg", "mwtaccg", 32, + { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_3 } } + }, +/* mcop1$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_MCOP1, "mcop1", "mcop1", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_1 } } + }, +/* mcop2$pack $FRi,$FRj,$FRk */ + { + FRV_INSN_MCOP2, "mcop2", "mcop2", 32, + { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_1 } } + }, +/* fnop$pack */ + { + FRV_INSN_FNOP, "fnop", "fnop", 32, + { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_8 } } + }, +}; + +#undef OP +#undef A + +/* Initialize anything needed to be done once, before any cpu_open call. */ +static void init_tables PARAMS ((void)); + +static void +init_tables () +{ +} + +static const CGEN_MACH * lookup_mach_via_bfd_name + PARAMS ((const CGEN_MACH *, const char *)); +static void build_hw_table PARAMS ((CGEN_CPU_TABLE *)); +static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *)); +static void build_operand_table PARAMS ((CGEN_CPU_TABLE *)); +static void build_insn_table PARAMS ((CGEN_CPU_TABLE *)); +static void frv_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *)); + +/* Subroutine of frv_cgen_cpu_open to look up a mach via its bfd name. */ + +static const CGEN_MACH * +lookup_mach_via_bfd_name (table, name) + const CGEN_MACH *table; + const char *name; +{ + while (table->name) + { + if (strcmp (name, table->bfd_name) == 0) + return table; + ++table; + } + abort (); +} + +/* Subroutine of frv_cgen_cpu_open to build the hardware table. */ + +static void +build_hw_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + int machs = cd->machs; + const CGEN_HW_ENTRY *init = & frv_cgen_hw_table[0]; + /* MAX_HW is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_HW_ENTRY **selected = + (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); + + cd->hw_table.init_entries = init; + cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); + memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); + /* ??? For now we just use machs to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->hw_table.entries = selected; + cd->hw_table.num_entries = MAX_HW; +} + +/* Subroutine of frv_cgen_cpu_open to build the hardware table. */ + +static void +build_ifield_table (cd) + CGEN_CPU_TABLE *cd; +{ + cd->ifld_table = & frv_cgen_ifld_table[0]; +} + +/* Subroutine of frv_cgen_cpu_open to build the hardware table. */ + +static void +build_operand_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + int machs = cd->machs; + const CGEN_OPERAND *init = & frv_cgen_operand_table[0]; + /* MAX_OPERANDS is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_OPERAND **selected = + (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + + cd->operand_table.init_entries = init; + cd->operand_table.entry_size = sizeof (CGEN_OPERAND); + memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + /* ??? For now we just use mach to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->operand_table.entries = selected; + cd->operand_table.num_entries = MAX_OPERANDS; +} + +/* Subroutine of frv_cgen_cpu_open to build the hardware table. + ??? This could leave out insns not supported by the specified mach/isa, + but that would cause errors like "foo only supported by bar" to become + "unknown insn", so for now we include all insns and require the app to + do the checking later. + ??? On the other hand, parsing of such insns may require their hardware or + operand elements to be in the table [which they mightn't be]. */ + +static void +build_insn_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + const CGEN_IBASE *ib = & frv_cgen_insn_table[0]; + CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + + memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); + for (i = 0; i < MAX_INSNS; ++i) + insns[i].base = &ib[i]; + cd->insn_table.init_entries = insns; + cd->insn_table.entry_size = sizeof (CGEN_IBASE); + cd->insn_table.num_init_entries = MAX_INSNS; +} + +/* Subroutine of frv_cgen_cpu_open to rebuild the tables. */ + +static void +frv_cgen_rebuild_tables (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + unsigned int isas = cd->isas; + unsigned int machs = cd->machs; + + cd->int_insn_p = CGEN_INT_INSN_P; + + /* Data derived from the isa spec. */ +#define UNSET (CGEN_SIZE_UNKNOWN + 1) + cd->default_insn_bitsize = UNSET; + cd->base_insn_bitsize = UNSET; + cd->min_insn_bitsize = 65535; /* some ridiculously big number */ + cd->max_insn_bitsize = 0; + for (i = 0; i < MAX_ISAS; ++i) + if (((1 << i) & isas) != 0) + { + const CGEN_ISA *isa = & frv_cgen_isa_table[i]; + + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ + if (cd->default_insn_bitsize == UNSET) + cd->default_insn_bitsize = isa->default_insn_bitsize; + else if (isa->default_insn_bitsize == cd->default_insn_bitsize) + ; /* this is ok */ + else + cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ + if (cd->base_insn_bitsize == UNSET) + cd->base_insn_bitsize = isa->base_insn_bitsize; + else if (isa->base_insn_bitsize == cd->base_insn_bitsize) + ; /* this is ok */ + else + cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Set min,max insn sizes. */ + if (isa->min_insn_bitsize < cd->min_insn_bitsize) + cd->min_insn_bitsize = isa->min_insn_bitsize; + if (isa->max_insn_bitsize > cd->max_insn_bitsize) + cd->max_insn_bitsize = isa->max_insn_bitsize; + } + + /* Data derived from the mach spec. */ + for (i = 0; i < MAX_MACHS; ++i) + if (((1 << i) & machs) != 0) + { + const CGEN_MACH *mach = & frv_cgen_mach_table[i]; + + if (mach->insn_chunk_bitsize != 0) + { + if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) + { + fprintf (stderr, "frv_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); + abort (); + } + + cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; + } + } + + /* Determine which hw elements are used by MACH. */ + build_hw_table (cd); + + /* Build the ifield table. */ + build_ifield_table (cd); + + /* Determine which operands are used by MACH/ISA. */ + build_operand_table (cd); + + /* Build the instruction table. */ + build_insn_table (cd); +} + +/* Initialize a cpu table and return a descriptor. + It's much like opening a file, and must be the first function called. + The arguments are a set of (type/value) pairs, terminated with + CGEN_CPU_OPEN_END. + + Currently supported values: + CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr + CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr + CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name + CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_END: terminates arguments + + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. + + ??? We only support ISO C stdargs here, not K&R. + Laziness, plus experiment to see if anything requires K&R - eventually + K&R will no longer be supported - e.g. GDB is currently trying this. */ + +CGEN_CPU_DESC +frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) +{ + CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); + static int init_p; + unsigned int isas = 0; /* 0 = "unspecified" */ + unsigned int machs = 0; /* 0 = "unspecified" */ + enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + va_list ap; + + if (! init_p) + { + init_tables (); + init_p = 1; + } + + memset (cd, 0, sizeof (*cd)); + + va_start (ap, arg_type); + while (arg_type != CGEN_CPU_OPEN_END) + { + switch (arg_type) + { + case CGEN_CPU_OPEN_ISAS : + isas = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_MACHS : + machs = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_BFDMACH : + { + const char *name = va_arg (ap, const char *); + const CGEN_MACH *mach = + lookup_mach_via_bfd_name (frv_cgen_mach_table, name); + + machs |= 1 << mach->num; + break; + } + case CGEN_CPU_OPEN_ENDIAN : + endian = va_arg (ap, enum cgen_endian); + break; + default : + fprintf (stderr, "frv_cgen_cpu_open: unsupported argument `%d'\n", + arg_type); + abort (); /* ??? return NULL? */ + } + arg_type = va_arg (ap, enum cgen_cpu_open_arg); + } + va_end (ap); + + /* mach unspecified means "all" */ + if (machs == 0) + machs = (1 << MAX_MACHS) - 1; + /* base mach is always selected */ + machs |= 1; + /* isa unspecified means "all" */ + if (isas == 0) + isas = (1 << MAX_ISAS) - 1; + if (endian == CGEN_ENDIAN_UNKNOWN) + { + /* ??? If target has only one, could have a default. */ + fprintf (stderr, "frv_cgen_cpu_open: no endianness specified\n"); + abort (); + } + + cd->isas = isas; + cd->machs = machs; + cd->endian = endian; + /* FIXME: for the sparc case we can determine insn-endianness statically. + The worry here is where both data and insn endian can be independently + chosen, in which case this function will need another argument. + Actually, will want to allow for more arguments in the future anyway. */ + cd->insn_endian = endian; + + /* Table (re)builder. */ + cd->rebuild_tables = frv_cgen_rebuild_tables; + frv_cgen_rebuild_tables (cd); + + /* Default to not allowing signed overflow. */ + cd->signed_overflow_ok_p = 0; + + return (CGEN_CPU_DESC) cd; +} + +/* Cover fn to frv_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. + MACH_NAME is the bfd name of the mach. */ + +CGEN_CPU_DESC +frv_cgen_cpu_open_1 (mach_name, endian) + const char *mach_name; + enum cgen_endian endian; +{ + return frv_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); +} + +/* Close a cpu table. + ??? This can live in a machine independent file, but there's currently + no place to put this file (there's no libcgen). libopcodes is the wrong + place as some simulator ports use this but they don't use libopcodes. */ + +void +frv_cgen_cpu_close (cd) + CGEN_CPU_DESC cd; +{ + unsigned int i; + CGEN_INSN *insns; + + if (cd->macro_insn_table.init_entries) + { + insns = cd->macro_insn_table.init_entries; + for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) + { + if (CGEN_INSN_RX ((insns))) + regfree(CGEN_INSN_RX (insns)); + } + } + + if (cd->insn_table.init_entries) + { + insns = cd->insn_table.init_entries; + for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) + { + if (CGEN_INSN_RX (insns)) + regfree(CGEN_INSN_RX (insns)); + } + } + + + + if (cd->macro_insn_table.init_entries) + free ((CGEN_INSN *) cd->macro_insn_table.init_entries); + + if (cd->insn_table.init_entries) + free ((CGEN_INSN *) cd->insn_table.init_entries); + + if (cd->hw_table.entries) + free ((CGEN_HW_ENTRY *) cd->hw_table.entries); + + if (cd->operand_table.entries) + free ((CGEN_HW_ENTRY *) cd->operand_table.entries); + + free (cd); +} + diff --git a/opcodes/frv-desc.h b/opcodes/frv-desc.h new file mode 100644 index 00000000000..893919fc2dc --- /dev/null +++ b/opcodes/frv-desc.h @@ -0,0 +1,748 @@ +/* CPU data header for frv. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifndef FRV_CPU_H +#define FRV_CPU_H + +#define CGEN_ARCH frv + +/* Given symbol S, return frv_cgen_<S>. */ +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define CGEN_SYM(s) frv##_cgen_##s +#else +#define CGEN_SYM(s) frv/**/_cgen_/**/s +#endif + + +/* Selected cpu families. */ +#define HAVE_CPU_FRVBF + +#define CGEN_INSN_LSB0_P 1 + +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 4 + +/* Maximum size of any insn (in bytes). */ +#define CGEN_MAX_INSN_SIZE 4 + +#define CGEN_INT_INSN_P 1 + +/* Maximum number of syntax elements in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 22 + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS + +/* Maximum number of fields in an instruction. */ +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 10 + +/* Enums. */ + +/* Enum declaration for insn op enums. */ +typedef enum insn_op { + OP_00, OP_01, OP_02, OP_03 + , OP_04, OP_05, OP_06, OP_07 + , OP_08, OP_09, OP_0A, OP_0B + , OP_0C, OP_0D, OP_0E, OP_0F + , OP_10, OP_11, OP_12, OP_13 + , OP_14, OP_15, OP_16, OP_17 + , OP_18, OP_19, OP_1A, OP_1B + , OP_1C, OP_1D, OP_1E, OP_1F + , OP_20, OP_21, OP_22, OP_23 + , OP_24, OP_25, OP_26, OP_27 + , OP_28, OP_29, OP_2A, OP_2B + , OP_2C, OP_2D, OP_2E, OP_2F + , OP_30, OP_31, OP_32, OP_33 + , OP_34, OP_35, OP_36, OP_37 + , OP_38, OP_39, OP_3A, OP_3B + , OP_3C, OP_3D, OP_3E, OP_3F + , OP_40, OP_41, OP_42, OP_43 + , OP_44, OP_45, OP_46, OP_47 + , OP_48, OP_49, OP_4A, OP_4B + , OP_4C, OP_4D, OP_4E, OP_4F + , OP_50, OP_51, OP_52, OP_53 + , OP_54, OP_55, OP_56, OP_57 + , OP_58, OP_59, OP_5A, OP_5B + , OP_5C, OP_5D, OP_5E, OP_5F + , OP_60, OP_61, OP_62, OP_63 + , OP_64, OP_65, OP_66, OP_67 + , OP_68, OP_69, OP_6A, OP_6B + , OP_6C, OP_6D, OP_6E, OP_6F + , OP_70, OP_71, OP_72, OP_73 + , OP_74, OP_75, OP_76, OP_77 + , OP_78, OP_79, OP_7A, OP_7B + , OP_7C, OP_7D, OP_7E, OP_7F +} INSN_OP; + +/* Enum declaration for insn ope enums. */ +typedef enum insn_ope1 { + OPE1_00, OPE1_01, OPE1_02, OPE1_03 + , OPE1_04, OPE1_05, OPE1_06, OPE1_07 + , OPE1_08, OPE1_09, OPE1_0A, OPE1_0B + , OPE1_0C, OPE1_0D, OPE1_0E, OPE1_0F + , OPE1_10, OPE1_11, OPE1_12, OPE1_13 + , OPE1_14, OPE1_15, OPE1_16, OPE1_17 + , OPE1_18, OPE1_19, OPE1_1A, OPE1_1B + , OPE1_1C, OPE1_1D, OPE1_1E, OPE1_1F + , OPE1_20, OPE1_21, OPE1_22, OPE1_23 + , OPE1_24, OPE1_25, OPE1_26, OPE1_27 + , OPE1_28, OPE1_29, OPE1_2A, OPE1_2B + , OPE1_2C, OPE1_2D, OPE1_2E, OPE1_2F + , OPE1_30, OPE1_31, OPE1_32, OPE1_33 + , OPE1_34, OPE1_35, OPE1_36, OPE1_37 + , OPE1_38, OPE1_39, OPE1_3A, OPE1_3B + , OPE1_3C, OPE1_3D, OPE1_3E, OPE1_3F +} INSN_OPE1; + +/* Enum declaration for insn ope enums. */ +typedef enum insn_ope2 { + OPE2_00, OPE2_01, OPE2_02, OPE2_03 + , OPE2_04, OPE2_05, OPE2_06, OPE2_07 + , OPE2_08, OPE2_09, OPE2_0A, OPE2_0B + , OPE2_0C, OPE2_0D, OPE2_0E, OPE2_0F +} INSN_OPE2; + +/* Enum declaration for insn ope enums. */ +typedef enum insn_ope3 { + OPE3_00, OPE3_01, OPE3_02, OPE3_03 + , OPE3_04, OPE3_05, OPE3_06, OPE3_07 +} INSN_OPE3; + +/* Enum declaration for insn ope enums. */ +typedef enum insn_ope4 { + OPE4_0, OPE4_1, OPE4_2, OPE4_3 +} INSN_OPE4; + +/* Enum declaration for integer branch cond enums. */ +typedef enum int_cc { + ICC_NEV, ICC_C, ICC_V, ICC_LT + , ICC_EQ, ICC_LS, ICC_N, ICC_LE + , ICC_RA, ICC_NC, ICC_NV, ICC_GE + , ICC_NE, ICC_HI, ICC_P, ICC_GT +} INT_CC; + +/* Enum declaration for float branch cond enums. */ +typedef enum flt_cc { + FCC_NEV, FCC_U, FCC_GT, FCC_UG + , FCC_LT, FCC_UL, FCC_LG, FCC_NE + , FCC_EQ, FCC_UE, FCC_GE, FCC_UGE + , FCC_LE, FCC_ULE, FCC_O, FCC_RA +} FLT_CC; + +/* Enum declaration for . */ +typedef enum gr_names { + H_GR_SP = 1, H_GR_FP = 2, H_GR_GR0 = 0, H_GR_GR1 = 1 + , H_GR_GR2 = 2, H_GR_GR3 = 3, H_GR_GR4 = 4, H_GR_GR5 = 5 + , H_GR_GR6 = 6, H_GR_GR7 = 7, H_GR_GR8 = 8, H_GR_GR9 = 9 + , H_GR_GR10 = 10, H_GR_GR11 = 11, H_GR_GR12 = 12, H_GR_GR13 = 13 + , H_GR_GR14 = 14, H_GR_GR15 = 15, H_GR_GR16 = 16, H_GR_GR17 = 17 + , H_GR_GR18 = 18, H_GR_GR19 = 19, H_GR_GR20 = 20, H_GR_GR21 = 21 + , H_GR_GR22 = 22, H_GR_GR23 = 23, H_GR_GR24 = 24, H_GR_GR25 = 25 + , H_GR_GR26 = 26, H_GR_GR27 = 27, H_GR_GR28 = 28, H_GR_GR29 = 29 + , H_GR_GR30 = 30, H_GR_GR31 = 31, H_GR_GR32 = 32, H_GR_GR33 = 33 + , H_GR_GR34 = 34, H_GR_GR35 = 35, H_GR_GR36 = 36, H_GR_GR37 = 37 + , H_GR_GR38 = 38, H_GR_GR39 = 39, H_GR_GR40 = 40, H_GR_GR41 = 41 + , H_GR_GR42 = 42, H_GR_GR43 = 43, H_GR_GR44 = 44, H_GR_GR45 = 45 + , H_GR_GR46 = 46, H_GR_GR47 = 47, H_GR_GR48 = 48, H_GR_GR49 = 49 + , H_GR_GR50 = 50, H_GR_GR51 = 51, H_GR_GR52 = 52, H_GR_GR53 = 53 + , H_GR_GR54 = 54, H_GR_GR55 = 55, H_GR_GR56 = 56, H_GR_GR57 = 57 + , H_GR_GR58 = 58, H_GR_GR59 = 59, H_GR_GR60 = 60, H_GR_GR61 = 61 + , H_GR_GR62 = 62, H_GR_GR63 = 63 +} GR_NAMES; + +/* Enum declaration for . */ +typedef enum fr_names { + H_FR_FR0, H_FR_FR1, H_FR_FR2, H_FR_FR3 + , H_FR_FR4, H_FR_FR5, H_FR_FR6, H_FR_FR7 + , H_FR_FR8, H_FR_FR9, H_FR_FR10, H_FR_FR11 + , H_FR_FR12, H_FR_FR13, H_FR_FR14, H_FR_FR15 + , H_FR_FR16, H_FR_FR17, H_FR_FR18, H_FR_FR19 + , H_FR_FR20, H_FR_FR21, H_FR_FR22, H_FR_FR23 + , H_FR_FR24, H_FR_FR25, H_FR_FR26, H_FR_FR27 + , H_FR_FR28, H_FR_FR29, H_FR_FR30, H_FR_FR31 + , H_FR_FR32, H_FR_FR33, H_FR_FR34, H_FR_FR35 + , H_FR_FR36, H_FR_FR37, H_FR_FR38, H_FR_FR39 + , H_FR_FR40, H_FR_FR41, H_FR_FR42, H_FR_FR43 + , H_FR_FR44, H_FR_FR45, H_FR_FR46, H_FR_FR47 + , H_FR_FR48, H_FR_FR49, H_FR_FR50, H_FR_FR51 + , H_FR_FR52, H_FR_FR53, H_FR_FR54, H_FR_FR55 + , H_FR_FR56, H_FR_FR57, H_FR_FR58, H_FR_FR59 + , H_FR_FR60, H_FR_FR61, H_FR_FR62, H_FR_FR63 +} FR_NAMES; + +/* Enum declaration for . */ +typedef enum cpr_names { + H_CPR_CPR0, H_CPR_CPR1, H_CPR_CPR2, H_CPR_CPR3 + , H_CPR_CPR4, H_CPR_CPR5, H_CPR_CPR6, H_CPR_CPR7 + , H_CPR_CPR8, H_CPR_CPR9, H_CPR_CPR10, H_CPR_CPR11 + , H_CPR_CPR12, H_CPR_CPR13, H_CPR_CPR14, H_CPR_CPR15 + , H_CPR_CPR16, H_CPR_CPR17, H_CPR_CPR18, H_CPR_CPR19 + , H_CPR_CPR20, H_CPR_CPR21, H_CPR_CPR22, H_CPR_CPR23 + , H_CPR_CPR24, H_CPR_CPR25, H_CPR_CPR26, H_CPR_CPR27 + , H_CPR_CPR28, H_CPR_CPR29, H_CPR_CPR30, H_CPR_CPR31 + , H_CPR_CPR32, H_CPR_CPR33, H_CPR_CPR34, H_CPR_CPR35 + , H_CPR_CPR36, H_CPR_CPR37, H_CPR_CPR38, H_CPR_CPR39 + , H_CPR_CPR40, H_CPR_CPR41, H_CPR_CPR42, H_CPR_CPR43 + , H_CPR_CPR44, H_CPR_CPR45, H_CPR_CPR46, H_CPR_CPR47 + , H_CPR_CPR48, H_CPR_CPR49, H_CPR_CPR50, H_CPR_CPR51 + , H_CPR_CPR52, H_CPR_CPR53, H_CPR_CPR54, H_CPR_CPR55 + , H_CPR_CPR56, H_CPR_CPR57, H_CPR_CPR58, H_CPR_CPR59 + , H_CPR_CPR60, H_CPR_CPR61, H_CPR_CPR62, H_CPR_CPR63 +} CPR_NAMES; + +/* Enum declaration for . */ +typedef enum spr_names { + H_SPR_PSR = 0, H_SPR_PCSR = 1, H_SPR_BPCSR = 2, H_SPR_TBR = 3 + , H_SPR_BPSR = 4, H_SPR_HSR0 = 16, H_SPR_HSR1 = 17, H_SPR_HSR2 = 18 + , H_SPR_HSR3 = 19, H_SPR_HSR4 = 20, H_SPR_HSR5 = 21, H_SPR_HSR6 = 22 + , H_SPR_HSR7 = 23, H_SPR_HSR8 = 24, H_SPR_HSR9 = 25, H_SPR_HSR10 = 26 + , H_SPR_HSR11 = 27, H_SPR_HSR12 = 28, H_SPR_HSR13 = 29, H_SPR_HSR14 = 30 + , H_SPR_HSR15 = 31, H_SPR_HSR16 = 32, H_SPR_HSR17 = 33, H_SPR_HSR18 = 34 + , H_SPR_HSR19 = 35, H_SPR_HSR20 = 36, H_SPR_HSR21 = 37, H_SPR_HSR22 = 38 + , H_SPR_HSR23 = 39, H_SPR_HSR24 = 40, H_SPR_HSR25 = 41, H_SPR_HSR26 = 42 + , H_SPR_HSR27 = 43, H_SPR_HSR28 = 44, H_SPR_HSR29 = 45, H_SPR_HSR30 = 46 + , H_SPR_HSR31 = 47, H_SPR_HSR32 = 48, H_SPR_HSR33 = 49, H_SPR_HSR34 = 50 + , H_SPR_HSR35 = 51, H_SPR_HSR36 = 52, H_SPR_HSR37 = 53, H_SPR_HSR38 = 54 + , H_SPR_HSR39 = 55, H_SPR_HSR40 = 56, H_SPR_HSR41 = 57, H_SPR_HSR42 = 58 + , H_SPR_HSR43 = 59, H_SPR_HSR44 = 60, H_SPR_HSR45 = 61, H_SPR_HSR46 = 62 + , H_SPR_HSR47 = 63, H_SPR_HSR48 = 64, H_SPR_HSR49 = 65, H_SPR_HSR50 = 66 + , H_SPR_HSR51 = 67, H_SPR_HSR52 = 68, H_SPR_HSR53 = 69, H_SPR_HSR54 = 70 + , H_SPR_HSR55 = 71, H_SPR_HSR56 = 72, H_SPR_HSR57 = 73, H_SPR_HSR58 = 74 + , H_SPR_HSR59 = 75, H_SPR_HSR60 = 76, H_SPR_HSR61 = 77, H_SPR_HSR62 = 78 + , H_SPR_HSR63 = 79, H_SPR_CCR = 256, H_SPR_CCCR = 263, H_SPR_LR = 272 + , H_SPR_LCR = 273, H_SPR_ISR = 288, H_SPR_NEEAR0 = 352, H_SPR_NEEAR1 = 353 + , H_SPR_NEEAR2 = 354, H_SPR_NEEAR3 = 355, H_SPR_NEEAR4 = 356, H_SPR_NEEAR5 = 357 + , H_SPR_NEEAR6 = 358, H_SPR_NEEAR7 = 359, H_SPR_NEEAR8 = 360, H_SPR_NEEAR9 = 361 + , H_SPR_NEEAR10 = 362, H_SPR_NEEAR11 = 363, H_SPR_NEEAR12 = 364, H_SPR_NEEAR13 = 365 + , H_SPR_NEEAR14 = 366, H_SPR_NEEAR15 = 367, H_SPR_NEEAR16 = 368, H_SPR_NEEAR17 = 369 + , H_SPR_NEEAR18 = 370, H_SPR_NEEAR19 = 371, H_SPR_NEEAR20 = 372, H_SPR_NEEAR21 = 373 + , H_SPR_NEEAR22 = 374, H_SPR_NEEAR23 = 375, H_SPR_NEEAR24 = 376, H_SPR_NEEAR25 = 377 + , H_SPR_NEEAR26 = 378, H_SPR_NEEAR27 = 379, H_SPR_NEEAR28 = 380, H_SPR_NEEAR29 = 381 + , H_SPR_NEEAR30 = 382, H_SPR_NEEAR31 = 383, H_SPR_NESR0 = 384, H_SPR_NESR1 = 385 + , H_SPR_NESR2 = 386, H_SPR_NESR3 = 387, H_SPR_NESR4 = 388, H_SPR_NESR5 = 389 + , H_SPR_NESR6 = 390, H_SPR_NESR7 = 391, H_SPR_NESR8 = 392, H_SPR_NESR9 = 393 + , H_SPR_NESR10 = 394, H_SPR_NESR11 = 395, H_SPR_NESR12 = 396, H_SPR_NESR13 = 397 + , H_SPR_NESR14 = 398, H_SPR_NESR15 = 399, H_SPR_NESR16 = 400, H_SPR_NESR17 = 401 + , H_SPR_NESR18 = 402, H_SPR_NESR19 = 403, H_SPR_NESR20 = 404, H_SPR_NESR21 = 405 + , H_SPR_NESR22 = 406, H_SPR_NESR23 = 407, H_SPR_NESR24 = 408, H_SPR_NESR25 = 409 + , H_SPR_NESR26 = 410, H_SPR_NESR27 = 411, H_SPR_NESR28 = 412, H_SPR_NESR29 = 413 + , H_SPR_NESR30 = 414, H_SPR_NESR31 = 415, H_SPR_NECR = 416, H_SPR_GNER0 = 432 + , H_SPR_GNER1 = 433, H_SPR_FNER0 = 434, H_SPR_FNER1 = 435, H_SPR_EPCR0 = 512 + , H_SPR_EPCR1 = 513, H_SPR_EPCR2 = 514, H_SPR_EPCR3 = 515, H_SPR_EPCR4 = 516 + , H_SPR_EPCR5 = 517, H_SPR_EPCR6 = 518, H_SPR_EPCR7 = 519, H_SPR_EPCR8 = 520 + , H_SPR_EPCR9 = 521, H_SPR_EPCR10 = 522, H_SPR_EPCR11 = 523, H_SPR_EPCR12 = 524 + , H_SPR_EPCR13 = 525, H_SPR_EPCR14 = 526, H_SPR_EPCR15 = 527, H_SPR_EPCR16 = 528 + , H_SPR_EPCR17 = 529, H_SPR_EPCR18 = 530, H_SPR_EPCR19 = 531, H_SPR_EPCR20 = 532 + , H_SPR_EPCR21 = 533, H_SPR_EPCR22 = 534, H_SPR_EPCR23 = 535, H_SPR_EPCR24 = 536 + , H_SPR_EPCR25 = 537, H_SPR_EPCR26 = 538, H_SPR_EPCR27 = 539, H_SPR_EPCR28 = 540 + , H_SPR_EPCR29 = 541, H_SPR_EPCR30 = 542, H_SPR_EPCR31 = 543, H_SPR_EPCR32 = 544 + , H_SPR_EPCR33 = 545, H_SPR_EPCR34 = 546, H_SPR_EPCR35 = 547, H_SPR_EPCR36 = 548 + , H_SPR_EPCR37 = 549, H_SPR_EPCR38 = 550, H_SPR_EPCR39 = 551, H_SPR_EPCR40 = 552 + , H_SPR_EPCR41 = 553, H_SPR_EPCR42 = 554, H_SPR_EPCR43 = 555, H_SPR_EPCR44 = 556 + , H_SPR_EPCR45 = 557, H_SPR_EPCR46 = 558, H_SPR_EPCR47 = 559, H_SPR_EPCR48 = 560 + , H_SPR_EPCR49 = 561, H_SPR_EPCR50 = 562, H_SPR_EPCR51 = 563, H_SPR_EPCR52 = 564 + , H_SPR_EPCR53 = 565, H_SPR_EPCR54 = 566, H_SPR_EPCR55 = 567, H_SPR_EPCR56 = 568 + , H_SPR_EPCR57 = 569, H_SPR_EPCR58 = 570, H_SPR_EPCR59 = 571, H_SPR_EPCR60 = 572 + , H_SPR_EPCR61 = 573, H_SPR_EPCR62 = 574, H_SPR_EPCR63 = 575, H_SPR_ESR0 = 576 + , H_SPR_ESR1 = 577, H_SPR_ESR2 = 578, H_SPR_ESR3 = 579, H_SPR_ESR4 = 580 + , H_SPR_ESR5 = 581, H_SPR_ESR6 = 582, H_SPR_ESR7 = 583, H_SPR_ESR8 = 584 + , H_SPR_ESR9 = 585, H_SPR_ESR10 = 586, H_SPR_ESR11 = 587, H_SPR_ESR12 = 588 + , H_SPR_ESR13 = 589, H_SPR_ESR14 = 590, H_SPR_ESR15 = 591, H_SPR_ESR16 = 592 + , H_SPR_ESR17 = 593, H_SPR_ESR18 = 594, H_SPR_ESR19 = 595, H_SPR_ESR20 = 596 + , H_SPR_ESR21 = 597, H_SPR_ESR22 = 598, H_SPR_ESR23 = 599, H_SPR_ESR24 = 600 + , H_SPR_ESR25 = 601, H_SPR_ESR26 = 602, H_SPR_ESR27 = 603, H_SPR_ESR28 = 604 + , H_SPR_ESR29 = 605, H_SPR_ESR30 = 606, H_SPR_ESR31 = 607, H_SPR_ESR32 = 608 + , H_SPR_ESR33 = 609, H_SPR_ESR34 = 610, H_SPR_ESR35 = 611, H_SPR_ESR36 = 612 + , H_SPR_ESR37 = 613, H_SPR_ESR38 = 614, H_SPR_ESR39 = 615, H_SPR_ESR40 = 616 + , H_SPR_ESR41 = 617, H_SPR_ESR42 = 618, H_SPR_ESR43 = 619, H_SPR_ESR44 = 620 + , H_SPR_ESR45 = 621, H_SPR_ESR46 = 622, H_SPR_ESR47 = 623, H_SPR_ESR48 = 624 + , H_SPR_ESR49 = 625, H_SPR_ESR50 = 626, H_SPR_ESR51 = 627, H_SPR_ESR52 = 628 + , H_SPR_ESR53 = 629, H_SPR_ESR54 = 630, H_SPR_ESR55 = 631, H_SPR_ESR56 = 632 + , H_SPR_ESR57 = 633, H_SPR_ESR58 = 634, H_SPR_ESR59 = 635, H_SPR_ESR60 = 636 + , H_SPR_ESR61 = 637, H_SPR_ESR62 = 638, H_SPR_ESR63 = 639, H_SPR_EIR0 = 640 + , H_SPR_EIR1 = 641, H_SPR_EIR2 = 642, H_SPR_EIR3 = 643, H_SPR_EIR4 = 644 + , H_SPR_EIR5 = 645, H_SPR_EIR6 = 646, H_SPR_EIR7 = 647, H_SPR_EIR8 = 648 + , H_SPR_EIR9 = 649, H_SPR_EIR10 = 650, H_SPR_EIR11 = 651, H_SPR_EIR12 = 652 + , H_SPR_EIR13 = 653, H_SPR_EIR14 = 654, H_SPR_EIR15 = 655, H_SPR_EIR16 = 656 + , H_SPR_EIR17 = 657, H_SPR_EIR18 = 658, H_SPR_EIR19 = 659, H_SPR_EIR20 = 660 + , H_SPR_EIR21 = 661, H_SPR_EIR22 = 662, H_SPR_EIR23 = 663, H_SPR_EIR24 = 664 + , H_SPR_EIR25 = 665, H_SPR_EIR26 = 666, H_SPR_EIR27 = 667, H_SPR_EIR28 = 668 + , H_SPR_EIR29 = 669, H_SPR_EIR30 = 670, H_SPR_EIR31 = 671, H_SPR_ESFR0 = 672 + , H_SPR_ESFR1 = 673, H_SPR_SR0 = 768, H_SPR_SR1 = 769, H_SPR_SR2 = 770 + , H_SPR_SR3 = 771, H_SPR_FSR0 = 1024, H_SPR_FSR1 = 1025, H_SPR_FSR2 = 1026 + , H_SPR_FSR3 = 1027, H_SPR_FSR4 = 1028, H_SPR_FSR5 = 1029, H_SPR_FSR6 = 1030 + , H_SPR_FSR7 = 1031, H_SPR_FSR8 = 1032, H_SPR_FSR9 = 1033, H_SPR_FSR10 = 1034 + , H_SPR_FSR11 = 1035, H_SPR_FSR12 = 1036, H_SPR_FSR13 = 1037, H_SPR_FSR14 = 1038 + , H_SPR_FSR15 = 1039, H_SPR_FSR16 = 1040, H_SPR_FSR17 = 1041, H_SPR_FSR18 = 1042 + , H_SPR_FSR19 = 1043, H_SPR_FSR20 = 1044, H_SPR_FSR21 = 1045, H_SPR_FSR22 = 1046 + , H_SPR_FSR23 = 1047, H_SPR_FSR24 = 1048, H_SPR_FSR25 = 1049, H_SPR_FSR26 = 1050 + , H_SPR_FSR27 = 1051, H_SPR_FSR28 = 1052, H_SPR_FSR29 = 1053, H_SPR_FSR30 = 1054 + , H_SPR_FSR31 = 1055, H_SPR_FSR32 = 1056, H_SPR_FSR33 = 1057, H_SPR_FSR34 = 1058 + , H_SPR_FSR35 = 1059, H_SPR_FSR36 = 1060, H_SPR_FSR37 = 1061, H_SPR_FSR38 = 1062 + , H_SPR_FSR39 = 1063, H_SPR_FSR40 = 1064, H_SPR_FSR41 = 1065, H_SPR_FSR42 = 1066 + , H_SPR_FSR43 = 1067, H_SPR_FSR44 = 1068, H_SPR_FSR45 = 1069, H_SPR_FSR46 = 1070 + , H_SPR_FSR47 = 1071, H_SPR_FSR48 = 1072, H_SPR_FSR49 = 1073, H_SPR_FSR50 = 1074 + , H_SPR_FSR51 = 1075, H_SPR_FSR52 = 1076, H_SPR_FSR53 = 1077, H_SPR_FSR54 = 1078 + , H_SPR_FSR55 = 1079, H_SPR_FSR56 = 1080, H_SPR_FSR57 = 1081, H_SPR_FSR58 = 1082 + , H_SPR_FSR59 = 1083, H_SPR_FSR60 = 1084, H_SPR_FSR61 = 1085, H_SPR_FSR62 = 1086 + , H_SPR_FSR63 = 1087, H_SPR_FQOP0 = 1088, H_SPR_FQOP1 = 1090, H_SPR_FQOP2 = 1092 + , H_SPR_FQOP3 = 1094, H_SPR_FQOP4 = 1096, H_SPR_FQOP5 = 1098, H_SPR_FQOP6 = 1100 + , H_SPR_FQOP7 = 1102, H_SPR_FQOP8 = 1104, H_SPR_FQOP9 = 1106, H_SPR_FQOP10 = 1108 + , H_SPR_FQOP11 = 1110, H_SPR_FQOP12 = 1112, H_SPR_FQOP13 = 1114, H_SPR_FQOP14 = 1116 + , H_SPR_FQOP15 = 1118, H_SPR_FQOP16 = 1120, H_SPR_FQOP17 = 1122, H_SPR_FQOP18 = 1124 + , H_SPR_FQOP19 = 1126, H_SPR_FQOP20 = 1128, H_SPR_FQOP21 = 1130, H_SPR_FQOP22 = 1132 + , H_SPR_FQOP23 = 1134, H_SPR_FQOP24 = 1136, H_SPR_FQOP25 = 1138, H_SPR_FQOP26 = 1140 + , H_SPR_FQOP27 = 1142, H_SPR_FQOP28 = 1144, H_SPR_FQOP29 = 1146, H_SPR_FQOP30 = 1148 + , H_SPR_FQOP31 = 1150, H_SPR_FQST0 = 1089, H_SPR_FQST1 = 1091, H_SPR_FQST2 = 1093 + , H_SPR_FQST3 = 1095, H_SPR_FQST4 = 1097, H_SPR_FQST5 = 1099, H_SPR_FQST6 = 1101 + , H_SPR_FQST7 = 1103, H_SPR_FQST8 = 1105, H_SPR_FQST9 = 1107, H_SPR_FQST10 = 1109 + , H_SPR_FQST11 = 1111, H_SPR_FQST12 = 1113, H_SPR_FQST13 = 1115, H_SPR_FQST14 = 1117 + , H_SPR_FQST15 = 1119, H_SPR_FQST16 = 1121, H_SPR_FQST17 = 1123, H_SPR_FQST18 = 1125 + , H_SPR_FQST19 = 1127, H_SPR_FQST20 = 1129, H_SPR_FQST21 = 1131, H_SPR_FQST22 = 1133 + , H_SPR_FQST23 = 1135, H_SPR_FQST24 = 1137, H_SPR_FQST25 = 1139, H_SPR_FQST26 = 1141 + , H_SPR_FQST27 = 1143, H_SPR_FQST28 = 1145, H_SPR_FQST29 = 1147, H_SPR_FQST30 = 1149 + , H_SPR_FQST31 = 1151, H_SPR_MCILR0 = 1272, H_SPR_MCILR1 = 1273, H_SPR_MSR0 = 1280 + , H_SPR_MSR1 = 1281, H_SPR_MSR2 = 1282, H_SPR_MSR3 = 1283, H_SPR_MSR4 = 1284 + , H_SPR_MSR5 = 1285, H_SPR_MSR6 = 1286, H_SPR_MSR7 = 1287, H_SPR_MSR8 = 1288 + , H_SPR_MSR9 = 1289, H_SPR_MSR10 = 1290, H_SPR_MSR11 = 1291, H_SPR_MSR12 = 1292 + , H_SPR_MSR13 = 1293, H_SPR_MSR14 = 1294, H_SPR_MSR15 = 1295, H_SPR_MSR16 = 1296 + , H_SPR_MSR17 = 1297, H_SPR_MSR18 = 1298, H_SPR_MSR19 = 1299, H_SPR_MSR20 = 1300 + , H_SPR_MSR21 = 1301, H_SPR_MSR22 = 1302, H_SPR_MSR23 = 1303, H_SPR_MSR24 = 1304 + , H_SPR_MSR25 = 1305, H_SPR_MSR26 = 1306, H_SPR_MSR27 = 1307, H_SPR_MSR28 = 1308 + , H_SPR_MSR29 = 1309, H_SPR_MSR30 = 1310, H_SPR_MSR31 = 1311, H_SPR_MSR32 = 1312 + , H_SPR_MSR33 = 1313, H_SPR_MSR34 = 1314, H_SPR_MSR35 = 1315, H_SPR_MSR36 = 1316 + , H_SPR_MSR37 = 1317, H_SPR_MSR38 = 1318, H_SPR_MSR39 = 1319, H_SPR_MSR40 = 1320 + , H_SPR_MSR41 = 1321, H_SPR_MSR42 = 1322, H_SPR_MSR43 = 1323, H_SPR_MSR44 = 1324 + , H_SPR_MSR45 = 1325, H_SPR_MSR46 = 1326, H_SPR_MSR47 = 1327, H_SPR_MSR48 = 1328 + , H_SPR_MSR49 = 1329, H_SPR_MSR50 = 1330, H_SPR_MSR51 = 1331, H_SPR_MSR52 = 1332 + , H_SPR_MSR53 = 1333, H_SPR_MSR54 = 1334, H_SPR_MSR55 = 1335, H_SPR_MSR56 = 1336 + , H_SPR_MSR57 = 1337, H_SPR_MSR58 = 1338, H_SPR_MSR59 = 1339, H_SPR_MSR60 = 1340 + , H_SPR_MSR61 = 1341, H_SPR_MSR62 = 1342, H_SPR_MSR63 = 1343, H_SPR_MQOP0 = 1344 + , H_SPR_MQOP1 = 1346, H_SPR_MQOP2 = 1348, H_SPR_MQOP3 = 1350, H_SPR_MQOP4 = 1352 + , H_SPR_MQOP5 = 1354, H_SPR_MQOP6 = 1356, H_SPR_MQOP7 = 1358, H_SPR_MQOP8 = 1360 + , H_SPR_MQOP9 = 1362, H_SPR_MQOP10 = 1364, H_SPR_MQOP11 = 1366, H_SPR_MQOP12 = 1368 + , H_SPR_MQOP13 = 1370, H_SPR_MQOP14 = 1372, H_SPR_MQOP15 = 1374, H_SPR_MQOP16 = 1376 + , H_SPR_MQOP17 = 1378, H_SPR_MQOP18 = 1380, H_SPR_MQOP19 = 1382, H_SPR_MQOP20 = 1384 + , H_SPR_MQOP21 = 1386, H_SPR_MQOP22 = 1388, H_SPR_MQOP23 = 1390, H_SPR_MQOP24 = 1392 + , H_SPR_MQOP25 = 1394, H_SPR_MQOP26 = 1396, H_SPR_MQOP27 = 1398, H_SPR_MQOP28 = 1400 + , H_SPR_MQOP29 = 1402, H_SPR_MQOP30 = 1404, H_SPR_MQOP31 = 1406, H_SPR_MQST0 = 1345 + , H_SPR_MQST1 = 1347, H_SPR_MQST2 = 1349, H_SPR_MQST3 = 1351, H_SPR_MQST4 = 1353 + , H_SPR_MQST5 = 1355, H_SPR_MQST6 = 1357, H_SPR_MQST7 = 1359, H_SPR_MQST8 = 1361 + , H_SPR_MQST9 = 1363, H_SPR_MQST10 = 1365, H_SPR_MQST11 = 1367, H_SPR_MQST12 = 1369 + , H_SPR_MQST13 = 1371, H_SPR_MQST14 = 1373, H_SPR_MQST15 = 1375, H_SPR_MQST16 = 1377 + , H_SPR_MQST17 = 1379, H_SPR_MQST18 = 1381, H_SPR_MQST19 = 1383, H_SPR_MQST20 = 1385 + , H_SPR_MQST21 = 1387, H_SPR_MQST22 = 1389, H_SPR_MQST23 = 1391, H_SPR_MQST24 = 1393 + , H_SPR_MQST25 = 1395, H_SPR_MQST26 = 1397, H_SPR_MQST27 = 1399, H_SPR_MQST28 = 1401 + , H_SPR_MQST29 = 1403, H_SPR_MQST30 = 1405, H_SPR_MQST31 = 1407, H_SPR_EAR0 = 1536 + , H_SPR_EAR1 = 1537, H_SPR_EAR2 = 1538, H_SPR_EAR3 = 1539, H_SPR_EAR4 = 1540 + , H_SPR_EAR5 = 1541, H_SPR_EAR6 = 1542, H_SPR_EAR7 = 1543, H_SPR_EAR8 = 1544 + , H_SPR_EAR9 = 1545, H_SPR_EAR10 = 1546, H_SPR_EAR11 = 1547, H_SPR_EAR12 = 1548 + , H_SPR_EAR13 = 1549, H_SPR_EAR14 = 1550, H_SPR_EAR15 = 1551, H_SPR_EAR16 = 1552 + , H_SPR_EAR17 = 1553, H_SPR_EAR18 = 1554, H_SPR_EAR19 = 1555, H_SPR_EAR20 = 1556 + , H_SPR_EAR21 = 1557, H_SPR_EAR22 = 1558, H_SPR_EAR23 = 1559, H_SPR_EAR24 = 1560 + , H_SPR_EAR25 = 1561, H_SPR_EAR26 = 1562, H_SPR_EAR27 = 1563, H_SPR_EAR28 = 1564 + , H_SPR_EAR29 = 1565, H_SPR_EAR30 = 1566, H_SPR_EAR31 = 1567, H_SPR_EAR32 = 1568 + , H_SPR_EAR33 = 1569, H_SPR_EAR34 = 1570, H_SPR_EAR35 = 1571, H_SPR_EAR36 = 1572 + , H_SPR_EAR37 = 1573, H_SPR_EAR38 = 1574, H_SPR_EAR39 = 1575, H_SPR_EAR40 = 1576 + , H_SPR_EAR41 = 1577, H_SPR_EAR42 = 1578, H_SPR_EAR43 = 1579, H_SPR_EAR44 = 1580 + , H_SPR_EAR45 = 1581, H_SPR_EAR46 = 1582, H_SPR_EAR47 = 1583, H_SPR_EAR48 = 1584 + , H_SPR_EAR49 = 1585, H_SPR_EAR50 = 1586, H_SPR_EAR51 = 1587, H_SPR_EAR52 = 1588 + , H_SPR_EAR53 = 1589, H_SPR_EAR54 = 1590, H_SPR_EAR55 = 1591, H_SPR_EAR56 = 1592 + , H_SPR_EAR57 = 1593, H_SPR_EAR58 = 1594, H_SPR_EAR59 = 1595, H_SPR_EAR60 = 1596 + , H_SPR_EAR61 = 1597, H_SPR_EAR62 = 1598, H_SPR_EAR63 = 1599, H_SPR_EDR0 = 1600 + , H_SPR_EDR1 = 1601, H_SPR_EDR2 = 1602, H_SPR_EDR3 = 1603, H_SPR_EDR4 = 1604 + , H_SPR_EDR5 = 1605, H_SPR_EDR6 = 1606, H_SPR_EDR7 = 1607, H_SPR_EDR8 = 1608 + , H_SPR_EDR9 = 1609, H_SPR_EDR10 = 1610, H_SPR_EDR11 = 1611, H_SPR_EDR12 = 1612 + , H_SPR_EDR13 = 1613, H_SPR_EDR14 = 1614, H_SPR_EDR15 = 1615, H_SPR_EDR16 = 1616 + , H_SPR_EDR17 = 1617, H_SPR_EDR18 = 1618, H_SPR_EDR19 = 1619, H_SPR_EDR20 = 1620 + , H_SPR_EDR21 = 1621, H_SPR_EDR22 = 1622, H_SPR_EDR23 = 1623, H_SPR_EDR24 = 1624 + , H_SPR_EDR25 = 1625, H_SPR_EDR26 = 1626, H_SPR_EDR27 = 1627, H_SPR_EDR28 = 1628 + , H_SPR_EDR29 = 1629, H_SPR_EDR30 = 1630, H_SPR_EDR31 = 1631, H_SPR_EDR32 = 1632 + , H_SPR_EDR33 = 1636, H_SPR_EDR34 = 1634, H_SPR_EDR35 = 1635, H_SPR_EDR36 = 1636 + , H_SPR_EDR37 = 1637, H_SPR_EDR38 = 1638, H_SPR_EDR39 = 1639, H_SPR_EDR40 = 1640 + , H_SPR_EDR41 = 1641, H_SPR_EDR42 = 1642, H_SPR_EDR43 = 1643, H_SPR_EDR44 = 1644 + , H_SPR_EDR45 = 1645, H_SPR_EDR46 = 1646, H_SPR_EDR47 = 1647, H_SPR_EDR48 = 1648 + , H_SPR_EDR49 = 1649, H_SPR_EDR50 = 1650, H_SPR_EDR51 = 1651, H_SPR_EDR52 = 1652 + , H_SPR_EDR53 = 1653, H_SPR_EDR54 = 1654, H_SPR_EDR55 = 1655, H_SPR_EDR56 = 1656 + , H_SPR_EDR57 = 1657, H_SPR_EDR58 = 1658, H_SPR_EDR59 = 1659, H_SPR_EDR60 = 1660 + , H_SPR_EDR61 = 1661, H_SPR_EDR62 = 1662, H_SPR_EDR63 = 1663, H_SPR_IAMLR0 = 1664 + , H_SPR_IAMLR1 = 1665, H_SPR_IAMLR2 = 1666, H_SPR_IAMLR3 = 1667, H_SPR_IAMLR4 = 1668 + , H_SPR_IAMLR5 = 1669, H_SPR_IAMLR6 = 1670, H_SPR_IAMLR7 = 1671, H_SPR_IAMLR8 = 1672 + , H_SPR_IAMLR9 = 1673, H_SPR_IAMLR10 = 1674, H_SPR_IAMLR11 = 1675, H_SPR_IAMLR12 = 1676 + , H_SPR_IAMLR13 = 1677, H_SPR_IAMLR14 = 1678, H_SPR_IAMLR15 = 1679, H_SPR_IAMLR16 = 1680 + , H_SPR_IAMLR17 = 1681, H_SPR_IAMLR18 = 1682, H_SPR_IAMLR19 = 1683, H_SPR_IAMLR20 = 1684 + , H_SPR_IAMLR21 = 1685, H_SPR_IAMLR22 = 1686, H_SPR_IAMLR23 = 1687, H_SPR_IAMLR24 = 1688 + , H_SPR_IAMLR25 = 1689, H_SPR_IAMLR26 = 1690, H_SPR_IAMLR27 = 1691, H_SPR_IAMLR28 = 1692 + , H_SPR_IAMLR29 = 1693, H_SPR_IAMLR30 = 1694, H_SPR_IAMLR31 = 1695, H_SPR_IAMLR32 = 1696 + , H_SPR_IAMLR33 = 1697, H_SPR_IAMLR34 = 1698, H_SPR_IAMLR35 = 1699, H_SPR_IAMLR36 = 1700 + , H_SPR_IAMLR37 = 1701, H_SPR_IAMLR38 = 1702, H_SPR_IAMLR39 = 1703, H_SPR_IAMLR40 = 1704 + , H_SPR_IAMLR41 = 1705, H_SPR_IAMLR42 = 1706, H_SPR_IAMLR43 = 1707, H_SPR_IAMLR44 = 1708 + , H_SPR_IAMLR45 = 1709, H_SPR_IAMLR46 = 1710, H_SPR_IAMLR47 = 1711, H_SPR_IAMLR48 = 1712 + , H_SPR_IAMLR49 = 1713, H_SPR_IAMLR50 = 1714, H_SPR_IAMLR51 = 1715, H_SPR_IAMLR52 = 1716 + , H_SPR_IAMLR53 = 1717, H_SPR_IAMLR54 = 1718, H_SPR_IAMLR55 = 1719, H_SPR_IAMLR56 = 1720 + , H_SPR_IAMLR57 = 1721, H_SPR_IAMLR58 = 1722, H_SPR_IAMLR59 = 1723, H_SPR_IAMLR60 = 1724 + , H_SPR_IAMLR61 = 1725, H_SPR_IAMLR62 = 1726, H_SPR_IAMLR63 = 1727, H_SPR_IAMPR0 = 1728 + , H_SPR_IAMPR1 = 1729, H_SPR_IAMPR2 = 1730, H_SPR_IAMPR3 = 1731, H_SPR_IAMPR4 = 1732 + , H_SPR_IAMPR5 = 1733, H_SPR_IAMPR6 = 1734, H_SPR_IAMPR7 = 1735, H_SPR_IAMPR8 = 1736 + , H_SPR_IAMPR9 = 1737, H_SPR_IAMPR10 = 1738, H_SPR_IAMPR11 = 1739, H_SPR_IAMPR12 = 1740 + , H_SPR_IAMPR13 = 1741, H_SPR_IAMPR14 = 1742, H_SPR_IAMPR15 = 1743, H_SPR_IAMPR16 = 1744 + , H_SPR_IAMPR17 = 1745, H_SPR_IAMPR18 = 1746, H_SPR_IAMPR19 = 1747, H_SPR_IAMPR20 = 1748 + , H_SPR_IAMPR21 = 1749, H_SPR_IAMPR22 = 1750, H_SPR_IAMPR23 = 1751, H_SPR_IAMPR24 = 1752 + , H_SPR_IAMPR25 = 1753, H_SPR_IAMPR26 = 1754, H_SPR_IAMPR27 = 1755, H_SPR_IAMPR28 = 1756 + , H_SPR_IAMPR29 = 1757, H_SPR_IAMPR30 = 1758, H_SPR_IAMPR31 = 1759, H_SPR_IAMPR32 = 1760 + , H_SPR_IAMPR33 = 1761, H_SPR_IAMPR34 = 1762, H_SPR_IAMPR35 = 1763, H_SPR_IAMPR36 = 1764 + , H_SPR_IAMPR37 = 1765, H_SPR_IAMPR38 = 1766, H_SPR_IAMPR39 = 1767, H_SPR_IAMPR40 = 1768 + , H_SPR_IAMPR41 = 1769, H_SPR_IAMPR42 = 1770, H_SPR_IAMPR43 = 1771, H_SPR_IAMPR44 = 1772 + , H_SPR_IAMPR45 = 1773, H_SPR_IAMPR46 = 1774, H_SPR_IAMPR47 = 1775, H_SPR_IAMPR48 = 1776 + , H_SPR_IAMPR49 = 1777, H_SPR_IAMPR50 = 1778, H_SPR_IAMPR51 = 1779, H_SPR_IAMPR52 = 1780 + , H_SPR_IAMPR53 = 1781, H_SPR_IAMPR54 = 1782, H_SPR_IAMPR55 = 1783, H_SPR_IAMPR56 = 1784 + , H_SPR_IAMPR57 = 1785, H_SPR_IAMPR58 = 1786, H_SPR_IAMPR59 = 1787, H_SPR_IAMPR60 = 1788 + , H_SPR_IAMPR61 = 1789, H_SPR_IAMPR62 = 1790, H_SPR_IAMPR63 = 1791, H_SPR_DAMLR0 = 1792 + , H_SPR_DAMLR1 = 1793, H_SPR_DAMLR2 = 1794, H_SPR_DAMLR3 = 1795, H_SPR_DAMLR4 = 1796 + , H_SPR_DAMLR5 = 1797, H_SPR_DAMLR6 = 1798, H_SPR_DAMLR7 = 1799, H_SPR_DAMLR8 = 1800 + , H_SPR_DAMLR9 = 1801, H_SPR_DAMLR10 = 1802, H_SPR_DAMLR11 = 1803, H_SPR_DAMLR12 = 1804 + , H_SPR_DAMLR13 = 1805, H_SPR_DAMLR14 = 1806, H_SPR_DAMLR15 = 1807, H_SPR_DAMLR16 = 1808 + , H_SPR_DAMLR17 = 1809, H_SPR_DAMLR18 = 1810, H_SPR_DAMLR19 = 1811, H_SPR_DAMLR20 = 1812 + , H_SPR_DAMLR21 = 1813, H_SPR_DAMLR22 = 1814, H_SPR_DAMLR23 = 1815, H_SPR_DAMLR24 = 1816 + , H_SPR_DAMLR25 = 1817, H_SPR_DAMLR26 = 1818, H_SPR_DAMLR27 = 1819, H_SPR_DAMLR28 = 1820 + , H_SPR_DAMLR29 = 1821, H_SPR_DAMLR30 = 1822, H_SPR_DAMLR31 = 1823, H_SPR_DAMLR32 = 1824 + , H_SPR_DAMLR33 = 1825, H_SPR_DAMLR34 = 1826, H_SPR_DAMLR35 = 1827, H_SPR_DAMLR36 = 1828 + , H_SPR_DAMLR37 = 1829, H_SPR_DAMLR38 = 1830, H_SPR_DAMLR39 = 1831, H_SPR_DAMLR40 = 1832 + , H_SPR_DAMLR41 = 1833, H_SPR_DAMLR42 = 1834, H_SPR_DAMLR43 = 1835, H_SPR_DAMLR44 = 1836 + , H_SPR_DAMLR45 = 1837, H_SPR_DAMLR46 = 1838, H_SPR_DAMLR47 = 1839, H_SPR_DAMLR48 = 1840 + , H_SPR_DAMLR49 = 1841, H_SPR_DAMLR50 = 1842, H_SPR_DAMLR51 = 1843, H_SPR_DAMLR52 = 1844 + , H_SPR_DAMLR53 = 1845, H_SPR_DAMLR54 = 1846, H_SPR_DAMLR55 = 1847, H_SPR_DAMLR56 = 1848 + , H_SPR_DAMLR57 = 1849, H_SPR_DAMLR58 = 1850, H_SPR_DAMLR59 = 1851, H_SPR_DAMLR60 = 1852 + , H_SPR_DAMLR61 = 1853, H_SPR_DAMLR62 = 1854, H_SPR_DAMLR63 = 1855, H_SPR_DAMPR0 = 1856 + , H_SPR_DAMPR1 = 1857, H_SPR_DAMPR2 = 1858, H_SPR_DAMPR3 = 1859, H_SPR_DAMPR4 = 1860 + , H_SPR_DAMPR5 = 1861, H_SPR_DAMPR6 = 1862, H_SPR_DAMPR7 = 1863, H_SPR_DAMPR8 = 1864 + , H_SPR_DAMPR9 = 1865, H_SPR_DAMPR10 = 1866, H_SPR_DAMPR11 = 1867, H_SPR_DAMPR12 = 1868 + , H_SPR_DAMPR13 = 1869, H_SPR_DAMPR14 = 1870, H_SPR_DAMPR15 = 1871, H_SPR_DAMPR16 = 1872 + , H_SPR_DAMPR17 = 1873, H_SPR_DAMPR18 = 1874, H_SPR_DAMPR19 = 1875, H_SPR_DAMPR20 = 1876 + , H_SPR_DAMPR21 = 1877, H_SPR_DAMPR22 = 1878, H_SPR_DAMPR23 = 1879, H_SPR_DAMPR24 = 1880 + , H_SPR_DAMPR25 = 1881, H_SPR_DAMPR26 = 1882, H_SPR_DAMPR27 = 1883, H_SPR_DAMPR28 = 1884 + , H_SPR_DAMPR29 = 1885, H_SPR_DAMPR30 = 1886, H_SPR_DAMPR31 = 1887, H_SPR_DAMPR32 = 1888 + , H_SPR_DAMPR33 = 1889, H_SPR_DAMPR34 = 1890, H_SPR_DAMPR35 = 1891, H_SPR_DAMPR36 = 1892 + , H_SPR_DAMPR37 = 1893, H_SPR_DAMPR38 = 1894, H_SPR_DAMPR39 = 1895, H_SPR_DAMPR40 = 1896 + , H_SPR_DAMPR41 = 1897, H_SPR_DAMPR42 = 1898, H_SPR_DAMPR43 = 1899, H_SPR_DAMPR44 = 1900 + , H_SPR_DAMPR45 = 1901, H_SPR_DAMPR46 = 1902, H_SPR_DAMPR47 = 1903, H_SPR_DAMPR48 = 1904 + , H_SPR_DAMPR49 = 1905, H_SPR_DAMPR50 = 1906, H_SPR_DAMPR51 = 1907, H_SPR_DAMPR52 = 1908 + , H_SPR_DAMPR53 = 1909, H_SPR_DAMPR54 = 1910, H_SPR_DAMPR55 = 1911, H_SPR_DAMPR56 = 1912 + , H_SPR_DAMPR57 = 1913, H_SPR_DAMPR58 = 1914, H_SPR_DAMPR59 = 1915, H_SPR_DAMPR60 = 1916 + , H_SPR_DAMPR61 = 1917, H_SPR_DAMPR62 = 1918, H_SPR_DAMPR63 = 1919, H_SPR_AMCR = 1920 + , H_SPR_STBAR = 1921, H_SPR_MMCR = 1922, H_SPR_DCR = 2048, H_SPR_BRR = 2049 + , H_SPR_NMAR = 2050, H_SPR_IBAR0 = 2052, H_SPR_IBAR1 = 2053, H_SPR_IBAR2 = 2054 + , H_SPR_IBAR3 = 2055, H_SPR_DBAR0 = 2056, H_SPR_DBAR1 = 2057, H_SPR_DBAR2 = 2058 + , H_SPR_DBAR3 = 2059, H_SPR_DBDR00 = 2060, H_SPR_DBDR01 = 2061, H_SPR_DBDR02 = 2062 + , H_SPR_DBDR03 = 2063, H_SPR_DBDR10 = 2064, H_SPR_DBDR11 = 2065, H_SPR_DBDR12 = 2066 + , H_SPR_DBDR13 = 2067, H_SPR_DBDR20 = 2068, H_SPR_DBDR21 = 2069, H_SPR_DBDR22 = 2070 + , H_SPR_DBDR23 = 2071, H_SPR_DBDR30 = 2072, H_SPR_DBDR31 = 2073, H_SPR_DBDR32 = 2074 + , H_SPR_DBDR33 = 2075, H_SPR_DBMR00 = 2076, H_SPR_DBMR01 = 2077, H_SPR_DBMR02 = 2078 + , H_SPR_DBMR03 = 2079, H_SPR_DBMR10 = 2080, H_SPR_DBMR11 = 2081, H_SPR_DBMR12 = 2082 + , H_SPR_DBMR13 = 2083, H_SPR_DBMR20 = 2084, H_SPR_DBMR21 = 2085, H_SPR_DBMR22 = 2086 + , H_SPR_DBMR23 = 2087, H_SPR_DBMR30 = 2088, H_SPR_DBMR31 = 2089, H_SPR_DBMR32 = 2090 + , H_SPR_DBMR33 = 2091, H_SPR_CPCFR = 2092, H_SPR_CPCR = 2093, H_SPR_CPSR = 2094 + , H_SPR_CPESR0 = 2096, H_SPR_CPESR1 = 2097, H_SPR_CPEMR0 = 2098, H_SPR_CPEMR1 = 2099 + , H_SPR_IHSR8 = 3848 +} SPR_NAMES; + +/* Enum declaration for . */ +typedef enum accg_names { + H_ACCG_ACCG0, H_ACCG_ACCG1, H_ACCG_ACCG2, H_ACCG_ACCG3 + , H_ACCG_ACCG4, H_ACCG_ACCG5, H_ACCG_ACCG6, H_ACCG_ACCG7 + , H_ACCG_ACCG8, H_ACCG_ACCG9, H_ACCG_ACCG10, H_ACCG_ACCG11 + , H_ACCG_ACCG12, H_ACCG_ACCG13, H_ACCG_ACCG14, H_ACCG_ACCG15 + , H_ACCG_ACCG16, H_ACCG_ACCG17, H_ACCG_ACCG18, H_ACCG_ACCG19 + , H_ACCG_ACCG20, H_ACCG_ACCG21, H_ACCG_ACCG22, H_ACCG_ACCG23 + , H_ACCG_ACCG24, H_ACCG_ACCG25, H_ACCG_ACCG26, H_ACCG_ACCG27 + , H_ACCG_ACCG28, H_ACCG_ACCG29, H_ACCG_ACCG30, H_ACCG_ACCG31 + , H_ACCG_ACCG32, H_ACCG_ACCG33, H_ACCG_ACCG34, H_ACCG_ACCG35 + , H_ACCG_ACCG36, H_ACCG_ACCG37, H_ACCG_ACCG38, H_ACCG_ACCG39 + , H_ACCG_ACCG40, H_ACCG_ACCG41, H_ACCG_ACCG42, H_ACCG_ACCG43 + , H_ACCG_ACCG44, H_ACCG_ACCG45, H_ACCG_ACCG46, H_ACCG_ACCG47 + , H_ACCG_ACCG48, H_ACCG_ACCG49, H_ACCG_ACCG50, H_ACCG_ACCG51 + , H_ACCG_ACCG52, H_ACCG_ACCG53, H_ACCG_ACCG54, H_ACCG_ACCG55 + , H_ACCG_ACCG56, H_ACCG_ACCG57, H_ACCG_ACCG58, H_ACCG_ACCG59 + , H_ACCG_ACCG60, H_ACCG_ACCG61, H_ACCG_ACCG62, H_ACCG_ACCG63 +} ACCG_NAMES; + +/* Enum declaration for . */ +typedef enum acc_names { + H_ACC40_ACC0, H_ACC40_ACC1, H_ACC40_ACC2, H_ACC40_ACC3 + , H_ACC40_ACC4, H_ACC40_ACC5, H_ACC40_ACC6, H_ACC40_ACC7 + , H_ACC40_ACC8, H_ACC40_ACC9, H_ACC40_ACC10, H_ACC40_ACC11 + , H_ACC40_ACC12, H_ACC40_ACC13, H_ACC40_ACC14, H_ACC40_ACC15 + , H_ACC40_ACC16, H_ACC40_ACC17, H_ACC40_ACC18, H_ACC40_ACC19 + , H_ACC40_ACC20, H_ACC40_ACC21, H_ACC40_ACC22, H_ACC40_ACC23 + , H_ACC40_ACC24, H_ACC40_ACC25, H_ACC40_ACC26, H_ACC40_ACC27 + , H_ACC40_ACC28, H_ACC40_ACC29, H_ACC40_ACC30, H_ACC40_ACC31 + , H_ACC40_ACC32, H_ACC40_ACC33, H_ACC40_ACC34, H_ACC40_ACC35 + , H_ACC40_ACC36, H_ACC40_ACC37, H_ACC40_ACC38, H_ACC40_ACC39 + , H_ACC40_ACC40, H_ACC40_ACC41, H_ACC40_ACC42, H_ACC40_ACC43 + , H_ACC40_ACC44, H_ACC40_ACC45, H_ACC40_ACC46, H_ACC40_ACC47 + , H_ACC40_ACC48, H_ACC40_ACC49, H_ACC40_ACC50, H_ACC40_ACC51 + , H_ACC40_ACC52, H_ACC40_ACC53, H_ACC40_ACC54, H_ACC40_ACC55 + , H_ACC40_ACC56, H_ACC40_ACC57, H_ACC40_ACC58, H_ACC40_ACC59 + , H_ACC40_ACC60, H_ACC40_ACC61, H_ACC40_ACC62, H_ACC40_ACC63 +} ACC_NAMES; + +/* Enum declaration for . */ +typedef enum iccr_names { + H_ICCR_ICC0, H_ICCR_ICC1, H_ICCR_ICC2, H_ICCR_ICC3 +} ICCR_NAMES; + +/* Enum declaration for . */ +typedef enum fccr_names { + H_FCCR_FCC0, H_FCCR_FCC1, H_FCCR_FCC2, H_FCCR_FCC3 +} FCCR_NAMES; + +/* Enum declaration for . */ +typedef enum cccr_names { + H_CCCR_CC0, H_CCCR_CC1, H_CCCR_CC2, H_CCCR_CC3 + , H_CCCR_CC4, H_CCCR_CC5, H_CCCR_CC6, H_CCCR_CC7 +} CCCR_NAMES; + +/* Attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_BASE, MACH_FRV, MACH_FR500, MACH_FR400 + , MACH_TOMCAT, MACH_SIMPLE, MACH_MAX +} MACH_ATTR; + +/* Enum declaration for instruction set selection. */ +typedef enum isa_attr { + ISA_FRV, ISA_MAX +} ISA_ATTR; + +/* Enum declaration for parallel execution pipeline selection. */ +typedef enum unit_attr { + UNIT_NIL, UNIT_I0, UNIT_I1, UNIT_I01 + , UNIT_FM0, UNIT_FM1, UNIT_FM01, UNIT_B0 + , UNIT_B1, UNIT_B01, UNIT_C, UNIT_MULT_DIV + , UNIT_LOAD, UNIT_NUM_UNITS +} UNIT_ATTR; + +/* Enum declaration for fr400 major insn categories. */ +typedef enum fr400_major_attr { + FR400_MAJOR_NONE, FR400_MAJOR_I_1, FR400_MAJOR_I_2, FR400_MAJOR_I_3 + , FR400_MAJOR_I_4, FR400_MAJOR_I_5, FR400_MAJOR_B_1, FR400_MAJOR_B_2 + , FR400_MAJOR_B_3, FR400_MAJOR_B_4, FR400_MAJOR_B_5, FR400_MAJOR_B_6 + , FR400_MAJOR_C_1, FR400_MAJOR_C_2, FR400_MAJOR_M_1, FR400_MAJOR_M_2 +} FR400_MAJOR_ATTR; + +/* Enum declaration for fr500 major insn categories. */ +typedef enum fr500_major_attr { + FR500_MAJOR_NONE, FR500_MAJOR_I_1, FR500_MAJOR_I_2, FR500_MAJOR_I_3 + , FR500_MAJOR_I_4, FR500_MAJOR_I_5, FR500_MAJOR_I_6, FR500_MAJOR_B_1 + , FR500_MAJOR_B_2, FR500_MAJOR_B_3, FR500_MAJOR_B_4, FR500_MAJOR_B_5 + , FR500_MAJOR_B_6, FR500_MAJOR_C_1, FR500_MAJOR_C_2, FR500_MAJOR_F_1 + , FR500_MAJOR_F_2, FR500_MAJOR_F_3, FR500_MAJOR_F_4, FR500_MAJOR_F_5 + , FR500_MAJOR_F_6, FR500_MAJOR_F_7, FR500_MAJOR_F_8, FR500_MAJOR_M_1 + , FR500_MAJOR_M_2, FR500_MAJOR_M_3, FR500_MAJOR_M_4, FR500_MAJOR_M_5 + , FR500_MAJOR_M_6, FR500_MAJOR_M_7, FR500_MAJOR_M_8 +} FR500_MAJOR_ATTR; + +/* Number of architecture variants. */ +#define MAX_ISAS 1 +#define MAX_MACHS ((int) MACH_MAX) + +/* Ifield support. */ + +extern const struct cgen_ifld frv_cgen_ifld_table[]; + +/* Ifield attribute indices. */ + +/* Enum declaration for cgen_ifld attrs. */ +typedef enum cgen_ifld_attr { + CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 + , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS +} CGEN_IFLD_ATTR; + +/* Number of non-boolean elements in cgen_ifld_attr. */ +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) + +/* Enum declaration for frv ifield types. */ +typedef enum ifield_type { + FRV_F_NIL, FRV_F_ANYOF, FRV_F_PACK, FRV_F_OP + , FRV_F_OPE1, FRV_F_OPE2, FRV_F_OPE3, FRV_F_OPE4 + , FRV_F_GRI, FRV_F_GRJ, FRV_F_GRK, FRV_F_FRI + , FRV_F_FRJ, FRV_F_FRK, FRV_F_CPRI, FRV_F_CPRJ + , FRV_F_CPRK, FRV_F_ACCGI, FRV_F_ACCGK, FRV_F_ACC40SI + , FRV_F_ACC40UI, FRV_F_ACC40SK, FRV_F_ACC40UK, FRV_F_CRI + , FRV_F_CRJ, FRV_F_CRK, FRV_F_CCI, FRV_F_CRJ_INT + , FRV_F_CRJ_FLOAT, FRV_F_ICCI_1, FRV_F_ICCI_2, FRV_F_ICCI_3 + , FRV_F_FCCI_1, FRV_F_FCCI_2, FRV_F_FCCI_3, FRV_F_FCCK + , FRV_F_EIR, FRV_F_S10, FRV_F_S12, FRV_F_D12 + , FRV_F_U16, FRV_F_S16, FRV_F_S6, FRV_F_S6_1 + , FRV_F_U6, FRV_F_S5, FRV_F_U12_H, FRV_F_U12_L + , FRV_F_U12, FRV_F_INT_CC, FRV_F_FLT_CC, FRV_F_COND + , FRV_F_CCOND, FRV_F_HINT, FRV_F_LI, FRV_F_LOCK + , FRV_F_DEBUG, FRV_F_A, FRV_F_AE, FRV_F_SPR_H + , FRV_F_SPR_L, FRV_F_SPR, FRV_F_LABEL16, FRV_F_LABELH6 + , FRV_F_LABELL18, FRV_F_LABEL24, FRV_F_ICCI_1_NULL, FRV_F_ICCI_2_NULL + , FRV_F_ICCI_3_NULL, FRV_F_FCCI_1_NULL, FRV_F_FCCI_2_NULL, FRV_F_FCCI_3_NULL + , FRV_F_RS_NULL, FRV_F_GRI_NULL, FRV_F_GRJ_NULL, FRV_F_GRK_NULL + , FRV_F_FRI_NULL, FRV_F_FRJ_NULL, FRV_F_ACCJ_NULL, FRV_F_RD_NULL + , FRV_F_COND_NULL, FRV_F_CCOND_NULL, FRV_F_S12_NULL, FRV_F_LABEL16_NULL + , FRV_F_MISC_NULL_1, FRV_F_MISC_NULL_2, FRV_F_MISC_NULL_3, FRV_F_MISC_NULL_4 + , FRV_F_MISC_NULL_5, FRV_F_MISC_NULL_6, FRV_F_MISC_NULL_7, FRV_F_MISC_NULL_8 + , FRV_F_MISC_NULL_9, FRV_F_MISC_NULL_10, FRV_F_MISC_NULL_11, FRV_F_LI_OFF + , FRV_F_LI_ON, FRV_F_MAX +} IFIELD_TYPE; + +#define MAX_IFLD ((int) FRV_F_MAX) + +/* Hardware attribute indices. */ + +/* Enum declaration for cgen_hw attrs. */ +typedef enum cgen_hw_attr { + CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE + , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS +} CGEN_HW_ATTR; + +/* Number of non-boolean elements in cgen_hw_attr. */ +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) + +/* Enum declaration for frv hardware types. */ +typedef enum cgen_hw_type { + HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR + , HW_H_IADDR, HW_H_PC, HW_H_PSR_IMPLE, HW_H_PSR_VER + , HW_H_PSR_ICE, HW_H_PSR_NEM, HW_H_PSR_CM, HW_H_PSR_BE + , HW_H_PSR_ESR, HW_H_PSR_EF, HW_H_PSR_EM, HW_H_PSR_PIL + , HW_H_PSR_PS, HW_H_PSR_ET, HW_H_PSR_S, HW_H_TBR_TBA + , HW_H_TBR_TT, HW_H_BPSR_BS, HW_H_BPSR_BET, HW_H_GR + , HW_H_GR_DOUBLE, HW_H_GR_HI, HW_H_GR_LO, HW_H_FR + , HW_H_FR_DOUBLE, HW_H_FR_INT, HW_H_FR_HI, HW_H_FR_LO + , HW_H_FR_0, HW_H_FR_1, HW_H_FR_2, HW_H_FR_3 + , HW_H_CPR, HW_H_CPR_DOUBLE, HW_H_SPR, HW_H_ACCG + , HW_H_ACC40S, HW_H_ACC40U, HW_H_ICCR, HW_H_FCCR + , HW_H_CCCR, HW_H_PACK, HW_H_HINT_TAKEN, HW_H_HINT_NOT_TAKEN + , HW_MAX +} CGEN_HW_TYPE; + +#define MAX_HW ((int) HW_MAX) + +/* Operand attribute indices. */ + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + , CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH + , CGEN_OPERAND_END_NBOOLS +} CGEN_OPERAND_ATTR; + +/* Number of non-boolean elements in cgen_operand_attr. */ +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) + +/* Enum declaration for frv operand types. */ +typedef enum cgen_operand_type { + FRV_OPERAND_PC, FRV_OPERAND_PACK, FRV_OPERAND_GRI, FRV_OPERAND_GRJ + , FRV_OPERAND_GRK, FRV_OPERAND_GRKHI, FRV_OPERAND_GRKLO, FRV_OPERAND_GRDOUBLEK + , FRV_OPERAND_ACC40SI, FRV_OPERAND_ACC40UI, FRV_OPERAND_ACC40SK, FRV_OPERAND_ACC40UK + , FRV_OPERAND_ACCGI, FRV_OPERAND_ACCGK, FRV_OPERAND_CPRI, FRV_OPERAND_CPRJ + , FRV_OPERAND_CPRK, FRV_OPERAND_CPRDOUBLEK, FRV_OPERAND_FRINTI, FRV_OPERAND_FRINTJ + , FRV_OPERAND_FRINTK, FRV_OPERAND_FRI, FRV_OPERAND_FRJ, FRV_OPERAND_FRK + , FRV_OPERAND_FRKHI, FRV_OPERAND_FRKLO, FRV_OPERAND_FRDOUBLEI, FRV_OPERAND_FRDOUBLEJ + , FRV_OPERAND_FRDOUBLEK, FRV_OPERAND_CRI, FRV_OPERAND_CRJ, FRV_OPERAND_CRJ_INT + , FRV_OPERAND_CRJ_FLOAT, FRV_OPERAND_CRK, FRV_OPERAND_CCI, FRV_OPERAND_ICCI_1 + , FRV_OPERAND_ICCI_2, FRV_OPERAND_ICCI_3, FRV_OPERAND_FCCI_1, FRV_OPERAND_FCCI_2 + , FRV_OPERAND_FCCI_3, FRV_OPERAND_FCCK, FRV_OPERAND_EIR, FRV_OPERAND_S10 + , FRV_OPERAND_U16, FRV_OPERAND_S16, FRV_OPERAND_S6, FRV_OPERAND_S6_1 + , FRV_OPERAND_U6, FRV_OPERAND_S5, FRV_OPERAND_COND, FRV_OPERAND_CCOND + , FRV_OPERAND_HINT, FRV_OPERAND_HINT_TAKEN, FRV_OPERAND_HINT_NOT_TAKEN, FRV_OPERAND_LI + , FRV_OPERAND_LOCK, FRV_OPERAND_DEBUG, FRV_OPERAND_A, FRV_OPERAND_AE + , FRV_OPERAND_LABEL16, FRV_OPERAND_LABEL24, FRV_OPERAND_D12, FRV_OPERAND_S12 + , FRV_OPERAND_U12, FRV_OPERAND_SPR, FRV_OPERAND_ULO16, FRV_OPERAND_SLO16 + , FRV_OPERAND_UHI16, FRV_OPERAND_PSR_ESR, FRV_OPERAND_PSR_S, FRV_OPERAND_PSR_PS + , FRV_OPERAND_PSR_ET, FRV_OPERAND_BPSR_BS, FRV_OPERAND_BPSR_BET, FRV_OPERAND_TBR_TBA + , FRV_OPERAND_TBR_TT, FRV_OPERAND_MAX +} CGEN_OPERAND_TYPE; + +/* Number of operands types. */ +#define MAX_OPERANDS 77 + +/* Maximum number of operands referenced by any insn. */ +#define MAX_OPERAND_INSTANCES 8 + +/* Insn attribute indices. */ + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_PRIVILEGED, CGEN_INSN_NON_EXCEPTING + , CGEN_INSN_CONDITIONAL, CGEN_INSN_FR_ACCESS, CGEN_INSN_PRESERVE_OVF, CGEN_INSN_END_BOOLS + , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_UNIT, CGEN_INSN_FR400_MAJOR + , CGEN_INSN_FR500_MAJOR, CGEN_INSN_END_NBOOLS +} CGEN_INSN_ATTR; + +/* Number of non-boolean elements in cgen_insn_attr. */ +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +/* Attributes. */ +extern const CGEN_ATTR_TABLE frv_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE frv_cgen_ifield_attr_table[]; +extern const CGEN_ATTR_TABLE frv_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE frv_cgen_insn_attr_table[]; + +/* Hardware decls. */ + +extern CGEN_KEYWORD frv_cgen_opval_gr_names; +extern CGEN_KEYWORD frv_cgen_opval_gr_names; +extern CGEN_KEYWORD frv_cgen_opval_gr_names; +extern CGEN_KEYWORD frv_cgen_opval_gr_names; +extern CGEN_KEYWORD frv_cgen_opval_fr_names; +extern CGEN_KEYWORD frv_cgen_opval_fr_names; +extern CGEN_KEYWORD frv_cgen_opval_fr_names; +extern CGEN_KEYWORD frv_cgen_opval_fr_names; +extern CGEN_KEYWORD frv_cgen_opval_fr_names; +extern CGEN_KEYWORD frv_cgen_opval_fr_names; +extern CGEN_KEYWORD frv_cgen_opval_fr_names; +extern CGEN_KEYWORD frv_cgen_opval_fr_names; +extern CGEN_KEYWORD frv_cgen_opval_fr_names; +extern CGEN_KEYWORD frv_cgen_opval_cpr_names; +extern CGEN_KEYWORD frv_cgen_opval_cpr_names; +extern CGEN_KEYWORD frv_cgen_opval_spr_names; +extern CGEN_KEYWORD frv_cgen_opval_accg_names; +extern CGEN_KEYWORD frv_cgen_opval_acc_names; +extern CGEN_KEYWORD frv_cgen_opval_acc_names; +extern CGEN_KEYWORD frv_cgen_opval_iccr_names; +extern CGEN_KEYWORD frv_cgen_opval_fccr_names; +extern CGEN_KEYWORD frv_cgen_opval_cccr_names; +extern CGEN_KEYWORD frv_cgen_opval_h_pack; +extern CGEN_KEYWORD frv_cgen_opval_h_hint_taken; +extern CGEN_KEYWORD frv_cgen_opval_h_hint_not_taken; + + + + +#endif /* FRV_CPU_H */ diff --git a/opcodes/frv-dis.c b/opcodes/frv-dis.c new file mode 100644 index 00000000000..a6378763868 --- /dev/null +++ b/opcodes/frv-dis.c @@ -0,0 +1,789 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +THIS FILE IS MACHINE GENERATED WITH CGEN. +- the resultant file is machine generated, cgen-dis.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include <stdio.h> +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "frv-desc.h" +#include "frv-opc.h" +#include "opintl.h" + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int)); +static void print_address + PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int)); +static void print_keyword + PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int)); +static void print_insn_normal + PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, + bfd_vma, int)); +static int print_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned)); +static int default_print_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); +static int read_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, + CGEN_EXTRACT_INFO *, unsigned long *)); + +/* -- disassembler routines inserted here */ + +/* -- dis.c */ +static void print_spr + PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned)); +static void print_hi + PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); +static void print_lo + PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); + +static void +print_spr (cd, dis_info, names, regno, attrs) + CGEN_CPU_DESC cd; + PTR dis_info; + CGEN_KEYWORD *names; + long regno; + unsigned int attrs; +{ + /* Use the register index format for any unnamed registers. */ + if (cgen_keyword_lookup_value (names, regno) == NULL) + { + disassemble_info *info = (disassemble_info *) dis_info; + (*info->fprintf_func) (info->stream, "spr[%ld]", regno); + } + else + print_keyword (cd, dis_info, names, regno, attrs); +} + +static void +print_hi (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + long value; + unsigned int attrs ATTRIBUTE_UNUSED; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + if (value) + (*info->fprintf_func) (info->stream, "0x%lx", value); + else + (*info->fprintf_func) (info->stream, "hi(0x%lx)", value); +} + +static void +print_lo (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + long value; + unsigned int attrs ATTRIBUTE_UNUSED; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + if (value) + (*info->fprintf_func) (info->stream, "0x%lx", value); + else + (*info->fprintf_func) (info->stream, "lo(0x%lx)", value); +} + +/* -- */ + +void frv_cgen_print_operand + PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, + void const *, bfd_vma, int)); + +/* Main entry point for printing operands. + XINFO is a `void *' and not a `disassemble_info *' to not put a requirement + of dis-asm.h on cgen.h. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +void +frv_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) + CGEN_CPU_DESC cd; + int opindex; + PTR xinfo; + CGEN_FIELDS *fields; + void const *attrs ATTRIBUTE_UNUSED; + bfd_vma pc; + int length; +{ + disassemble_info *info = (disassemble_info *) xinfo; + + switch (opindex) + { + case FRV_OPERAND_A : + print_normal (cd, info, fields->f_A, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); + break; + case FRV_OPERAND_ACC40SI : + print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Si, 0); + break; + case FRV_OPERAND_ACC40SK : + print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Sk, 0); + break; + case FRV_OPERAND_ACC40UI : + print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Ui, 0); + break; + case FRV_OPERAND_ACC40UK : + print_keyword (cd, info, & frv_cgen_opval_acc_names, fields->f_ACC40Uk, 0); + break; + case FRV_OPERAND_ACCGI : + print_keyword (cd, info, & frv_cgen_opval_accg_names, fields->f_ACCGi, 0); + break; + case FRV_OPERAND_ACCGK : + print_keyword (cd, info, & frv_cgen_opval_accg_names, fields->f_ACCGk, 0); + break; + case FRV_OPERAND_CCI : + print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CCi, 0); + break; + case FRV_OPERAND_CPRDOUBLEK : + print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRk, 0); + break; + case FRV_OPERAND_CPRI : + print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRi, 0); + break; + case FRV_OPERAND_CPRJ : + print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRj, 0); + break; + case FRV_OPERAND_CPRK : + print_keyword (cd, info, & frv_cgen_opval_cpr_names, fields->f_CPRk, 0); + break; + case FRV_OPERAND_CRI : + print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRi, 0); + break; + case FRV_OPERAND_CRJ : + print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRj, 0); + break; + case FRV_OPERAND_CRJ_FLOAT : + print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRj_float, 0); + break; + case FRV_OPERAND_CRJ_INT : + print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRj_int, 0); + break; + case FRV_OPERAND_CRK : + print_keyword (cd, info, & frv_cgen_opval_cccr_names, fields->f_CRk, 0); + break; + case FRV_OPERAND_FCCI_1 : + print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCi_1, 0); + break; + case FRV_OPERAND_FCCI_2 : + print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCi_2, 0); + break; + case FRV_OPERAND_FCCI_3 : + print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCi_3, 0); + break; + case FRV_OPERAND_FCCK : + print_keyword (cd, info, & frv_cgen_opval_fccr_names, fields->f_FCCk, 0); + break; + case FRV_OPERAND_FRDOUBLEI : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0); + break; + case FRV_OPERAND_FRDOUBLEJ : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0); + break; + case FRV_OPERAND_FRDOUBLEK : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0); + break; + case FRV_OPERAND_FRI : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0); + break; + case FRV_OPERAND_FRINTI : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0); + break; + case FRV_OPERAND_FRINTJ : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0); + break; + case FRV_OPERAND_FRINTK : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0); + break; + case FRV_OPERAND_FRJ : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0); + break; + case FRV_OPERAND_FRK : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0); + break; + case FRV_OPERAND_FRKHI : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0); + break; + case FRV_OPERAND_FRKLO : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0); + break; + case FRV_OPERAND_GRDOUBLEK : + print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0); + break; + case FRV_OPERAND_GRI : + print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRi, 0); + break; + case FRV_OPERAND_GRJ : + print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRj, 0); + break; + case FRV_OPERAND_GRK : + print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0); + break; + case FRV_OPERAND_GRKHI : + print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0); + break; + case FRV_OPERAND_GRKLO : + print_keyword (cd, info, & frv_cgen_opval_gr_names, fields->f_GRk, 0); + break; + case FRV_OPERAND_ICCI_1 : + print_keyword (cd, info, & frv_cgen_opval_iccr_names, fields->f_ICCi_1, 0); + break; + case FRV_OPERAND_ICCI_2 : + print_keyword (cd, info, & frv_cgen_opval_iccr_names, fields->f_ICCi_2, 0); + break; + case FRV_OPERAND_ICCI_3 : + print_keyword (cd, info, & frv_cgen_opval_iccr_names, fields->f_ICCi_3, 0); + break; + case FRV_OPERAND_LI : + print_normal (cd, info, fields->f_LI, 0, pc, length); + break; + case FRV_OPERAND_AE : + print_normal (cd, info, fields->f_ae, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); + break; + case FRV_OPERAND_CCOND : + print_normal (cd, info, fields->f_ccond, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); + break; + case FRV_OPERAND_COND : + print_normal (cd, info, fields->f_cond, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); + break; + case FRV_OPERAND_D12 : + print_normal (cd, info, fields->f_d12, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); + break; + case FRV_OPERAND_DEBUG : + print_normal (cd, info, fields->f_debug, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); + break; + case FRV_OPERAND_EIR : + print_normal (cd, info, fields->f_eir, 0, pc, length); + break; + case FRV_OPERAND_HINT : + print_normal (cd, info, fields->f_hint, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); + break; + case FRV_OPERAND_HINT_NOT_TAKEN : + print_keyword (cd, info, & frv_cgen_opval_h_hint_not_taken, fields->f_hint, 0); + break; + case FRV_OPERAND_HINT_TAKEN : + print_keyword (cd, info, & frv_cgen_opval_h_hint_taken, fields->f_hint, 0); + break; + case FRV_OPERAND_LABEL16 : + print_address (cd, info, fields->f_label16, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); + break; + case FRV_OPERAND_LABEL24 : + print_address (cd, info, fields->f_label24, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); + break; + case FRV_OPERAND_LOCK : + print_normal (cd, info, fields->f_lock, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); + break; + case FRV_OPERAND_PACK : + print_keyword (cd, info, & frv_cgen_opval_h_pack, fields->f_pack, 0); + break; + case FRV_OPERAND_S10 : + print_normal (cd, info, fields->f_s10, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); + break; + case FRV_OPERAND_S12 : + print_normal (cd, info, fields->f_d12, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); + break; + case FRV_OPERAND_S16 : + print_normal (cd, info, fields->f_s16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); + break; + case FRV_OPERAND_S5 : + print_normal (cd, info, fields->f_s5, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); + break; + case FRV_OPERAND_S6 : + print_normal (cd, info, fields->f_s6, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); + break; + case FRV_OPERAND_S6_1 : + print_normal (cd, info, fields->f_s6_1, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); + break; + case FRV_OPERAND_SLO16 : + print_lo (cd, info, fields->f_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); + break; + case FRV_OPERAND_SPR : + print_spr (cd, info, & frv_cgen_opval_spr_names, fields->f_spr, 0|(1<<CGEN_OPERAND_VIRTUAL)); + break; + case FRV_OPERAND_U12 : + print_normal (cd, info, fields->f_u12, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); + break; + case FRV_OPERAND_U16 : + print_normal (cd, info, fields->f_u16, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); + break; + case FRV_OPERAND_U6 : + print_normal (cd, info, fields->f_u6, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); + break; + case FRV_OPERAND_UHI16 : + print_hi (cd, info, fields->f_u16, 0, pc, length); + break; + case FRV_OPERAND_ULO16 : + print_lo (cd, info, fields->f_u16, 0, pc, length); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), + opindex); + abort (); + } +} + +cgen_print_fn * const frv_cgen_print_handlers[] = +{ + print_insn_normal, +}; + + +void +frv_cgen_init_dis (cd) + CGEN_CPU_DESC cd; +{ + frv_cgen_init_opcode_table (cd); + frv_cgen_init_ibld_table (cd); + cd->print_handlers = & frv_cgen_print_handlers[0]; + cd->print_operand = frv_cgen_print_operand; +} + + +/* Default print handler. */ + +static void +print_normal (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + long value; + unsigned int attrs; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_NORMAL + CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Default address handler. */ + +static void +print_address (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + bfd_vma value; + unsigned int attrs; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_ADDRESS + CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (cd, dis_info, keyword_table, value, attrs) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + CGEN_KEYWORD *keyword_table; + long value; + unsigned int attrs ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn printer. + + DIS_INFO is defined as `PTR' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (cd, dis_info, insn, fields, pc, length) + CGEN_CPU_DESC cd; + PTR dis_info; + const CGEN_INSN *insn; + CGEN_FIELDS *fields; + bfd_vma pc; + int length; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_INIT_PRINT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + frv_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ + +static int +read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + bfd_vma pc; + disassemble_info *info; + char *buf; + int buflen; + CGEN_EXTRACT_INFO *ex_info; + unsigned long *insn_value; +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (cd, pc, info, buf, buflen) + CGEN_CPU_DESC cd; + bfd_vma pc; + disassemble_info *info; + char *buf; + unsigned int buflen; +{ + CGEN_INSN_INT insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + int basesize; + + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); + + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + unsigned long insn_value_cropped; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not needed as insn shouldn't be in hash lists if not supported. */ + /* Supported by this cpu? */ + if (! frv_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); + else + insn_value_cropped = insn_value; + + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); + + /* length < 0 -> error */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* length is in bits, result is in bytes */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (cd, pc, info) + CGEN_CPU_DESC cd; + bfd_vma pc; + disassemble_info *info; +{ + char buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +typedef struct cpu_desc_list { + struct cpu_desc_list *next; + int isa; + int mach; + int endian; + CGEN_CPU_DESC cd; +} cpu_desc_list; + +int +print_insn_frv (pc, info) + bfd_vma pc; + disassemble_info *info; +{ + static cpu_desc_list *cd_list = 0; + cpu_desc_list *cl = 0; + static CGEN_CPU_DESC cd = 0; + static int prev_isa; + static int prev_mach; + static int prev_endian; + int length; + int isa,mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_frv +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the machine or isa number + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + +#ifdef CGEN_COMPUTE_ISA + isa = CGEN_COMPUTE_ISA (info); +#else + isa = info->insn_sets; +#endif + + /* If we've switched cpu's, try to find a handle we've used before */ + if (cd + && (isa != prev_isa + || mach != prev_mach + || endian != prev_endian)) + { + cd = 0; + for (cl = cd_list; cl; cl = cl->next) + { + if (cl->isa == isa && + cl->mach == mach && + cl->endian == endian) + { + cd = cl->cd; + break; + } + } + } + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = isa; + prev_mach = mach; + prev_endian = endian; + cd = frv_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + + /* save this away for future reference */ + cl = xmalloc (sizeof (struct cpu_desc_list)); + cl->cd = cd; + cl->isa = isa; + cl->mach = mach; + cl->endian = endian; + cl->next = cd_list; + cd_list = cl; + + frv_cgen_init_dis (cd); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; +} diff --git a/opcodes/frv-ibld.c b/opcodes/frv-ibld.c new file mode 100644 index 00000000000..316b2cc1bdb --- /dev/null +++ b/opcodes/frv-ibld.c @@ -0,0 +1,2051 @@ +/* Instruction building/extraction support for frv. -*- C -*- + +THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. +- the resultant file is machine generated, cgen-ibld.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include <stdio.h> +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "frv-desc.h" +#include "frv-opc.h" +#include "opintl.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR)); +static const char * insert_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); +static int extract_normal + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *)); +static int extract_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); +#if CGEN_INT_INSN_P +static void put_insn_int_value + PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *)); +static CGEN_INLINE int fill_cache + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma)); +static CGEN_INLINE long extract_1 + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, + unsigned char *, bfd_vma)); +#endif + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (cd, value, start, length, word_length, bufp) + CGEN_CPU_DESC cd; + unsigned long value; + int start,length,word_length; + unsigned char *bufp; +{ + unsigned long x,mask; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (cd, value, attrs, word_offset, start, length, word_length, + total_length, buffer) + CGEN_CPU_DESC cd; + long value; + unsigned int attrs; + unsigned int word_offset, start, length, word_length, total_length; + CGEN_INSN_BYTES_PTR buffer; +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + +#if 0 + if (CGEN_INT_INSN_P + && word_offset != 0) + abort (); +#endif + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + + if ((unsigned long) value > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%lu not between 0 and %lu)"), + value, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (cd, insn, fields, buffer, pc) + CGEN_CPU_DESC cd; + const CGEN_INSN * insn; + CGEN_FIELDS * fields; + CGEN_INSN_BYTES_PTR buffer; + bfd_vma pc; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +#if CGEN_INT_INSN_P +/* Cover function to store an insn value into an integral insn. Must go here + because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (cd, buf, length, insn_length, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + CGEN_INSN_BYTES_PTR buf; + int length; + int insn_length; + CGEN_INSN_INT value; +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} +#endif + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (cd, ex_info, offset, bytes, pc) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + CGEN_EXTRACT_INFO *ex_info; + int offset, bytes; + bfd_vma pc; +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + unsigned int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (cd, ex_info, start, length, word_length, bufp, pc) + CGEN_CPU_DESC cd; + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; + int start,length,word_length; + unsigned char *bufp; + bfd_vma pc ATTRIBUTE_UNUSED; +{ + unsigned long x; + int shift; +#if 0 + int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; +#endif + x = cgen_get_insn_value (cd, bufp, word_length); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, + word_length, total_length, pc, valuep) + CGEN_CPU_DESC cd; +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info; +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; +#endif + CGEN_INSN_INT insn_value; + unsigned int attrs; + unsigned int word_offset, start, length, word_length, total_length; +#if ! CGEN_INT_INSN_P + bfd_vma pc; +#else + bfd_vma pc ATTRIBUTE_UNUSED; +#endif + long *valuep; +{ + long value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + +#if 0 + if (CGEN_INT_INSN_P + && word_offset != 0) + abort (); +#endif + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Does the value reside in INSN_VALUE, and at the right alignment? */ + + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 32) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc) + CGEN_CPU_DESC cd; + const CGEN_INSN *insn; + CGEN_EXTRACT_INFO *ex_info; + CGEN_INSN_INT insn_value; + CGEN_FIELDS *fields; + bfd_vma pc; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* machine generated code added here */ + +const char * frv_cgen_insert_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + +/* Main entry point for operand insertion. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. It's also needed by GAS to insert operands that couldn't be + resolved during parsing. */ + +const char * +frv_cgen_insert_operand (cd, opindex, fields, buffer, pc) + CGEN_CPU_DESC cd; + int opindex; + CGEN_FIELDS * fields; + CGEN_INSN_BYTES_PTR buffer; + bfd_vma pc ATTRIBUTE_UNUSED; +{ + const char * errmsg = NULL; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case FRV_OPERAND_A : + errmsg = insert_normal (cd, fields->f_A, 0, 0, 17, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_ACC40SI : + errmsg = insert_normal (cd, fields->f_ACC40Si, 0, 0, 17, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_ACC40SK : + errmsg = insert_normal (cd, fields->f_ACC40Sk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_ACC40UI : + errmsg = insert_normal (cd, fields->f_ACC40Ui, 0, 0, 17, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_ACC40UK : + errmsg = insert_normal (cd, fields->f_ACC40Uk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_ACCGI : + errmsg = insert_normal (cd, fields->f_ACCGi, 0, 0, 17, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_ACCGK : + errmsg = insert_normal (cd, fields->f_ACCGk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_CCI : + errmsg = insert_normal (cd, fields->f_CCi, 0, 0, 11, 3, 32, total_length, buffer); + break; + case FRV_OPERAND_CPRDOUBLEK : + errmsg = insert_normal (cd, fields->f_CPRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_CPRI : + errmsg = insert_normal (cd, fields->f_CPRi, 0, 0, 17, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_CPRJ : + errmsg = insert_normal (cd, fields->f_CPRj, 0, 0, 5, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_CPRK : + errmsg = insert_normal (cd, fields->f_CPRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_CRI : + errmsg = insert_normal (cd, fields->f_CRi, 0, 0, 14, 3, 32, total_length, buffer); + break; + case FRV_OPERAND_CRJ : + errmsg = insert_normal (cd, fields->f_CRj, 0, 0, 2, 3, 32, total_length, buffer); + break; + case FRV_OPERAND_CRJ_FLOAT : + errmsg = insert_normal (cd, fields->f_CRj_float, 0, 0, 26, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_CRJ_INT : + { + long value = fields->f_CRj_int; + value = ((value) - (4)); + errmsg = insert_normal (cd, value, 0, 0, 26, 2, 32, total_length, buffer); + } + break; + case FRV_OPERAND_CRK : + errmsg = insert_normal (cd, fields->f_CRk, 0, 0, 27, 3, 32, total_length, buffer); + break; + case FRV_OPERAND_FCCI_1 : + errmsg = insert_normal (cd, fields->f_FCCi_1, 0, 0, 11, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_FCCI_2 : + errmsg = insert_normal (cd, fields->f_FCCi_2, 0, 0, 26, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_FCCI_3 : + errmsg = insert_normal (cd, fields->f_FCCi_3, 0, 0, 1, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_FCCK : + errmsg = insert_normal (cd, fields->f_FCCk, 0, 0, 26, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_FRDOUBLEI : + errmsg = insert_normal (cd, fields->f_FRi, 0, 0, 17, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRDOUBLEJ : + errmsg = insert_normal (cd, fields->f_FRj, 0, 0, 5, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRDOUBLEK : + errmsg = insert_normal (cd, fields->f_FRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRI : + errmsg = insert_normal (cd, fields->f_FRi, 0, 0, 17, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRINTI : + errmsg = insert_normal (cd, fields->f_FRi, 0, 0, 17, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRINTJ : + errmsg = insert_normal (cd, fields->f_FRj, 0, 0, 5, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRINTK : + errmsg = insert_normal (cd, fields->f_FRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRJ : + errmsg = insert_normal (cd, fields->f_FRj, 0, 0, 5, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRK : + errmsg = insert_normal (cd, fields->f_FRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRKHI : + errmsg = insert_normal (cd, fields->f_FRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_FRKLO : + errmsg = insert_normal (cd, fields->f_FRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_GRDOUBLEK : + errmsg = insert_normal (cd, fields->f_GRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_GRI : + errmsg = insert_normal (cd, fields->f_GRi, 0, 0, 17, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_GRJ : + errmsg = insert_normal (cd, fields->f_GRj, 0, 0, 5, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_GRK : + errmsg = insert_normal (cd, fields->f_GRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_GRKHI : + errmsg = insert_normal (cd, fields->f_GRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_GRKLO : + errmsg = insert_normal (cd, fields->f_GRk, 0, 0, 30, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_ICCI_1 : + errmsg = insert_normal (cd, fields->f_ICCi_1, 0, 0, 11, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_ICCI_2 : + errmsg = insert_normal (cd, fields->f_ICCi_2, 0, 0, 26, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_ICCI_3 : + errmsg = insert_normal (cd, fields->f_ICCi_3, 0, 0, 1, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_LI : + errmsg = insert_normal (cd, fields->f_LI, 0, 0, 25, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_AE : + errmsg = insert_normal (cd, fields->f_ae, 0, 0, 25, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_CCOND : + errmsg = insert_normal (cd, fields->f_ccond, 0, 0, 12, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_COND : + errmsg = insert_normal (cd, fields->f_cond, 0, 0, 8, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_D12 : + errmsg = insert_normal (cd, fields->f_d12, 0|(1<<CGEN_IFLD_SIGNED), 0, 11, 12, 32, total_length, buffer); + break; + case FRV_OPERAND_DEBUG : + errmsg = insert_normal (cd, fields->f_debug, 0, 0, 25, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_EIR : + errmsg = insert_normal (cd, fields->f_eir, 0, 0, 17, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_HINT : + errmsg = insert_normal (cd, fields->f_hint, 0, 0, 17, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_HINT_NOT_TAKEN : + errmsg = insert_normal (cd, fields->f_hint, 0, 0, 17, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_HINT_TAKEN : + errmsg = insert_normal (cd, fields->f_hint, 0, 0, 17, 2, 32, total_length, buffer); + break; + case FRV_OPERAND_LABEL16 : + { + long value = fields->f_label16; + value = ((int) (((value) - (pc))) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 16, 32, total_length, buffer); + } + break; + case FRV_OPERAND_LABEL24 : + { +{ + FLD (f_labelH6) = ((int) (((FLD (f_label24)) - (pc))) >> (20)); + FLD (f_labelL18) = ((((unsigned int) (((FLD (f_label24)) - (pc))) >> (2))) & (262143)); +} + errmsg = insert_normal (cd, fields->f_labelH6, 0|(1<<CGEN_IFLD_SIGNED), 0, 30, 6, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_labelL18, 0, 0, 17, 18, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case FRV_OPERAND_LOCK : + errmsg = insert_normal (cd, fields->f_lock, 0, 0, 25, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_PACK : + errmsg = insert_normal (cd, fields->f_pack, 0, 0, 31, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_S10 : + errmsg = insert_normal (cd, fields->f_s10, 0|(1<<CGEN_IFLD_SIGNED), 0, 9, 10, 32, total_length, buffer); + break; + case FRV_OPERAND_S12 : + errmsg = insert_normal (cd, fields->f_d12, 0|(1<<CGEN_IFLD_SIGNED), 0, 11, 12, 32, total_length, buffer); + break; + case FRV_OPERAND_S16 : + errmsg = insert_normal (cd, fields->f_s16, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, buffer); + break; + case FRV_OPERAND_S5 : + errmsg = insert_normal (cd, fields->f_s5, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 5, 32, total_length, buffer); + break; + case FRV_OPERAND_S6 : + errmsg = insert_normal (cd, fields->f_s6, 0|(1<<CGEN_IFLD_SIGNED), 0, 5, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_S6_1 : + errmsg = insert_normal (cd, fields->f_s6_1, 0|(1<<CGEN_IFLD_SIGNED), 0, 11, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_SLO16 : + errmsg = insert_normal (cd, fields->f_s16, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, buffer); + break; + case FRV_OPERAND_SPR : + { +{ + FLD (f_spr_h) = ((unsigned int) (FLD (f_spr)) >> (6)); + FLD (f_spr_l) = ((FLD (f_spr)) & (63)); +} + errmsg = insert_normal (cd, fields->f_spr_h, 0, 0, 30, 6, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_spr_l, 0, 0, 17, 6, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case FRV_OPERAND_U12 : + { +{ + FLD (f_u12_h) = ((int) (FLD (f_u12)) >> (6)); + FLD (f_u12_l) = ((FLD (f_u12)) & (63)); +} + errmsg = insert_normal (cd, fields->f_u12_h, 0|(1<<CGEN_IFLD_SIGNED), 0, 17, 6, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_u12_l, 0, 0, 5, 6, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case FRV_OPERAND_U16 : + errmsg = insert_normal (cd, fields->f_u16, 0, 0, 15, 16, 32, total_length, buffer); + break; + case FRV_OPERAND_U6 : + errmsg = insert_normal (cd, fields->f_u6, 0, 0, 5, 6, 32, total_length, buffer); + break; + case FRV_OPERAND_UHI16 : + errmsg = insert_normal (cd, fields->f_u16, 0, 0, 15, 16, 32, total_length, buffer); + break; + case FRV_OPERAND_ULO16 : + errmsg = insert_normal (cd, fields->f_u16, 0, 0, 15, 16, 32, total_length, buffer); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while building insn.\n"), + opindex); + abort (); + } + + return errmsg; +} + +int frv_cgen_extract_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + CGEN_FIELDS *, bfd_vma)); + +/* Main entry point for operand extraction. + The result is <= 0 for error, >0 for success. + ??? Actual values aren't well defined right now. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +int +frv_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) + CGEN_CPU_DESC cd; + int opindex; + CGEN_EXTRACT_INFO *ex_info; + CGEN_INSN_INT insn_value; + CGEN_FIELDS * fields; + bfd_vma pc; +{ + /* Assume success (for those operands that are nops). */ + int length = 1; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case FRV_OPERAND_A : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 1, 32, total_length, pc, & fields->f_A); + break; + case FRV_OPERAND_ACC40SI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_ACC40Si); + break; + case FRV_OPERAND_ACC40SK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_ACC40Sk); + break; + case FRV_OPERAND_ACC40UI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_ACC40Ui); + break; + case FRV_OPERAND_ACC40UK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_ACC40Uk); + break; + case FRV_OPERAND_ACCGI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_ACCGi); + break; + case FRV_OPERAND_ACCGK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_ACCGk); + break; + case FRV_OPERAND_CCI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 3, 32, total_length, pc, & fields->f_CCi); + break; + case FRV_OPERAND_CPRDOUBLEK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_CPRk); + break; + case FRV_OPERAND_CPRI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_CPRi); + break; + case FRV_OPERAND_CPRJ : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_CPRj); + break; + case FRV_OPERAND_CPRK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_CPRk); + break; + case FRV_OPERAND_CRI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 3, 32, total_length, pc, & fields->f_CRi); + break; + case FRV_OPERAND_CRJ : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 3, 32, total_length, pc, & fields->f_CRj); + break; + case FRV_OPERAND_CRJ_FLOAT : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 2, 32, total_length, pc, & fields->f_CRj_float); + break; + case FRV_OPERAND_CRJ_INT : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 2, 32, total_length, pc, & value); + value = ((value) + (4)); + fields->f_CRj_int = value; + } + break; + case FRV_OPERAND_CRK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 27, 3, 32, total_length, pc, & fields->f_CRk); + break; + case FRV_OPERAND_FCCI_1 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 2, 32, total_length, pc, & fields->f_FCCi_1); + break; + case FRV_OPERAND_FCCI_2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 2, 32, total_length, pc, & fields->f_FCCi_2); + break; + case FRV_OPERAND_FCCI_3 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 1, 2, 32, total_length, pc, & fields->f_FCCi_3); + break; + case FRV_OPERAND_FCCK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 2, 32, total_length, pc, & fields->f_FCCk); + break; + case FRV_OPERAND_FRDOUBLEI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_FRi); + break; + case FRV_OPERAND_FRDOUBLEJ : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_FRj); + break; + case FRV_OPERAND_FRDOUBLEK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_FRk); + break; + case FRV_OPERAND_FRI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_FRi); + break; + case FRV_OPERAND_FRINTI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_FRi); + break; + case FRV_OPERAND_FRINTJ : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_FRj); + break; + case FRV_OPERAND_FRINTK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_FRk); + break; + case FRV_OPERAND_FRJ : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_FRj); + break; + case FRV_OPERAND_FRK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_FRk); + break; + case FRV_OPERAND_FRKHI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_FRk); + break; + case FRV_OPERAND_FRKLO : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_FRk); + break; + case FRV_OPERAND_GRDOUBLEK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_GRk); + break; + case FRV_OPERAND_GRI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_GRi); + break; + case FRV_OPERAND_GRJ : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_GRj); + break; + case FRV_OPERAND_GRK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_GRk); + break; + case FRV_OPERAND_GRKHI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_GRk); + break; + case FRV_OPERAND_GRKLO : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_GRk); + break; + case FRV_OPERAND_ICCI_1 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 2, 32, total_length, pc, & fields->f_ICCi_1); + break; + case FRV_OPERAND_ICCI_2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 2, 32, total_length, pc, & fields->f_ICCi_2); + break; + case FRV_OPERAND_ICCI_3 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 1, 2, 32, total_length, pc, & fields->f_ICCi_3); + break; + case FRV_OPERAND_LI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_LI); + break; + case FRV_OPERAND_AE : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_ae); + break; + case FRV_OPERAND_CCOND : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 1, 32, total_length, pc, & fields->f_ccond); + break; + case FRV_OPERAND_COND : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_cond); + break; + case FRV_OPERAND_D12 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 11, 12, 32, total_length, pc, & fields->f_d12); + break; + case FRV_OPERAND_DEBUG : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_debug); + break; + case FRV_OPERAND_EIR : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_eir); + break; + case FRV_OPERAND_HINT : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 2, 32, total_length, pc, & fields->f_hint); + break; + case FRV_OPERAND_HINT_NOT_TAKEN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 2, 32, total_length, pc, & fields->f_hint); + break; + case FRV_OPERAND_HINT_TAKEN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 2, 32, total_length, pc, & fields->f_hint); + break; + case FRV_OPERAND_LABEL16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 16, 32, total_length, pc, & value); + value = ((((value) << (2))) + (pc)); + fields->f_label16 = value; + } + break; + case FRV_OPERAND_LABEL24 : + { + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 30, 6, 32, total_length, pc, & fields->f_labelH6); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 18, 32, total_length, pc, & fields->f_labelL18); + if (length <= 0) break; +{ + FLD (f_label24) = ((((((((FLD (f_labelH6)) << (18))) | (FLD (f_labelL18)))) << (2))) + (pc)); +} + } + break; + case FRV_OPERAND_LOCK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_lock); + break; + case FRV_OPERAND_PACK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 1, 32, total_length, pc, & fields->f_pack); + break; + case FRV_OPERAND_S10 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 9, 10, 32, total_length, pc, & fields->f_s10); + break; + case FRV_OPERAND_S12 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 11, 12, 32, total_length, pc, & fields->f_d12); + break; + case FRV_OPERAND_S16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, pc, & fields->f_s16); + break; + case FRV_OPERAND_S5 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 5, 32, total_length, pc, & fields->f_s5); + break; + case FRV_OPERAND_S6 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 5, 6, 32, total_length, pc, & fields->f_s6); + break; + case FRV_OPERAND_S6_1 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 11, 6, 32, total_length, pc, & fields->f_s6_1); + break; + case FRV_OPERAND_SLO16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, pc, & fields->f_s16); + break; + case FRV_OPERAND_SPR : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_spr_h); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_spr_l); + if (length <= 0) break; +{ + FLD (f_spr) = ((((FLD (f_spr_h)) << (6))) | (FLD (f_spr_l))); +} + } + break; + case FRV_OPERAND_U12 : + { + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 17, 6, 32, total_length, pc, & fields->f_u12_h); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_u12_l); + if (length <= 0) break; +{ + FLD (f_u12) = ((((FLD (f_u12_h)) << (6))) | (FLD (f_u12_l))); +} + } + break; + case FRV_OPERAND_U16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_u16); + break; + case FRV_OPERAND_U6 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_u6); + break; + case FRV_OPERAND_UHI16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_u16); + break; + case FRV_OPERAND_ULO16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_u16); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), + opindex); + abort (); + } + + return length; +} + +cgen_insert_fn * const frv_cgen_insert_handlers[] = +{ + insert_insn_normal, +}; + +cgen_extract_fn * const frv_cgen_extract_handlers[] = +{ + extract_insn_normal, +}; + +int frv_cgen_get_int_operand + PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); +bfd_vma frv_cgen_get_vma_operand + PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); + +/* Getting values from cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they return. + TODO: floating point, inlining support, remove cases where result type + not appropriate. */ + +int +frv_cgen_get_int_operand (cd, opindex, fields) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + const CGEN_FIELDS * fields; +{ + int value; + + switch (opindex) + { + case FRV_OPERAND_A : + value = fields->f_A; + break; + case FRV_OPERAND_ACC40SI : + value = fields->f_ACC40Si; + break; + case FRV_OPERAND_ACC40SK : + value = fields->f_ACC40Sk; + break; + case FRV_OPERAND_ACC40UI : + value = fields->f_ACC40Ui; + break; + case FRV_OPERAND_ACC40UK : + value = fields->f_ACC40Uk; + break; + case FRV_OPERAND_ACCGI : + value = fields->f_ACCGi; + break; + case FRV_OPERAND_ACCGK : + value = fields->f_ACCGk; + break; + case FRV_OPERAND_CCI : + value = fields->f_CCi; + break; + case FRV_OPERAND_CPRDOUBLEK : + value = fields->f_CPRk; + break; + case FRV_OPERAND_CPRI : + value = fields->f_CPRi; + break; + case FRV_OPERAND_CPRJ : + value = fields->f_CPRj; + break; + case FRV_OPERAND_CPRK : + value = fields->f_CPRk; + break; + case FRV_OPERAND_CRI : + value = fields->f_CRi; + break; + case FRV_OPERAND_CRJ : + value = fields->f_CRj; + break; + case FRV_OPERAND_CRJ_FLOAT : + value = fields->f_CRj_float; + break; + case FRV_OPERAND_CRJ_INT : + value = fields->f_CRj_int; + break; + case FRV_OPERAND_CRK : + value = fields->f_CRk; + break; + case FRV_OPERAND_FCCI_1 : + value = fields->f_FCCi_1; + break; + case FRV_OPERAND_FCCI_2 : + value = fields->f_FCCi_2; + break; + case FRV_OPERAND_FCCI_3 : + value = fields->f_FCCi_3; + break; + case FRV_OPERAND_FCCK : + value = fields->f_FCCk; + break; + case FRV_OPERAND_FRDOUBLEI : + value = fields->f_FRi; + break; + case FRV_OPERAND_FRDOUBLEJ : + value = fields->f_FRj; + break; + case FRV_OPERAND_FRDOUBLEK : + value = fields->f_FRk; + break; + case FRV_OPERAND_FRI : + value = fields->f_FRi; + break; + case FRV_OPERAND_FRINTI : + value = fields->f_FRi; + break; + case FRV_OPERAND_FRINTJ : + value = fields->f_FRj; + break; + case FRV_OPERAND_FRINTK : + value = fields->f_FRk; + break; + case FRV_OPERAND_FRJ : + value = fields->f_FRj; + break; + case FRV_OPERAND_FRK : + value = fields->f_FRk; + break; + case FRV_OPERAND_FRKHI : + value = fields->f_FRk; + break; + case FRV_OPERAND_FRKLO : + value = fields->f_FRk; + break; + case FRV_OPERAND_GRDOUBLEK : + value = fields->f_GRk; + break; + case FRV_OPERAND_GRI : + value = fields->f_GRi; + break; + case FRV_OPERAND_GRJ : + value = fields->f_GRj; + break; + case FRV_OPERAND_GRK : + value = fields->f_GRk; + break; + case FRV_OPERAND_GRKHI : + value = fields->f_GRk; + break; + case FRV_OPERAND_GRKLO : + value = fields->f_GRk; + break; + case FRV_OPERAND_ICCI_1 : + value = fields->f_ICCi_1; + break; + case FRV_OPERAND_ICCI_2 : + value = fields->f_ICCi_2; + break; + case FRV_OPERAND_ICCI_3 : + value = fields->f_ICCi_3; + break; + case FRV_OPERAND_LI : + value = fields->f_LI; + break; + case FRV_OPERAND_AE : + value = fields->f_ae; + break; + case FRV_OPERAND_CCOND : + value = fields->f_ccond; + break; + case FRV_OPERAND_COND : + value = fields->f_cond; + break; + case FRV_OPERAND_D12 : + value = fields->f_d12; + break; + case FRV_OPERAND_DEBUG : + value = fields->f_debug; + break; + case FRV_OPERAND_EIR : + value = fields->f_eir; + break; + case FRV_OPERAND_HINT : + value = fields->f_hint; + break; + case FRV_OPERAND_HINT_NOT_TAKEN : + value = fields->f_hint; + break; + case FRV_OPERAND_HINT_TAKEN : + value = fields->f_hint; + break; + case FRV_OPERAND_LABEL16 : + value = fields->f_label16; + break; + case FRV_OPERAND_LABEL24 : + value = fields->f_label24; + break; + case FRV_OPERAND_LOCK : + value = fields->f_lock; + break; + case FRV_OPERAND_PACK : + value = fields->f_pack; + break; + case FRV_OPERAND_S10 : + value = fields->f_s10; + break; + case FRV_OPERAND_S12 : + value = fields->f_d12; + break; + case FRV_OPERAND_S16 : + value = fields->f_s16; + break; + case FRV_OPERAND_S5 : + value = fields->f_s5; + break; + case FRV_OPERAND_S6 : + value = fields->f_s6; + break; + case FRV_OPERAND_S6_1 : + value = fields->f_s6_1; + break; + case FRV_OPERAND_SLO16 : + value = fields->f_s16; + break; + case FRV_OPERAND_SPR : + value = fields->f_spr; + break; + case FRV_OPERAND_U12 : + value = fields->f_u12; + break; + case FRV_OPERAND_U16 : + value = fields->f_u16; + break; + case FRV_OPERAND_U6 : + value = fields->f_u6; + break; + case FRV_OPERAND_UHI16 : + value = fields->f_u16; + break; + case FRV_OPERAND_ULO16 : + value = fields->f_u16; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), + opindex); + abort (); + } + + return value; +} + +bfd_vma +frv_cgen_get_vma_operand (cd, opindex, fields) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + const CGEN_FIELDS * fields; +{ + bfd_vma value; + + switch (opindex) + { + case FRV_OPERAND_A : + value = fields->f_A; + break; + case FRV_OPERAND_ACC40SI : + value = fields->f_ACC40Si; + break; + case FRV_OPERAND_ACC40SK : + value = fields->f_ACC40Sk; + break; + case FRV_OPERAND_ACC40UI : + value = fields->f_ACC40Ui; + break; + case FRV_OPERAND_ACC40UK : + value = fields->f_ACC40Uk; + break; + case FRV_OPERAND_ACCGI : + value = fields->f_ACCGi; + break; + case FRV_OPERAND_ACCGK : + value = fields->f_ACCGk; + break; + case FRV_OPERAND_CCI : + value = fields->f_CCi; + break; + case FRV_OPERAND_CPRDOUBLEK : + value = fields->f_CPRk; + break; + case FRV_OPERAND_CPRI : + value = fields->f_CPRi; + break; + case FRV_OPERAND_CPRJ : + value = fields->f_CPRj; + break; + case FRV_OPERAND_CPRK : + value = fields->f_CPRk; + break; + case FRV_OPERAND_CRI : + value = fields->f_CRi; + break; + case FRV_OPERAND_CRJ : + value = fields->f_CRj; + break; + case FRV_OPERAND_CRJ_FLOAT : + value = fields->f_CRj_float; + break; + case FRV_OPERAND_CRJ_INT : + value = fields->f_CRj_int; + break; + case FRV_OPERAND_CRK : + value = fields->f_CRk; + break; + case FRV_OPERAND_FCCI_1 : + value = fields->f_FCCi_1; + break; + case FRV_OPERAND_FCCI_2 : + value = fields->f_FCCi_2; + break; + case FRV_OPERAND_FCCI_3 : + value = fields->f_FCCi_3; + break; + case FRV_OPERAND_FCCK : + value = fields->f_FCCk; + break; + case FRV_OPERAND_FRDOUBLEI : + value = fields->f_FRi; + break; + case FRV_OPERAND_FRDOUBLEJ : + value = fields->f_FRj; + break; + case FRV_OPERAND_FRDOUBLEK : + value = fields->f_FRk; + break; + case FRV_OPERAND_FRI : + value = fields->f_FRi; + break; + case FRV_OPERAND_FRINTI : + value = fields->f_FRi; + break; + case FRV_OPERAND_FRINTJ : + value = fields->f_FRj; + break; + case FRV_OPERAND_FRINTK : + value = fields->f_FRk; + break; + case FRV_OPERAND_FRJ : + value = fields->f_FRj; + break; + case FRV_OPERAND_FRK : + value = fields->f_FRk; + break; + case FRV_OPERAND_FRKHI : + value = fields->f_FRk; + break; + case FRV_OPERAND_FRKLO : + value = fields->f_FRk; + break; + case FRV_OPERAND_GRDOUBLEK : + value = fields->f_GRk; + break; + case FRV_OPERAND_GRI : + value = fields->f_GRi; + break; + case FRV_OPERAND_GRJ : + value = fields->f_GRj; + break; + case FRV_OPERAND_GRK : + value = fields->f_GRk; + break; + case FRV_OPERAND_GRKHI : + value = fields->f_GRk; + break; + case FRV_OPERAND_GRKLO : + value = fields->f_GRk; + break; + case FRV_OPERAND_ICCI_1 : + value = fields->f_ICCi_1; + break; + case FRV_OPERAND_ICCI_2 : + value = fields->f_ICCi_2; + break; + case FRV_OPERAND_ICCI_3 : + value = fields->f_ICCi_3; + break; + case FRV_OPERAND_LI : + value = fields->f_LI; + break; + case FRV_OPERAND_AE : + value = fields->f_ae; + break; + case FRV_OPERAND_CCOND : + value = fields->f_ccond; + break; + case FRV_OPERAND_COND : + value = fields->f_cond; + break; + case FRV_OPERAND_D12 : + value = fields->f_d12; + break; + case FRV_OPERAND_DEBUG : + value = fields->f_debug; + break; + case FRV_OPERAND_EIR : + value = fields->f_eir; + break; + case FRV_OPERAND_HINT : + value = fields->f_hint; + break; + case FRV_OPERAND_HINT_NOT_TAKEN : + value = fields->f_hint; + break; + case FRV_OPERAND_HINT_TAKEN : + value = fields->f_hint; + break; + case FRV_OPERAND_LABEL16 : + value = fields->f_label16; + break; + case FRV_OPERAND_LABEL24 : + value = fields->f_label24; + break; + case FRV_OPERAND_LOCK : + value = fields->f_lock; + break; + case FRV_OPERAND_PACK : + value = fields->f_pack; + break; + case FRV_OPERAND_S10 : + value = fields->f_s10; + break; + case FRV_OPERAND_S12 : + value = fields->f_d12; + break; + case FRV_OPERAND_S16 : + value = fields->f_s16; + break; + case FRV_OPERAND_S5 : + value = fields->f_s5; + break; + case FRV_OPERAND_S6 : + value = fields->f_s6; + break; + case FRV_OPERAND_S6_1 : + value = fields->f_s6_1; + break; + case FRV_OPERAND_SLO16 : + value = fields->f_s16; + break; + case FRV_OPERAND_SPR : + value = fields->f_spr; + break; + case FRV_OPERAND_U12 : + value = fields->f_u12; + break; + case FRV_OPERAND_U16 : + value = fields->f_u16; + break; + case FRV_OPERAND_U6 : + value = fields->f_u6; + break; + case FRV_OPERAND_UHI16 : + value = fields->f_u16; + break; + case FRV_OPERAND_ULO16 : + value = fields->f_u16; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), + opindex); + abort (); + } + + return value; +} + +void frv_cgen_set_int_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int)); +void frv_cgen_set_vma_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma)); + +/* Stuffing values in cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they accept. + TODO: floating point, inlining support, remove cases where argument type + not appropriate. */ + +void +frv_cgen_set_int_operand (cd, opindex, fields, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + CGEN_FIELDS * fields; + int value; +{ + switch (opindex) + { + case FRV_OPERAND_A : + fields->f_A = value; + break; + case FRV_OPERAND_ACC40SI : + fields->f_ACC40Si = value; + break; + case FRV_OPERAND_ACC40SK : + fields->f_ACC40Sk = value; + break; + case FRV_OPERAND_ACC40UI : + fields->f_ACC40Ui = value; + break; + case FRV_OPERAND_ACC40UK : + fields->f_ACC40Uk = value; + break; + case FRV_OPERAND_ACCGI : + fields->f_ACCGi = value; + break; + case FRV_OPERAND_ACCGK : + fields->f_ACCGk = value; + break; + case FRV_OPERAND_CCI : + fields->f_CCi = value; + break; + case FRV_OPERAND_CPRDOUBLEK : + fields->f_CPRk = value; + break; + case FRV_OPERAND_CPRI : + fields->f_CPRi = value; + break; + case FRV_OPERAND_CPRJ : + fields->f_CPRj = value; + break; + case FRV_OPERAND_CPRK : + fields->f_CPRk = value; + break; + case FRV_OPERAND_CRI : + fields->f_CRi = value; + break; + case FRV_OPERAND_CRJ : + fields->f_CRj = value; + break; + case FRV_OPERAND_CRJ_FLOAT : + fields->f_CRj_float = value; + break; + case FRV_OPERAND_CRJ_INT : + fields->f_CRj_int = value; + break; + case FRV_OPERAND_CRK : + fields->f_CRk = value; + break; + case FRV_OPERAND_FCCI_1 : + fields->f_FCCi_1 = value; + break; + case FRV_OPERAND_FCCI_2 : + fields->f_FCCi_2 = value; + break; + case FRV_OPERAND_FCCI_3 : + fields->f_FCCi_3 = value; + break; + case FRV_OPERAND_FCCK : + fields->f_FCCk = value; + break; + case FRV_OPERAND_FRDOUBLEI : + fields->f_FRi = value; + break; + case FRV_OPERAND_FRDOUBLEJ : + fields->f_FRj = value; + break; + case FRV_OPERAND_FRDOUBLEK : + fields->f_FRk = value; + break; + case FRV_OPERAND_FRI : + fields->f_FRi = value; + break; + case FRV_OPERAND_FRINTI : + fields->f_FRi = value; + break; + case FRV_OPERAND_FRINTJ : + fields->f_FRj = value; + break; + case FRV_OPERAND_FRINTK : + fields->f_FRk = value; + break; + case FRV_OPERAND_FRJ : + fields->f_FRj = value; + break; + case FRV_OPERAND_FRK : + fields->f_FRk = value; + break; + case FRV_OPERAND_FRKHI : + fields->f_FRk = value; + break; + case FRV_OPERAND_FRKLO : + fields->f_FRk = value; + break; + case FRV_OPERAND_GRDOUBLEK : + fields->f_GRk = value; + break; + case FRV_OPERAND_GRI : + fields->f_GRi = value; + break; + case FRV_OPERAND_GRJ : + fields->f_GRj = value; + break; + case FRV_OPERAND_GRK : + fields->f_GRk = value; + break; + case FRV_OPERAND_GRKHI : + fields->f_GRk = value; + break; + case FRV_OPERAND_GRKLO : + fields->f_GRk = value; + break; + case FRV_OPERAND_ICCI_1 : + fields->f_ICCi_1 = value; + break; + case FRV_OPERAND_ICCI_2 : + fields->f_ICCi_2 = value; + break; + case FRV_OPERAND_ICCI_3 : + fields->f_ICCi_3 = value; + break; + case FRV_OPERAND_LI : + fields->f_LI = value; + break; + case FRV_OPERAND_AE : + fields->f_ae = value; + break; + case FRV_OPERAND_CCOND : + fields->f_ccond = value; + break; + case FRV_OPERAND_COND : + fields->f_cond = value; + break; + case FRV_OPERAND_D12 : + fields->f_d12 = value; + break; + case FRV_OPERAND_DEBUG : + fields->f_debug = value; + break; + case FRV_OPERAND_EIR : + fields->f_eir = value; + break; + case FRV_OPERAND_HINT : + fields->f_hint = value; + break; + case FRV_OPERAND_HINT_NOT_TAKEN : + fields->f_hint = value; + break; + case FRV_OPERAND_HINT_TAKEN : + fields->f_hint = value; + break; + case FRV_OPERAND_LABEL16 : + fields->f_label16 = value; + break; + case FRV_OPERAND_LABEL24 : + fields->f_label24 = value; + break; + case FRV_OPERAND_LOCK : + fields->f_lock = value; + break; + case FRV_OPERAND_PACK : + fields->f_pack = value; + break; + case FRV_OPERAND_S10 : + fields->f_s10 = value; + break; + case FRV_OPERAND_S12 : + fields->f_d12 = value; + break; + case FRV_OPERAND_S16 : + fields->f_s16 = value; + break; + case FRV_OPERAND_S5 : + fields->f_s5 = value; + break; + case FRV_OPERAND_S6 : + fields->f_s6 = value; + break; + case FRV_OPERAND_S6_1 : + fields->f_s6_1 = value; + break; + case FRV_OPERAND_SLO16 : + fields->f_s16 = value; + break; + case FRV_OPERAND_SPR : + fields->f_spr = value; + break; + case FRV_OPERAND_U12 : + fields->f_u12 = value; + break; + case FRV_OPERAND_U16 : + fields->f_u16 = value; + break; + case FRV_OPERAND_U6 : + fields->f_u6 = value; + break; + case FRV_OPERAND_UHI16 : + fields->f_u16 = value; + break; + case FRV_OPERAND_ULO16 : + fields->f_u16 = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), + opindex); + abort (); + } +} + +void +frv_cgen_set_vma_operand (cd, opindex, fields, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + CGEN_FIELDS * fields; + bfd_vma value; +{ + switch (opindex) + { + case FRV_OPERAND_A : + fields->f_A = value; + break; + case FRV_OPERAND_ACC40SI : + fields->f_ACC40Si = value; + break; + case FRV_OPERAND_ACC40SK : + fields->f_ACC40Sk = value; + break; + case FRV_OPERAND_ACC40UI : + fields->f_ACC40Ui = value; + break; + case FRV_OPERAND_ACC40UK : + fields->f_ACC40Uk = value; + break; + case FRV_OPERAND_ACCGI : + fields->f_ACCGi = value; + break; + case FRV_OPERAND_ACCGK : + fields->f_ACCGk = value; + break; + case FRV_OPERAND_CCI : + fields->f_CCi = value; + break; + case FRV_OPERAND_CPRDOUBLEK : + fields->f_CPRk = value; + break; + case FRV_OPERAND_CPRI : + fields->f_CPRi = value; + break; + case FRV_OPERAND_CPRJ : + fields->f_CPRj = value; + break; + case FRV_OPERAND_CPRK : + fields->f_CPRk = value; + break; + case FRV_OPERAND_CRI : + fields->f_CRi = value; + break; + case FRV_OPERAND_CRJ : + fields->f_CRj = value; + break; + case FRV_OPERAND_CRJ_FLOAT : + fields->f_CRj_float = value; + break; + case FRV_OPERAND_CRJ_INT : + fields->f_CRj_int = value; + break; + case FRV_OPERAND_CRK : + fields->f_CRk = value; + break; + case FRV_OPERAND_FCCI_1 : + fields->f_FCCi_1 = value; + break; + case FRV_OPERAND_FCCI_2 : + fields->f_FCCi_2 = value; + break; + case FRV_OPERAND_FCCI_3 : + fields->f_FCCi_3 = value; + break; + case FRV_OPERAND_FCCK : + fields->f_FCCk = value; + break; + case FRV_OPERAND_FRDOUBLEI : + fields->f_FRi = value; + break; + case FRV_OPERAND_FRDOUBLEJ : + fields->f_FRj = value; + break; + case FRV_OPERAND_FRDOUBLEK : + fields->f_FRk = value; + break; + case FRV_OPERAND_FRI : + fields->f_FRi = value; + break; + case FRV_OPERAND_FRINTI : + fields->f_FRi = value; + break; + case FRV_OPERAND_FRINTJ : + fields->f_FRj = value; + break; + case FRV_OPERAND_FRINTK : + fields->f_FRk = value; + break; + case FRV_OPERAND_FRJ : + fields->f_FRj = value; + break; + case FRV_OPERAND_FRK : + fields->f_FRk = value; + break; + case FRV_OPERAND_FRKHI : + fields->f_FRk = value; + break; + case FRV_OPERAND_FRKLO : + fields->f_FRk = value; + break; + case FRV_OPERAND_GRDOUBLEK : + fields->f_GRk = value; + break; + case FRV_OPERAND_GRI : + fields->f_GRi = value; + break; + case FRV_OPERAND_GRJ : + fields->f_GRj = value; + break; + case FRV_OPERAND_GRK : + fields->f_GRk = value; + break; + case FRV_OPERAND_GRKHI : + fields->f_GRk = value; + break; + case FRV_OPERAND_GRKLO : + fields->f_GRk = value; + break; + case FRV_OPERAND_ICCI_1 : + fields->f_ICCi_1 = value; + break; + case FRV_OPERAND_ICCI_2 : + fields->f_ICCi_2 = value; + break; + case FRV_OPERAND_ICCI_3 : + fields->f_ICCi_3 = value; + break; + case FRV_OPERAND_LI : + fields->f_LI = value; + break; + case FRV_OPERAND_AE : + fields->f_ae = value; + break; + case FRV_OPERAND_CCOND : + fields->f_ccond = value; + break; + case FRV_OPERAND_COND : + fields->f_cond = value; + break; + case FRV_OPERAND_D12 : + fields->f_d12 = value; + break; + case FRV_OPERAND_DEBUG : + fields->f_debug = value; + break; + case FRV_OPERAND_EIR : + fields->f_eir = value; + break; + case FRV_OPERAND_HINT : + fields->f_hint = value; + break; + case FRV_OPERAND_HINT_NOT_TAKEN : + fields->f_hint = value; + break; + case FRV_OPERAND_HINT_TAKEN : + fields->f_hint = value; + break; + case FRV_OPERAND_LABEL16 : + fields->f_label16 = value; + break; + case FRV_OPERAND_LABEL24 : + fields->f_label24 = value; + break; + case FRV_OPERAND_LOCK : + fields->f_lock = value; + break; + case FRV_OPERAND_PACK : + fields->f_pack = value; + break; + case FRV_OPERAND_S10 : + fields->f_s10 = value; + break; + case FRV_OPERAND_S12 : + fields->f_d12 = value; + break; + case FRV_OPERAND_S16 : + fields->f_s16 = value; + break; + case FRV_OPERAND_S5 : + fields->f_s5 = value; + break; + case FRV_OPERAND_S6 : + fields->f_s6 = value; + break; + case FRV_OPERAND_S6_1 : + fields->f_s6_1 = value; + break; + case FRV_OPERAND_SLO16 : + fields->f_s16 = value; + break; + case FRV_OPERAND_SPR : + fields->f_spr = value; + break; + case FRV_OPERAND_U12 : + fields->f_u12 = value; + break; + case FRV_OPERAND_U16 : + fields->f_u16 = value; + break; + case FRV_OPERAND_U6 : + fields->f_u6 = value; + break; + case FRV_OPERAND_UHI16 : + fields->f_u16 = value; + break; + case FRV_OPERAND_ULO16 : + fields->f_u16 = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), + opindex); + abort (); + } +} + +/* Function to call before using the instruction builder tables. */ + +void +frv_cgen_init_ibld_table (cd) + CGEN_CPU_DESC cd; +{ + cd->insert_handlers = & frv_cgen_insert_handlers[0]; + cd->extract_handlers = & frv_cgen_extract_handlers[0]; + + cd->insert_operand = frv_cgen_insert_operand; + cd->extract_operand = frv_cgen_extract_operand; + + cd->get_int_operand = frv_cgen_get_int_operand; + cd->set_int_operand = frv_cgen_set_int_operand; + cd->get_vma_operand = frv_cgen_get_vma_operand; + cd->set_vma_operand = frv_cgen_set_vma_operand; +} diff --git a/opcodes/frv-opc.c b/opcodes/frv-opc.c new file mode 100644 index 00000000000..96325570a83 --- /dev/null +++ b/opcodes/frv-opc.c @@ -0,0 +1,5842 @@ +/* Instruction opcode table for frv. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "frv-desc.h" +#include "frv-opc.h" +#include "libiberty.h" + +/* -- opc.c */ +#include "elf/frv.h" + +static int match_unit + PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE, CGEN_ATTR_VALUE_TYPE)); +static int match_vliw + PARAMS ((VLIW_COMBO *, VLIW_COMBO *, int)); +static VLIW_COMBO * add_next_to_vliw + PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); +static int find_major_in_vliw + PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); +static int fr400_check_insn_major_constraints + PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); +static int fr500_check_insn_major_constraints + PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); +static int check_insn_major_constraints + PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); + +int +frv_is_branch_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) +{ + switch (mach) + { + case bfd_mach_fr400: + if (major >= FR400_MAJOR_B_1 && major <= FR400_MAJOR_B_6) + return 1; /* is a branch */ + break; + default: + if (major >= FR500_MAJOR_B_1 && major <= FR500_MAJOR_B_6) + return 1; /* is a branch */ + break; + } + + return 0; /* not a branch */ +} + +int +frv_is_float_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) +{ + switch (mach) + { + case bfd_mach_fr400: + return 0; /* No float insns */ + default: + if (major >= FR500_MAJOR_F_1 && major <= FR500_MAJOR_F_8) + return 1; /* is a float insn */ + break; + } + + return 0; /* not a branch */ +} + +int +frv_is_media_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) +{ + switch (mach) + { + case bfd_mach_fr400: + if (major >= FR400_MAJOR_M_1 && major <= FR400_MAJOR_M_2) + return 1; /* is a media insn */ + break; + default: + if (major >= FR500_MAJOR_M_1 && major <= FR500_MAJOR_M_8) + return 1; /* is a media insn */ + break; + } + + return 0; /* not a branch */ +} + +int +frv_is_branch_insn (const CGEN_INSN *insn) +{ + if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR), + bfd_mach_fr400)) + return 1; + if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR), + bfd_mach_fr500)) + return 1; + + return 0; +} + +int +frv_is_float_insn (const CGEN_INSN *insn) +{ + if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR), + bfd_mach_fr400)) + return 1; + if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR), + bfd_mach_fr500)) + return 1; + + return 0; +} + +int +frv_is_media_insn (const CGEN_INSN *insn) +{ + if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR), + bfd_mach_fr400)) + return 1; + if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR), + bfd_mach_fr500)) + return 1; + + return 0; +} + +/* This table represents the allowable packing for vliw insns for the fr400. + The fr400 has only 2 vliw slots. Represent this by not allowing any insns + in slots 2 and 3. + Subsets of any given row are also allowed. */ +static VLIW_COMBO fr400_allowed_vliw[] = +{ + /* slot0 slot1 slot2 slot3 */ + { UNIT_I0, UNIT_I1, UNIT_NIL, UNIT_NIL }, + { UNIT_I0, UNIT_FM0, UNIT_NIL, UNIT_NIL }, + { UNIT_I0, UNIT_B0, UNIT_NIL, UNIT_NIL }, + { UNIT_FM0, UNIT_FM1, UNIT_NIL, UNIT_NIL }, + { UNIT_FM0, UNIT_B0, UNIT_NIL, UNIT_NIL }, + { UNIT_B0, UNIT_NIL, UNIT_NIL, UNIT_NIL }, + { UNIT_C, UNIT_NIL, UNIT_NIL, UNIT_NIL }, + { UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL } +}; + +/* This table represents the allowable packing for vliw insns for the fr500. + Subsets of any given row are also allowed. */ +static VLIW_COMBO fr500_allowed_vliw[] = +{ + /* slot0 slot1 slot2 slot3 */ + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1 }, + { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_B0 }, + { UNIT_I0, UNIT_FM0, UNIT_FM1, UNIT_B0 }, + { UNIT_I0, UNIT_FM0, UNIT_B0, UNIT_B1 }, + { UNIT_I0, UNIT_I1, UNIT_B0, UNIT_B1 }, + { UNIT_I0, UNIT_B0, UNIT_B1, UNIT_NIL }, + { UNIT_FM0, UNIT_FM1, UNIT_B0, UNIT_B1 }, + { UNIT_FM0, UNIT_B0, UNIT_B1, UNIT_NIL }, + { UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL }, + { UNIT_C, UNIT_NIL, UNIT_NIL, UNIT_NIL }, + { UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL } +}; + +/* Some insns are assigned specialized implementation units which map to + different actual implementation units on different machines. These + tables perform that mapping. */ +static CGEN_ATTR_VALUE_TYPE fr400_unit_mapping[] = +{ +/* unit in insn actual unit */ +/* NIL */ UNIT_NIL, +/* I0 */ UNIT_I0, +/* I1 */ UNIT_I1, +/* I01 */ UNIT_I01, +/* FM0 */ UNIT_FM0, +/* FM1 */ UNIT_FM1, +/* FM01 */ UNIT_FM01, +/* B0 */ UNIT_B0, /* branches only in B0 unit. */ +/* B1 */ UNIT_B0, +/* B01 */ UNIT_B0, +/* C */ UNIT_C, +/* MULT-DIV */ UNIT_I0, /* multiply and divide only in I0 unit. */ +/* LOAD */ UNIT_I0 /* load only in I0 unit. */ +}; + +static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] = +{ +/* unit in insn actual unit */ +/* NIL */ UNIT_NIL, +/* I0 */ UNIT_I0, +/* I1 */ UNIT_I1, +/* I01 */ UNIT_I01, +/* FM0 */ UNIT_FM0, +/* FM1 */ UNIT_FM1, +/* FM01 */ UNIT_FM01, +/* B0 */ UNIT_B0, +/* B1 */ UNIT_B1, +/* B01 */ UNIT_B01, +/* C */ UNIT_C, +/* MULT-DIV */ UNIT_I01, /* multiply and divide in I0 or I1 unit. */ +/* LOAD */ UNIT_I01 /* load in I0 or I1 unit. */ +}; + +void +frv_vliw_reset (FRV_VLIW *vliw, unsigned long mach, unsigned long elf_flags) +{ + vliw->next_slot = 0; + vliw->constraint_violation = 0; + vliw->mach = mach; + vliw->elf_flags = elf_flags; + + switch (mach) + { + case bfd_mach_fr400: + vliw->current_vliw = fr400_allowed_vliw; + vliw->unit_mapping = fr400_unit_mapping; + break; + default: + vliw->current_vliw = fr500_allowed_vliw; + vliw->unit_mapping = fr500_unit_mapping; + break; + } +} + +/* Return 1 if unit1 is a match for unit2. + Unit1 comes from the insn's UNIT attribute. unit2 comes from one of the + *_allowed_vliw tables above. */ +static int +match_unit (FRV_VLIW *vliw, + CGEN_ATTR_VALUE_TYPE unit1, CGEN_ATTR_VALUE_TYPE unit2) +{ + /* Map any specialized implementation units to actual ones. */ + unit1 = vliw->unit_mapping[unit1]; + + if (unit1 == unit2) + return 1; + if (unit1 < unit2) + return 0; + + switch (unit1) + { + case UNIT_I01: + case UNIT_FM01: + case UNIT_B01: + /* The 01 versions of these units are within 2 enums of the 0 or 1 + versions. */ + if (unit1 - unit2 <= 2) + return 1; + break; + default: + break; + } + + return 0; +} + +/* Return 1 if the vliws match, 0 otherwise. */ + +static int +match_vliw (VLIW_COMBO *vliw1, VLIW_COMBO *vliw2, int vliw_size) +{ + int i; + + for (i = 0; i < vliw_size; ++i) + { + if ((*vliw1)[i] != (*vliw2)[i]) + return 0; + } + + return 1; +} + +/* Find the next vliw vliw in the table that can accomodate the new insn. + If one is found then return it. Otherwise return NULL. */ + +static VLIW_COMBO * +add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit) +{ + int next = vliw->next_slot; + VLIW_COMBO *current = vliw->current_vliw; + VLIW_COMBO *potential; + + if (next <= 0) + abort (); /* Should never happen */ + + /* The table is sorted by units allowed within slots, so vliws with + identical starting sequences are together. */ + potential = current; + do + { + if (match_unit (vliw, unit, (*potential)[next])) + return potential; + ++potential; + } + while (match_vliw (potential, current, next)); + + return NULL; +} + +/* Look for the given major insn type in the given vliw. Return 1 if found, + return 0 otherwise. */ + +static int +find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) +{ + int i; + + for (i = 0; i < vliw->next_slot; ++i) + if (vliw->major[i] == major) + return 1; + + return 0; +} + +/* Check for constraints between the insns in the vliw due to major insn + types. */ + +static int +fr400_check_insn_major_constraints ( + FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major +) +{ + /* In the cpu file, all media insns are represented as being allowed in + both media units. This makes it easier since this is the case for fr500. + Catch the invalid combinations here. Insns of major class FR400_MAJOR_M_2 + cannot coexist with any other media insn in a vliw. */ + switch (major) + { + case FR400_MAJOR_M_2: + return ! find_major_in_vliw (vliw, FR400_MAJOR_M_1) + && ! find_major_in_vliw (vliw, FR400_MAJOR_M_2); + default: + break; + } + return 1; +} + +static int +fr500_check_insn_major_constraints ( + FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major +) +{ + /* TODO: A table might be faster for some of the more complex instances + here. */ + switch (major) + { + case FR500_MAJOR_I_1: + case FR500_MAJOR_I_4: + case FR500_MAJOR_I_5: + case FR500_MAJOR_I_6: + case FR500_MAJOR_B_1: + case FR500_MAJOR_B_2: + case FR500_MAJOR_B_3: + case FR500_MAJOR_B_4: + case FR500_MAJOR_B_5: + case FR500_MAJOR_B_6: + case FR500_MAJOR_F_4: + case FR500_MAJOR_F_8: + case FR500_MAJOR_M_8: + return 1; /* OK */ + case FR500_MAJOR_I_2: + /* Cannot coexist with I-3 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_I_3); + case FR500_MAJOR_I_3: + /* Cannot coexist with I-2 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_I_2); + case FR500_MAJOR_F_1: + case FR500_MAJOR_F_2: + /* Cannot coexist with F-5, F-6, or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_F_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_F_3: + /* Cannot coexist with F-7, or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_F_7) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_F_5: + /* Cannot coexist with F-1, F-2, F-6, F-7, or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_F_1) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_2) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_7) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_F_6: + /* Cannot coexist with F-1, F-2, F-5, F-6, or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_F_1) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_2) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_F_7: + /* Cannot coexist with F-3, F-5, F-7, or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_F_3) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_7) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_M_1: + /* Cannot coexist with M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_M_2: + case FR500_MAJOR_M_3: + /* Cannot coexist with M-5, M-6 or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_M_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_M_4: + /* Cannot coexist with M-6 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_M_6); + case FR500_MAJOR_M_5: + /* Cannot coexist with M-2, M-3, M-5, M-6 or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_M_2) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_3) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_M_6: + /* Cannot coexist with M-2, M-3, M-4, M-5, M-6 or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_M_2) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_3) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_4) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); + case FR500_MAJOR_M_7: + /* Cannot coexist with M-1, M-2, M-3, M-5, M-6 or M-7 insn. */ + return ! find_major_in_vliw (vliw, FR500_MAJOR_M_1) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_2) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_3) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_1) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_2) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_3) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_5) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_6) + && ! find_major_in_vliw (vliw, FR500_MAJOR_F_7); + default: + abort (); + break; + } + return 1; +} + +static int +check_insn_major_constraints ( + FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major +) +{ + int rc; + switch (vliw->mach) + { + case bfd_mach_fr400: + rc = fr400_check_insn_major_constraints (vliw, major); + break; + default: + rc = fr500_check_insn_major_constraints (vliw, major); + break; + } + return rc; +} + +/* Add in insn to the VLIW vliw if possible. Return 0 if successful, + non-zero otherwise. */ +int +frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn) +{ + int index; + CGEN_ATTR_VALUE_TYPE major; + CGEN_ATTR_VALUE_TYPE unit; + VLIW_COMBO *new_vliw; + + if (vliw->constraint_violation || CGEN_INSN_INVALID_P (insn)) + return 1; + + index = vliw->next_slot; + if (index >= FRV_VLIW_SIZE) + return 1; + + unit = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_UNIT); + if (unit == UNIT_NIL) + abort (); /* no UNIT specified for this insn in frv.cpu */ + + if (vliw->mach == bfd_mach_fr400) + major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR); + else + major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR); + + if (index <= 0) + { + /* Any insn can be added to slot 0. */ + while (! match_unit (vliw, unit, (*vliw->current_vliw)[0])) + ++vliw->current_vliw; + vliw->major[0] = major; + vliw->next_slot = 1; + return 0; + } + + /* If there are already insns in the vliw(s) check to see that + this one can be added. Do this by finding an allowable vliw + combination that can accept the new insn. */ + if (! (vliw->elf_flags & EF_FRV_NOPACK)) + { + new_vliw = add_next_to_vliw (vliw, unit); + if (new_vliw && check_insn_major_constraints (vliw, major)) + { + vliw->current_vliw = new_vliw; + vliw->major[index] = major; + vliw->next_slot++; + return 0; + } + + /* The frv machine supports all packing conbinations. If we fail, + to add the insn, then it could not be handled as if it was the fr500. + Just return as if it was handled ok. */ + if (vliw->mach == bfd_mach_frv) + return 0; + } + + vliw->constraint_violation = 1; + return 1; +} + +int +spr_valid (regno) + long regno; +{ + if (regno < 0) return 0; + if (regno <= 4095) return 1; + return 0; +} +/* -- */ +/* The hash functions are recorded here to help keep assembler code out of + the disassembler and vice versa. */ + +static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); +static unsigned int asm_hash_insn PARAMS ((const char *)); +static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); +static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); + +/* Instruction formats. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define F(f) & frv_cgen_ifld_table[FRV_##f] +#else +#define F(f) & frv_cgen_ifld_table[FRV_/**/f] +#endif +static const CGEN_IFMT ifmt_empty = { + 0, 0, 0x0, { { 0 } } +}; + +static const CGEN_IFMT ifmt_add = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1_NULL) }, { F (F_OPE2) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_not = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_ICCI_1_NULL) }, { F (F_OPE2) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_smul = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1_NULL) }, { F (F_OPE2) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cadd = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cnot = { + 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_csmul = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addcc = { + 32, 32, 0x1fc03c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1) }, { F (F_OPE2) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_smulcc = { + 32, 32, 0x1fc03c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1) }, { F (F_OPE2) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addi = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_smuli = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addicc = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1) }, { F (F_S10) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_smulicc = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1) }, { F (F_S10) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmpb = { + 32, 32, 0x7ffc03c0, { { F (F_PACK) }, { F (F_GRK_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1) }, { F (F_OPE2) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_setlo = { + 32, 32, 0x1ff0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_MISC_NULL_4) }, { F (F_U16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sethi = { + 32, 32, 0x1ff0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_MISC_NULL_4) }, { F (F_U16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_setlos = { + 32, 32, 0x1ff0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_MISC_NULL_4) }, { F (F_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldsb = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldbf = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldc = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_CPRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldd = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lddf = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lddc = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_CPRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldsbi = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldbfi = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lddi = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lddfi = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stdf = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cldbf = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clddf = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cstdf = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stdfi = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movgf = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmovgf = { + 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movgs = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_OP) }, { F (F_SPR) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bra = { + 32, 32, 0x7ffc0000, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_LABEL16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bno = { + 32, 32, 0x7ffcffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_LABEL16_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_beq = { + 32, 32, 0x79fc0000, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2) }, { F (F_OP) }, { F (F_HINT) }, { F (F_LABEL16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbra = { + 32, 32, 0x7ffc0000, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_LABEL16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbno = { + 32, 32, 0x7ffcffff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_LABEL16_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbne = { + 32, 32, 0x79fc0000, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_HINT) }, { F (F_LABEL16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bctrlr = { + 32, 32, 0x7ffcefff, { { F (F_PACK) }, { F (F_COND_NULL) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bralr = { + 32, 32, 0x7ffcffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bnolr = { + 32, 32, 0x7ffcffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_beqlr = { + 32, 32, 0x79fcffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbralr = { + 32, 32, 0x7ffcffff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbnolr = { + 32, 32, 0x7ffcffff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fbeqlr = { + 32, 32, 0x79fcffff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bcralr = { + 32, 32, 0x7ffcefff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bceqlr = { + 32, 32, 0x79fcefff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fcbralr = { + 32, 32, 0x7ffcefff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fcbeqlr = { + 32, 32, 0x79fcefff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmpl = { + 32, 32, 0x7ffc0fc0, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LI_OFF) }, { F (F_OP) }, { F (F_GRI) }, { F (F_MISC_NULL_2) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_calll = { + 32, 32, 0x7ffc0fc0, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LI_ON) }, { F (F_OP) }, { F (F_GRI) }, { F (F_MISC_NULL_2) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmpil = { + 32, 32, 0x7ffc0000, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LI_OFF) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_callil = { + 32, 32, 0x7ffc0000, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LI_ON) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_call = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_OP) }, { F (F_LABEL24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rett = { + 32, 32, 0x7dffffff, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_DEBUG) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rei = { + 32, 32, 0x7ffc0fff, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_EIR) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tra = { + 32, 32, 0x7ffc0fc0, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_MISC_NULL_3) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tno = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_GRI_NULL) }, { F (F_MISC_NULL_3) }, { F (F_OPE4) }, { F (F_GRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_teq = { + 32, 32, 0x79fc0fc0, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2) }, { F (F_OP) }, { F (F_GRI) }, { F (F_MISC_NULL_3) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ftra = { + 32, 32, 0x7ffc0fc0, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_MISC_NULL_3) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ftno = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_GRI_NULL) }, { F (F_MISC_NULL_3) }, { F (F_OPE4) }, { F (F_GRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ftne = { + 32, 32, 0x79fc0fc0, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_GRI) }, { F (F_MISC_NULL_3) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tira = { + 32, 32, 0x7ffc0000, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tino = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_GRI_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tieq = { + 32, 32, 0x79fc0000, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ftira = { + 32, 32, 0x7ffc0000, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ftino = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2_NULL) }, { F (F_OP) }, { F (F_GRI_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ftine = { + 32, 32, 0x79fc0000, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_break = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_MISC_NULL_3) }, { F (F_OPE4) }, { F (F_GRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_andcr = { + 32, 32, 0x71ff8ff8, { { F (F_PACK) }, { F (F_MISC_NULL_6) }, { F (F_CRK) }, { F (F_OP) }, { F (F_MISC_NULL_7) }, { F (F_CRI) }, { F (F_OPE1) }, { F (F_MISC_NULL_8) }, { F (F_CRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_notcr = { + 32, 32, 0x71fffff8, { { F (F_PACK) }, { F (F_MISC_NULL_6) }, { F (F_CRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_MISC_NULL_8) }, { F (F_CRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ckra = { + 32, 32, 0x79ffffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_CRJ_INT) }, { F (F_OP) }, { F (F_MISC_NULL_5) }, { F (F_ICCI_3_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ckeq = { + 32, 32, 0x79fffffc, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_CRJ_INT) }, { F (F_OP) }, { F (F_MISC_NULL_5) }, { F (F_ICCI_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fckra = { + 32, 32, 0x79fffffc, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_CRJ_FLOAT) }, { F (F_OP) }, { F (F_MISC_NULL_5) }, { F (F_FCCI_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cckra = { + 32, 32, 0x79fff0ff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_CRJ_INT) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_MISC_NULL_9) }, { F (F_ICCI_3_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cckeq = { + 32, 32, 0x79fff0fc, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_CRJ_INT) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_MISC_NULL_9) }, { F (F_ICCI_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cfckra = { + 32, 32, 0x79fff0ff, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_CRJ_FLOAT) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_MISC_NULL_9) }, { F (F_FCCI_3_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cfckne = { + 32, 32, 0x79fff0fc, { { F (F_PACK) }, { F (F_FLT_CC) }, { F (F_CRJ_FLOAT) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_MISC_NULL_9) }, { F (F_FCCI_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cjmpl = { + 32, 32, 0x7ffc00c0, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LI_OFF) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ccalll = { + 32, 32, 0x7ffc00c0, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LI_ON) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ici = { + 32, 32, 0x7ffc0fc0, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_icei = { + 32, 32, 0x7dfc0fc0, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_AE) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_icpl = { + 32, 32, 0x7dfc0fc0, { { F (F_PACK) }, { F (F_MISC_NULL_1) }, { F (F_LOCK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_icul = { + 32, 32, 0x7ffc0fff, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bar = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_GRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cop1 = { + 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_CPRK) }, { F (F_OP) }, { F (F_CPRI) }, { F (F_S6_1) }, { F (F_CPRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clrgr = { + 32, 32, 0x1ffffff, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_GRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clrfr = { + 32, 32, 0x1ffffff, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_GRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fitos = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fstoi = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fitod = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fdtoi = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cfitos = { + 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cfstoi = { + 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fmovs = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fmovd = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cfmovs = { + 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fadds = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_faddd = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cfadds = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fcmps = { + 32, 32, 0x79fc0fc0, { { F (F_PACK) }, { F (F_COND_NULL) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fcmpd = { + 32, 32, 0x79fc0fc0, { { F (F_PACK) }, { F (F_COND_NULL) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cfcmps = { + 32, 32, 0x79fc00c0, { { F (F_PACK) }, { F (F_COND_NULL) }, { F (F_FCCI_2) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mhsetlos = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_OPE1) }, { F (F_U12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mhsethis = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_OPE1) }, { F (F_U12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mhdsets = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_OPE1) }, { F (F_U12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mhsetloh = { + 32, 32, 0x1ffffe0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_MISC_NULL_11) }, { F (F_S5) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mhsethih = { + 32, 32, 0x1ffffe0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_MISC_NULL_11) }, { F (F_S5) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mhdseth = { + 32, 32, 0x1ffffe0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_MISC_NULL_11) }, { F (F_S5) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mand = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmand = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mnot = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmnot = { + 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mrotli = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_U6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mcut = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mcuti = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_S6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mcmpsh = { + 32, 32, 0x79fc0fc0, { { F (F_PACK) }, { F (F_COND_NULL) }, { F (F_FCCK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mabshs = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_maddaccs = { + 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_ACCJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mmulhs = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmmulhs = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mmachu = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_ACC40UK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmmachu = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_ACC40UK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmexpdhw = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_U6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_munpackh = { + 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmbtoh = { + 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mclracc = { + 32, 32, 0x1fdffff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_A) }, { F (F_MISC_NULL_10) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mrdacc = { + 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mrdaccg = { + 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_ACCGI) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mwtacc = { + 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mwtaccg = { + 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_ACCGK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fnop = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +}; + +#undef F + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) FRV_OPERAND_##op +#else +#define OPERAND(op) FRV_OPERAND_/**/op +#endif +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The instruction table. */ + +static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, +/* add$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x0 } + }, +/* sub$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x100 } + }, +/* and$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x40000 } + }, +/* or$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x40080 } + }, +/* xor$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x40100 } + }, +/* not$pack $GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_not, { 0x40180 } + }, +/* sdiv$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x380 } + }, +/* nsdiv$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x40380 } + }, +/* udiv$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x3c0 } + }, +/* nudiv$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x403c0 } + }, +/* smul$pack $GRi,$GRj,$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRDOUBLEK), 0 } }, + & ifmt_smul, { 0x200 } + }, +/* umul$pack $GRi,$GRj,$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRDOUBLEK), 0 } }, + & ifmt_smul, { 0x280 } + }, +/* sll$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x40200 } + }, +/* srl$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x40280 } + }, +/* sra$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x40300 } + }, +/* scan$pack $GRi,$GRj,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), 0 } }, + & ifmt_add, { 0x2c0000 } + }, +/* cadd$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1600000 } + }, +/* csub$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1600040 } + }, +/* cand$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1680000 } + }, +/* cor$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1680040 } + }, +/* cxor$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1680080 } + }, +/* cnot$pack $GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cnot, { 0x16800c0 } + }, +/* csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRDOUBLEK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_csmul, { 0x1600080 } + }, +/* csdiv$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x16000c0 } + }, +/* cudiv$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x16400c0 } + }, +/* csll$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1700000 } + }, +/* csrl$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1700040 } + }, +/* csra$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1700080 } + }, +/* cscan$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x19400c0 } + }, +/* addcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x40 } + }, +/* subcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x140 } + }, +/* andcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x40040 } + }, +/* orcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x400c0 } + }, +/* xorcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x40140 } + }, +/* sllcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x40240 } + }, +/* srlcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x402c0 } + }, +/* sracc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x40340 } + }, +/* smulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRDOUBLEK), ',', OP (ICCI_1), 0 } }, + & ifmt_smulcc, { 0x240 } + }, +/* umulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRDOUBLEK), ',', OP (ICCI_1), 0 } }, + & ifmt_smulcc, { 0x2c0 } + }, +/* caddcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1640000 } + }, +/* csubcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1640040 } + }, +/* csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRDOUBLEK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_csmul, { 0x1640080 } + }, +/* candcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x16c0000 } + }, +/* corcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x16c0040 } + }, +/* cxorcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x16c0080 } + }, +/* csllcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1740000 } + }, +/* csrlcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1740040 } + }, +/* csracc$pack $GRi,$GRj,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1740080 } + }, +/* addx$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x80 } + }, +/* subx$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x180 } + }, +/* addxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0xc0 } + }, +/* subxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addcc, { 0x1c0 } + }, +/* addi$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0x400000 } + }, +/* subi$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0x500000 } + }, +/* andi$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0x800000 } + }, +/* ori$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0x880000 } + }, +/* xori$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0x900000 } + }, +/* sdivi$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0x780000 } + }, +/* nsdivi$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0xb80000 } + }, +/* udivi$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0x7c0000 } + }, +/* nudivi$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0xbc0000 } + }, +/* smuli$pack $GRi,$s12,$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRDOUBLEK), 0 } }, + & ifmt_smuli, { 0x600000 } + }, +/* umuli$pack $GRi,$s12,$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRDOUBLEK), 0 } }, + & ifmt_smuli, { 0x680000 } + }, +/* slli$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0xa00000 } + }, +/* srli$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0xa80000 } + }, +/* srai$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0xb00000 } + }, +/* scani$pack $GRi,$s12,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), ',', OP (GRK), 0 } }, + & ifmt_addi, { 0x11c0000 } + }, +/* addicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0x440000 } + }, +/* subicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0x540000 } + }, +/* andicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0x840000 } + }, +/* oricc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0x8c0000 } + }, +/* xoricc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0x940000 } + }, +/* smulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRDOUBLEK), ',', OP (ICCI_1), 0 } }, + & ifmt_smulicc, { 0x640000 } + }, +/* umulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRDOUBLEK), ',', OP (ICCI_1), 0 } }, + & ifmt_smulicc, { 0x6c0000 } + }, +/* sllicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0xa40000 } + }, +/* srlicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0xac0000 } + }, +/* sraicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0xb40000 } + }, +/* addxi$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0x480000 } + }, +/* subxi$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0x580000 } + }, +/* addxicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0x4c0000 } + }, +/* subxicc$pack $GRi,$s10,$GRk,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (GRK), ',', OP (ICCI_1), 0 } }, + & ifmt_addicc, { 0x5c0000 } + }, +/* cmpb$pack $GRi,$GRj,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (ICCI_1), 0 } }, + & ifmt_cmpb, { 0x300 } + }, +/* cmpba$pack $GRi,$GRj,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (ICCI_1), 0 } }, + & ifmt_cmpb, { 0x340 } + }, +/* setlo$pack $ulo16,$GRklo */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ULO16), ',', OP (GRKLO), 0 } }, + & ifmt_setlo, { 0xf40000 } + }, +/* sethi$pack $uhi16,$GRkhi */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (UHI16), ',', OP (GRKHI), 0 } }, + & ifmt_sethi, { 0xf80000 } + }, +/* setlos$pack $slo16,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (SLO16), ',', OP (GRK), 0 } }, + & ifmt_setlos, { 0xfc0000 } + }, +/* ldsb$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80000 } + }, +/* ldub$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80040 } + }, +/* ldsh$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80080 } + }, +/* lduh$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x800c0 } + }, +/* ld$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80100 } + }, +/* ldbf$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80200 } + }, +/* ldhf$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80240 } + }, +/* ldf$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80280 } + }, +/* ldc$pack @($GRi,$GRj),$CPRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CPRK), 0 } }, + & ifmt_ldc, { 0x80340 } + }, +/* nldsb$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80800 } + }, +/* nldub$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80840 } + }, +/* nldsh$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80880 } + }, +/* nlduh$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x808c0 } + }, +/* nld$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80900 } + }, +/* nldbf$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80a00 } + }, +/* nldhf$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80a40 } + }, +/* nldf$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80a80 } + }, +/* ldd$pack @($GRi,$GRj),$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRDOUBLEK), 0 } }, + & ifmt_ldd, { 0x80140 } + }, +/* lddf$pack @($GRi,$GRj),$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRDOUBLEK), 0 } }, + & ifmt_lddf, { 0x802c0 } + }, +/* lddc$pack @($GRi,$GRj),$CPRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CPRDOUBLEK), 0 } }, + & ifmt_lddc, { 0x80380 } + }, +/* nldd$pack @($GRi,$GRj),$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRDOUBLEK), 0 } }, + & ifmt_ldd, { 0x80940 } + }, +/* nlddf$pack @($GRi,$GRj),$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRDOUBLEK), 0 } }, + & ifmt_lddf, { 0x80ac0 } + }, +/* ldq$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80180 } + }, +/* ldqf$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80300 } + }, +/* ldqc$pack @($GRi,$GRj),$CPRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CPRK), 0 } }, + & ifmt_ldc, { 0x803c0 } + }, +/* nldq$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80980 } + }, +/* nldqf$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80b00 } + }, +/* ldsbu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80400 } + }, +/* ldubu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80440 } + }, +/* ldshu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80480 } + }, +/* lduhu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x804c0 } + }, +/* ldu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80500 } + }, +/* nldsbu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80c00 } + }, +/* nldubu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80c40 } + }, +/* nldshu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80c80 } + }, +/* nlduhu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80cc0 } + }, +/* nldu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80d00 } + }, +/* ldbfu$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80600 } + }, +/* ldhfu$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80640 } + }, +/* ldfu$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80680 } + }, +/* ldcu$pack @($GRi,$GRj),$CPRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CPRK), 0 } }, + & ifmt_ldc, { 0x80740 } + }, +/* nldbfu$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80e00 } + }, +/* nldhfu$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80e40 } + }, +/* nldfu$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80e80 } + }, +/* lddu$pack @($GRi,$GRj),$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRDOUBLEK), 0 } }, + & ifmt_ldd, { 0x80540 } + }, +/* nlddu$pack @($GRi,$GRj),$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRDOUBLEK), 0 } }, + & ifmt_ldd, { 0x80d40 } + }, +/* lddfu$pack @($GRi,$GRj),$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRDOUBLEK), 0 } }, + & ifmt_lddf, { 0x806c0 } + }, +/* lddcu$pack @($GRi,$GRj),$CPRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CPRDOUBLEK), 0 } }, + & ifmt_lddc, { 0x80780 } + }, +/* nlddfu$pack @($GRi,$GRj),$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRDOUBLEK), 0 } }, + & ifmt_lddf, { 0x80ec0 } + }, +/* ldqu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80580 } + }, +/* nldqu$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0x80d80 } + }, +/* ldqfu$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80700 } + }, +/* ldqcu$pack @($GRi,$GRj),$CPRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CPRK), 0 } }, + & ifmt_ldc, { 0x807c0 } + }, +/* nldqfu$pack @($GRi,$GRj),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbf, { 0x80f00 } + }, +/* ldsbi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0xc00000 } + }, +/* ldshi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0xc40000 } + }, +/* ldi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0xc80000 } + }, +/* ldubi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0xd40000 } + }, +/* lduhi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0xd80000 } + }, +/* ldbfi$pack @($GRi,$d12),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbfi, { 0xe00000 } + }, +/* ldhfi$pack @($GRi,$d12),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbfi, { 0xe40000 } + }, +/* ldfi$pack @($GRi,$d12),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbfi, { 0xe80000 } + }, +/* nldsbi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0x1000000 } + }, +/* nldubi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0x1040000 } + }, +/* nldshi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0x1080000 } + }, +/* nlduhi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0x10c0000 } + }, +/* nldi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0x1100000 } + }, +/* nldbfi$pack @($GRi,$d12),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbfi, { 0x1200000 } + }, +/* nldhfi$pack @($GRi,$d12),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbfi, { 0x1240000 } + }, +/* nldfi$pack @($GRi,$d12),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbfi, { 0x1280000 } + }, +/* lddi$pack @($GRi,$d12),$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRDOUBLEK), 0 } }, + & ifmt_lddi, { 0xcc0000 } + }, +/* lddfi$pack @($GRi,$d12),$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRDOUBLEK), 0 } }, + & ifmt_lddfi, { 0xec0000 } + }, +/* nlddi$pack @($GRi,$d12),$GRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRDOUBLEK), 0 } }, + & ifmt_lddi, { 0x1140000 } + }, +/* nlddfi$pack @($GRi,$d12),$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRDOUBLEK), 0 } }, + & ifmt_lddfi, { 0x12c0000 } + }, +/* ldqi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0xd00000 } + }, +/* ldqfi$pack @($GRi,$d12),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbfi, { 0xf00000 } + }, +/* nldqi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0x1180000 } + }, +/* nldqfi$pack @($GRi,$d12),$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (FRINTK), 0 } }, + & ifmt_ldbfi, { 0x1300000 } + }, +/* stb$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc0000 } + }, +/* sth$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc0040 } + }, +/* st$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc0080 } + }, +/* stbf$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0200 } + }, +/* sthf$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0240 } + }, +/* stf$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0280 } + }, +/* stc$pack $CPRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CPRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldc, { 0xc0940 } + }, +/* rstb$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc0800 } + }, +/* rsth$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc0840 } + }, +/* rst$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc0880 } + }, +/* rstbf$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0a00 } + }, +/* rsthf$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0a40 } + }, +/* rstf$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0a80 } + }, +/* std$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc00c0 } + }, +/* stdf$pack $FRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_stdf, { 0xc02c0 } + }, +/* stdc$pack $CPRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CPRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldc, { 0xc0980 } + }, +/* rstd$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc08c0 } + }, +/* rstdf$pack $FRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_stdf, { 0xc0ac0 } + }, +/* stq$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc0100 } + }, +/* stqf$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0300 } + }, +/* stqc$pack $CPRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CPRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldc, { 0xc09c0 } + }, +/* rstq$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc0900 } + }, +/* rstqf$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0b00 } + }, +/* stbu$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc0400 } + }, +/* sthu$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc0440 } + }, +/* stu$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc0480 } + }, +/* stbfu$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0600 } + }, +/* sthfu$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0640 } + }, +/* stfu$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0680 } + }, +/* stcu$pack $CPRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CPRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldc, { 0xc0b40 } + }, +/* stdu$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc04c0 } + }, +/* stdfu$pack $FRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_stdf, { 0xc06c0 } + }, +/* stdcu$pack $CPRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CPRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldc, { 0xc0b80 } + }, +/* stqu$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc0500 } + }, +/* stqfu$pack $FRintk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldbf, { 0xc0700 } + }, +/* stqcu$pack $CPRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CPRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldc, { 0xc0bc0 } + }, +/* cldsb$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1780000 } + }, +/* cldub$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1780040 } + }, +/* cldsh$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1780080 } + }, +/* clduh$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x17800c0 } + }, +/* cld$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x17c0000 } + }, +/* cldbf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x1800000 } + }, +/* cldhf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x1800040 } + }, +/* cldf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x1800080 } + }, +/* cldd$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRDOUBLEK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_csmul, { 0x17c0040 } + }, +/* clddf$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRDOUBLEK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_clddf, { 0x18000c0 } + }, +/* cldq$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x17c0080 } + }, +/* cldsbu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1840000 } + }, +/* cldubu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1840040 } + }, +/* cldshu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1840080 } + }, +/* clduhu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x18400c0 } + }, +/* cldu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1880000 } + }, +/* cldbfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x18c0000 } + }, +/* cldhfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x18c0040 } + }, +/* cldfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x18c0080 } + }, +/* clddu$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRDOUBLEK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_csmul, { 0x1880040 } + }, +/* clddfu$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (FRDOUBLEK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_clddf, { 0x18c00c0 } + }, +/* cldqu$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1880080 } + }, +/* cstb$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1900000 } + }, +/* csth$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1900040 } + }, +/* cst$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1900080 } + }, +/* cstbf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x1980000 } + }, +/* csthf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x1980040 } + }, +/* cstf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x1980080 } + }, +/* cstd$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x19000c0 } + }, +/* cstdf$pack $FRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cstdf, { 0x19800c0 } + }, +/* cstq$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1940000 } + }, +/* cstbu$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x19c0000 } + }, +/* csthu$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x19c0040 } + }, +/* cstu$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x19c0080 } + }, +/* cstbfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x1a00000 } + }, +/* csthfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x1a00040 } + }, +/* cstfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cldbf, { 0x1a00080 } + }, +/* cstdu$pack $GRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x19c00c0 } + }, +/* cstdfu$pack $FRk,@($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cstdf, { 0x1a000c0 } + }, +/* stbi$pack $GRk,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_ldsbi, { 0x1400000 } + }, +/* sthi$pack $GRk,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_ldsbi, { 0x1440000 } + }, +/* sti$pack $GRk,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_ldsbi, { 0x1480000 } + }, +/* stbfi$pack $FRintk,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_ldbfi, { 0x1380000 } + }, +/* sthfi$pack $FRintk,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_ldbfi, { 0x13c0000 } + }, +/* stfi$pack $FRintk,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_ldbfi, { 0x1540000 } + }, +/* stdi$pack $GRk,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_ldsbi, { 0x14c0000 } + }, +/* stdfi$pack $FRk,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_stdfi, { 0x1580000 } + }, +/* stqi$pack $GRk,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_ldsbi, { 0x1500000 } + }, +/* stqfi$pack $FRintk,@($GRi,$d12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (D12), ')', 0 } }, + & ifmt_ldbfi, { 0x15c0000 } + }, +/* swap$pack @($GRi,$GRj),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsb, { 0xc0140 } + }, +/* swapi$pack @($GRi,$d12),$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (D12), ')', ',', OP (GRK), 0 } }, + & ifmt_ldsbi, { 0x1340000 } + }, +/* cswap$pack @($GRi,$GRj),$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cadd, { 0x1940080 } + }, +/* movgf$pack $GRj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (FRINTK), 0 } }, + & ifmt_movgf, { 0xc0540 } + }, +/* movfg$pack $FRintk,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', OP (GRJ), 0 } }, + & ifmt_movgf, { 0xc0340 } + }, +/* movgfd$pack $GRj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (FRINTK), 0 } }, + & ifmt_movgf, { 0xc0580 } + }, +/* movfgd$pack $FRintk,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', OP (GRJ), 0 } }, + & ifmt_movgf, { 0xc0380 } + }, +/* movgfq$pack $GRj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (FRINTK), 0 } }, + & ifmt_movgf, { 0xc05c0 } + }, +/* movfgq$pack $FRintk,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', OP (GRJ), 0 } }, + & ifmt_movgf, { 0xc03c0 } + }, +/* cmovgf$pack $GRj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmovgf, { 0x1a40000 } + }, +/* cmovfg$pack $FRintk,$GRj,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', OP (GRJ), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmovgf, { 0x1a40080 } + }, +/* cmovgfd$pack $GRj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmovgf, { 0x1a40040 } + }, +/* cmovfgd$pack $FRintk,$GRj,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', OP (GRJ), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmovgf, { 0x1a400c0 } + }, +/* movgs$pack $GRj,$spr */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRJ), ',', OP (SPR), 0 } }, + & ifmt_movgs, { 0xc0180 } + }, +/* movsg$pack $spr,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (SPR), ',', OP (GRJ), 0 } }, + & ifmt_movgs, { 0xc01c0 } + }, +/* bra$pack $hint_taken$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (HINT_TAKEN), OP (LABEL16), 0 } }, + & ifmt_bra, { 0x40180000 } + }, +/* bno$pack$hint_not_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), OP (HINT_NOT_TAKEN), 0 } }, + & ifmt_bno, { 0x180000 } + }, +/* beq$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x20180000 } + }, +/* bne$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x60180000 } + }, +/* ble$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x38180000 } + }, +/* bgt$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x78180000 } + }, +/* blt$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x18180000 } + }, +/* bge$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x58180000 } + }, +/* bls$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x28180000 } + }, +/* bhi$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x68180000 } + }, +/* bc$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x8180000 } + }, +/* bnc$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x48180000 } + }, +/* bn$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x30180000 } + }, +/* bp$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x70180000 } + }, +/* bv$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x10180000 } + }, +/* bnv$pack $ICCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_beq, { 0x50180000 } + }, +/* fbra$pack $hint_taken$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (HINT_TAKEN), OP (LABEL16), 0 } }, + & ifmt_fbra, { 0x781c0000 } + }, +/* fbno$pack$hint_not_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), OP (HINT_NOT_TAKEN), 0 } }, + & ifmt_fbno, { 0x1c0000 } + }, +/* fbne$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x381c0000 } + }, +/* fbeq$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x401c0000 } + }, +/* fblg$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x301c0000 } + }, +/* fbue$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x481c0000 } + }, +/* fbul$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x281c0000 } + }, +/* fbge$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x501c0000 } + }, +/* fblt$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x201c0000 } + }, +/* fbuge$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x581c0000 } + }, +/* fbug$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x181c0000 } + }, +/* fble$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x601c0000 } + }, +/* fbgt$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x101c0000 } + }, +/* fbule$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x681c0000 } + }, +/* fbu$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x81c0000 } + }, +/* fbo$pack $FCCi_2,$hint,$label16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), ',', OP (LABEL16), 0 } }, + & ifmt_fbne, { 0x701c0000 } + }, +/* bctrlr$pack $ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bctrlr, { 0x382000 } + }, +/* bralr$pack$hint_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), OP (HINT_TAKEN), 0 } }, + & ifmt_bralr, { 0x40384000 } + }, +/* bnolr$pack$hint_not_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), OP (HINT_NOT_TAKEN), 0 } }, + & ifmt_bnolr, { 0x384000 } + }, +/* beqlr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x20384000 } + }, +/* bnelr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x60384000 } + }, +/* blelr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x38384000 } + }, +/* bgtlr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x78384000 } + }, +/* bltlr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x18384000 } + }, +/* bgelr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x58384000 } + }, +/* blslr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x28384000 } + }, +/* bhilr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x68384000 } + }, +/* bclr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x8384000 } + }, +/* bnclr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x48384000 } + }, +/* bnlr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x30384000 } + }, +/* bplr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x70384000 } + }, +/* bvlr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x10384000 } + }, +/* bnvlr$pack $ICCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (HINT), 0 } }, + & ifmt_beqlr, { 0x50384000 } + }, +/* fbralr$pack$hint_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), OP (HINT_TAKEN), 0 } }, + & ifmt_fbralr, { 0x7838c000 } + }, +/* fbnolr$pack$hint_not_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), OP (HINT_NOT_TAKEN), 0 } }, + & ifmt_fbnolr, { 0x38c000 } + }, +/* fbeqlr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x4038c000 } + }, +/* fbnelr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x3838c000 } + }, +/* fblglr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x3038c000 } + }, +/* fbuelr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x4838c000 } + }, +/* fbullr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x2838c000 } + }, +/* fbgelr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x5038c000 } + }, +/* fbltlr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x2038c000 } + }, +/* fbugelr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x5838c000 } + }, +/* fbuglr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x1838c000 } + }, +/* fblelr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x6038c000 } + }, +/* fbgtlr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x1038c000 } + }, +/* fbulelr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x6838c000 } + }, +/* fbulr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x838c000 } + }, +/* fbolr$pack $FCCi_2,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (HINT), 0 } }, + & ifmt_fbeqlr, { 0x7038c000 } + }, +/* bcralr$pack $ccond$hint_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CCOND), OP (HINT_TAKEN), 0 } }, + & ifmt_bcralr, { 0x40386000 } + }, +/* bcnolr$pack$hint_not_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), OP (HINT_NOT_TAKEN), 0 } }, + & ifmt_bnolr, { 0x386000 } + }, +/* bceqlr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x20386000 } + }, +/* bcnelr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x60386000 } + }, +/* bclelr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x38386000 } + }, +/* bcgtlr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x78386000 } + }, +/* bcltlr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x18386000 } + }, +/* bcgelr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x58386000 } + }, +/* bclslr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x28386000 } + }, +/* bchilr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x68386000 } + }, +/* bcclr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x8386000 } + }, +/* bcnclr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x48386000 } + }, +/* bcnlr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x30386000 } + }, +/* bcplr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x70386000 } + }, +/* bcvlr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x10386000 } + }, +/* bcnvlr$pack $ICCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_bceqlr, { 0x50386000 } + }, +/* fcbralr$pack $ccond$hint_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CCOND), OP (HINT_TAKEN), 0 } }, + & ifmt_fcbralr, { 0x7838e000 } + }, +/* fcbnolr$pack$hint_not_taken */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), OP (HINT_NOT_TAKEN), 0 } }, + & ifmt_fbnolr, { 0x38e000 } + }, +/* fcbeqlr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x4038e000 } + }, +/* fcbnelr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x3838e000 } + }, +/* fcblglr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x3038e000 } + }, +/* fcbuelr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x4838e000 } + }, +/* fcbullr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x2838e000 } + }, +/* fcbgelr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x5038e000 } + }, +/* fcbltlr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x2038e000 } + }, +/* fcbugelr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x5838e000 } + }, +/* fcbuglr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x1838e000 } + }, +/* fcblelr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x6038e000 } + }, +/* fcbgtlr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x1038e000 } + }, +/* fcbulelr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x6838e000 } + }, +/* fcbulr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x838e000 } + }, +/* fcbolr$pack $FCCi_2,$ccond,$hint */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (CCOND), ',', OP (HINT), 0 } }, + & ifmt_fcbeqlr, { 0x7038e000 } + }, +/* jmpl$pack @($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_jmpl, { 0x300000 } + }, +/* calll$pack @($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_calll, { 0x2300000 } + }, +/* jmpil$pack @($GRi,$s12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (S12), ')', 0 } }, + & ifmt_jmpil, { 0x340000 } + }, +/* callil$pack @($GRi,$s12) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (S12), ')', 0 } }, + & ifmt_callil, { 0x2340000 } + }, +/* call$pack $label24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (LABEL24), 0 } }, + & ifmt_call, { 0x3c0000 } + }, +/* rett$pack $debug */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (DEBUG), 0 } }, + & ifmt_rett, { 0x140000 } + }, +/* rei$pack $eir */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (EIR), 0 } }, + & ifmt_rei, { 0xdc0000 } + }, +/* tra$pack $GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_tra, { 0x40100000 } + }, +/* tno$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_tno, { 0x100000 } + }, +/* teq$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x20100000 } + }, +/* tne$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x60100000 } + }, +/* tle$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x38100000 } + }, +/* tgt$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x78100000 } + }, +/* tlt$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x18100000 } + }, +/* tge$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x58100000 } + }, +/* tls$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x28100000 } + }, +/* thi$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x68100000 } + }, +/* tc$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x8100000 } + }, +/* tnc$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x48100000 } + }, +/* tn$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x30100000 } + }, +/* tp$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x70100000 } + }, +/* tv$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x10100000 } + }, +/* tnv$pack $ICCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_teq, { 0x50100000 } + }, +/* ftra$pack $GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftra, { 0x78100040 } + }, +/* ftno$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_ftno, { 0x100040 } + }, +/* ftne$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x38100040 } + }, +/* fteq$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x40100040 } + }, +/* ftlg$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x30100040 } + }, +/* ftue$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x48100040 } + }, +/* ftul$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x28100040 } + }, +/* ftge$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x50100040 } + }, +/* ftlt$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x20100040 } + }, +/* ftuge$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x58100040 } + }, +/* ftug$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x18100040 } + }, +/* ftle$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x60100040 } + }, +/* ftgt$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x10100040 } + }, +/* ftule$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x68100040 } + }, +/* ftu$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x8100040 } + }, +/* fto$pack $FCCi_2,$GRi,$GRj */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (GRJ), 0 } }, + & ifmt_ftne, { 0x70100040 } + }, +/* tira$pack $GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tira, { 0x40700000 } + }, +/* tino$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_tino, { 0x700000 } + }, +/* tieq$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x20700000 } + }, +/* tine$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x60700000 } + }, +/* tile$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x38700000 } + }, +/* tigt$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x78700000 } + }, +/* tilt$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x18700000 } + }, +/* tige$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x58700000 } + }, +/* tils$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x28700000 } + }, +/* tihi$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x68700000 } + }, +/* tic$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x8700000 } + }, +/* tinc$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x48700000 } + }, +/* tin$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x30700000 } + }, +/* tip$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x70700000 } + }, +/* tiv$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x10700000 } + }, +/* tinv$pack $ICCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_tieq, { 0x50700000 } + }, +/* ftira$pack $GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftira, { 0x78740000 } + }, +/* ftino$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_ftino, { 0x740000 } + }, +/* ftine$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x38740000 } + }, +/* ftieq$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x40740000 } + }, +/* ftilg$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x30740000 } + }, +/* ftiue$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x48740000 } + }, +/* ftiul$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x28740000 } + }, +/* ftige$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x50740000 } + }, +/* ftilt$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x20740000 } + }, +/* ftiuge$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x58740000 } + }, +/* ftiug$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x18740000 } + }, +/* ftile$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x60740000 } + }, +/* ftigt$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x10740000 } + }, +/* ftiule$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x68740000 } + }, +/* ftiu$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x8740000 } + }, +/* ftio$pack $FCCi_2,$GRi,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_2), ',', OP (GRI), ',', OP (S12), 0 } }, + & ifmt_ftine, { 0x70740000 } + }, +/* break$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_break, { 0x1000c0 } + }, +/* mtrap$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_break, { 0x100080 } + }, +/* andcr$pack $CRi,$CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRI), ',', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_andcr, { 0x280200 } + }, +/* orcr$pack $CRi,$CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRI), ',', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_andcr, { 0x280240 } + }, +/* xorcr$pack $CRi,$CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRI), ',', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_andcr, { 0x280280 } + }, +/* nandcr$pack $CRi,$CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRI), ',', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_andcr, { 0x280300 } + }, +/* norcr$pack $CRi,$CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRI), ',', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_andcr, { 0x280340 } + }, +/* andncr$pack $CRi,$CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRI), ',', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_andcr, { 0x280400 } + }, +/* orncr$pack $CRi,$CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRI), ',', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_andcr, { 0x280440 } + }, +/* nandncr$pack $CRi,$CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRI), ',', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_andcr, { 0x280500 } + }, +/* norncr$pack $CRi,$CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRI), ',', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_andcr, { 0x280540 } + }, +/* notcr$pack $CRj,$CRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRJ), ',', OP (CRK), 0 } }, + & ifmt_notcr, { 0x2802c0 } + }, +/* ckra$pack $CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRJ_INT), 0 } }, + & ifmt_ckra, { 0x40200000 } + }, +/* ckno$pack $CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRJ_INT), 0 } }, + & ifmt_ckra, { 0x200000 } + }, +/* ckeq$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x20200000 } + }, +/* ckne$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x60200000 } + }, +/* ckle$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x38200000 } + }, +/* ckgt$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x78200000 } + }, +/* cklt$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x18200000 } + }, +/* ckge$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x58200000 } + }, +/* ckls$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x28200000 } + }, +/* ckhi$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x68200000 } + }, +/* ckc$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x8200000 } + }, +/* cknc$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x48200000 } + }, +/* ckn$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x30200000 } + }, +/* ckp$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x70200000 } + }, +/* ckv$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x10200000 } + }, +/* cknv$pack $ICCi_3,$CRj_int */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), 0 } }, + & ifmt_ckeq, { 0x50200000 } + }, +/* fckra$pack $CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x78240000 } + }, +/* fckno$pack $CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x240000 } + }, +/* fckne$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x38240000 } + }, +/* fckeq$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x40240000 } + }, +/* fcklg$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x30240000 } + }, +/* fckue$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x48240000 } + }, +/* fckul$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x28240000 } + }, +/* fckge$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x50240000 } + }, +/* fcklt$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x20240000 } + }, +/* fckuge$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x58240000 } + }, +/* fckug$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x18240000 } + }, +/* fckle$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x60240000 } + }, +/* fckgt$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x10240000 } + }, +/* fckule$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x68240000 } + }, +/* fcku$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x8240000 } + }, +/* fcko$pack $FCCi_3,$CRj_float */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), 0 } }, + & ifmt_fckra, { 0x70240000 } + }, +/* cckra$pack $CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckra, { 0x41a80000 } + }, +/* cckno$pack $CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckra, { 0x1a80000 } + }, +/* cckeq$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x21a80000 } + }, +/* cckne$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x61a80000 } + }, +/* cckle$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x39a80000 } + }, +/* cckgt$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x79a80000 } + }, +/* ccklt$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x19a80000 } + }, +/* cckge$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x59a80000 } + }, +/* cckls$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x29a80000 } + }, +/* cckhi$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x69a80000 } + }, +/* cckc$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x9a80000 } + }, +/* ccknc$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x49a80000 } + }, +/* cckn$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x31a80000 } + }, +/* cckp$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x71a80000 } + }, +/* cckv$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x11a80000 } + }, +/* ccknv$pack $ICCi_3,$CRj_int,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ICCI_3), ',', OP (CRJ_INT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cckeq, { 0x51a80000 } + }, +/* cfckra$pack $CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckra, { 0x79a80040 } + }, +/* cfckno$pack $CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckra, { 0x1a80040 } + }, +/* cfckne$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x39a80040 } + }, +/* cfckeq$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x41a80040 } + }, +/* cfcklg$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x31a80040 } + }, +/* cfckue$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x49a80040 } + }, +/* cfckul$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x29a80040 } + }, +/* cfckge$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x51a80040 } + }, +/* cfcklt$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x21a80040 } + }, +/* cfckuge$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x59a80040 } + }, +/* cfckug$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x19a80040 } + }, +/* cfckle$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x61a80040 } + }, +/* cfckgt$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x11a80040 } + }, +/* cfckule$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x69a80040 } + }, +/* cfcku$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x9a80040 } + }, +/* cfcko$pack $FCCi_3,$CRj_float,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FCCI_3), ',', OP (CRJ_FLOAT), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfckne, { 0x71a80040 } + }, +/* cjmpl$pack @($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cjmpl, { 0x1a80080 } + }, +/* ccalll$pack @($GRi,$GRj),$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_ccalll, { 0x3a80080 } + }, +/* ici$pack @($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ici, { 0xc0e00 } + }, +/* dci$pack @($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ici, { 0xc0f00 } + }, +/* icei$pack @($GRi,$GRj),$ae */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (AE), 0 } }, + & ifmt_icei, { 0xc0e40 } + }, +/* dcei$pack @($GRi,$GRj),$ae */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (AE), 0 } }, + & ifmt_icei, { 0xc0e80 } + }, +/* dcf$pack @($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ici, { 0xc0f40 } + }, +/* dcef$pack @($GRi,$GRj),$ae */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', ',', OP (AE), 0 } }, + & ifmt_icei, { 0xc0ec0 } + }, +/* witlb$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc0c80 } + }, +/* wdtlb$pack $GRk,@($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ldsb, { 0xc0d80 } + }, +/* itlbi$pack @($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ici, { 0xc0cc0 } + }, +/* dtlbi$pack @($GRi,$GRj) */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, + & ifmt_ici, { 0xc0dc0 } + }, +/* icpl$pack $GRi,$GRj,$lock */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (LOCK), 0 } }, + & ifmt_icpl, { 0xc0c00 } + }, +/* dcpl$pack $GRi,$GRj,$lock */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (LOCK), 0 } }, + & ifmt_icpl, { 0xc0d00 } + }, +/* icul$pack $GRi */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), 0 } }, + & ifmt_icul, { 0xc0c40 } + }, +/* dcul$pack $GRi */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), 0 } }, + & ifmt_icul, { 0xc0d40 } + }, +/* bar$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_bar, { 0xc0f80 } + }, +/* membar$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_bar, { 0xc0fc0 } + }, +/* cop1$pack $s6_1,$CPRi,$CPRj,$CPRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (S6_1), ',', OP (CPRI), ',', OP (CPRJ), ',', OP (CPRK), 0 } }, + & ifmt_cop1, { 0x1f80000 } + }, +/* cop2$pack $s6_1,$CPRi,$CPRj,$CPRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (S6_1), ',', OP (CPRI), ',', OP (CPRJ), ',', OP (CPRK), 0 } }, + & ifmt_cop1, { 0x1fc0000 } + }, +/* clrgr$pack $GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), 0 } }, + & ifmt_clrgr, { 0x280000 } + }, +/* clrfr$pack $FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRK), 0 } }, + & ifmt_clrfr, { 0x280080 } + }, +/* clrga$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_bar, { 0x280040 } + }, +/* clrfa$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_bar, { 0x2800c0 } + }, +/* commitgr$pack $GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRK), 0 } }, + & ifmt_clrgr, { 0x280100 } + }, +/* commitfr$pack $FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRK), 0 } }, + & ifmt_clrfr, { 0x280180 } + }, +/* commitga$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_bar, { 0x280140 } + }, +/* commitfa$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_bar, { 0x2801c0 } + }, +/* fitos$pack $FRintj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRK), 0 } }, + & ifmt_fitos, { 0x1e40000 } + }, +/* fstoi$pack $FRj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRINTK), 0 } }, + & ifmt_fstoi, { 0x1e40040 } + }, +/* fitod$pack $FRintj,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_fitod, { 0x1e80000 } + }, +/* fdtoi$pack $FRdoublej,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEJ), ',', OP (FRINTK), 0 } }, + & ifmt_fdtoi, { 0x1e80040 } + }, +/* fditos$pack $FRintj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRK), 0 } }, + & ifmt_fitos, { 0x1e40400 } + }, +/* fdstoi$pack $FRj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRINTK), 0 } }, + & ifmt_fstoi, { 0x1e40440 } + }, +/* nfditos$pack $FRintj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRK), 0 } }, + & ifmt_fitos, { 0x1e40c00 } + }, +/* nfdstoi$pack $FRj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRINTK), 0 } }, + & ifmt_fstoi, { 0x1e40c40 } + }, +/* cfitos$pack $FRintj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfitos, { 0x1ac0000 } + }, +/* cfstoi$pack $FRj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfstoi, { 0x1ac0040 } + }, +/* nfitos$pack $FRintj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRK), 0 } }, + & ifmt_fitos, { 0x1e40800 } + }, +/* nfstoi$pack $FRj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRINTK), 0 } }, + & ifmt_fstoi, { 0x1e40840 } + }, +/* fmovs$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e40080 } + }, +/* fmovd$pack $FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_fmovd, { 0x1e80080 } + }, +/* fdmovs$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e40480 } + }, +/* cfmovs$pack $FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfmovs, { 0x1b00000 } + }, +/* fnegs$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e400c0 } + }, +/* fnegd$pack $FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_fmovd, { 0x1e800c0 } + }, +/* fdnegs$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e404c0 } + }, +/* cfnegs$pack $FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfmovs, { 0x1b00040 } + }, +/* fabss$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e40100 } + }, +/* fabsd$pack $FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_fmovd, { 0x1e80100 } + }, +/* fdabss$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e40500 } + }, +/* cfabss$pack $FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfmovs, { 0x1b00080 } + }, +/* fsqrts$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e40140 } + }, +/* fdsqrts$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e40540 } + }, +/* nfdsqrts$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e40d40 } + }, +/* fsqrtd$pack $FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_fmovd, { 0x1e80140 } + }, +/* cfsqrts$pack $FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfmovs, { 0x1b80080 } + }, +/* nfsqrts$pack $FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fmovs, { 0x1e40940 } + }, +/* fadds$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40180 } + }, +/* fsubs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e401c0 } + }, +/* fmuls$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40200 } + }, +/* fdivs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40240 } + }, +/* faddd$pack $FRdoublei,$FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEI), ',', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_faddd, { 0x1e80180 } + }, +/* fsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEI), ',', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_faddd, { 0x1e801c0 } + }, +/* fmuld$pack $FRdoublei,$FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEI), ',', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_faddd, { 0x1e80200 } + }, +/* fdivd$pack $FRdoublei,$FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEI), ',', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_faddd, { 0x1e80240 } + }, +/* cfadds$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfadds, { 0x1b40000 } + }, +/* cfsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfadds, { 0x1b40040 } + }, +/* cfmuls$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfadds, { 0x1b80000 } + }, +/* cfdivs$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfadds, { 0x1b80040 } + }, +/* nfadds$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40980 } + }, +/* nfsubs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e409c0 } + }, +/* nfmuls$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40a00 } + }, +/* nfdivs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40a40 } + }, +/* fcmps$pack $FRi,$FRj,$FCCi_2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FCCI_2), 0 } }, + & ifmt_fcmps, { 0x1e40280 } + }, +/* fcmpd$pack $FRdoublei,$FRdoublej,$FCCi_2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEI), ',', OP (FRDOUBLEJ), ',', OP (FCCI_2), 0 } }, + & ifmt_fcmpd, { 0x1e80280 } + }, +/* cfcmps$pack $FRi,$FRj,$FCCi_2,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FCCI_2), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfcmps, { 0x1b40080 } + }, +/* fdcmps$pack $FRi,$FRj,$FCCi_2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FCCI_2), 0 } }, + & ifmt_fcmps, { 0x1e40680 } + }, +/* fmadds$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e402c0 } + }, +/* fmsubs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40300 } + }, +/* fmaddd$pack $FRdoublei,$FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEI), ',', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_faddd, { 0x1e802c0 } + }, +/* fmsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRDOUBLEI), ',', OP (FRDOUBLEJ), ',', OP (FRDOUBLEK), 0 } }, + & ifmt_faddd, { 0x1e80300 } + }, +/* fdmadds$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e406c0 } + }, +/* nfdmadds$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40ec0 } + }, +/* cfmadds$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfadds, { 0x1bc0000 } + }, +/* cfmsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfadds, { 0x1bc0040 } + }, +/* nfmadds$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40ac0 } + }, +/* nfmsubs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40b00 } + }, +/* fmas$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40380 } + }, +/* fmss$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e403c0 } + }, +/* fdmas$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40700 } + }, +/* fdmss$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40740 } + }, +/* nfdmas$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40f00 } + }, +/* nfdmss$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40f40 } + }, +/* cfmas$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfadds, { 0x1bc0080 } + }, +/* cfmss$pack $FRi,$FRj,$FRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cfadds, { 0x1bc00c0 } + }, +/* fmad$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e80380 } + }, +/* fmsd$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e803c0 } + }, +/* nfmas$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40b80 } + }, +/* nfmss$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40bc0 } + }, +/* fdadds$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40580 } + }, +/* fdsubs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e405c0 } + }, +/* fdmuls$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40600 } + }, +/* fddivs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40640 } + }, +/* fdsads$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40780 } + }, +/* fdmulcs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e407c0 } + }, +/* nfdmulcs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40fc0 } + }, +/* nfdadds$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40d80 } + }, +/* nfdsubs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40dc0 } + }, +/* nfdmuls$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40e00 } + }, +/* nfddivs$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40e40 } + }, +/* nfdsads$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1e40f80 } + }, +/* nfdcmps$pack $FRi,$FRj,$FCCi_2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FCCI_2), 0 } }, + & ifmt_fcmps, { 0x1e40e80 } + }, +/* mhsetlos$pack $u12,$FRklo */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (U12), ',', OP (FRKLO), 0 } }, + & ifmt_mhsetlos, { 0x1e00800 } + }, +/* mhsethis$pack $u12,$FRkhi */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (U12), ',', OP (FRKHI), 0 } }, + & ifmt_mhsethis, { 0x1e00880 } + }, +/* mhdsets$pack $u12,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (U12), ',', OP (FRINTK), 0 } }, + & ifmt_mhdsets, { 0x1e00900 } + }, +/* mhsetloh$pack $s5,$FRklo */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (S5), ',', OP (FRKLO), 0 } }, + & ifmt_mhsetloh, { 0x1e00840 } + }, +/* mhsethih$pack $s5,$FRkhi */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (S5), ',', OP (FRKHI), 0 } }, + & ifmt_mhsethih, { 0x1e008c0 } + }, +/* mhdseth$pack $s5,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (S5), ',', OP (FRINTK), 0 } }, + & ifmt_mhdseth, { 0x1e00940 } + }, +/* mand$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0000 } + }, +/* mor$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0040 } + }, +/* mxor$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0080 } + }, +/* cmand$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1c00000 } + }, +/* cmor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1c00040 } + }, +/* cmxor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1c00080 } + }, +/* mnot$pack $FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mnot, { 0x1ec00c0 } + }, +/* cmnot$pack $FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmnot, { 0x1c000c0 } + }, +/* mrotli$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1ec0100 } + }, +/* mrotri$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1ec0140 } + }, +/* mwcut$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0180 } + }, +/* mwcuti$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1ec01c0 } + }, +/* mcut$pack $ACC40Si,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mcut, { 0x1ec0b00 } + }, +/* mcuti$pack $ACC40Si,$s6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (S6), ',', OP (FRINTK), 0 } }, + & ifmt_mcuti, { 0x1ec0b80 } + }, +/* mcutss$pack $ACC40Si,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mcut, { 0x1ec0b40 } + }, +/* mcutssi$pack $ACC40Si,$s6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (S6), ',', OP (FRINTK), 0 } }, + & ifmt_mcuti, { 0x1ec0bc0 } + }, +/* mdcutssi$pack $ACC40Si,$s6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (S6), ',', OP (FRINTK), 0 } }, + & ifmt_mcuti, { 0x1e00380 } + }, +/* maveh$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0200 } + }, +/* msllhi$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1ec0240 } + }, +/* msrlhi$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1ec0280 } + }, +/* msrahi$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1ec02c0 } + }, +/* mdrotli$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1e002c0 } + }, +/* mcplhi$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1e00300 } + }, +/* mcpli$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1e00340 } + }, +/* msaths$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0300 } + }, +/* mqsaths$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1e003c0 } + }, +/* msathu$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0340 } + }, +/* mcmpsh$pack $FRinti,$FRintj,$FCCk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FCCK), 0 } }, + & ifmt_mcmpsh, { 0x1ec0380 } + }, +/* mcmpuh$pack $FRinti,$FRintj,$FCCk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FCCK), 0 } }, + & ifmt_mcmpsh, { 0x1ec03c0 } + }, +/* mabshs$pack $FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mabshs, { 0x1e00280 } + }, +/* maddhss$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0400 } + }, +/* maddhus$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0440 } + }, +/* msubhss$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0480 } + }, +/* msubhus$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec04c0 } + }, +/* cmaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1c40000 } + }, +/* cmaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1c40040 } + }, +/* cmsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1c40080 } + }, +/* cmsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1c400c0 } + }, +/* mqaddhss$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0600 } + }, +/* mqaddhus$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0640 } + }, +/* mqsubhss$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0680 } + }, +/* mqsubhus$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec06c0 } + }, +/* cmqaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1cc0000 } + }, +/* cmqaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1cc0040 } + }, +/* cmqsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1cc0080 } + }, +/* cmqsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmand, { 0x1cc00c0 } + }, +/* maddaccs$pack $ACC40Si,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (ACC40SK), 0 } }, + & ifmt_maddaccs, { 0x1e00100 } + }, +/* msubaccs$pack $ACC40Si,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (ACC40SK), 0 } }, + & ifmt_maddaccs, { 0x1e00140 } + }, +/* mdaddaccs$pack $ACC40Si,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (ACC40SK), 0 } }, + & ifmt_maddaccs, { 0x1e00180 } + }, +/* mdsubaccs$pack $ACC40Si,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (ACC40SK), 0 } }, + & ifmt_maddaccs, { 0x1e001c0 } + }, +/* masaccs$pack $ACC40Si,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (ACC40SK), 0 } }, + & ifmt_maddaccs, { 0x1e00200 } + }, +/* mdasaccs$pack $ACC40Si,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (ACC40SK), 0 } }, + & ifmt_maddaccs, { 0x1e00240 } + }, +/* mmulhs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0500 } + }, +/* mmulhu$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0540 } + }, +/* mmulxhs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0a00 } + }, +/* mmulxhu$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0a40 } + }, +/* cmmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmulhs, { 0x1c80000 } + }, +/* cmmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmulhs, { 0x1c80040 } + }, +/* mqmulhs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0700 } + }, +/* mqmulhu$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0740 } + }, +/* mqmulxhs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0a80 } + }, +/* mqmulxhu$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0ac0 } + }, +/* cmqmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmulhs, { 0x1d00000 } + }, +/* cmqmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmulhs, { 0x1d00040 } + }, +/* mmachs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0580 } + }, +/* mmachu$pack $FRinti,$FRintj,$ACC40Uk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40UK), 0 } }, + & ifmt_mmachu, { 0x1ec05c0 } + }, +/* mmrdhs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0c00 } + }, +/* mmrdhu$pack $FRinti,$FRintj,$ACC40Uk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40UK), 0 } }, + & ifmt_mmachu, { 0x1ec0c40 } + }, +/* cmmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmulhs, { 0x1c80080 } + }, +/* cmmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40UK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmachu, { 0x1c800c0 } + }, +/* mqmachs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0780 } + }, +/* mqmachu$pack $FRinti,$FRintj,$ACC40Uk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40UK), 0 } }, + & ifmt_mmachu, { 0x1ec07c0 } + }, +/* cmqmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmulhs, { 0x1d00080 } + }, +/* cmqmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40UK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmachu, { 0x1d000c0 } + }, +/* mqxmachs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1e00000 } + }, +/* mqxmacxhs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1e00040 } + }, +/* mqmacxhs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1e00080 } + }, +/* mcpxrs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0800 } + }, +/* mcpxru$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0840 } + }, +/* mcpxis$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0880 } + }, +/* mcpxiu$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec08c0 } + }, +/* cmcpxrs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmulhs, { 0x1d40000 } + }, +/* cmcpxru$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmulhs, { 0x1d40040 } + }, +/* cmcpxis$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmulhs, { 0x1d40080 } + }, +/* cmcpxiu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmmulhs, { 0x1d400c0 } + }, +/* mqcpxrs$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0900 } + }, +/* mqcpxru$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0940 } + }, +/* mqcpxis$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec0980 } + }, +/* mqcpxiu$pack $FRinti,$FRintj,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, + & ifmt_mmulhs, { 0x1ec09c0 } + }, +/* mexpdhw$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1ec0c80 } + }, +/* cmexpdhw$pack $FRinti,$u6,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmexpdhw, { 0x1d80080 } + }, +/* mexpdhd$pack $FRinti,$u6,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, + & ifmt_mrotli, { 0x1ec0cc0 } + }, +/* cmexpdhd$pack $FRinti,$u6,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmexpdhw, { 0x1d800c0 } + }, +/* mpackh$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0d00 } + }, +/* mdpackh$pack $FRinti,$FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mand, { 0x1ec0d80 } + }, +/* munpackh$pack $FRinti,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTK), 0 } }, + & ifmt_munpackh, { 0x1ec0d40 } + }, +/* mdunpackh$pack $FRinti,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTK), 0 } }, + & ifmt_munpackh, { 0x1ec0dc0 } + }, +/* mbtoh$pack $FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mabshs, { 0x1ec0e00 } + }, +/* cmbtoh$pack $FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmbtoh, { 0x1dc0000 } + }, +/* mhtob$pack $FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mabshs, { 0x1ec0e40 } + }, +/* cmhtob$pack $FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmbtoh, { 0x1dc0040 } + }, +/* mbtohe$pack $FRintj,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), 0 } }, + & ifmt_mabshs, { 0x1ec0e80 } + }, +/* cmbtohe$pack $FRintj,$FRintk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmbtoh, { 0x1dc0080 } + }, +/* mclracc$pack $ACC40Sk,$A */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SK), ',', OP (A), 0 } }, + & ifmt_mclracc, { 0x1ec0ec0 } + }, +/* mrdacc$pack $ACC40Si,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (FRINTK), 0 } }, + & ifmt_mrdacc, { 0x1ec0f00 } + }, +/* mrdaccg$pack $ACCGi,$FRintk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (ACCGI), ',', OP (FRINTK), 0 } }, + & ifmt_mrdaccg, { 0x1ec0f80 } + }, +/* mwtacc$pack $FRinti,$ACC40Sk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (ACC40SK), 0 } }, + & ifmt_mwtacc, { 0x1ec0f40 } + }, +/* mwtaccg$pack $FRinti,$ACCGk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (ACCGK), 0 } }, + & ifmt_mwtaccg, { 0x1ec0fc0 } + }, +/* mcop1$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1f00000 } + }, +/* mcop2$pack $FRi,$FRj,$FRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRI), ',', OP (FRJ), ',', OP (FRK), 0 } }, + & ifmt_fadds, { 0x1f40000 } + }, +/* fnop$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_fnop, { 0x1e40340 } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +/* Formats for ALIAS macro-insns. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define F(f) & frv_cgen_ifld_table[FRV_##f] +#else +#define F(f) & frv_cgen_ifld_table[FRV_/**/f] +#endif +static const CGEN_IFMT ifmt_nop = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mnop = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_A) }, { F (F_MISC_NULL_10) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ret = { + 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmp = { + 32, 32, 0x7ffc03c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1) }, { F (F_OPE2) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmpi = { + 32, 32, 0x7ffc0000, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_ICCI_1) }, { F (F_S10) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ccmp = { + 32, 32, 0x7ffc00c0, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov = { + 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmov = { + 32, 32, 0x1fc00ff, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_GRJ) }, { 0 } } +}; + +#undef F + +/* Each non-simple macro entry points to an array of expansion possibilities. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) FRV_OPERAND_##op +#else +#define OPERAND(op) FRV_OPERAND_/**/op +#endif +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The macro instruction table. */ + +static const CGEN_IBASE frv_cgen_macro_insn_table[] = +{ +/* nop$pack */ + { + -1, "nop", "nop", 32, + { 0|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* mnop$pack */ + { + -1, "mnop", "mnop", 32, + { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_3 } } + }, +/* ret$pack */ + { + -1, "ret", "ret", 32, + { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3 } } + }, +/* cmp$pack $GRi,$GRj,$ICCi_1 */ + { + -1, "cmp", "cmp", 32, + { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* cmpi$pack $GRi,$s10,$ICCi_1 */ + { + -1, "cmpi", "cmpi", 32, + { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* ccmp$pack $GRi,$GRj,$CCi,$cond */ + { + -1, "ccmp", "ccmp", 32, + { 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* mov$pack $GRi,$GRk */ + { + -1, "mov", "mov", 32, + { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +/* cmov$pack $GRi,$GRk,$CCi,$cond */ + { + -1, "cmov", "cmov", 32, + { 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } + }, +}; + +/* The macro instruction opcode table. */ + +static const CGEN_OPCODE frv_cgen_macro_insn_opcode_table[] = +{ +/* nop$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_nop, { 0x880000 } + }, +/* mnop$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_mnop, { 0x7fee0ec0 } + }, +/* ret$pack */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), 0 } }, + & ifmt_ret, { 0x403a4000 } + }, +/* cmp$pack $GRi,$GRj,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (ICCI_1), 0 } }, + & ifmt_cmp, { 0x140 } + }, +/* cmpi$pack $GRi,$s10,$ICCi_1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (S10), ',', OP (ICCI_1), 0 } }, + & ifmt_cmpi, { 0x540000 } + }, +/* ccmp$pack $GRi,$GRj,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_ccmp, { 0x1640040 } + }, +/* mov$pack $GRi,$GRk */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRK), 0 } }, + & ifmt_mov, { 0x880000 } + }, +/* cmov$pack $GRi,$GRk,$CCi,$cond */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmov, { 0x1680040 } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +#ifndef CGEN_ASM_HASH_P +#define CGEN_ASM_HASH_P(insn) 1 +#endif + +#ifndef CGEN_DIS_HASH_P +#define CGEN_DIS_HASH_P(insn) 1 +#endif + +/* Return non-zero if INSN is to be added to the hash table. + Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */ + +static int +asm_hash_insn_p (insn) + const CGEN_INSN *insn ATTRIBUTE_UNUSED; +{ + return CGEN_ASM_HASH_P (insn); +} + +static int +dis_hash_insn_p (insn) + const CGEN_INSN *insn; +{ + /* If building the hash table and the NO-DIS attribute is present, + ignore. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS)) + return 0; + return CGEN_DIS_HASH_P (insn); +} + +#ifndef CGEN_ASM_HASH +#define CGEN_ASM_HASH_SIZE 127 +#ifdef CGEN_MNEMONIC_OPERANDS +#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) +#else +#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/ +#endif +#endif + +/* It doesn't make much sense to provide a default here, + but while this is under development we do. + BUFFER is a pointer to the bytes of the insn, target order. + VALUE is the first base_insn_bitsize bits as an int in host order. */ + +#ifndef CGEN_DIS_HASH +#define CGEN_DIS_HASH_SIZE 256 +#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf)) +#endif + +/* The result is the hash value of the insn. + Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */ + +static unsigned int +asm_hash_insn (mnem) + const char * mnem; +{ + return CGEN_ASM_HASH (mnem); +} + +/* BUF is a pointer to the bytes of the insn, target order. + VALUE is the first base_insn_bitsize bits as an int in host order. */ + +static unsigned int +dis_hash_insn (buf, value) + const char * buf ATTRIBUTE_UNUSED; + CGEN_INSN_INT value ATTRIBUTE_UNUSED; +{ + return CGEN_DIS_HASH (buf, value); +} + +static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int)); + +/* Set the recorded length of the insn in the CGEN_FIELDS struct. */ + +static void +set_fields_bitsize (fields, size) + CGEN_FIELDS *fields; + int size; +{ + CGEN_FIELDS_BITSIZE (fields) = size; +} + +/* Function to call before using the operand instance table. + This plugs the opcode entries and macro instructions into the cpu table. */ + +void +frv_cgen_init_opcode_table (cd) + CGEN_CPU_DESC cd; +{ + int i; + int num_macros = (sizeof (frv_cgen_macro_insn_table) / + sizeof (frv_cgen_macro_insn_table[0])); + const CGEN_IBASE *ib = & frv_cgen_macro_insn_table[0]; + const CGEN_OPCODE *oc = & frv_cgen_macro_insn_opcode_table[0]; + CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN)); + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); + for (i = 0; i < num_macros; ++i) + { + insns[i].base = &ib[i]; + insns[i].opcode = &oc[i]; + frv_cgen_build_insn_regex (& insns[i]); + } + cd->macro_insn_table.init_entries = insns; + cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); + cd->macro_insn_table.num_init_entries = num_macros; + + oc = & frv_cgen_insn_opcode_table[0]; + insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + { + insns[i].opcode = &oc[i]; + frv_cgen_build_insn_regex (& insns[i]); + } + + cd->sizeof_fields = sizeof (CGEN_FIELDS); + cd->set_fields_bitsize = set_fields_bitsize; + + cd->asm_hash_p = asm_hash_insn_p; + cd->asm_hash = asm_hash_insn; + cd->asm_hash_size = CGEN_ASM_HASH_SIZE; + + cd->dis_hash_p = dis_hash_insn_p; + cd->dis_hash = dis_hash_insn; + cd->dis_hash_size = CGEN_DIS_HASH_SIZE; +} diff --git a/opcodes/frv-opc.h b/opcodes/frv-opc.h new file mode 100644 index 00000000000..266031b6419 --- /dev/null +++ b/opcodes/frv-opc.h @@ -0,0 +1,372 @@ +/* Instruction opcode header for frv. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifndef FRV_OPC_H +#define FRV_OPC_H + +/* -- opc.h */ + +#undef CGEN_DIS_HASH_SIZE +#define CGEN_DIS_HASH_SIZE 128 +#undef CGEN_DIS_HASH +#define CGEN_DIS_HASH(buffer, value) (((value) >> 18) & 127) + +/* Vliw support. */ +#define FRV_VLIW_SIZE 4 /* fr500 has largest vliw size of 4. */ +typedef CGEN_ATTR_VALUE_TYPE VLIW_COMBO[FRV_VLIW_SIZE]; + +typedef struct +{ + int next_slot; + int constraint_violation; + unsigned long mach; + unsigned long elf_flags; + CGEN_ATTR_VALUE_TYPE *unit_mapping; + VLIW_COMBO *current_vliw; + CGEN_ATTR_VALUE_TYPE major[FRV_VLIW_SIZE]; +} FRV_VLIW; + +int frv_is_branch_major PARAMS ((CGEN_ATTR_VALUE_TYPE, unsigned long)); +int frv_is_float_major PARAMS ((CGEN_ATTR_VALUE_TYPE, unsigned long)); +int frv_is_media_major PARAMS ((CGEN_ATTR_VALUE_TYPE, unsigned long)); +int frv_is_branch_insn PARAMS ((const CGEN_INSN *)); +int frv_is_float_insn PARAMS ((const CGEN_INSN *)); +int frv_is_media_insn PARAMS ((const CGEN_INSN *)); +void frv_vliw_reset PARAMS ((FRV_VLIW *, unsigned long mach, unsigned long elf_flags)); +int frv_vliw_add_insn PARAMS ((FRV_VLIW *, const CGEN_INSN *)); +int spr_valid PARAMS ((long)); +/* -- */ +/* Enum declaration for frv instruction types. */ +typedef enum cgen_insn_type { + FRV_INSN_INVALID, FRV_INSN_ADD, FRV_INSN_SUB, FRV_INSN_AND + , FRV_INSN_OR, FRV_INSN_XOR, FRV_INSN_NOT, FRV_INSN_SDIV + , FRV_INSN_NSDIV, FRV_INSN_UDIV, FRV_INSN_NUDIV, FRV_INSN_SMUL + , FRV_INSN_UMUL, FRV_INSN_SLL, FRV_INSN_SRL, FRV_INSN_SRA + , FRV_INSN_SCAN, FRV_INSN_CADD, FRV_INSN_CSUB, FRV_INSN_CAND + , FRV_INSN_COR, FRV_INSN_CXOR, FRV_INSN_CNOT, FRV_INSN_CSMUL + , FRV_INSN_CSDIV, FRV_INSN_CUDIV, FRV_INSN_CSLL, FRV_INSN_CSRL + , FRV_INSN_CSRA, FRV_INSN_CSCAN, FRV_INSN_ADDCC, FRV_INSN_SUBCC + , FRV_INSN_ANDCC, FRV_INSN_ORCC, FRV_INSN_XORCC, FRV_INSN_SLLCC + , FRV_INSN_SRLCC, FRV_INSN_SRACC, FRV_INSN_SMULCC, FRV_INSN_UMULCC + , FRV_INSN_CADDCC, FRV_INSN_CSUBCC, FRV_INSN_CSMULCC, FRV_INSN_CANDCC + , FRV_INSN_CORCC, FRV_INSN_CXORCC, FRV_INSN_CSLLCC, FRV_INSN_CSRLCC + , FRV_INSN_CSRACC, FRV_INSN_ADDX, FRV_INSN_SUBX, FRV_INSN_ADDXCC + , FRV_INSN_SUBXCC, FRV_INSN_ADDI, FRV_INSN_SUBI, FRV_INSN_ANDI + , FRV_INSN_ORI, FRV_INSN_XORI, FRV_INSN_SDIVI, FRV_INSN_NSDIVI + , FRV_INSN_UDIVI, FRV_INSN_NUDIVI, FRV_INSN_SMULI, FRV_INSN_UMULI + , FRV_INSN_SLLI, FRV_INSN_SRLI, FRV_INSN_SRAI, FRV_INSN_SCANI + , FRV_INSN_ADDICC, FRV_INSN_SUBICC, FRV_INSN_ANDICC, FRV_INSN_ORICC + , FRV_INSN_XORICC, FRV_INSN_SMULICC, FRV_INSN_UMULICC, FRV_INSN_SLLICC + , FRV_INSN_SRLICC, FRV_INSN_SRAICC, FRV_INSN_ADDXI, FRV_INSN_SUBXI + , FRV_INSN_ADDXICC, FRV_INSN_SUBXICC, FRV_INSN_CMPB, FRV_INSN_CMPBA + , FRV_INSN_SETLO, FRV_INSN_SETHI, FRV_INSN_SETLOS, FRV_INSN_LDSB + , FRV_INSN_LDUB, FRV_INSN_LDSH, FRV_INSN_LDUH, FRV_INSN_LD + , FRV_INSN_LDBF, FRV_INSN_LDHF, FRV_INSN_LDF, FRV_INSN_LDC + , FRV_INSN_NLDSB, FRV_INSN_NLDUB, FRV_INSN_NLDSH, FRV_INSN_NLDUH + , FRV_INSN_NLD, FRV_INSN_NLDBF, FRV_INSN_NLDHF, FRV_INSN_NLDF + , FRV_INSN_LDD, FRV_INSN_LDDF, FRV_INSN_LDDC, FRV_INSN_NLDD + , FRV_INSN_NLDDF, FRV_INSN_LDQ, FRV_INSN_LDQF, FRV_INSN_LDQC + , FRV_INSN_NLDQ, FRV_INSN_NLDQF, FRV_INSN_LDSBU, FRV_INSN_LDUBU + , FRV_INSN_LDSHU, FRV_INSN_LDUHU, FRV_INSN_LDU, FRV_INSN_NLDSBU + , FRV_INSN_NLDUBU, FRV_INSN_NLDSHU, FRV_INSN_NLDUHU, FRV_INSN_NLDU + , FRV_INSN_LDBFU, FRV_INSN_LDHFU, FRV_INSN_LDFU, FRV_INSN_LDCU + , FRV_INSN_NLDBFU, FRV_INSN_NLDHFU, FRV_INSN_NLDFU, FRV_INSN_LDDU + , FRV_INSN_NLDDU, FRV_INSN_LDDFU, FRV_INSN_LDDCU, FRV_INSN_NLDDFU + , FRV_INSN_LDQU, FRV_INSN_NLDQU, FRV_INSN_LDQFU, FRV_INSN_LDQCU + , FRV_INSN_NLDQFU, FRV_INSN_LDSBI, FRV_INSN_LDSHI, FRV_INSN_LDI + , FRV_INSN_LDUBI, FRV_INSN_LDUHI, FRV_INSN_LDBFI, FRV_INSN_LDHFI + , FRV_INSN_LDFI, FRV_INSN_NLDSBI, FRV_INSN_NLDUBI, FRV_INSN_NLDSHI + , FRV_INSN_NLDUHI, FRV_INSN_NLDI, FRV_INSN_NLDBFI, FRV_INSN_NLDHFI + , FRV_INSN_NLDFI, FRV_INSN_LDDI, FRV_INSN_LDDFI, FRV_INSN_NLDDI + , FRV_INSN_NLDDFI, FRV_INSN_LDQI, FRV_INSN_LDQFI, FRV_INSN_NLDQI + , FRV_INSN_NLDQFI, FRV_INSN_STB, FRV_INSN_STH, FRV_INSN_ST + , FRV_INSN_STBF, FRV_INSN_STHF, FRV_INSN_STF, FRV_INSN_STC + , FRV_INSN_RSTB, FRV_INSN_RSTH, FRV_INSN_RST, FRV_INSN_RSTBF + , FRV_INSN_RSTHF, FRV_INSN_RSTF, FRV_INSN_STD, FRV_INSN_STDF + , FRV_INSN_STDC, FRV_INSN_RSTD, FRV_INSN_RSTDF, FRV_INSN_STQ + , FRV_INSN_STQF, FRV_INSN_STQC, FRV_INSN_RSTQ, FRV_INSN_RSTQF + , FRV_INSN_STBU, FRV_INSN_STHU, FRV_INSN_STU, FRV_INSN_STBFU + , FRV_INSN_STHFU, FRV_INSN_STFU, FRV_INSN_STCU, FRV_INSN_STDU + , FRV_INSN_STDFU, FRV_INSN_STDCU, FRV_INSN_STQU, FRV_INSN_STQFU + , FRV_INSN_STQCU, FRV_INSN_CLDSB, FRV_INSN_CLDUB, FRV_INSN_CLDSH + , FRV_INSN_CLDUH, FRV_INSN_CLD, FRV_INSN_CLDBF, FRV_INSN_CLDHF + , FRV_INSN_CLDF, FRV_INSN_CLDD, FRV_INSN_CLDDF, FRV_INSN_CLDQ + , FRV_INSN_CLDSBU, FRV_INSN_CLDUBU, FRV_INSN_CLDSHU, FRV_INSN_CLDUHU + , FRV_INSN_CLDU, FRV_INSN_CLDBFU, FRV_INSN_CLDHFU, FRV_INSN_CLDFU + , FRV_INSN_CLDDU, FRV_INSN_CLDDFU, FRV_INSN_CLDQU, FRV_INSN_CSTB + , FRV_INSN_CSTH, FRV_INSN_CST, FRV_INSN_CSTBF, FRV_INSN_CSTHF + , FRV_INSN_CSTF, FRV_INSN_CSTD, FRV_INSN_CSTDF, FRV_INSN_CSTQ + , FRV_INSN_CSTBU, FRV_INSN_CSTHU, FRV_INSN_CSTU, FRV_INSN_CSTBFU + , FRV_INSN_CSTHFU, FRV_INSN_CSTFU, FRV_INSN_CSTDU, FRV_INSN_CSTDFU + , FRV_INSN_STBI, FRV_INSN_STHI, FRV_INSN_STI, FRV_INSN_STBFI + , FRV_INSN_STHFI, FRV_INSN_STFI, FRV_INSN_STDI, FRV_INSN_STDFI + , FRV_INSN_STQI, FRV_INSN_STQFI, FRV_INSN_SWAP, FRV_INSN_SWAPI + , FRV_INSN_CSWAP, FRV_INSN_MOVGF, FRV_INSN_MOVFG, FRV_INSN_MOVGFD + , FRV_INSN_MOVFGD, FRV_INSN_MOVGFQ, FRV_INSN_MOVFGQ, FRV_INSN_CMOVGF + , FRV_INSN_CMOVFG, FRV_INSN_CMOVGFD, FRV_INSN_CMOVFGD, FRV_INSN_MOVGS + , FRV_INSN_MOVSG, FRV_INSN_BRA, FRV_INSN_BNO, FRV_INSN_BEQ + , FRV_INSN_BNE, FRV_INSN_BLE, FRV_INSN_BGT, FRV_INSN_BLT + , FRV_INSN_BGE, FRV_INSN_BLS, FRV_INSN_BHI, FRV_INSN_BC + , FRV_INSN_BNC, FRV_INSN_BN, FRV_INSN_BP, FRV_INSN_BV + , FRV_INSN_BNV, FRV_INSN_FBRA, FRV_INSN_FBNO, FRV_INSN_FBNE + , FRV_INSN_FBEQ, FRV_INSN_FBLG, FRV_INSN_FBUE, FRV_INSN_FBUL + , FRV_INSN_FBGE, FRV_INSN_FBLT, FRV_INSN_FBUGE, FRV_INSN_FBUG + , FRV_INSN_FBLE, FRV_INSN_FBGT, FRV_INSN_FBULE, FRV_INSN_FBU + , FRV_INSN_FBO, FRV_INSN_BCTRLR, FRV_INSN_BRALR, FRV_INSN_BNOLR + , FRV_INSN_BEQLR, FRV_INSN_BNELR, FRV_INSN_BLELR, FRV_INSN_BGTLR + , FRV_INSN_BLTLR, FRV_INSN_BGELR, FRV_INSN_BLSLR, FRV_INSN_BHILR + , FRV_INSN_BCLR, FRV_INSN_BNCLR, FRV_INSN_BNLR, FRV_INSN_BPLR + , FRV_INSN_BVLR, FRV_INSN_BNVLR, FRV_INSN_FBRALR, FRV_INSN_FBNOLR + , FRV_INSN_FBEQLR, FRV_INSN_FBNELR, FRV_INSN_FBLGLR, FRV_INSN_FBUELR + , FRV_INSN_FBULLR, FRV_INSN_FBGELR, FRV_INSN_FBLTLR, FRV_INSN_FBUGELR + , FRV_INSN_FBUGLR, FRV_INSN_FBLELR, FRV_INSN_FBGTLR, FRV_INSN_FBULELR + , FRV_INSN_FBULR, FRV_INSN_FBOLR, FRV_INSN_BCRALR, FRV_INSN_BCNOLR + , FRV_INSN_BCEQLR, FRV_INSN_BCNELR, FRV_INSN_BCLELR, FRV_INSN_BCGTLR + , FRV_INSN_BCLTLR, FRV_INSN_BCGELR, FRV_INSN_BCLSLR, FRV_INSN_BCHILR + , FRV_INSN_BCCLR, FRV_INSN_BCNCLR, FRV_INSN_BCNLR, FRV_INSN_BCPLR + , FRV_INSN_BCVLR, FRV_INSN_BCNVLR, FRV_INSN_FCBRALR, FRV_INSN_FCBNOLR + , FRV_INSN_FCBEQLR, FRV_INSN_FCBNELR, FRV_INSN_FCBLGLR, FRV_INSN_FCBUELR + , FRV_INSN_FCBULLR, FRV_INSN_FCBGELR, FRV_INSN_FCBLTLR, FRV_INSN_FCBUGELR + , FRV_INSN_FCBUGLR, FRV_INSN_FCBLELR, FRV_INSN_FCBGTLR, FRV_INSN_FCBULELR + , FRV_INSN_FCBULR, FRV_INSN_FCBOLR, FRV_INSN_JMPL, FRV_INSN_CALLL + , FRV_INSN_JMPIL, FRV_INSN_CALLIL, FRV_INSN_CALL, FRV_INSN_RETT + , FRV_INSN_REI, FRV_INSN_TRA, FRV_INSN_TNO, FRV_INSN_TEQ + , FRV_INSN_TNE, FRV_INSN_TLE, FRV_INSN_TGT, FRV_INSN_TLT + , FRV_INSN_TGE, FRV_INSN_TLS, FRV_INSN_THI, FRV_INSN_TC + , FRV_INSN_TNC, FRV_INSN_TN, FRV_INSN_TP, FRV_INSN_TV + , FRV_INSN_TNV, FRV_INSN_FTRA, FRV_INSN_FTNO, FRV_INSN_FTNE + , FRV_INSN_FTEQ, FRV_INSN_FTLG, FRV_INSN_FTUE, FRV_INSN_FTUL + , FRV_INSN_FTGE, FRV_INSN_FTLT, FRV_INSN_FTUGE, FRV_INSN_FTUG + , FRV_INSN_FTLE, FRV_INSN_FTGT, FRV_INSN_FTULE, FRV_INSN_FTU + , FRV_INSN_FTO, FRV_INSN_TIRA, FRV_INSN_TINO, FRV_INSN_TIEQ + , FRV_INSN_TINE, FRV_INSN_TILE, FRV_INSN_TIGT, FRV_INSN_TILT + , FRV_INSN_TIGE, FRV_INSN_TILS, FRV_INSN_TIHI, FRV_INSN_TIC + , FRV_INSN_TINC, FRV_INSN_TIN, FRV_INSN_TIP, FRV_INSN_TIV + , FRV_INSN_TINV, FRV_INSN_FTIRA, FRV_INSN_FTINO, FRV_INSN_FTINE + , FRV_INSN_FTIEQ, FRV_INSN_FTILG, FRV_INSN_FTIUE, FRV_INSN_FTIUL + , FRV_INSN_FTIGE, FRV_INSN_FTILT, FRV_INSN_FTIUGE, FRV_INSN_FTIUG + , FRV_INSN_FTILE, FRV_INSN_FTIGT, FRV_INSN_FTIULE, FRV_INSN_FTIU + , FRV_INSN_FTIO, FRV_INSN_BREAK, FRV_INSN_MTRAP, FRV_INSN_ANDCR + , FRV_INSN_ORCR, FRV_INSN_XORCR, FRV_INSN_NANDCR, FRV_INSN_NORCR + , FRV_INSN_ANDNCR, FRV_INSN_ORNCR, FRV_INSN_NANDNCR, FRV_INSN_NORNCR + , FRV_INSN_NOTCR, FRV_INSN_CKRA, FRV_INSN_CKNO, FRV_INSN_CKEQ + , FRV_INSN_CKNE, FRV_INSN_CKLE, FRV_INSN_CKGT, FRV_INSN_CKLT + , FRV_INSN_CKGE, FRV_INSN_CKLS, FRV_INSN_CKHI, FRV_INSN_CKC + , FRV_INSN_CKNC, FRV_INSN_CKN, FRV_INSN_CKP, FRV_INSN_CKV + , FRV_INSN_CKNV, FRV_INSN_FCKRA, FRV_INSN_FCKNO, FRV_INSN_FCKNE + , FRV_INSN_FCKEQ, FRV_INSN_FCKLG, FRV_INSN_FCKUE, FRV_INSN_FCKUL + , FRV_INSN_FCKGE, FRV_INSN_FCKLT, FRV_INSN_FCKUGE, FRV_INSN_FCKUG + , FRV_INSN_FCKLE, FRV_INSN_FCKGT, FRV_INSN_FCKULE, FRV_INSN_FCKU + , FRV_INSN_FCKO, FRV_INSN_CCKRA, FRV_INSN_CCKNO, FRV_INSN_CCKEQ + , FRV_INSN_CCKNE, FRV_INSN_CCKLE, FRV_INSN_CCKGT, FRV_INSN_CCKLT + , FRV_INSN_CCKGE, FRV_INSN_CCKLS, FRV_INSN_CCKHI, FRV_INSN_CCKC + , FRV_INSN_CCKNC, FRV_INSN_CCKN, FRV_INSN_CCKP, FRV_INSN_CCKV + , FRV_INSN_CCKNV, FRV_INSN_CFCKRA, FRV_INSN_CFCKNO, FRV_INSN_CFCKNE + , FRV_INSN_CFCKEQ, FRV_INSN_CFCKLG, FRV_INSN_CFCKUE, FRV_INSN_CFCKUL + , FRV_INSN_CFCKGE, FRV_INSN_CFCKLT, FRV_INSN_CFCKUGE, FRV_INSN_CFCKUG + , FRV_INSN_CFCKLE, FRV_INSN_CFCKGT, FRV_INSN_CFCKULE, FRV_INSN_CFCKU + , FRV_INSN_CFCKO, FRV_INSN_CJMPL, FRV_INSN_CCALLL, FRV_INSN_ICI + , FRV_INSN_DCI, FRV_INSN_ICEI, FRV_INSN_DCEI, FRV_INSN_DCF + , FRV_INSN_DCEF, FRV_INSN_WITLB, FRV_INSN_WDTLB, FRV_INSN_ITLBI + , FRV_INSN_DTLBI, FRV_INSN_ICPL, FRV_INSN_DCPL, FRV_INSN_ICUL + , FRV_INSN_DCUL, FRV_INSN_BAR, FRV_INSN_MEMBAR, FRV_INSN_COP1 + , FRV_INSN_COP2, FRV_INSN_CLRGR, FRV_INSN_CLRFR, FRV_INSN_CLRGA + , FRV_INSN_CLRFA, FRV_INSN_COMMITGR, FRV_INSN_COMMITFR, FRV_INSN_COMMITGA + , FRV_INSN_COMMITFA, FRV_INSN_FITOS, FRV_INSN_FSTOI, FRV_INSN_FITOD + , FRV_INSN_FDTOI, FRV_INSN_FDITOS, FRV_INSN_FDSTOI, FRV_INSN_NFDITOS + , FRV_INSN_NFDSTOI, FRV_INSN_CFITOS, FRV_INSN_CFSTOI, FRV_INSN_NFITOS + , FRV_INSN_NFSTOI, FRV_INSN_FMOVS, FRV_INSN_FMOVD, FRV_INSN_FDMOVS + , FRV_INSN_CFMOVS, FRV_INSN_FNEGS, FRV_INSN_FNEGD, FRV_INSN_FDNEGS + , FRV_INSN_CFNEGS, FRV_INSN_FABSS, FRV_INSN_FABSD, FRV_INSN_FDABSS + , FRV_INSN_CFABSS, FRV_INSN_FSQRTS, FRV_INSN_FDSQRTS, FRV_INSN_NFDSQRTS + , FRV_INSN_FSQRTD, FRV_INSN_CFSQRTS, FRV_INSN_NFSQRTS, FRV_INSN_FADDS + , FRV_INSN_FSUBS, FRV_INSN_FMULS, FRV_INSN_FDIVS, FRV_INSN_FADDD + , FRV_INSN_FSUBD, FRV_INSN_FMULD, FRV_INSN_FDIVD, FRV_INSN_CFADDS + , FRV_INSN_CFSUBS, FRV_INSN_CFMULS, FRV_INSN_CFDIVS, FRV_INSN_NFADDS + , FRV_INSN_NFSUBS, FRV_INSN_NFMULS, FRV_INSN_NFDIVS, FRV_INSN_FCMPS + , FRV_INSN_FCMPD, FRV_INSN_CFCMPS, FRV_INSN_FDCMPS, FRV_INSN_FMADDS + , FRV_INSN_FMSUBS, FRV_INSN_FMADDD, FRV_INSN_FMSUBD, FRV_INSN_FDMADDS + , FRV_INSN_NFDMADDS, FRV_INSN_CFMADDS, FRV_INSN_CFMSUBS, FRV_INSN_NFMADDS + , FRV_INSN_NFMSUBS, FRV_INSN_FMAS, FRV_INSN_FMSS, FRV_INSN_FDMAS + , FRV_INSN_FDMSS, FRV_INSN_NFDMAS, FRV_INSN_NFDMSS, FRV_INSN_CFMAS + , FRV_INSN_CFMSS, FRV_INSN_FMAD, FRV_INSN_FMSD, FRV_INSN_NFMAS + , FRV_INSN_NFMSS, FRV_INSN_FDADDS, FRV_INSN_FDSUBS, FRV_INSN_FDMULS + , FRV_INSN_FDDIVS, FRV_INSN_FDSADS, FRV_INSN_FDMULCS, FRV_INSN_NFDMULCS + , FRV_INSN_NFDADDS, FRV_INSN_NFDSUBS, FRV_INSN_NFDMULS, FRV_INSN_NFDDIVS + , FRV_INSN_NFDSADS, FRV_INSN_NFDCMPS, FRV_INSN_MHSETLOS, FRV_INSN_MHSETHIS + , FRV_INSN_MHDSETS, FRV_INSN_MHSETLOH, FRV_INSN_MHSETHIH, FRV_INSN_MHDSETH + , FRV_INSN_MAND, FRV_INSN_MOR, FRV_INSN_MXOR, FRV_INSN_CMAND + , FRV_INSN_CMOR, FRV_INSN_CMXOR, FRV_INSN_MNOT, FRV_INSN_CMNOT + , FRV_INSN_MROTLI, FRV_INSN_MROTRI, FRV_INSN_MWCUT, FRV_INSN_MWCUTI + , FRV_INSN_MCUT, FRV_INSN_MCUTI, FRV_INSN_MCUTSS, FRV_INSN_MCUTSSI + , FRV_INSN_MDCUTSSI, FRV_INSN_MAVEH, FRV_INSN_MSLLHI, FRV_INSN_MSRLHI + , FRV_INSN_MSRAHI, FRV_INSN_MDROTLI, FRV_INSN_MCPLHI, FRV_INSN_MCPLI + , FRV_INSN_MSATHS, FRV_INSN_MQSATHS, FRV_INSN_MSATHU, FRV_INSN_MCMPSH + , FRV_INSN_MCMPUH, FRV_INSN_MABSHS, FRV_INSN_MADDHSS, FRV_INSN_MADDHUS + , FRV_INSN_MSUBHSS, FRV_INSN_MSUBHUS, FRV_INSN_CMADDHSS, FRV_INSN_CMADDHUS + , FRV_INSN_CMSUBHSS, FRV_INSN_CMSUBHUS, FRV_INSN_MQADDHSS, FRV_INSN_MQADDHUS + , FRV_INSN_MQSUBHSS, FRV_INSN_MQSUBHUS, FRV_INSN_CMQADDHSS, FRV_INSN_CMQADDHUS + , FRV_INSN_CMQSUBHSS, FRV_INSN_CMQSUBHUS, FRV_INSN_MADDACCS, FRV_INSN_MSUBACCS + , FRV_INSN_MDADDACCS, FRV_INSN_MDSUBACCS, FRV_INSN_MASACCS, FRV_INSN_MDASACCS + , FRV_INSN_MMULHS, FRV_INSN_MMULHU, FRV_INSN_MMULXHS, FRV_INSN_MMULXHU + , FRV_INSN_CMMULHS, FRV_INSN_CMMULHU, FRV_INSN_MQMULHS, FRV_INSN_MQMULHU + , FRV_INSN_MQMULXHS, FRV_INSN_MQMULXHU, FRV_INSN_CMQMULHS, FRV_INSN_CMQMULHU + , FRV_INSN_MMACHS, FRV_INSN_MMACHU, FRV_INSN_MMRDHS, FRV_INSN_MMRDHU + , FRV_INSN_CMMACHS, FRV_INSN_CMMACHU, FRV_INSN_MQMACHS, FRV_INSN_MQMACHU + , FRV_INSN_CMQMACHS, FRV_INSN_CMQMACHU, FRV_INSN_MQXMACHS, FRV_INSN_MQXMACXHS + , FRV_INSN_MQMACXHS, FRV_INSN_MCPXRS, FRV_INSN_MCPXRU, FRV_INSN_MCPXIS + , FRV_INSN_MCPXIU, FRV_INSN_CMCPXRS, FRV_INSN_CMCPXRU, FRV_INSN_CMCPXIS + , FRV_INSN_CMCPXIU, FRV_INSN_MQCPXRS, FRV_INSN_MQCPXRU, FRV_INSN_MQCPXIS + , FRV_INSN_MQCPXIU, FRV_INSN_MEXPDHW, FRV_INSN_CMEXPDHW, FRV_INSN_MEXPDHD + , FRV_INSN_CMEXPDHD, FRV_INSN_MPACKH, FRV_INSN_MDPACKH, FRV_INSN_MUNPACKH + , FRV_INSN_MDUNPACKH, FRV_INSN_MBTOH, FRV_INSN_CMBTOH, FRV_INSN_MHTOB + , FRV_INSN_CMHTOB, FRV_INSN_MBTOHE, FRV_INSN_CMBTOHE, FRV_INSN_MCLRACC + , FRV_INSN_MRDACC, FRV_INSN_MRDACCG, FRV_INSN_MWTACC, FRV_INSN_MWTACCG + , FRV_INSN_MCOP1, FRV_INSN_MCOP2, FRV_INSN_FNOP +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID FRV_INSN_INVALID + +/* Total number of insns in table. */ +#define MAX_INSNS ((int) FRV_INSN_FNOP + 1) + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + int length; + long f_nil; + long f_anyof; + long f_pack; + long f_op; + long f_ope1; + long f_ope2; + long f_ope3; + long f_ope4; + long f_GRi; + long f_GRj; + long f_GRk; + long f_FRi; + long f_FRj; + long f_FRk; + long f_CPRi; + long f_CPRj; + long f_CPRk; + long f_ACCGi; + long f_ACCGk; + long f_ACC40Si; + long f_ACC40Ui; + long f_ACC40Sk; + long f_ACC40Uk; + long f_CRi; + long f_CRj; + long f_CRk; + long f_CCi; + long f_CRj_int; + long f_CRj_float; + long f_ICCi_1; + long f_ICCi_2; + long f_ICCi_3; + long f_FCCi_1; + long f_FCCi_2; + long f_FCCi_3; + long f_FCCk; + long f_eir; + long f_s10; + long f_s12; + long f_d12; + long f_u16; + long f_s16; + long f_s6; + long f_s6_1; + long f_u6; + long f_s5; + long f_u12_h; + long f_u12_l; + long f_u12; + long f_int_cc; + long f_flt_cc; + long f_cond; + long f_ccond; + long f_hint; + long f_LI; + long f_lock; + long f_debug; + long f_A; + long f_ae; + long f_spr_h; + long f_spr_l; + long f_spr; + long f_label16; + long f_labelH6; + long f_labelL18; + long f_label24; + long f_ICCi_1_null; + long f_ICCi_2_null; + long f_ICCi_3_null; + long f_FCCi_1_null; + long f_FCCi_2_null; + long f_FCCi_3_null; + long f_rs_null; + long f_GRi_null; + long f_GRj_null; + long f_GRk_null; + long f_FRi_null; + long f_FRj_null; + long f_ACCj_null; + long f_rd_null; + long f_cond_null; + long f_ccond_null; + long f_s12_null; + long f_label16_null; + long f_misc_null_1; + long f_misc_null_2; + long f_misc_null_3; + long f_misc_null_4; + long f_misc_null_5; + long f_misc_null_6; + long f_misc_null_7; + long f_misc_null_8; + long f_misc_null_9; + long f_misc_null_10; + long f_misc_null_11; + long f_LI_off; + long f_LI_on; +}; + +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} + + +#endif /* FRV_OPC_H */ diff --git a/opcodes/po/POTFILES.in b/opcodes/po/POTFILES.in index f247acb58e4..9851ce8d73a 100644 --- a/opcodes/po/POTFILES.in +++ b/opcodes/po/POTFILES.in @@ -26,6 +26,13 @@ fr30-dis.c fr30-ibld.c fr30-opc.c fr30-opc.h +frv-asm.c +frv-desc.c +frv-desc.h +frv-dis.c +frv-ibld.c +frv-opc.c +frv-opc.h h8300-dis.c h8500-dis.c h8500-opc.h |