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authorJason Molenda <jsm@bugshack.cygnus.com>1999-12-07 03:56:43 +0000
committerJason Molenda <jsm@bugshack.cygnus.com>1999-12-07 03:56:43 +0000
commitc13f725cbfef435a3cbc607745a9b917a756c101 (patch)
treeb999781830cb256067326b27503c405c89951ab4
parent2bf2db893284168bfee946e93365f74fc5babe40 (diff)
downloadgdb-c13f725cbfef435a3cbc607745a9b917a756c101.tar.gz
Initial revision
Diffstat
-rw-r--r--gdb/config/mips/tm-vr4xxx.h25
-rw-r--r--gdb/config/mips/tm-vr4xxxel.h25
-rw-r--r--gdb/config/mips/vr4xxx.mt5
-rw-r--r--gdb/config/mips/vr4xxxel.mt5
-rw-r--r--gdb/config/nm-linux.h50
-rw-r--r--gdb/config/tm-linux.h36
-rw-r--r--gdb/testsuite/gdb.base/coremaker2.c58
-rw-r--r--gdb/testsuite/gdb.disasm/am33.exp838
-rw-r--r--gdb/testsuite/gdb.disasm/am33.s524
-rw-r--r--sim/mn10300/am33.igen8683
10 files changed, 10249 insertions, 0 deletions
diff --git a/gdb/config/mips/tm-vr4xxx.h b/gdb/config/mips/tm-vr4xxx.h
new file mode 100644
index 00000000000..1f2a1313389
--- /dev/null
+++ b/gdb/config/mips/tm-vr4xxx.h
@@ -0,0 +1,25 @@
+/* Copyright (C) 1998 Free Software Foundation, Inc.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330,
+ Boston, MA 02111-1307, USA. */
+
+#define GDB_MULTI_ARCH 1
+#define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
+#define TARGET_BYTE_ORDER_SELECTABLE_P 1
+#define TARGET_MONITOR_PROMPT "<RISQ> "
+
+#include "mips/tm-bigmips64.h"
diff --git a/gdb/config/mips/tm-vr4xxxel.h b/gdb/config/mips/tm-vr4xxxel.h
new file mode 100644
index 00000000000..ae5227b5180
--- /dev/null
+++ b/gdb/config/mips/tm-vr4xxxel.h
@@ -0,0 +1,25 @@
+/* Copyright (C) 1998 Free Software Foundation, Inc.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330,
+ Boston, MA 02111-1307, USA. */
+
+#define GDB_MULTI_ARCH 1
+#define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
+#define TARGET_BYTE_ORDER_SELECTABLE_P 1
+#define TARGET_MONITOR_PROMPT "<RISQ> "
+
+#include "mips/tm-mips64.h"
diff --git a/gdb/config/mips/vr4xxx.mt b/gdb/config/mips/vr4xxx.mt
new file mode 100644
index 00000000000..4c79ec7552d
--- /dev/null
+++ b/gdb/config/mips/vr4xxx.mt
@@ -0,0 +1,5 @@
+# Target: Big-endian SIM monitor board.
+TDEPFILES= mips-tdep.o remote-mips.o
+TM_FILE= tm-vr4xxx.h
+SIM_OBS = remote-sim.o
+SIM = ../sim/mips/libsim.a
diff --git a/gdb/config/mips/vr4xxxel.mt b/gdb/config/mips/vr4xxxel.mt
new file mode 100644
index 00000000000..5124dd75461
--- /dev/null
+++ b/gdb/config/mips/vr4xxxel.mt
@@ -0,0 +1,5 @@
+# Target: Big-endian SIM monitor board.
+TDEPFILES= mips-tdep.o remote-mips.o
+TM_FILE= tm-vr4xxxel.h
+SIM_OBS = remote-sim.o
+SIM = ../sim/mips/libsim.a
diff --git a/gdb/config/nm-linux.h b/gdb/config/nm-linux.h
new file mode 100644
index 00000000000..980530681e3
--- /dev/null
+++ b/gdb/config/nm-linux.h
@@ -0,0 +1,50 @@
+/* Native support for GNU/Linux, for GDB, the GNU debugger.
+ Copyright (C) 1999
+ Free Software Foundation, Inc.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330,
+ Boston, MA 02111-1307, USA. */
+
+/* Linux is svr4ish but not that much */
+#undef USE_PROC_FS
+
+/* Tell gdb that we can attach and detach other processes */
+#define ATTACH_DETACH
+
+/* We define this if link.h is available, because with ELF we use SVR4 style
+ shared libraries. */
+
+#ifdef HAVE_LINK_H
+#define SVR4_SHARED_LIBS
+#include "solib.h" /* Support for shared libraries. */
+#endif
+
+/* Support for the glibc linuxthreads package. */
+
+struct objfile;
+
+extern void
+linuxthreads_new_objfile PARAMS ((struct objfile *objfile));
+#define target_new_objfile(OBJFILE) linuxthreads_new_objfile (OBJFILE)
+
+extern char *
+linuxthreads_pid_to_str PARAMS ((int pid));
+#define target_pid_to_str(PID) linuxthreads_pid_to_str (PID)
+
+extern int
+linuxthreads_prepare_to_proceed PARAMS ((int step));
+#define PREPARE_TO_PROCEED(select_it) linuxthreads_prepare_to_proceed (1)
diff --git a/gdb/config/tm-linux.h b/gdb/config/tm-linux.h
new file mode 100644
index 00000000000..d1040ac2df6
--- /dev/null
+++ b/gdb/config/tm-linux.h
@@ -0,0 +1,36 @@
+/* Native support for GNU/Linux, for GDB, the GNU debugger.
+ Copyright (C) 1999
+ Free Software Foundation, Inc.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330,
+ Boston, MA 02111-1307, USA. */
+
+/* Some versions of Linux have real-time signal support in the C library, and
+ some don't. We have to include this file to find out. */
+#include <signal.h>
+
+#ifdef __SIGRTMIN
+#define REALTIME_LO __SIGRTMIN
+#define REALTIME_HI (__SIGRTMAX + 1)
+#else
+#define REALTIME_LO 32
+#define REALTIME_HI 64
+#endif
+
+/* We need this file for the SOLIB_TRAMPOLINE stuff. */
+
+#include "tm-sysv4.h"
diff --git a/gdb/testsuite/gdb.base/coremaker2.c b/gdb/testsuite/gdb.base/coremaker2.c
new file mode 100644
index 00000000000..94f9d000f48
--- /dev/null
+++ b/gdb/testsuite/gdb.base/coremaker2.c
@@ -0,0 +1,58 @@
+/* Simple little program that just generates a core dump from inside some
+ nested function calls. Keep this as self contained as possible, I.E.
+ use no environment resources other than possibly abort(). */
+
+#ifndef __STDC__
+#define const /**/
+#endif
+
+#ifndef HAVE_ABORT
+#define HAVE_ABORT 1
+#endif
+
+#if HAVE_ABORT
+#define ABORT abort()
+#else
+#define ABORT {char *invalid = 0; *invalid = 0xFF;}
+#endif
+
+/* Don't make these automatic vars or we will have to walk back up the
+ stack to access them. */
+
+char *buf1;
+char *buf2;
+
+int coremaker_data = 1; /* In Data section */
+int coremaker_bss; /* In BSS section */
+
+const int coremaker_ro = 201; /* In Read-Only Data section */
+
+void
+func2 (int x)
+{
+ int coremaker_local[5];
+ int i;
+ static int y;
+
+ /* Make sure that coremaker_local doesn't get optimized away. */
+ for (i = 0; i < 5; i++)
+ coremaker_local[i] = i;
+ coremaker_bss = 0;
+ for (i = 0; i < 5; i++)
+ coremaker_bss += coremaker_local[i];
+ coremaker_data = coremaker_ro + 1;
+ y = 10 * x;
+ ABORT;
+}
+
+void
+func1 (int x)
+{
+ func2 (x * 2);
+}
+
+int main ()
+{
+ func1 (10);
+ return 0;
+}
diff --git a/gdb/testsuite/gdb.disasm/am33.exp b/gdb/testsuite/gdb.disasm/am33.exp
new file mode 100644
index 00000000000..0337be8a54b
--- /dev/null
+++ b/gdb/testsuite/gdb.disasm/am33.exp
@@ -0,0 +1,838 @@
+
+# Copyright (C) 1997 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+# Please email any bugs, comments, and/or additions to this file to:
+# bug-gdb@prep.ai.mit.edu
+
+# This file was written by Jeff Law. (law@cygnus.com)
+
+if $tracelevel then {
+ strace $tracelevel
+}
+
+if ![istarget "mn10300*-*-*"] {
+ verbose "Tests ignored for all but mn10300 based targets."
+ return
+}
+
+global exec_output
+set prms_id 0
+set bug_id 0
+
+set testfile "am33"
+set srcfile ${srcdir}/${subdir}/${testfile}.s
+set binfile ${objdir}/${subdir}/${testfile}
+if { [gdb_compile "${srcfile}" "${binfile}" object ""] != "" } {
+ gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail."
+}
+
+proc call_tests { } {
+ global gdb_prompt
+ global hex
+ global decimal
+
+ send_gdb "x/8i call_tests\n"
+ gdb_expect {
+ -re "
+.*call .*,.a2,a3,exreg0.,9.*
+.*call .*,.a2,a3,exreg1.,9.*
+.*call .*,.a2,a3,exother.,9.*
+.*call .*,.d2,d3,a2,a3,other,exreg0,exreg1,exother.,9.*
+.*call .*,.a2,a3,exreg0.,9.*
+.*call .*,.a2,a3,exreg1.,9.*
+.*call .*,.a2,a3,exother.,9.*
+.*call .*,.d2,d3,a2,a3,other,exreg0,exreg1,exother.,9.*
+.*$gdb_prompt $" { pass "call tests" }
+ -re "$gdb_prompt $" { fail "call tests" }
+ timeout { fail "(timeout) call tests" }
+ }
+}
+
+proc movm_tests { } {
+ global gdb_prompt
+ global hex
+ global decimal
+
+ send_gdb "x/16i movm_tests\n"
+ gdb_expect {
+ -re "
+.*movm \\(sp\\),.a2,a3,exreg0.*
+.*movm \\(sp\\),.a2,a3,exreg1.*
+.*movm \\(sp\\),.a2,a3,exother.*
+.*movm \\(sp\\),.d2,d3,a2,a3,other,exreg0,exreg1,exother.*
+.*movm .a2,a3,exreg0.,\\(sp\\).*
+.*movm .a2,a3,exreg1.,\\(sp\\).*
+.*movm .a2,a3,exother.,\\(sp\\).*
+.*movm .d2,d3,a2,a3,other,exreg0,exreg1,exother.,\\(sp\\).*
+.*movm \\(usp\\),.a2,a3,exreg0.*
+.*movm \\(usp\\),.a2,a3,exreg1.*
+.*movm \\(usp\\),.a2,a3,exother.*
+.*movm \\(usp\\),.d2,d3,a2,a3,other,exreg0,exreg1,exother.*
+.*movm .a2,a3,exreg0.,\\(usp\\).*
+.*movm .a2,a3,exreg1.,\\(usp\\).*
+.*movm .a2,a3,exother.,\\(usp\\).*
+.*movm .d2,d3,a2,a3,other,exreg0,exreg1,exother.,\\(usp\\).*
+.*$gdb_prompt $" { pass "movm tests" }
+ -re "$gdb_prompt $" { fail "movm tests" }
+ timeout { fail "(timeout) movm tests" }
+ }
+}
+
+proc misc_tests { } {
+ global gdb_prompt
+ global hex
+ global decimal
+
+ send_gdb "x/11i misc_tests\n"
+ gdb_expect {
+ -re "
+.*syscall 4.*
+.*mcst9 d0.*
+.*mcst48 d1.*
+.*getchx d0.*
+.*getclx d1.*
+.*clr a1.*
+.*sat16 a1,a0.*
+.*mcste r7,r6.*
+.*swap r5,r4.*
+.*swaph r3,r2.*
+.*swhw r1,r0.*
+.*$gdb_prompt $" { pass "misc tests" }
+ -re "$gdb_prompt $" { fail "misc tests" }
+ timeout { fail "(timeout) misc tests" }
+ }
+}
+
+proc mov_tests { } {
+ global gdb_prompt
+ global hex
+ global decimal
+
+ send_gdb "x/45i mov_tests\n"
+ gdb_expect {
+ -re "
+.*mov r0,r1.*
+.*mov sp,r1.*
+.*mov r1,xr2.*
+.*mov \\(r1\\),r2.*
+.*mov r3,\\(r4\\).*
+.*mov \\(sp\\),r5.*
+.*mov r6,\\(sp\\).*
+.*mov 16,r1.*
+.*mov 16,xr1.*
+.*mov \\(16,r1\\),r2.*
+.*mov r2,\\(16,r1\\).*
+.*mov \\(16,sp\\),r2.*
+.*mov r2,\\(16,sp\\).*
+.*mov 2096895,r2.*
+.*mov 2096895,xr2.*
+.*mov \\(2096895,r1\\),r2.*
+.*mov r2,\\(2096895,r1\\).*
+.*mov \\(2096895,sp\\),r2.*
+.*mov r2,\\(2096895,sp\\).*
+.*mov \\(0x1ffeff\\),r2.*
+.*mov r2,\\(0x1ffeff\\).*
+.*mov 2147417596,r2.*
+.*mov 2147417596,xr2.*
+.*mov \\(2147417596,r1\\),r2.*
+.*mov r2,\\(2147417596,r1\\).*
+.*mov \\(2147417596,sp\\),r2.*
+.*mov r2,\\(2147417596,sp\\).*
+.*mov \\(0x7ffefdfc\\),r2.*
+.*mov r2,\\(0x7ffefdfc\\).*
+.*movu 16,r1.*
+.*movu 2096895,r2.*
+.*movu 2147417596,r2.*
+.*mov usp,a0.*
+.*mov ssp,a1.*
+.*mov msp,a2.*
+.*mov pc,a3.*
+.*mov a0,usp.*
+.*mov a1,ssp.*
+.*mov a2,msp.*
+.*mov epsw,d0.*
+.*mov d1,epsw.*
+.*mov a0,r1.*
+.*mov d2,r3.*
+.*mov r5,a1.*
+.*mov r7,d3.*
+.*$gdb_prompt $" { pass "mov tests" }
+ -re "$gdb_prompt $" { fail "mov tests" }
+ timeout { fail "(timeout) mov tests" }
+ }
+}
+
+proc ext_tests { } {
+ global gdb_prompt
+ global hex
+ global decimal
+
+ send_gdb "x/5i ext_tests\n"
+ gdb_expect {
+ -re "
+.*ext r2.*
+.*extb r3,r4.*
+.*extbu r4,r5.*
+.*exth r6,r7.*
+.*exthu r7,a0.*
+.*$gdb_prompt $" { pass "ext tests" }
+ -re "$gdb_prompt $" { fail "ext tests" }
+ timeout { fail "(timeout) ext tests" }
+ }
+}
+
+proc add_tests { } {
+ global gdb_prompt
+ global hex
+ global decimal
+
+ send_gdb "x/11i add_tests\n"
+ gdb_expect {
+ -re "
+.*add a2,a3.*
+.*add 16,r1.*
+.*add 2096895,r2.*
+.*add 2147417596,r2.*
+.*add r1,r2,r3.*
+.*addc d0,d1.*
+.*addc 16,r1.*
+.*addc 2096895,r2.*
+.*addc 2147417596,r2.*
+.*inc d1.*
+.*inc4 d0.*
+.*$gdb_prompt $" { pass "add tests" }
+ -re "$gdb_prompt $" { fail "add tests" }
+ timeout { fail "(timeout) add tests" }
+ }
+}
+
+proc sub_tests { } {
+ global gdb_prompt
+ global hex
+ global decimal
+
+ send_gdb "x/8i sub_tests\n"
+ gdb_expect {
+ -re "
+.*sub d2,d3.*
+.*sub 16,r1.*
+.*sub 2096895,r2.*
+.*sub 2147417596,r2.*
+.*subc d3,d2.*
+.*subc 16,r1.*
+.*subc 2096895,r2.*
+.*subc 2147417596,r2.*
+.*$gdb_prompt $" { pass "sub tests" }
+ -re "$gdb_prompt $" { fail "sub tests" }
+ timeout { fail "(timeout) sub tests" }
+ }
+}
+
+proc cmp_tests { } {
+ global gdb_prompt
+ global hex
+ global decimal
+
+ send_gdb "x/4i cmp_tests\n"
+ gdb_expect {
+ -re "
+.*cmp a3,a2.*
+.*cmp 16,r1.*
+.*cmp 2096895,r2.*
+.*cmp 2147417596,r2.*
+.*$gdb_prompt $" { pass "cmp tests" }
+ -re "$gdb_prompt $" { fail "cmp tests" }
+ timeout { fail "(timeout) cmp tests" }
+ }
+}
+
+proc logical_tests { } {
+ global gdb_prompt
+ global hex
+ global decimal
+
+ send_gdb "x/15i logical_tests\n"
+ gdb_expect {
+ -re "
+.*and r0,r1.*
+.*or r2,r3.*
+.*xor r4,r5.*
+.*not r6.*
+.*and 16,r1.*
+.*or 16,r1.*
+.*xor 16,r1.*
+.*and 2096895,r2.*
+.*or 2096895,r2.*
+.*xor 2096895,r2.*
+.*and 2147417596,r2.*
+.*or 2147417596,r2.*
+.*xor 2147417596,r2.*
+.*and 131072,epsw.*
+.*or 65535,epsw.*
+.*$gdb_prompt $" { pass "logical tests" }
+ -re "$gdb_prompt $" { fail "logical tests" }
+ timeout { fail "(timeout) logical tests" }
+ }
+}
+
+proc shift_tests { } {
+ global gdb_prompt
+ global hex
+ global decimal
+
+ send_gdb "x/15i shift_tests\n"
+ gdb_expect {
+ -re "
+.*asr r7,a0.*
+.*lsr a1,a2.*
+.*asl a3,d0.*
+.*asl2 d1.*
+.*ror d2.*
+.*rol d3.*
+.*asr 16,r1.*
+.*lsr 16,r1.*
+.*asl 16,r1.*
+.*asr 2096895,r2.*
+.*lsr 2096895,r2.*
+.*asl 2096895,r2.*
+.*asr 2147417596,r2.*
+.*lsr 2147417596,r2.*
+.*asl 2147417596,r2.*
+.*$gdb_prompt $" { pass "shift tests" }
+ -re "$gdb_prompt $" { fail "shift tests" }
+ timeout { fail "(timeout) shift tests" }
+ }
+}
+
+proc muldiv_tests { } {
+ global gdb_prompt
+ global hex
+ global decimal
+
+ send_gdb "x/16i muldiv_tests\n"
+ gdb_expect {
+ -re "
+.*mul r1,r2.*
+.*mulu r3,r4.*
+.*mul 16,r1.*
+.*mulu 16,r1.*
+.*mul 2096895,r2.*
+.*mulu 2096895,r2.*
+.*mul 2147417596,r2.*
+.*mulu 2147417596,r2.*
+.*div r5,r6.*
+.*divu r7,a0.*
+.*dmulh d1,d0.*
+.*dmulhu a3,a2.*
+.*dmulh 2147417596,r2.*
+.*dmulhu 2147417596,r2.*
+.*mul r1,r2,r3,r4.*
+.*mulu r1,r2,r3,r4.*
+.*$gdb_prompt $" { pass "muldiv tests" }
+ -re "$gdb_prompt $" { fail "muldiv tests" }
+ timeout { fail "(timeout) muldiv tests" }
+ }
+}
+
+proc movbu_tests { } {
+ global gdb_prompt
+ global hex
+ global decimal
+
+ send_gdb "x/20i movbu_tests\n"
+ gdb_expect {
+ -re "
+.*movbu \\(r5\\),r6.*
+.*movbu r7,\\(a0\\).*
+.*movbu \\(sp\\),r7.*
+.*movbu a0,\\(sp\\).*
+.*movbu \\(16,r1\\),r2.*
+.*movbu r2,\\(16,r1\\).*
+.*movbu \\(16,sp\\),r2.*
+.*movbu r2,\\(16,sp\\).*
+.*movbu \\(2096895,r1\\),r2.*
+.*movbu r2,\\(2096895,r1\\).*
+.*movbu \\(2096895,sp\\),r2.*
+.*movbu r2,\\(2096895,sp\\).*
+.*movbu \\(0x1ffeff\\),r2.*
+.*movbu r2,\\(0x1ffeff\\).*
+.*movbu \\(2147417596,r1\\),r2.*
+.*movbu r2,\\(2147417596,r1\\).*
+.*movbu \\(2147417596,sp\\),r2.*
+.*movbu r2,\\(2147417596,sp\\).*
+.*movbu \\(0x7ffefdfc\\),r2.*
+.*movbu r2,\\(0x7ffefdfc\\).*
+.*$gdb_prompt $" { pass "movbu tests" }
+ -re "$gdb_prompt $" { fail "movbu tests" }
+ timeout { fail "(timeout) movbu tests" }
+ }
+}
+
+proc movhu_tests { } {
+ global gdb_prompt
+ global hex
+ global decimal
+
+ send_gdb "x/20i movhu_tests\n"
+ gdb_expect {
+ -re "
+.*movhu \\(a1\\),a2.*
+.*movhu a3,\\(d0\\).*
+.*movhu \\(sp\\),a1.*
+.*movhu a2,\\(sp\\).*
+.*movhu \\(16,r1\\),r2.*
+.*movhu r2,\\(16,r1\\).*
+.*movhu \\(16,sp\\),r2.*
+.*movhu r2,\\(16,sp\\).*
+.*movhu \\(2096895,r1\\),r2.*
+.*movhu r2,\\(2096895,r1\\).*
+.*movhu \\(2096895,sp\\),r2.*
+.*movhu r2,\\(2096895,sp\\).*
+.*movhu \\(0x1ffeff\\),r2.*
+.*movhu r2,\\(0x1ffeff\\).*
+.*movhu \\(2147417596,r1\\),r2.*
+.*movhu r2,\\(2147417596,r1\\).*
+.*movhu \\(2147417596,sp\\),r2.*
+.*movhu r2,\\(2147417596,sp\\).*
+.*movhu \\(0x7ffefdfc\\),r2.*
+.*movhu r2,\\(0x7ffefdfc\\).*
+.*$gdb_prompt $" { pass "movhu tests" }
+ -re "$gdb_prompt $" { fail "movhu tests" }
+ timeout { fail "(timeout) movhu tests" }
+ }
+}
+
+proc mac_tests { } {
+ global gdb_prompt
+ global hex
+ global decimal
+
+ send_gdb "x/28i mac_tests\n"
+ gdb_expect {
+ -re "
+.*mac r1,r2.*
+.*macu r3,r4.*
+.*macb r5,r6.*
+.*macbu r7,a0.*
+.*mach a1,a2.*
+.*machu a3,d0.*
+.*dmach d1,d2.*
+.*dmachu d3,d2.*
+.*mac 16,r1.*
+.*macu 16,r1.*
+.*macb 16,r1.*
+.*macbu 16,r1.*
+.*mach 16,r1.*
+.*machu 16,r1.*
+.*mac 2096895,r2.*
+.*macu 2096895,r2.*
+.*macb 2096895,r2.*
+.*macbu 2096895,r2.*
+.*mach 2096895,r2.*
+.*machu 2096895,r2.*
+.*mac 2147417596,r2.*
+.*macu 2147417596,r2.*
+.*macb 2147417596,r2.*
+.*macbu 2147417596,r2.*
+.*mach 2147417596,r2.*
+.*machu 2147417596,r2.*
+.*dmach 2147417596,r2.*
+.*dmachu 2147417596,r2.*
+.*$gdb_prompt $" { pass "mac tests" }
+ -re "$gdb_prompt $" { fail "mac tests" }
+ timeout { fail "(timeout) mac tests" }
+ }
+}
+
+proc bit_tests { } {
+ global gdb_prompt
+ global hex
+ global decimal
+
+ send_gdb "x/4i bit_tests\n"
+ gdb_expect {
+ -re "
+.*bsch r1,r2.*
+.*btst 16,r1.*
+.*btst 2096895,r2.*
+.*btst 2147417596,r2.*
+.*$gdb_prompt $" { pass "bit tests" }
+ -re "$gdb_prompt $" { fail "bit tests" }
+ timeout { fail "(timeout) bit tests" }
+ }
+}
+
+proc dsp_add_tests { } {
+ global gdb_prompt
+ global hex
+ global decimal
+
+ send_gdb "x/28i dsp_add_tests\n"
+ gdb_expect {
+ -re "
+.*add_add r4,r1,r2,r3.*
+.*add_add r4,r1,2,r3.*
+.*add_sub r4,r1,r2,r3.*
+.*add_sub r4,r1,2,r3.*
+.*add_cmp r4,r1,r2,r3.*
+.*add_cmp r4,r1,2,r3.*
+.*add_mov r4,r1,r2,r3.*
+.*add_mov r4,r1,2,r3.*
+.*add_asr r4,r1,r2,r3.*
+.*add_asr r4,r1,2,r3.*
+.*add_lsr r4,r1,r2,r3.*
+.*add_lsr r4,r1,2,r3.*
+.*add_asl r4,r1,r2,r3.*
+.*add_asl r4,r1,2,r3.*
+.*add_add 4,r1,r2,r3.*
+.*add_add 4,r1,2,r3.*
+.*add_sub 4,r1,r2,r3.*
+.*add_sub 4,r1,2,r3.*
+.*add_cmp 4,r1,r2,r3.*
+.*add_cmp 4,r1,2,r3.*
+.*add_mov 4,r1,r2,r3.*
+.*add_mov 4,r1,2,r3.*
+.*add_asr 4,r1,r2,r3.*
+.*add_asr 4,r1,2,r3.*
+.*add_lsr 4,r1,r2,r3.*
+.*add_lsr 4,r1,2,r3.*
+.*add_asl 4,r1,r2,r3.*
+.*add_asl 4,r1,2,r3.*
+.*$gdb_prompt $" { pass "dsp_add tests" }
+ -re "$gdb_prompt $" { fail "dsp_add tests" }
+ timeout { fail "(timeout) dsp_add tests" }
+ }
+}
+
+proc dsp_cmp_tests { } {
+ global gdb_prompt
+ global hex
+ global decimal
+
+ send_gdb "x/24i dsp_cmp_tests\n"
+ gdb_expect {
+ -re "
+.*cmp_add r4,r1,r2,r3.*
+.*cmp_add r4,r1,2,r3.*
+.*cmp_sub r4,r1,r2,r3.*
+.*cmp_sub r4,r1,2,r3.*
+.*cmp_mov r4,r1,r2,r3.*
+.*cmp_mov r4,r1,2,r3.*
+.*cmp_asr r4,r1,r2,r3.*
+.*cmp_asr r4,r1,2,r3.*
+.*cmp_lsr r4,r1,r2,r3.*
+.*cmp_lsr r4,r1,2,r3.*
+.*cmp_asl r4,r1,r2,r3.*
+.*cmp_asl r4,r1,2,r3.*
+.*cmp_add 4,r1,r2,r3.*
+.*cmp_add 4,r1,2,r3.*
+.*cmp_sub 4,r1,r2,r3.*
+.*cmp_sub 4,r1,2,r3.*
+.*cmp_mov 4,r1,r2,r3.*
+.*cmp_mov 4,r1,2,r3.*
+.*cmp_asr 4,r1,r2,r3.*
+.*cmp_asr 4,r1,2,r3.*
+.*cmp_lsr 4,r1,r2,r3.*
+.*cmp_lsr 4,r1,2,r3.*
+.*cmp_asl 4,r1,r2,r3.*
+.*cmp_asl 4,r1,2,r3.*
+.*$gdb_prompt $" { pass "dsp_cmp tests" }
+ -re "$gdb_prompt $" { fail "dsp_cmp tests" }
+ timeout { fail "(timeout) dsp_cmp tests" }
+ }
+}
+
+proc dsp_sub_tests { } {
+ global gdb_prompt
+ global hex
+ global decimal
+
+ send_gdb "x/28i dsp_sub_tests\n"
+ gdb_expect {
+ -re "
+.*sub_add r4,r1,r2,r3.*
+.*sub_add r4,r1,2,r3.*
+.*sub_sub r4,r1,r2,r3.*
+.*sub_sub r4,r1,2,r3.*
+.*sub_cmp r4,r1,r2,r3.*
+.*sub_cmp r4,r1,2,r3.*
+.*sub_mov r4,r1,r2,r3.*
+.*sub_mov r4,r1,2,r3.*
+.*sub_asr r4,r1,r2,r3.*
+.*sub_asr r4,r1,2,r3.*
+.*sub_lsr r4,r1,r2,r3.*
+.*sub_lsr r4,r1,2,r3.*
+.*sub_asl r4,r1,r2,r3.*
+.*sub_asl r4,r1,2,r3.*
+.*sub_add 4,r1,r2,r3.*
+.*sub_add 4,r1,2,r3.*
+.*sub_sub 4,r1,r2,r3.*
+.*sub_sub 4,r1,2,r3.*
+.*sub_cmp 4,r1,r2,r3.*
+.*sub_cmp 4,r1,2,r3.*
+.*sub_mov 4,r1,r2,r3.*
+.*sub_mov 4,r1,2,r3.*
+.*sub_asr 4,r1,r2,r3.*
+.*sub_asr 4,r1,2,r3.*
+.*sub_lsr 4,r1,r2,r3.*
+.*sub_lsr 4,r1,2,r3.*
+.*sub_asl 4,r1,r2,r3.*
+.*sub_asl 4,r1,2,r3.*
+.*$gdb_prompt $" { pass "dsp_sub tests" }
+ -re "$gdb_prompt $" { fail "dsp_sub tests" }
+ timeout { fail "(timeout) dsp_sub tests" }
+ }
+}
+
+proc dsp_mov_tests { } {
+ global gdb_prompt
+ global hex
+ global decimal
+
+ send_gdb "x/28i dsp_mov_tests\n"
+ gdb_expect {
+ -re "
+.*mov_add r4,r1,r2,r3.*
+.*mov_add r4,r1,2,r3.*
+.*mov_sub r4,r1,r2,r3.*
+.*mov_sub r4,r1,2,r3.*
+.*mov_cmp r4,r1,r2,r3.*
+.*mov_cmp r4,r1,2,r3.*
+.*mov_mov r4,r1,r2,r3.*
+.*mov_mov r4,r1,2,r3.*
+.*mov_asr r4,r1,r2,r3.*
+.*mov_asr r4,r1,2,r3.*
+.*mov_lsr r4,r1,r2,r3.*
+.*mov_lsr r4,r1,2,r3.*
+.*mov_asl r4,r1,r2,r3.*
+.*mov_asl r4,r1,2,r3.*
+.*mov_add 4,r1,r2,r3.*
+.*mov_add 4,r1,2,r3.*
+.*mov_sub 4,r1,r2,r3.*
+.*mov_sub 4,r1,2,r3.*
+.*mov_cmp 4,r1,r2,r3.*
+.*mov_cmp 4,r1,2,r3.*
+.*mov_mov 4,r1,r2,r3.*
+.*mov_mov 4,r1,2,r3.*
+.*mov_asr 4,r1,r2,r3.*
+.*mov_asr 4,r1,2,r3.*
+.*mov_lsr 4,r1,r2,r3.*
+.*mov_lsr 4,r1,2,r3.*
+.*mov_asl 4,r1,r2,r3.*
+.*mov_asl 4,r1,2,r3.*
+.*$gdb_prompt $" { pass "dsp_mov tests" }
+ -re "$gdb_prompt $" { fail "dsp_mov tests" }
+ timeout { fail "(timeout) dsp_mov tests" }
+ }
+}
+
+proc dsp_logical_tests { } {
+ global gdb_prompt
+ global hex
+ global decimal
+
+ send_gdb "x/42i dsp_logical_tests\n"
+ gdb_expect {
+ -re "
+.*and_add r4,r1,r2,r3.*
+.*and_add r4,r1,2,r3.*
+.*and_sub r4,r1,r2,r3.*
+.*and_sub r4,r1,2,r3.*
+.*and_cmp r4,r1,r2,r3.*
+.*and_cmp r4,r1,2,r3.*
+.*and_mov r4,r1,r2,r3.*
+.*and_mov r4,r1,2,r3.*
+.*and_asr r4,r1,r2,r3.*
+.*and_asr r4,r1,2,r3.*
+.*and_lsr r4,r1,r2,r3.*
+.*and_lsr r4,r1,2,r3.*
+.*and_asl r4,r1,r2,r3.*
+.*and_asl r4,r1,2,r3.*
+.*xor_add r4,r1,r2,r3.*
+.*xor_add r4,r1,2,r3.*
+.*xor_sub r4,r1,r2,r3.*
+.*xor_sub r4,r1,2,r3.*
+.*xor_cmp r4,r1,r2,r3.*
+.*xor_cmp r4,r1,2,r3.*
+.*xor_mov r4,r1,r2,r3.*
+.*xor_mov r4,r1,2,r3.*
+.*xor_asr r4,r1,r2,r3.*
+.*xor_asr r4,r1,2,r3.*
+.*xor_lsr r4,r1,r2,r3.*
+.*xor_lsr r4,r1,2,r3.*
+.*xor_asl r4,r1,r2,r3.*
+.*xor_asl r4,r1,2,r3.*
+.*or_add r4,r1,r2,r3.*
+.*or_add r4,r1,2,r3.*
+.*or_sub r4,r1,r2,r3.*
+.*or_sub r4,r1,2,r3.*
+.*or_cmp r4,r1,r2,r3.*
+.*or_cmp r4,r1,2,r3.*
+.*or_mov r4,r1,r2,r3.*
+.*or_mov r4,r1,2,r3.*
+.*or_asr r4,r1,r2,r3.*
+.*or_asr r4,r1,2,r3.*
+.*or_lsr r4,r1,r2,r3.*
+.*or_lsr r4,r1,2,r3.*
+.*or_asl r4,r1,r2,r3.*
+.*or_asl r4,r1,2,r3.*
+.*$gdb_prompt $" { pass "dsp_logical tests" }
+ -re "$gdb_prompt $" { fail "dsp_logical tests" }
+ timeout { fail "(timeout) dsp_logical tests" }
+ }
+}
+
+proc dsp_misc_tests { } {
+ global gdb_prompt
+ global hex
+ global decimal
+
+ send_gdb "x/42i dsp_misc_tests\n"
+ gdb_expect {
+ -re "
+.*dmach_add r4,r1,r2,r3.*
+.*dmach_add r4,r1,2,r3.*
+.*dmach_sub r4,r1,r2,r3.*
+.*dmach_sub r4,r1,2,r3.*
+.*dmach_cmp r4,r1,r2,r3.*
+.*dmach_cmp r4,r1,2,r3.*
+.*dmach_mov r4,r1,r2,r3.*
+.*dmach_mov r4,r1,2,r3.*
+.*dmach_asr r4,r1,r2,r3.*
+.*dmach_asr r4,r1,2,r3.*
+.*dmach_lsr r4,r1,r2,r3.*
+.*dmach_lsr r4,r1,2,r3.*
+.*dmach_asl r4,r1,r2,r3.*
+.*dmach_asl r4,r1,2,r3.*
+.*swhw_add r4,r1,r2,r3.*
+.*swhw_add r4,r1,2,r3.*
+.*swhw_sub r4,r1,r2,r3.*
+.*swhw_sub r4,r1,2,r3.*
+.*swhw_cmp r4,r1,r2,r3.*
+.*swhw_cmp r4,r1,2,r3.*
+.*swhw_mov r4,r1,r2,r3.*
+.*swhw_mov r4,r1,2,r3.*
+.*swhw_asr r4,r1,r2,r3.*
+.*swhw_asr r4,r1,2,r3.*
+.*swhw_lsr r4,r1,r2,r3.*
+.*swhw_lsr r4,r1,2,r3.*
+.*swhw_asl r4,r1,r2,r3.*
+.*swhw_asl r4,r1,2,r3.*
+.*sat16_add r4,r1,r2,r3.*
+.*sat16_add r4,r1,2,r3.*
+.*sat16_sub r4,r1,r2,r3.*
+.*sat16_sub r4,r1,2,r3.*
+.*sat16_cmp r4,r1,r2,r3.*
+.*sat16_cmp r4,r1,2,r3.*
+.*sat16_mov r4,r1,r2,r3.*
+.*sat16_mov r4,r1,2,r3.*
+.*sat16_asr r4,r1,r2,r3.*
+.*sat16_asr r4,r1,2,r3.*
+.*sat16_lsr r4,r1,r2,r3.*
+.*sat16_lsr r4,r1,2,r3.*
+.*sat16_asl r4,r1,r2,r3.*
+.*sat16_asl r4,r1,2,r3.*
+.*$gdb_prompt $" { pass "dsp_misc tests" }
+ -re "$gdb_prompt $" { fail "dsp_misc tests" }
+ timeout { fail "(timeout) dsp_misc tests" }
+ }
+}
+
+proc autoincrement_tests { } {
+ global gdb_prompt
+ global hex
+ global decimal
+
+ send_gdb "x/16i autoincrement_tests\n"
+ gdb_expect {
+ -re "
+.*mov \\(r1\\+\\),r2.*
+.*mov r3,\\(r4\\+\\).*
+.*movhu \\(r6\\+\\),r7.*
+.*movhu a0,\\(a1\\+\\).*
+.*mov \\(r1\\+,64\\),r2.*
+.*mov r1,\\(r2\\+,64\\).*
+.*movhu \\(r1\\+,64\\),r2.*
+.*movhu r1,\\(r2\\+,64\\).*
+.*mov \\(r1\\+,131055\\),r2.*
+.*mov r1,\\(r2\\+,131055\\).*
+.*movhu \\(r1\\+,131055\\),r2.*
+.*movhu r1,\\(r2\\+,131055\\).*
+.*mov \\(r1\\+,2147417596\\),r2.*
+.*mov r1,\\(r2\\+,2147417596\\).*
+.*movhu \\(r1\\+,2147417596\\),r2.*
+.*movhu r1,\\(r2\\+,2147417596\\).*
+.*$gdb_prompt $" { pass "autoincrement tests" }
+ -re "$gdb_prompt $" { fail "autoincrement tests" }
+ timeout { fail "(timeout) autoincrement tests" }
+ }
+}
+
+proc dsp_autoincrement_tests { } {
+ global gdb_prompt
+ global hex
+ global decimal
+
+ send_gdb "x/11i dsp_autoincrement_tests\n"
+ gdb_expect {
+ -re "
+.*mov_llt \\(r1\\+,4\\),r2.*
+.*mov_lgt \\(r1\\+,4\\),r2.*
+.*mov_lge \\(r1\\+,4\\),r2.*
+.*mov_lle \\(r1\\+,4\\),r2.*
+.*mov_lcs \\(r1\\+,4\\),r2.*
+.*mov_lhi \\(r1\\+,4\\),r2.*
+.*mov_lcc \\(r1\\+,4\\),r2.*
+.*mov_lls \\(r1\\+,4\\),r2.*
+.*mov_leq \\(r1\\+,4\\),r2.*
+.*mov_lne \\(r1\\+,4\\),r2.*
+.*mov_lra \\(r1\\+,4\\),r2.*
+.*$gdb_prompt $" { pass "autoincrement tests" }
+ -re "$gdb_prompt $" { fail "autoincrement tests" }
+ timeout { fail "(timeout) autoincrement tests" }
+ }
+}
+
+# Start with a fresh gdb.
+
+gdb_exit
+gdb_start
+gdb_reinitialize_dir $srcdir/$subdir
+gdb_load $binfile
+
+call_tests
+movm_tests
+misc_tests
+mov_tests
+ext_tests
+add_tests
+sub_tests
+cmp_tests
+logical_tests
+shift_tests
+muldiv_tests
+movbu_tests
+movhu_tests
+mac_tests
+bit_tests
+dsp_add_tests
+dsp_cmp_tests
+dsp_sub_tests
+dsp_mov_tests
+dsp_logical_tests
+autoincrement_tests
+dsp_autoincrement_tests
diff --git a/gdb/testsuite/gdb.disasm/am33.s b/gdb/testsuite/gdb.disasm/am33.s
new file mode 100644
index 00000000000..a686cef2f74
--- /dev/null
+++ b/gdb/testsuite/gdb.disasm/am33.s
@@ -0,0 +1,524 @@
+
+ .globl _main
+ .globl call_tests
+ .globl movm_tests
+ .globl misc_tests
+ .globl mov_tests
+ .globl ext_tests
+ .globl add_tests
+ .globl sub_tests
+ .globl cmp_tests
+ .globl logical_tests
+ .globl shift_tests
+ .globl muldiv_tests
+ .globl movbu_tests
+ .globl movhu_tests
+ .globl mac_tests
+ .globl bit_tests
+ .globl dsp_add_tests
+ .globl dsp_cmp_tests
+ .globl dsp_sub_tests
+ .globl dsp_mov_tests
+ .globl dsp_logical_tests
+ .globl dsp_misc_tests
+ .globl autoincrement_tests
+ .globl dsp_autoincrement_tests
+
+ .text
+ .am33
+_main:
+call_tests:
+ call 256,[a2,a3,exreg0],9
+ call 256,[a2,a3,exreg1],9
+ call 256,[a2,a3,exother],9
+ call 256,[a2,a3,all],9
+ call 131071,[a2,a3,exreg0],9
+ call 131071,[a2,a3,exreg1],9
+ call 131071,[a2,a3,exother],9
+ call 131071,[a2,a3,all],9
+
+movm_tests:
+ movm (sp),[a2,a3,exreg0]
+ movm (sp),[a2,a3,exreg1]
+ movm (sp),[a2,a3,exother]
+ movm (sp),[a2,a3,all]
+ movm [a2,a3,exreg0],(sp)
+ movm [a2,a3,exreg1],(sp)
+ movm [a2,a3,exother],(sp)
+ movm [a2,a3,all],(sp)
+ movm (usp),[a2,a3,exreg0]
+ movm (usp),[a2,a3,exreg1]
+ movm (usp),[a2,a3,exother]
+ movm (usp),[a2,a3,all]
+ movm [a2,a3,exreg0],(usp)
+ movm [a2,a3,exreg1],(usp)
+ movm [a2,a3,exother],(usp)
+ movm [a2,a3,all],(usp)
+
+misc_tests:
+ syscall 0x4
+ mcst9 d0
+ mcst48 d1
+ getchx d0
+ getclx d1
+ clr r9
+ sat16 r9,r8
+ mcste r7,r6
+ swap r5,r4
+ swaph r3,r2
+ swhw r1,r0
+
+
+mov_tests:
+ mov r0,r1
+ mov xr0, r1
+ mov r1, xr2
+ mov (r1),r2
+ mov r3,(r4)
+ mov (sp),r5
+ mov r6,(sp)
+ mov 16,r1
+ mov 16,xr1
+ mov (16,r1),r2
+ mov r2,(16,r1)
+ mov (16,sp),r2
+ mov r2,(16,sp)
+ mov 0x1ffeff,r2
+ mov 0x1ffeff,xr2
+ mov (0x1ffeff,r1),r2
+ mov r2,(0x1ffeff,r1)
+ mov (0x1ffeff,sp),r2
+ mov r2,(0x1ffeff,sp)
+ mov (0x1ffeff),r2
+ mov r2,(0x1ffeff)
+ mov 0x7ffefdfc,r2
+ mov 0x7ffefdfc,xr2
+ mov (0x7ffefdfc,r1),r2
+ mov r2,(0x7ffefdfc,r1)
+ mov (0x7ffefdfc,sp),r2
+ mov r2,(0x7ffefdfc,sp)
+ mov (0x7ffefdfc),r2
+ mov r2,(0x7ffefdfc)
+ movu 16,r1
+ movu 0x1ffeff,r2
+ movu 0x7ffefdfc,r2
+ mov usp,a0
+ mov ssp,a1
+ mov msp,a2
+ mov pc,a3
+ mov a0,usp
+ mov a1,ssp
+ mov a2,msp
+ mov epsw,d0
+ mov d1,epsw
+ mov a0,r1
+ mov d2,r3
+ mov r5,a1
+ mov r7,d3
+
+ext_tests:
+ ext r2
+ extb r3,r4
+ extbu r4,r5
+ exth r6,r7
+ exthu r7,r8
+
+add_tests:
+ add r10,r11
+ add 16,r1
+ add 0x1ffeff,r2
+ add 0x7ffefdfc,r2
+ add r1,r2,r3
+ addc r12,r13
+ addc 16,r1
+ addc 0x1ffeff,r2
+ addc 0x7ffefdfc,r2
+ inc r13
+ inc4 r12
+
+
+sub_tests:
+ sub r14,r15
+ sub 16,r1
+ sub 0x1ffeff,r2
+ sub 0x7ffefdfc,r2
+ subc r15,r14
+ subc 16,r1
+ subc 0x1ffeff,r2
+ subc 0x7ffefdfc,r2
+
+cmp_tests:
+ cmp r11,r10
+ cmp 16,r1
+ cmp 0x1ffeff,r2
+ cmp 0x7ffefdfc,r2
+
+logical_tests:
+ and r0,r1
+ or r2,r3
+ xor r4,r5
+ not r6
+ and 16,r1
+ or 16,r1
+ xor 16,r1
+ and 0x1ffeff,r2
+ or 0x1ffeff,r2
+ xor 0x1ffeff,r2
+ and 0x7ffefdfc,r2
+ or 0x7ffefdfc,r2
+ xor 0x7ffefdfc,r2
+ and 131072,epsw
+ or 65535,epsw
+
+shift_tests:
+ asr r7,r8
+ lsr r9,r10
+ asl r11,r12
+ asl2 r13
+ ror r14
+ rol r15
+ asr 16,r1
+ lsr 16,r1
+ asl 16,r1
+ asr 0x1ffeff,r2
+ lsr 0x1ffeff,r2
+ asl 0x1ffeff,r2
+ asr 0x7ffefdfc,r2
+ lsr 0x7ffefdfc,r2
+ asl 0x7ffefdfc,r2
+
+muldiv_tests:
+ mul r1,r2
+ mulu r3,r4
+ mul 16,r1
+ mulu 16,r1
+ mul 0x1ffeff,r2
+ mulu 0x1ffeff,r2
+ mul 0x7ffefdfc,r2
+ mulu 0x7ffefdfc,r2
+ div r5,r6
+ divu r7,r8
+ dmulh r13,r12
+ dmulhu r11,r10
+ dmulh 0x7ffefdfc,r2
+ dmulhu 0x7ffefdfc,r2
+ mul r1,r2,r3,r4
+ mulu r1,r2,r3,r4
+
+movbu_tests:
+ movbu (r5),r6
+ movbu r7,(r8)
+ movbu (sp),r7
+ movbu r8,(sp)
+ movbu (16,r1),r2
+ movbu r2,(16,r1)
+ movbu (16,sp),r2
+ movbu r2,(16,sp)
+ movbu (0x1ffeff,r1),r2
+ movbu r2,(0x1ffeff,r1)
+ movbu (0x1ffeff,sp),r2
+ movbu r2,(0x1ffeff,sp)
+ movbu (0x1ffeff),r2
+ movbu r2,(0x1ffeff)
+ movbu (0x7ffefdfc,r1),r2
+ movbu r2,(0x7ffefdfc,r1)
+ movbu (0x7ffefdfc,sp),r2
+ movbu r2,(0x7ffefdfc,sp)
+ movbu (0x7ffefdfc),r2
+ movbu r2,(0x7ffefdfc)
+
+movhu_tests:
+ movhu (r9),r10
+ movhu r11,(r12)
+ movhu (sp),r9
+ movhu r10,(sp)
+ movhu (16,r1),r2
+ movhu r2,(16,r1)
+ movhu (16,sp),r2
+ movhu r2,(16,sp)
+ movhu (0x1ffeff,r1),r2
+ movhu r2,(0x1ffeff,r1)
+ movhu (0x1ffeff,sp),r2
+ movhu r2,(0x1ffeff,sp)
+ movhu (0x1ffeff),r2
+ movhu r2,(0x1ffeff)
+ movhu (0x7ffefdfc,r1),r2
+ movhu r2,(0x7ffefdfc,r1)
+ movhu (0x7ffefdfc,sp),r2
+ movhu r2,(0x7ffefdfc,sp)
+ movhu (0x7ffefdfc),r2
+ movhu r2,(0x7ffefdfc)
+
+
+mac_tests:
+ mac r1,r2
+ macu r3,r4
+ macb r5,r6
+ macbu r7,r8
+ mach r9,r10
+ machu r11,r12
+ dmach r13,r14
+ dmachu r15,r14
+ mac 16,r1
+ macu 16,r1
+ macb 16,r1
+ macbu 16,r1
+ mach 16,r1
+ machu 16,r1
+ mac 0x1ffeff,r2
+ macu 0x1ffeff,r2
+ macb 0x1ffeff,r2
+ macbu 0x1ffeff,r2
+ mach 0x1ffeff,r2
+ machu 0x1ffeff,r2
+ mac 0x7ffefdfc,r2
+ macu 0x7ffefdfc,r2
+ macb 0x7ffefdfc,r2
+ macbu 0x7ffefdfc,r2
+ mach 0x7ffefdfc,r2
+ machu 0x7ffefdfc,r2
+ dmach 0x7ffefdfc,r2
+ dmachu 0x7ffefdfc,r2
+
+bit_tests:
+ bsch r1,r2
+ btst 16,r1
+ btst 0x1ffeff,r2
+ btst 0x7ffefdfc,r2
+
+
+
+dsp_add_tests:
+ add_add r4,r1,r2,r3
+ add_add r4,r1,2,r3
+ add_sub r4,r1,r2,r3
+ add_sub r4,r1,2,r3
+ add_cmp r4,r1,r2,r3
+ add_cmp r4,r1,2,r3
+ add_mov r4,r1,r2,r3
+ add_mov r4,r1,2,r3
+ add_asr r4,r1,r2,r3
+ add_asr r4,r1,2,r3
+ add_lsr r4,r1,r2,r3
+ add_lsr r4,r1,2,r3
+ add_asl r4,r1,r2,r3
+ add_asl r4,r1,2,r3
+ add_add 4,r1,r2,r3
+ add_add 4,r1,2,r3
+ add_sub 4,r1,r2,r3
+ add_sub 4,r1,2,r3
+ add_cmp 4,r1,r2,r3
+ add_cmp 4,r1,2,r3
+ add_mov 4,r1,r2,r3
+ add_mov 4,r1,2,r3
+ add_asr 4,r1,r2,r3
+ add_asr 4,r1,2,r3
+ add_lsr 4,r1,r2,r3
+ add_lsr 4,r1,2,r3
+ add_asl 4,r1,r2,r3
+ add_asl 4,r1,2,r3
+
+dsp_cmp_tests:
+ cmp_add r4,r1,r2,r3
+ cmp_add r4,r1,2,r3
+ cmp_sub r4,r1,r2,r3
+ cmp_sub r4,r1,2,r3
+ cmp_mov r4,r1,r2,r3
+ cmp_mov r4,r1,2,r3
+ cmp_asr r4,r1,r2,r3
+ cmp_asr r4,r1,2,r3
+ cmp_lsr r4,r1,r2,r3
+ cmp_lsr r4,r1,2,r3
+ cmp_asl r4,r1,r2,r3
+ cmp_asl r4,r1,2,r3
+ cmp_add 4,r1,r2,r3
+ cmp_add 4,r1,2,r3
+ cmp_sub 4,r1,r2,r3
+ cmp_sub 4,r1,2,r3
+ cmp_mov 4,r1,r2,r3
+ cmp_mov 4,r1,2,r3
+ cmp_asr 4,r1,r2,r3
+ cmp_asr 4,r1,2,r3
+ cmp_lsr 4,r1,r2,r3
+ cmp_lsr 4,r1,2,r3
+ cmp_asl 4,r1,r2,r3
+ cmp_asl 4,r1,2,r3
+
+dsp_sub_tests:
+ sub_add r4,r1,r2,r3
+ sub_add r4,r1,2,r3
+ sub_sub r4,r1,r2,r3
+ sub_sub r4,r1,2,r3
+ sub_cmp r4,r1,r2,r3
+ sub_cmp r4,r1,2,r3
+ sub_mov r4,r1,r2,r3
+ sub_mov r4,r1,2,r3
+ sub_asr r4,r1,r2,r3
+ sub_asr r4,r1,2,r3
+ sub_lsr r4,r1,r2,r3
+ sub_lsr r4,r1,2,r3
+ sub_asl r4,r1,r2,r3
+ sub_asl r4,r1,2,r3
+ sub_add 4,r1,r2,r3
+ sub_add 4,r1,2,r3
+ sub_sub 4,r1,r2,r3
+ sub_sub 4,r1,2,r3
+ sub_cmp 4,r1,r2,r3
+ sub_cmp 4,r1,2,r3
+ sub_mov 4,r1,r2,r3
+ sub_mov 4,r1,2,r3
+ sub_asr 4,r1,r2,r3
+ sub_asr 4,r1,2,r3
+ sub_lsr 4,r1,r2,r3
+ sub_lsr 4,r1,2,r3
+ sub_asl 4,r1,r2,r3
+ sub_asl 4,r1,2,r3
+
+dsp_mov_tests:
+ mov_add r4,r1,r2,r3
+ mov_add r4,r1,2,r3
+ mov_sub r4,r1,r2,r3
+ mov_sub r4,r1,2,r3
+ mov_cmp r4,r1,r2,r3
+ mov_cmp r4,r1,2,r3
+ mov_mov r4,r1,r2,r3
+ mov_mov r4,r1,2,r3
+ mov_asr r4,r1,r2,r3
+ mov_asr r4,r1,2,r3
+ mov_lsr r4,r1,r2,r3
+ mov_lsr r4,r1,2,r3
+ mov_asl r4,r1,r2,r3
+ mov_asl r4,r1,2,r3
+ mov_add 4,r1,r2,r3
+ mov_add 4,r1,2,r3
+ mov_sub 4,r1,r2,r3
+ mov_sub 4,r1,2,r3
+ mov_cmp 4,r1,r2,r3
+ mov_cmp 4,r1,2,r3
+ mov_mov 4,r1,r2,r3
+ mov_mov 4,r1,2,r3
+ mov_asr 4,r1,r2,r3
+ mov_asr 4,r1,2,r3
+ mov_lsr 4,r1,r2,r3
+ mov_lsr 4,r1,2,r3
+ mov_asl 4,r1,r2,r3
+ mov_asl 4,r1,2,r3
+
+dsp_logical_tests:
+ and_add r4,r1,r2,r3
+ and_add r4,r1,2,r3
+ and_sub r4,r1,r2,r3
+ and_sub r4,r1,2,r3
+ and_cmp r4,r1,r2,r3
+ and_cmp r4,r1,2,r3
+ and_mov r4,r1,r2,r3
+ and_mov r4,r1,2,r3
+ and_asr r4,r1,r2,r3
+ and_asr r4,r1,2,r3
+ and_lsr r4,r1,r2,r3
+ and_lsr r4,r1,2,r3
+ and_asl r4,r1,r2,r3
+ and_asl r4,r1,2,r3
+ xor_add r4,r1,r2,r3
+ xor_add r4,r1,2,r3
+ xor_sub r4,r1,r2,r3
+ xor_sub r4,r1,2,r3
+ xor_cmp r4,r1,r2,r3
+ xor_cmp r4,r1,2,r3
+ xor_mov r4,r1,r2,r3
+ xor_mov r4,r1,2,r3
+ xor_asr r4,r1,r2,r3
+ xor_asr r4,r1,2,r3
+ xor_lsr r4,r1,r2,r3
+ xor_lsr r4,r1,2,r3
+ xor_asl r4,r1,r2,r3
+ xor_asl r4,r1,2,r3
+ or_add r4,r1,r2,r3
+ or_add r4,r1,2,r3
+ or_sub r4,r1,r2,r3
+ or_sub r4,r1,2,r3
+ or_cmp r4,r1,r2,r3
+ or_cmp r4,r1,2,r3
+ or_mov r4,r1,r2,r3
+ or_mov r4,r1,2,r3
+ or_asr r4,r1,r2,r3
+ or_asr r4,r1,2,r3
+ or_lsr r4,r1,r2,r3
+ or_lsr r4,r1,2,r3
+ or_asl r4,r1,r2,r3
+ or_asl r4,r1,2,r3
+
+dsp_misc_tests:
+ dmach_add r4,r1,r2,r3
+ dmach_add r4,r1,2,r3
+ dmach_sub r4,r1,r2,r3
+ dmach_sub r4,r1,2,r3
+ dmach_cmp r4,r1,r2,r3
+ dmach_cmp r4,r1,2,r3
+ dmach_mov r4,r1,r2,r3
+ dmach_mov r4,r1,2,r3
+ dmach_asr r4,r1,r2,r3
+ dmach_asr r4,r1,2,r3
+ dmach_lsr r4,r1,r2,r3
+ dmach_lsr r4,r1,2,r3
+ dmach_asl r4,r1,r2,r3
+ dmach_asl r4,r1,2,r3
+ swhw_add r4,r1,r2,r3
+ swhw_add r4,r1,2,r3
+ swhw_sub r4,r1,r2,r3
+ swhw_sub r4,r1,2,r3
+ swhw_cmp r4,r1,r2,r3
+ swhw_cmp r4,r1,2,r3
+ swhw_mov r4,r1,r2,r3
+ swhw_mov r4,r1,2,r3
+ swhw_asr r4,r1,r2,r3
+ swhw_asr r4,r1,2,r3
+ swhw_lsr r4,r1,r2,r3
+ swhw_lsr r4,r1,2,r3
+ swhw_asl r4,r1,r2,r3
+ swhw_asl r4,r1,2,r3
+ sat16_add r4,r1,r2,r3
+ sat16_add r4,r1,2,r3
+ sat16_sub r4,r1,r2,r3
+ sat16_sub r4,r1,2,r3
+ sat16_cmp r4,r1,r2,r3
+ sat16_cmp r4,r1,2,r3
+ sat16_mov r4,r1,r2,r3
+ sat16_mov r4,r1,2,r3
+ sat16_asr r4,r1,r2,r3
+ sat16_asr r4,r1,2,r3
+ sat16_lsr r4,r1,r2,r3
+ sat16_lsr r4,r1,2,r3
+ sat16_asl r4,r1,r2,r3
+ sat16_asl r4,r1,2,r3
+
+autoincrement_tests:
+ mov (r1+),r2
+ mov r3,(r4+)
+ movhu (r6+),r7
+ movhu r8,(r9+)
+ mov (r1+,64),r2
+ mov r1,(r2+,64)
+ movhu (r1+,64),r2
+ movhu r1,(r2+,64)
+ mov (r1+,0x1ffef),r2
+ mov r1,(r2+,0x1ffef)
+ movhu (r1+,0x1ffef),r2
+ movhu r1,(r2+,0x1ffef)
+ mov (r1+,0x7ffefdfc),r2
+ mov r1,(r2+,0x7ffefdfc)
+ movhu (r1+,0x7ffefdfc),r2
+ movhu r1,(r2+,0x7ffefdfc)
+
+dsp_autoincrement_tests:
+ mov_llt (r1+,4),r2
+ mov_lgt (r1+,4),r2
+ mov_lge (r1+,4),r2
+ mov_lle (r1+,4),r2
+ mov_lcs (r1+,4),r2
+ mov_lhi (r1+,4),r2
+ mov_lcc (r1+,4),r2
+ mov_lls (r1+,4),r2
+ mov_leq (r1+,4),r2
+ mov_lne (r1+,4),r2
+ mov_lra (r1+,4),r2
diff --git a/sim/mn10300/am33.igen b/sim/mn10300/am33.igen
new file mode 100644
index 00000000000..31bbc730de5
--- /dev/null
+++ b/sim/mn10300/am33.igen
@@ -0,0 +1,8683 @@
+// Helper:
+//
+// Given an extended register number, translate it into an index into the
+// register array. This is necessary as the upper 8 extended registers are
+// actually synonyms for the d0-d3/a0-a3 registers.
+//
+//
+
+:function:::int:translate_rreg:int rreg
+{
+
+ /* The higher register numbers actually correspond to the
+ basic machine's address and data registers. */
+ if (rreg > 7 && rreg < 12)
+ return REG_A0 + rreg - 8;
+ else if (rreg > 11 && rreg < 16)
+ return REG_D0 + rreg - 12;
+ else
+ return REG_E0 + rreg;
+}
+
+:function:::int:translate_xreg:int xreg
+{
+ switch (xreg)
+ {
+ case 0:
+ return REG_SP;
+ case 1:
+ return REG_MDRQ;
+ case 2:
+ return REG_MCRH;
+ case 3:
+ return REG_MCRL;
+ case 4:
+ return REG_MCVF;
+ default:
+ abort ();
+ }
+}
+
+// 1111 0000 0010 00An; mov USP,An
+8.0xf0+4.0x2,00,2.AN0:D0m:::mov
+"mov"
+*am33
+{
+ PC = cia;
+ State.regs[REG_A0 + AN0] = State.regs[REG_USP];
+}
+
+
+// 1111 0000 0010 01An; mov SSP,An
+8.0xf0+4.0x2,01,2.AN0:D0n:::mov
+"mov"
+*am33
+{
+ PC = cia;
+ State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
+}
+
+
+// 1111 0000 0010 10An; mov MSP,An
+8.0xf0+4.0x2,10,2.AN0:D0o:::mov
+"mov"
+*am33
+{
+ PC = cia;
+ State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
+}
+
+
+// 1111 0000 0010 11An; mov PC,An
+8.0xf0+4.0x2,11,2.AN0:D0p:::mov
+"mov"
+*am33
+{
+ PC = cia;
+ State.regs[REG_A0 + AN0] = PC;
+}
+
+
+// 1111 0000 0011 Am00; mov Am,USP
+8.0xf0+4.0x3,2.AM1,00:D0q:::mov
+"mov"
+*am33
+{
+ PC = cia;
+ State.regs[REG_USP] = State.regs[REG_A0 + AM1];
+}
+
+// 1111 0000 0011 Am01; mov Am,SSP
+8.0xf0+4.0x3,2.AM1,01:D0r:::mov
+"mov"
+*am33
+{
+ PC = cia;
+ State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
+}
+
+// 1111 0000 0011 Am10; mov Am,MSP
+8.0xf0+4.0x3,2.AM1,10:D0s:::mov
+"mov"
+*am33
+{
+ PC = cia;
+ State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
+}
+
+
+// 1111 0000 1110 imm4; syscall
+8.0xf0+4.0xe,IMM4:D0t:::syscall
+"syscall"
+*am33
+{
+ unsigned int sp, next_pc;
+
+ PC = cia;
+ sp = State.regs[REG_SP];
+ next_pc = State.regs[REG_PC] + 2;
+ store_word (sp - 4, next_pc);
+ store_word (sp - 8, PSW);
+ State.regs[REG_PC] = 0x40000000 + IMM4 * 8;
+ nia = PC;
+}
+
+
+// 1111 0010 1110 11Dn; mov EPSW,Dn
+8.0xf2+4.0xe,11,2.DN0:D0u:::mov
+"mov"
+*am33
+{
+ PC = cia;
+ State.regs[REG_D0 + DN0] = PSW;
+}
+
+
+// 1111 0010 1111 Dm01; mov Dm,EPSW
+8.0xf2+4.0xf,2.DM1,01:D0v:::mov
+"mov"
+*am33
+{
+ PC = cia;
+ PSW = State.regs[REG_D0 + DM1];
+}
+
+// 1111 0101 00Am Rn; mov Am,Rn
+8.0xf5+00,2.AM1,4.RN0:D0w:::mov
+"mov"
+*am33
+{
+ int destreg = translate_rreg (SD_, RN0);
+
+ PC = cia;
+ State.regs[destreg] = State.regs[REG_A0 + AM1];
+}
+
+// 1111 0101 01Dm Rn; mov Dm,Rn
+8.0xf5+01,2.DM1,4.RN0:D0x:::mov
+"mov"
+*am33
+{
+ int destreg = translate_rreg (SD_, RN0);
+
+ PC = cia;
+ State.regs[destreg] = State.regs[REG_D0 + DM1];
+}
+
+// 1111 0101 10Rm An; mov Rm,An
+8.0xf5+10,4.RM1,2.AN0:D0y:::mov
+"mov"
+*am33
+{
+ int destreg = translate_rreg (SD_, RM1);
+
+ PC = cia;
+ State.regs[REG_A0 + AN0] = State.regs[destreg];
+}
+
+// 1111 0101 11Rm Dn; mov Rm,Dn
+8.0xf5+11,4.RM1,2.DN0:D0z:::mov
+"mov"
+*am33
+{
+ int destreg = translate_rreg (SD_, RM1);
+
+ PC = cia;
+ State.regs[REG_D0 + DN0] = State.regs[destreg];
+}
+
+
+// 1111 1000 1100 1110 regs....; movm (USP),regs
+8.0xf8+8.0xce+8.REGS:D1a:::movm
+"movm"
+*am33
+{
+ unsigned long usp = State.regs[REG_USP];
+ unsigned long mask;
+
+ PC = cia;
+ mask = REGS;
+
+ if (mask & 0x8)
+ {
+ usp += 4;
+ State.regs[REG_LAR] = load_word (usp);
+ usp += 4;
+ State.regs[REG_LIR] = load_word (usp);
+ usp += 4;
+ State.regs[REG_MDR] = load_word (usp);
+ usp += 4;
+ State.regs[REG_A0 + 1] = load_word (usp);
+ usp += 4;
+ State.regs[REG_A0] = load_word (usp);
+ usp += 4;
+ State.regs[REG_D0 + 1] = load_word (usp);
+ usp += 4;
+ State.regs[REG_D0] = load_word (usp);
+ usp += 4;
+ }
+
+ if (mask & 0x10)
+ {
+ State.regs[REG_A0 + 3] = load_word (usp);
+ usp += 4;
+ }
+
+ if (mask & 0x20)
+ {
+ State.regs[REG_A0 + 2] = load_word (usp);
+ usp += 4;
+ }
+
+ if (mask & 0x40)
+ {
+ State.regs[REG_D0 + 3] = load_word (usp);
+ usp += 4;
+ }
+
+ if (mask & 0x80)
+ {
+ State.regs[REG_D0 + 2] = load_word (usp);
+ usp += 4;
+ }
+
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
+ {
+ if (mask & 0x1)
+ {
+ /* Need to restore MDQR, MCRH, MCRL, and MCVF */
+ usp += 16;
+ State.regs[REG_E0 + 1] = load_word (usp);
+ usp += 4;
+ State.regs[REG_E0 + 0] = load_word (usp);
+ usp += 4;
+ }
+
+ if (mask & 0x2)
+ {
+ State.regs[REG_E0 + 7] = load_word (usp);
+ usp += 4;
+ State.regs[REG_E0 + 6] = load_word (usp);
+ usp += 4;
+ State.regs[REG_E0 + 5] = load_word (usp);
+ usp += 4;
+ State.regs[REG_E0 + 4] = load_word (usp);
+ usp += 4;
+ }
+
+ if (mask & 0x4)
+ {
+ State.regs[REG_E0 + 3] = load_word (usp);
+ usp += 4;
+ State.regs[REG_E0 + 2] = load_word (usp);
+ usp += 4;
+ }
+ }
+
+ /* And make sure to update the stack pointer. */
+ State.regs[REG_USP] = usp;
+}
+
+// 1111 1000 1100 1111 regs....; movm (USP),regs
+8.0xf8+8.0xcf+8.REGS:D1b:::movm
+"movm"
+*am33
+{
+ unsigned long usp = State.regs[REG_USP];
+ unsigned long mask;
+
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
+ {
+ if (mask & 0x4)
+ {
+ usp -= 4;
+ store_word (usp, State.regs[REG_E0 + 2]);
+ usp -= 4;
+ store_word (usp, State.regs[REG_E0 + 3]);
+ }
+
+ if (mask & 0x2)
+ {
+ usp -= 4;
+ store_word (usp, State.regs[REG_E0 + 4]);
+ usp -= 4;
+ store_word (usp, State.regs[REG_E0 + 5]);
+ usp -= 4;
+ store_word (usp, State.regs[REG_E0 + 6]);
+ usp -= 4;
+ store_word (usp, State.regs[REG_E0 + 7]);
+ }
+
+ if (mask & 0x1)
+ {
+ usp -= 4;
+ store_word (usp, State.regs[REG_E0 + 0]);
+ usp -= 4;
+ store_word (usp, State.regs[REG_E0 + 1]);
+ usp -= 16;
+ /* Need to save MDQR, MCRH, MCRL, and MCVF */
+ }
+ }
+
+ if (mask & 0x80)
+ {
+ usp -= 4;
+ store_word (usp, State.regs[REG_D0 + 2]);
+ }
+
+ if (mask & 0x40)
+ {
+ usp -= 4;
+ store_word (usp, State.regs[REG_D0 + 3]);
+ }
+
+ if (mask & 0x20)
+ {
+ usp -= 4;
+ store_word (usp, State.regs[REG_A0 + 2]);
+ }
+
+ if (mask & 0x10)
+ {
+ usp -= 4;
+ store_word (usp, State.regs[REG_A0 + 3]);
+ }
+
+ if (mask & 0x8)
+ {
+ usp -= 4;
+ store_word (usp, State.regs[REG_D0]);
+ usp -= 4;
+ store_word (usp, State.regs[REG_D0 + 1]);
+ usp -= 4;
+ store_word (usp, State.regs[REG_A0]);
+ usp -= 4;
+ store_word (usp, State.regs[REG_A0 + 1]);
+ usp -= 4;
+ store_word (usp, State.regs[REG_MDR]);
+ usp -= 4;
+ store_word (usp, State.regs[REG_LIR]);
+ usp -= 4;
+ store_word (usp, State.regs[REG_LAR]);
+ usp -= 4;
+ }
+
+ /* And make sure to update the stack pointer. */
+ State.regs[REG_USP] = usp;
+}
+
+// 1111 1100 1111 1100 imm32...; and imm32,EPSW
+8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
+"and"
+*am33
+{
+ PC = cia;
+ PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
+}
+
+// 1111 1100 1111 1101 imm32...; or imm32,EPSW
+8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
+"or"
+*am33
+{
+ PC = cia;
+ PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
+}
+
+// 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn)
+8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
+"mov"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = State.regs[srcreg];
+}
+
+// 1111 1001 0001 1000 Rn Rn; ext Rn
+8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
+"mov"
+*am33
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN0);
+ if (State.regs[srcreg] & 0x80000000)
+ State.regs[REG_MDR] = -1;
+ else
+ State.regs[REG_MDR] = 0;
+}
+
+// 1111 1001 0010 1000 Rm Rn; extb Rm,Rn
+8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
+"extb"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = EXTEND8 (State.regs[srcreg]);
+}
+
+// 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn
+8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
+"extbu"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = State.regs[srcreg] & 0xff;
+}
+
+// 1111 1001 0100 1000 Rm Rn; exth Rm,Rn
+8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
+"exth"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = EXTEND16 (State.regs[srcreg]);
+}
+
+// 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn
+8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
+"exthu"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = State.regs[srcreg] & 0xffff;
+}
+
+// 1111 1001 0110 1000 Rn Rn; clr Rn
+8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
+"clr"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = 0;
+ PSW |= PSW_Z;
+ PSW &= ~(PSW_V | PSW_C | PSW_N);
+}
+
+// 1111 1001 0111 1000 Rm Rn; add Rm,Rn
+8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
+"add"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ genericAdd (State.regs[srcreg], dstreg);
+}
+
+// 1111 1001 1000 1000 Rm Rn; addc Rm,Rn
+8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
+"addc"
+*am33
+{
+ int srcreg, dstreg;
+ int z, c, n, v;
+ unsigned long reg1, reg2, sum;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ reg1 = State.regs[srcreg];
+ reg2 = State.regs[dstreg];
+ sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
+ State.regs[dstreg] = sum;
+
+ z = ((PSW & PSW_Z) != 0) && (sum == 0);
+ n = (sum & 0x80000000);
+ c = (sum < reg1) || (sum < reg2);
+ v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
+ && (reg2 & 0x80000000) != (sum & 0x80000000));
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
+ | (c ? PSW_C : 0) | (v ? PSW_V : 0));
+}
+
+// 1111 1001 1001 1000 Rm Rn; sub Rm,Rn
+8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
+"sub"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ genericSub (State.regs[srcreg], dstreg);
+}
+
+// 1111 1001 1010 1000 Rm Rn; subc Rm,Rn
+8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
+"subc"
+*am33
+{
+ int srcreg, dstreg;
+ int z, c, n, v;
+ unsigned long reg1, reg2, difference;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ reg1 = State.regs[srcreg];
+ reg2 = State.regs[dstreg];
+ difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
+ State.regs[dstreg] = difference;
+
+ z = ((PSW & PSW_Z) != 0) && (difference == 0);
+ n = (difference & 0x80000000);
+ c = (reg1 > reg2);
+ v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
+ && (reg2 & 0x80000000) != (difference & 0x80000000));
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
+ | (c ? PSW_C : 0) | (v ? PSW_V : 0));
+}
+
+// 1111 1001 1011 1000 Rn Rn; inc Rn
+8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
+"inc"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ genericAdd (1, dstreg);
+}
+
+// 1111 1001 1101 1000 Rn Rn; inc Rn
+8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
+"inc4"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] += 4;
+}
+
+// 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
+8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
+"cmp"
+*am33
+{
+ int srcreg1, srcreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RN0);
+ srcreg2 = translate_rreg (SD_, RM2);
+ genericCmp (State.regs[srcreg2], State.regs[srcreg1]);
+}
+
+// 1111 1001 1110 1000 XRm Rn; mov XRm,Rn
+8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
+"mov"
+*am33
+{
+ int dstreg, srcreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ srcreg = translate_xreg (SD_, XRM2);
+
+ State.regs[dstreg] = State.regs[srcreg];
+}
+
+// 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
+8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
+"mov"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_xreg (SD_, XRN0);
+
+ State.regs[dstreg] = State.regs[srcreg];
+}
+
+// 1111 1001 0000 1001 Rm Rn; and Rm,Rn
+8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
+"and"
+*am33
+{
+ int srcreg, dstreg;
+ int z, n;
+
+ PC = cia;
+
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] &= State.regs[srcreg];
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1001 0001 1001 Rm Rn; or Rm,Rn
+8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
+"or"
+*am33
+{
+ int srcreg, dstreg;
+ int z, n;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] |= State.regs[srcreg];
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1001 0010 1001 Rm Rn; xor Rm,Rn
+8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
+"xor"
+*am33
+{
+ int srcreg, dstreg;
+ int z, n;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] ^= State.regs[srcreg];
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1001 0011 1001 Rn Rn; not Rn
+8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
+"not"
+*am33
+{
+ int dstreg;
+ int z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] = ~State.regs[dstreg];
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1001 0100 1001 Rm Rn; asr Rm,Rn
+8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
+"asr"
+*am33
+{
+ int srcreg, dstreg;
+ long temp;
+ int c, z, n;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = State.regs[dstreg];
+ c = temp & 1;
+ temp >>= State.regs[srcreg];
+ State.regs[dstreg] = temp;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
+}
+
+// 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn
+8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
+"lsr"
+*am33
+{
+ int srcreg, dstreg;
+ int z, n, c;
+
+ PC = cia;
+
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ c = State.regs[dstreg] & 1;
+ State.regs[dstreg] >>= State.regs[srcreg];
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
+}
+
+// 1111 1001 0110 1001 Rm Rn; asl Rm,Rn
+8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
+"asl"
+*am33
+{
+ int srcreg, dstreg;
+ int z, n;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] <<= State.regs[srcreg];
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1001 0111 1001 Rn Rn; asl2 Rn
+8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
+"asl2"
+*am33
+{
+ int dstreg;
+ int n, z;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] <<= 2;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1001 1000 1001 Rn Rn; ror Rn
+8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
+"ror"
+*am33
+{
+ int dstreg;
+ int c, n, z;
+ unsigned long value;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ value = State.regs[dstreg];
+ c = (value & 0x1);
+
+ value >>= 1;
+ value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
+ State.regs[dstreg] = value;
+ z = (value == 0);
+ n = (value & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
+}
+
+// 1111 1001 1001 1001 Rn Rn; rol Rn
+8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
+"rol"
+*am33
+{
+ int dstreg;
+ int c, n, z;
+ unsigned long value;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ value = State.regs[dstreg];
+ c = (value & 0x80000000) ? 1 : 0;
+
+ value <<= 1;
+ value |= ((PSW & PSW_C) != 0);
+ State.regs[dstreg] = value;
+ z = (value == 0);
+ n = (value & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
+}
+
+// 1111 1001 1010 1001 Rm Rn; mul Rm,Rn
+8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
+"mul"
+*am33
+{
+ int srcreg, dstreg;
+ unsigned long long temp;
+ int n, z;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = ((signed64)(signed32)State.regs[dstreg]
+ * (signed64)(signed32)State.regs[srcreg]);
+ State.regs[dstreg] = temp & 0xffffffff;
+ State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn
+8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
+"mulu"
+*am33
+{
+ int srcreg, dstreg;
+ unsigned long long temp;
+ int n, z;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = ((unsigned64)State.regs[dstreg]
+ * (unsigned64)State.regs[srcreg]);
+ State.regs[dstreg] = temp & 0xffffffff;
+ State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1001 1100 1001 Rm Rn; div Rm,Rn
+8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
+"div"
+*am33
+{
+ int srcreg, dstreg;
+ long long temp;
+ int n, z;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = State.regs[REG_MDR];
+ temp <<= 32;
+ temp |= State.regs[dstreg];
+ State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg];
+ temp /= (signed32)State.regs[srcreg];
+ State.regs[dstreg] = temp & 0xffffffff;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1001 1101 1001 Rm Rn; divu Rm,Rn
+8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
+"divu"
+*am33
+{
+ int srcreg, dstreg;
+ unsigned long long temp;
+ int n, z;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = State.regs[REG_MDR];
+ temp <<= 32;
+ temp |= State.regs[dstreg];
+ State.regs[REG_MDR] = temp % State.regs[srcreg];
+ temp /= State.regs[srcreg];
+ State.regs[dstreg] = temp & 0xffffffff;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+
+// 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn
+8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
+"mov"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+}
+
+// 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn)
+8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
+"mov"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_word (State.regs[dstreg], State.regs[srcreg]);
+}
+
+// 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn
+8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
+"movbu"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_byte (State.regs[srcreg]);
+}
+
+// 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn)
+8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
+"movbu"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_byte (State.regs[dstreg], State.regs[srcreg]);
+}
+
+// 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn
+8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
+"movhu"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (State.regs[srcreg]);
+}
+
+// 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn)
+8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
+"movhu"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_half (State.regs[dstreg], State.regs[srcreg]);
+}
+
+// 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn
+8.0xf9+8.0x6a+4.RN2,4.RM0!RN2:D1y:::mov
+"mov"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += 4;
+}
+
+// 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+)
+8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
+"mov"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_word (State.regs[dstreg], State.regs[srcreg]);
+ State.regs[dstreg] += 4;
+}
+
+// 1111 1001 1000 1010 Rn 0000; mov (sp),Rn
+8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
+"mov"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (State.regs[REG_SP]);
+}
+
+// 1111 1001 1001 1010 Rm 0000; mov Rm, (sp)
+8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
+"mov"
+*am33
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_word (State.regs[REG_SP], State.regs[srcreg]);
+}
+
+// 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn
+8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
+"movbu"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_byte (State.regs[REG_SP]);
+}
+
+// 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp)
+8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
+"movbu"
+*am33
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_byte (State.regs[REG_SP], State.regs[srcreg]);
+}
+
+// 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn
+8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
+"movhu"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (State.regs[REG_SP]);
+}
+
+// 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp)
+8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
+"movhu"
+*am33
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_half (State.regs[REG_SP], State.regs[srcreg]);
+}
+
+// 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn
+8.0xf9+8.0xea+4.RN2,4.RM0!RN2:D1y:::movhu
+"movhu"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (State.regs[srcreg]);
+ State.regs[srcreg] += 2;
+}
+
+// 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+)
+8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
+"movhu"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_half (State.regs[dstreg], State.regs[srcreg]);
+ State.regs[dstreg] += 2;
+}
+
+
+// 1111 1001 0000 1011 Rm Rn; mac Rm,Rn
+8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
+"mac"
+*am33
+{
+ int srcreg1, srcreg2;
+ long long temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+
+ temp = ((signed64)(signed32)State.regs[srcreg2]
+ * (signed64)(signed32)State.regs[srcreg1]);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1001 0001 1011 Rm Rn; macu Rm,Rn
+8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
+"macu"
+*am33
+{
+ int srcreg1, srcreg2;
+ unsigned long long temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+
+ temp = ((unsigned64)State.regs[srcreg2]
+ * (unsigned64)State.regs[srcreg1]);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1001 0010 1011 Rm Rn; macb Rm,Rn
+8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
+"macb"
+*am33
+{
+ int srcreg1, srcreg2;
+ long temp, sum;
+ int v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+
+ temp = ((signed32)(signed8)(State.regs[srcreg2] & 0xff)
+ * (signed32)(signed8)(State.regs[srcreg1] & 0xff));
+ sum = State.regs[REG_MCRL] + temp;
+ v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRL] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1001 0011 1011 Rm Rn; macbu Rm,Rn
+8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
+"macbu"
+*am33
+{
+ int srcreg1, srcreg2;
+ long long temp, sum;
+ int v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+
+ temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
+ * (unsigned32)(State.regs[srcreg1] & 0xff));
+ sum = State.regs[REG_MCRL] + temp;
+ v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRL] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1001 0100 1011 Rm Rn; mach Rm,Rn
+8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
+"mach"
+*am33
+{
+ int srcreg1, srcreg2;
+ long long temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+
+ temp = ((unsigned64)(signed16)(State.regs[srcreg2] & 0xffff)
+ * (unsigned64)(signed16)(State.regs[srcreg1] & 0xffff));
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1001 0101 1011 Rm Rn; machu Rm,Rn
+8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
+"machu"
+*am33
+{
+ int srcreg1, srcreg2;
+ long long temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+
+ temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
+ * (unsigned64)(State.regs[srcreg1] & 0xffff));
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1001 0110 1011 Rm Rn; dmach Rm,Rn
+8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
+"dmach"
+*am33
+{
+ int srcreg1, srcreg2;
+ long temp, temp2, sum;
+ int v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+
+ temp = ((signed32)(signed16)(State.regs[srcreg2] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[srcreg2] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+ v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRL] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1001 0111 1011 Rm Rn; dmachu Rm,Rn
+8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
+"dmachu"
+*am33
+{
+ int srcreg1, srcreg2;
+ unsigned long temp, temp2, sum;
+ int v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+
+ temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
+ * (unsigned32)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+ v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRL] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1001 1000 1011 Rm Rn; dmulh Rm,Rn
+8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
+"dmulh"
+*am33
+{
+ int srcreg, dstreg;
+ long temp;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg] & 0xffff));
+ State.regs[REG_MDRQ] = temp;
+ temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[srcreg] >>16) & 0xffff));
+ State.regs[dstreg] = temp;
+}
+
+// 1111 1001 1001 1011 Rm Rn; dmulhu Rm,Rn
+8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
+"dmachu"
+*am33
+{
+ int srcreg, dstreg;
+ unsigned long temp;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
+ * (unsigned32)(State.regs[srcreg] & 0xffff));
+ State.regs[REG_MDRQ] = temp;
+ temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
+ * (unsigned32)((State.regs[srcreg] >>16) & 0xffff));
+ State.regs[dstreg] = temp;
+}
+
+// 1111 1001 1010 1011 Rm Rn; sat16 Rm,Rn
+8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
+"sat16"
+*am33
+{
+ int srcreg, dstreg;
+ int value, z, n;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ value = State.regs[srcreg];
+
+ if (value >= 0x7fff)
+ State.regs[dstreg] = 0x7fff;
+ else if (value <= 0xffff8000)
+ State.regs[dstreg] = 0xffff8000;
+ else
+ State.regs[dstreg] = value;
+
+ n = (State.regs[dstreg] & 0x8000) != 0;
+ z = (State.regs[dstreg] == 0);
+ PSW &= ~(PSW_Z | PSW_N);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1001 1011 1011 Rm Rn; mcste Rm,Rn
+8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
+"mcste"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ PSW &= ~(PSW_V | PSW_C);
+ PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
+
+ /* 32bit saturation. */
+ if (State.regs[srcreg] == 0x20)
+ {
+ long long tmp;
+
+ tmp = State.regs[REG_MCRH];
+ tmp <<= 32;
+ tmp += State.regs[REG_MCRL];
+
+ if (tmp > 0x7fffffff)
+ State.regs[dstreg] = 0x7fffffff;
+ else if (tmp < 0xffffffff80000000LL)
+ State.regs[dstreg] = 0x80000000;
+ else
+ State.regs[dstreg] = tmp;
+ }
+ /* 16bit saturation */
+ else if (State.regs[srcreg] == 0x10)
+ {
+ long long tmp;
+
+ tmp = State.regs[REG_MCRH];
+ tmp <<= 32;
+ tmp += State.regs[REG_MCRL];
+
+ if (tmp > 0x7fff)
+ State.regs[dstreg] = 0x7fff;
+ else if (tmp < 0xffffffffffff8000LL)
+ State.regs[dstreg] = 0x8000;
+ else
+ State.regs[dstreg] = tmp;
+ }
+ /* 8 bit saturation */
+ else if (State.regs[srcreg] == 0x8)
+ {
+ long long tmp;
+
+ tmp = State.regs[REG_MCRH];
+ tmp <<= 32;
+ tmp += State.regs[REG_MCRL];
+
+ if (tmp > 0x7f)
+ State.regs[dstreg] = 0x7f;
+ else if (tmp < 0xffffffffffffff80LL)
+ State.regs[dstreg] = 0x80;
+ else
+ State.regs[dstreg] = tmp;
+ }
+ /* 9 bit saturation */
+ else if (State.regs[srcreg] == 0x9)
+ {
+ long long tmp;
+
+ tmp = State.regs[REG_MCRH];
+ tmp <<= 32;
+ tmp += State.regs[REG_MCRL];
+
+ if (tmp > 0x80)
+ State.regs[dstreg] = 0x80;
+ else if (tmp < 0xffffffffffffff81LL)
+ State.regs[dstreg] = 0x81;
+ else
+ State.regs[dstreg] = tmp;
+ }
+ /* 9 bit saturation */
+ else if (State.regs[srcreg] == 0x30)
+ {
+ long long tmp;
+
+ tmp = State.regs[REG_MCRH];
+ tmp <<= 32;
+ tmp += State.regs[REG_MCRL];
+
+ if (tmp > 0x7fffffffffffLL)
+ tmp = 0x7fffffffffffLL;
+ else if (tmp < 0xffff800000000000LL)
+ tmp = 0xffff800000000000LL;
+
+ tmp >>= 16;
+ State.regs[dstreg] = tmp;
+ }
+}
+
+// 1111 1001 1100 1011 Rm Rn; swap Rm,Rn
+8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
+"swap"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24)
+ | (((State.regs[srcreg] >> 8) & 0xff) << 16)
+ | (((State.regs[srcreg] >> 16) & 0xff) << 8)
+ | ((State.regs[srcreg] >> 24) & 0xff));
+}
+
+// 1111 1101 1101 1011 Rm Rn; swaph Rm,Rn
+8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
+"swaph"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8)
+ | ((State.regs[srcreg] >> 8) & 0xff)
+ | (((State.regs[srcreg] >> 16) & 0xff) << 24)
+ | (((State.regs[srcreg] >> 24) & 0xff) << 16));
+}
+
+// 1111 1001 1110 1011 Rm Rn; swhw Rm,Rn
+8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
+"swhw"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16)
+ | ((State.regs[srcreg] >> 16) & 0xffff));
+}
+
+// 1111 1001 1111 1011 Rm Rn; bsch Rm,Rn
+8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
+"bsch"
+*am33
+{
+ int temp, c, i;
+ int srcreg, dstreg;
+ int start;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = State.regs[srcreg];
+ start = (State.regs[dstreg] & 0x1f) - 1;
+ if (start == -1)
+ start = 31;
+
+ for (i = start; i >= 0; i--)
+ {
+ if (temp & (1 << i))
+ {
+ c = 1;
+ State.regs[dstreg] = i;
+ break;
+ }
+ }
+
+ if (i < 0)
+ {
+ c = 0;
+ State.regs[dstreg] = 0;
+ }
+ PSW &= ~(PSW_C);
+ PSW |= (c ? PSW_C : 0);
+}
+
+
+// 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn
+8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
+"mov"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = EXTEND8 (IMM8);
+}
+
+// 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn
+8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
+"movu"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = IMM8 & 0xff;
+}
+
+// 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn
+8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
+"add"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ genericAdd (EXTEND8 (IMM8), dstreg);
+}
+
+// 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn
+8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
+"addc"
+*am33
+{
+ int dstreg, imm;
+ int z, c, n, v;
+ unsigned long reg1, reg2, sum;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ imm = EXTEND8 (IMM8);
+ reg2 = State.regs[dstreg];
+ sum = imm + reg2 + ((PSW & PSW_C) != 0);
+ State.regs[dstreg] = sum;
+
+ z = ((PSW & PSW_Z) != 0) && (sum == 0);
+ n = (sum & 0x80000000);
+ c = (sum < imm) || (sum < reg2);
+ v = ((reg2 & 0x80000000) == (imm & 0x80000000)
+ && (reg2 & 0x80000000) != (sum & 0x80000000));
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
+ | (c ? PSW_C : 0) | (v ? PSW_V : 0));
+}
+
+// 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn
+8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
+"sub"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ genericSub (EXTEND8 (IMM8), dstreg);
+}
+
+// 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn
+8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
+"subc"
+*am33
+{
+ int imm, dstreg;
+ int z, c, n, v;
+ unsigned long reg1, reg2, difference;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ imm = EXTEND8 (IMM8);
+ reg2 = State.regs[dstreg];
+ difference = reg2 - imm - ((PSW & PSW_C) != 0);
+ State.regs[dstreg] = difference;
+
+ z = ((PSW & PSW_Z) != 0) && (difference == 0);
+ n = (difference & 0x80000000);
+ c = (imm > reg2);
+ v = ((reg2 & 0x80000000) == (imm & 0x80000000)
+ && (reg2 & 0x80000000) != (difference & 0x80000000));
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
+ | (c ? PSW_C : 0) | (v ? PSW_V : 0));
+}
+
+// 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn
+8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
+"cmp"
+*am33
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN0);
+ genericCmp (EXTEND8 (IMM8), State.regs[srcreg]);
+}
+
+// 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn
+8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
+"mov"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_xreg (SD_, XRN0);
+
+ State.regs[dstreg] = IMM8;
+}
+
+// 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
+8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
+"and"
+*am33
+{
+ int dstreg;
+ int z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] &= (IMM8 & 0xff);
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn
+8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
+"or"
+*am33
+{
+ int dstreg;
+ int z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] |= (IMM8 & 0xff);
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn
+8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
+"xor"
+*am33
+{
+ int dstreg;
+ int z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] ^= (IMM8 & 0xff);
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn
+8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
+"asr"
+*am33
+{
+ int dstreg;
+ long temp;
+ int c, z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = State.regs[dstreg];
+ c = temp & 1;
+ temp >>= (IMM8 & 0xff);
+ State.regs[dstreg] = temp;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
+}
+
+// 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn
+8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
+"lsr"
+*am33
+{
+ int dstreg;
+ int z, n, c;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ c = State.regs[dstreg] & 1;
+ State.regs[dstreg] >>= (IMM8 & 0xff);
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
+}
+
+// 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn
+8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
+"asl"
+*am33
+{
+ int srcreg, dstreg;
+ int z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] <<= (IMM8 & 0xff);
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn
+8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
+"mul"
+*am33
+{
+ int dstreg;
+ unsigned long long temp;
+ int z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = ((signed64)(signed32)State.regs[dstreg]
+ * (signed64)(signed32)EXTEND8 (IMM8));
+ State.regs[dstreg] = temp & 0xffffffff;
+ State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn
+8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
+"mulu"
+*am33
+{
+ int dstreg;
+ unsigned long long temp;
+ int z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = ((unsigned64)State.regs[dstreg]
+ * (unsigned64)(IMM8 & 0xff));
+ State.regs[dstreg] = temp & 0xffffffff;
+ State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn
+8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
+"btst"
+*am33
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ genericBtst(IMM8, State.regs[srcreg]);
+}
+
+// 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn
+8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
+"mov"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
+}
+
+// 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
+8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
+"mov"
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
+}
+
+// 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
+8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
+"movbu"
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8));
+}
+
+// 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
+8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
+"movbu"
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
+}
+
+// 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
+8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
+"movhu"
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
+}
+
+// 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
+8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
+"movhu"
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
+}
+
+// 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn
+8.0xfb+8.0x6a+4.RN2,4.RM0!RN2+8.IMM8:D2y:::mov
+"mov"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND8 (IMM8);
+}
+
+// 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+)
+8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
+"mov"
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_word (State.regs[dstreg], State.regs[srcreg]);
+ State.regs[dstreg] += EXTEND8 (IMM8);
+}
+
+
+// 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
+8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
+"mov"
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (State.regs[REG_SP] + EXTEND8 (IMM8));
+}
+
+// 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,Rn)
+8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
+"mov"
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_word (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
+}
+
+// 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
+8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
+"movbu"
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_byte (State.regs[REG_SP] + EXTEND8 (IMM8));
+}
+
+// 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(sp,Rn)
+8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
+"movbu"
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_byte (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
+}
+
+// 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
+8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
+"movhu"
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (State.regs[REG_SP] + EXTEND8 (IMM8));
+}
+
+// 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
+8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
+"movhu"
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_half (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
+}
+
+// 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn
+8.0xfb+8.0xea+4.RN2,4.RM0!RN2+8.IMM8:D2y:::movhu
+"movhu"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND8 (IMM8);
+}
+
+// 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+)
+8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
+"movhu"
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_half (State.regs[dstreg], State.regs[srcreg]);
+ State.regs[dstreg] += EXTEND8 (IMM8);
+}
+
+
+// 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn
+8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
+"mac"
+{
+ int srcreg;
+ long long temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN2);
+
+ temp = ((signed64)(signed32)EXTEND8 (IMM8)
+ * (signed64)(signed32)State.regs[srcreg]);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn
+8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
+"macu"
+{
+ int srcreg;
+ long long temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN2);
+
+ temp = ((unsigned64) (IMM8)
+ * (unsigned64)State.regs[srcreg]);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn
+8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
+"macb"
+{
+ int srcreg;
+ long long temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN2);
+
+ temp = ((signed64)(signed8)EXTEND8 (IMM8)
+ * (signed64)(signed8)State.regs[srcreg] & 0xff);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn
+8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
+"macbu"
+{
+ int srcreg;
+ long long temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN2);
+
+ temp = ((unsigned64) (IMM8)
+ * (unsigned64)State.regs[srcreg] & 0xff);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn
+8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
+"mach"
+{
+ int srcreg;
+ long long temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN2);
+
+ temp = ((signed64)(signed16)EXTEND8 (IMM8)
+ * (signed64)(signed16)State.regs[srcreg] & 0xffff);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn
+8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
+"machu"
+{
+ int srcreg;
+ long long temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN2);
+
+ temp = ((unsigned64) (IMM8)
+ * (unsigned64)State.regs[srcreg] & 0xffff);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1011 1011 1011 Rn Rn IMM8; mcste imm8,Rn
+8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
+"mcste"
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ PSW &= ~(PSW_V | PSW_C);
+ PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
+
+ /* 32bit saturation. */
+ if (IMM8 == 0x20)
+ {
+ long long tmp;
+
+ tmp = State.regs[REG_MCRH];
+ tmp <<= 32;
+ tmp += State.regs[REG_MCRL];
+
+ if (tmp > 0x7fffffff)
+ State.regs[dstreg] = 0x7fffffff;
+ else if (tmp < 0xffffffff80000000LL)
+ State.regs[dstreg] = 0x80000000;
+ else
+ State.regs[dstreg] = tmp;
+ }
+ /* 16bit saturation */
+ else if (IMM8 == 0x10)
+ {
+ long long tmp;
+
+ tmp = State.regs[REG_MCRH];
+ tmp <<= 32;
+ tmp += State.regs[REG_MCRL];
+
+ if (tmp > 0x7fff)
+ State.regs[dstreg] = 0x7fff;
+ else if (tmp < 0xffffffffffff8000LL)
+ State.regs[dstreg] = 0x8000;
+ else
+ State.regs[dstreg] = tmp;
+ }
+ /* 8 bit saturation */
+ else if (IMM8 == 0x8)
+ {
+ long long tmp;
+
+ tmp = State.regs[REG_MCRH];
+ tmp <<= 32;
+ tmp += State.regs[REG_MCRL];
+
+ if (tmp > 0x7f)
+ State.regs[dstreg] = 0x7f;
+ else if (tmp < 0xffffffffffffff80LL)
+ State.regs[dstreg] = 0x80;
+ else
+ State.regs[dstreg] = tmp;
+ }
+ /* 9 bit saturation */
+ else if (IMM8 == 0x9)
+ {
+ long long tmp;
+
+ tmp = State.regs[REG_MCRH];
+ tmp <<= 32;
+ tmp += State.regs[REG_MCRL];
+
+ if (tmp > 0x80)
+ State.regs[dstreg] = 0x80;
+ else if (tmp < 0xffffffffffffff81LL)
+ State.regs[dstreg] = 0x81;
+ else
+ State.regs[dstreg] = tmp;
+ }
+ /* 9 bit saturation */
+ else if (IMM8 == 0x30)
+ {
+ long long tmp;
+
+ tmp = State.regs[REG_MCRH];
+ tmp <<= 32;
+ tmp += State.regs[REG_MCRL];
+
+ if (tmp > 0x7fffffffffffLL)
+ tmp = 0x7fffffffffffLL;
+ else if (tmp < 0xffff800000000000LL)
+ tmp = 0xffff800000000000LL;
+
+ tmp >>= 16;
+ State.regs[dstreg] = tmp;
+ }
+}
+
+// 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd
+8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
+"add"
+*am33
+{
+ int z, c, n, v;
+ unsigned long sum, source1, source2;
+ int srcreg1, srcreg2, dstreg;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ source1 = State.regs[srcreg1];
+ source2 = State.regs[srcreg2];
+ sum = source1 + source2;
+ State.regs[dstreg] = sum;
+
+ z = (sum == 0);
+ n = (sum & 0x80000000);
+ c = (sum < source1) || (sum < source2);
+ v = ((source1 & 0x80000000) == (source2 & 0x80000000)
+ && (source1 & 0x80000000) != (sum & 0x80000000));
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
+ | (c ? PSW_C : 0) | (v ? PSW_V : 0));
+}
+
+// 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd
+8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
+"addc"
+*am33
+{
+ int z, c, n, v;
+ unsigned long sum, source1, source2;
+ int srcreg1, srcreg2, dstreg;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ source1 = State.regs[srcreg1];
+ source2 = State.regs[srcreg2];
+ sum = source1 + source2 + ((PSW & PSW_C) != 0);
+ State.regs[dstreg] = sum;
+
+ z = ((PSW & PSW_Z) != 0) && (sum == 0);
+ n = (sum & 0x80000000);
+ c = (sum < source1) || (sum < source2);
+ v = ((source1 & 0x80000000) == (source2 & 0x80000000)
+ && (source1 & 0x80000000) != (sum & 0x80000000));
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
+ | (c ? PSW_C : 0) | (v ? PSW_V : 0));
+}
+
+// 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd
+8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
+"sub"
+*am33
+{
+ int z, c, n, v;
+ unsigned long difference, source1, source2;
+ int srcreg1, srcreg2, dstreg;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ source1 = State.regs[srcreg1];
+ source2 = State.regs[srcreg2];
+ difference = source2 - source1;
+ State.regs[dstreg] = difference;
+
+ z = (difference == 0);
+ n = (difference & 0x80000000);
+ c = (source1 > source1);
+ v = ((source1 & 0x80000000) == (source2 & 0x80000000)
+ && (source1 & 0x80000000) != (difference & 0x80000000));
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
+ | (c ? PSW_C : 0) | (v ? PSW_V : 0));
+}
+
+// 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd
+8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
+"subc"
+*am33
+{
+ int z, c, n, v;
+ unsigned long difference, source1, source2;
+ int srcreg1, srcreg2, dstreg;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ source1 = State.regs[srcreg1];
+ source2 = State.regs[srcreg2];
+ difference = source2 - source1 - ((PSW & PSW_C) != 0);
+ State.regs[dstreg] = difference;
+
+ z = ((PSW & PSW_Z) != 0) && (difference == 0);
+ n = (difference & 0x80000000);
+ c = (source1 > source2);
+ v = ((source1 & 0x80000000) == (source2 & 0x80000000)
+ && (source1 & 0x80000000) != (difference & 0x80000000));
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
+ | (c ? PSW_C : 0) | (v ? PSW_V : 0));
+}
+
+// 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd
+8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
+"and"
+*am33
+{
+ int z, n;
+ int srcreg1, srcreg2, dstreg;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2];
+
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000);
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
+}
+
+// 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd
+8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
+"or"
+*am33
+{
+ int z, n;
+ int srcreg1, srcreg2, dstreg;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2];
+
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000);
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
+}
+
+// 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd
+8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
+"xor"
+*am33
+{
+ int z, n;
+ int srcreg1, srcreg2, dstreg;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2];
+
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000);
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
+}
+
+// 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd
+8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
+"asr"
+*am33
+{
+ int z, c, n;
+ long temp;
+ int srcreg1, srcreg2, dstreg;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ temp = State.regs[srcreg2];
+ c = temp & 1;
+ temp >>= State.regs[srcreg1];
+ State.regs[dstreg] = temp;
+
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000);
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
+}
+
+// 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd
+8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
+"lsr"
+*am33
+{
+ int z, c, n;
+ int srcreg1, srcreg2, dstreg;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ c = State.regs[srcreg2] & 1;
+ State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1];
+
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000);
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
+}
+
+// 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd
+8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
+"asl"
+*am33
+{
+ int z, n;
+ int srcreg1, srcreg2, dstreg;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];
+
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000);
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
+}
+
+// 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2
+8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mul
+"mul"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ signed long long temp;
+ int n, z;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg1 = translate_rreg (SD_, RD0);
+ dstreg2 = translate_rreg (SD_, RD2);
+
+ temp = ((signed64)(signed32)State.regs[srcreg1]
+ * (signed64)(signed32)State.regs[srcreg2]);
+ State.regs[dstreg2] = temp & 0xffffffff;
+ State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
+
+ z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
+ n = (State.regs[dstreg1] & 0x80000000);
+
+ PSW &= ~(PSW_Z | PSW_N);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
+}
+
+// 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2
+8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mulu
+"mulu"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ signed long long temp;
+ int n, z;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg1 = translate_rreg (SD_, RD0);
+ dstreg2 = translate_rreg (SD_, RD2);
+
+ temp = ((unsigned64)State.regs[srcreg1]
+ * (unsigned64)State.regs[srcreg2]);
+ State.regs[dstreg2] = temp & 0xffffffff;
+ State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
+
+ z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
+ n = (State.regs[dstreg1] & 0x80000000);
+
+ PSW &= ~(PSW_Z | PSW_N);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
+}
+
+// 1111 1011 0000 1110 Rn 0000 abs8 ; mov (abs8),Rn
+8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
+"mov"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (IMM8);
+}
+
+// 1111 1011 0001 1110 Rm 0000 abs8 ; mov Rn,(abs8)
+8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
+"mov"
+*am33
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_word (IMM8, State.regs[srcreg]);
+}
+
+// 1111 1011 0010 1110 Rn 0000 abs8 ; movbu (abs8),Rn
+8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
+"movbu"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_byte (IMM8);
+}
+
+// 1111 1011 0011 1110 Rm 0000 abs8 ; movbu Rn,(abs8)
+8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
+"movbu"
+*am33
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_byte (IMM8, State.regs[srcreg]);
+}
+
+// 1111 1011 0100 1110 Rn 0000 abs8 ; movhu (abs8),Rn
+8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
+"movhu"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (IMM8);
+}
+
+// 1111 1011 0101 1110 Rm 0000 abs8 ; movhu Rn,(abs8)
+8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
+"movhu"
+*am33
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_half (IMM8, State.regs[srcreg]);
+}
+
+// 1111 1011 1000 1110 Ri Rm Rn; mov (Ri,Rm),Rn
+8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
+"mov"
+*am33
+{
+ int srcreg1, srcreg2, dstreg;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM0);
+ srcreg1 = translate_rreg (SD_, RI0);
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
+}
+
+// 1111 1011 1001 1110 Ri Rm Rn; mov Rn,(Ri,Rm)
+8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
+"mov"
+*am33
+{
+ int srcreg, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg1 = translate_rreg (SD_, RI0);
+ dstreg2 = translate_rreg (SD_, RN0);
+ store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
+}
+
+// 1111 1011 1010 1110 Ri Rm Rn; movbu (Ri,Rm),Rn
+8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
+"movbu"
+*am33
+{
+ int srcreg1, srcreg2, dstreg;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM0);
+ srcreg1 = translate_rreg (SD_, RI0);
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
+}
+
+// 1111 1011 1011 1110 Ri Rm Rn; movbu Rn,(Ri,Rm)
+8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
+"movbu"
+*am33
+{
+ int srcreg, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg1 = translate_rreg (SD_, RI0);
+ dstreg2 = translate_rreg (SD_, RN0);
+ store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
+}
+
+// 1111 1011 1100 1110 Ri Rm Rn; movhu (Ri,Rm),Rn
+8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
+"movhu"
+*am33
+{
+ int srcreg1, srcreg2, dstreg;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM0);
+ srcreg1 = translate_rreg (SD_, RI0);
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
+}
+
+// 1111 1011 1101 1110 Ri Rm Rn; movhu Rn,(Ri,Rm)
+8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
+"movhu"
+*am33
+{
+ int srcreg, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg1 = translate_rreg (SD_, RI0);
+ dstreg2 = translate_rreg (SD_, RN0);
+ store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
+}
+
+// 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2
+8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mac
+"mac"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ signed long long temp;
+ unsigned long sum;
+ int c, v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg1 = translate_rreg (SD_, RD0);
+ dstreg2 = translate_rreg (SD_, RD2);
+
+ temp = ((signed64)(signed32)State.regs[srcreg1]
+ * (signed64)(signed32)State.regs[srcreg2]);
+
+ sum = State.regs[dstreg2] + (temp & 0xffffffff);
+ c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
+ State.regs[dstreg2] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[dstreg1] + temp + c;
+ v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[dstreg1] = sum;
+ if (v)
+ {
+ State.regs[REG_MCVF] = 1;
+ PSW &= ~(PSW_V);
+ PSW |= (( v ? PSW_V : 0));
+ }
+}
+
+// 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2
+8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::macu
+"macu"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ signed long long temp;
+ unsigned long sum;
+ int c, v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg1 = translate_rreg (SD_, RD0);
+ dstreg2 = translate_rreg (SD_, RD2);
+
+ temp = ((unsigned64)State.regs[srcreg1]
+ * (unsigned64)State.regs[srcreg2]);
+
+ sum = State.regs[dstreg2] + (temp & 0xffffffff);
+ c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
+ State.regs[dstreg2] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[dstreg1] + temp + c;
+ v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[dstreg1] = sum;
+ if (v)
+ {
+ State.regs[REG_MCVF] = 1;
+ PSW &= ~(PSW_V);
+ PSW |= (( v ? PSW_V : 0));
+ }
+}
+
+// 1111 1011 0010 1111 Rm Rn Rd1; macb Rm,Rn,Rd1
+8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
+"macb"
+*am33
+{
+ int srcreg1, srcreg2, dstreg;
+ long temp, sum;
+ int v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ temp = ((signed32)(State.regs[srcreg2] & 0xff)
+ * (signed32)(State.regs[srcreg1] & 0xff));
+ sum = State.regs[dstreg] + temp;
+ v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[dstreg] = sum;
+ if (v)
+ {
+ State.regs[REG_MCVF] = 1;
+ PSW &= ~(PSW_V);
+ PSW |= ((v ? PSW_V : 0));
+ }
+}
+
+// 1111 1011 0011 1111 Rm Rn Rd1; macbu Rm,Rn,Rd1
+8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
+"macbu"
+*am33
+{
+ int srcreg1, srcreg2, dstreg;
+ long temp, sum;
+ int v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
+ * (unsigned32)(State.regs[srcreg1] & 0xff));
+ sum = State.regs[dstreg] + temp;
+ v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[dstreg] = sum;
+ if (v)
+ {
+ State.regs[REG_MCVF] = 1;
+ PSW &= ~(PSW_V);
+ PSW |= ((v ? PSW_V : 0));
+ }
+}
+
+// 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1,Rd2
+8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mach
+"mach"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ long long temp, sum;
+ int v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg1 = translate_rreg (SD_, RD0);
+ dstreg2 = translate_rreg (SD_, RD0);
+
+ temp = ((signed32)(State.regs[srcreg2] & 0xffff)
+ * (signed32)(State.regs[srcreg1] & 0xffff));
+ State.regs[dstreg2] += (temp & 0xffffffff);
+ sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
+ v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[dstreg1] = sum;
+ if (v)
+ {
+ State.regs[REG_MCVF] = 1;
+ PSW &= ~(PSW_V);
+ PSW |= ((v ? PSW_V : 0));
+ }
+}
+
+// 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1,Rd2
+8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::machu
+"machu"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ long long temp, sum;
+ int v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg1 = translate_rreg (SD_, RD0);
+ dstreg2 = translate_rreg (SD_, RD0);
+
+ temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
+ * (unsigned32)(State.regs[srcreg1] & 0xffff));
+ State.regs[dstreg2] += (temp & 0xffffffff);
+ sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
+ v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[dstreg1] = sum;
+ if (v)
+ {
+ State.regs[REG_MCVF] = 1;
+ PSW &= ~(PSW_V);
+ PSW |= ((v ? PSW_V : 0));
+ }
+}
+
+// 1111 1011 0110 1111 Rm Rn Rd1; dmach Rm,Rn,Rd1
+8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
+"dmach"
+*am33
+{
+ int srcreg1, srcreg2, dstreg;
+ long temp, temp2, sum;
+ int v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ temp = ((signed32)(State.regs[srcreg2] & 0xffff)
+ * (signed32)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)((State.regs[srcreg2] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[dstreg];
+ v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[dstreg] = sum;
+ if (v)
+ {
+ State.regs[REG_MCVF] = 1;
+ PSW &= ~(PSW_V);
+ PSW |= ((v ? PSW_V : 0));
+ }
+}
+
+// 1111 1011 0111 1111 Rm Rn Rd1; dmachu Rm,Rn,Rd1
+8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
+"dmachu"
+*am33
+{
+ int srcreg1, srcreg2, dstreg;
+ long temp, temp2, sum;
+ int v;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
+ * (unsigned32)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[dstreg];
+ v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[dstreg] = sum;
+ if (v)
+ {
+ State.regs[REG_MCVF] = 1;
+ PSW &= ~(PSW_V);
+ PSW |= ((v ? PSW_V : 0));
+ }
+}
+
+// 1111 1011 1000 1111 Rm Rn Rd1 Rd2; dmulh Rm,Rn,Rd1,Rd2
+8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulh
+"dmulh"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ signed long long temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg1 = translate_rreg (SD_, RD0);
+ dstreg2 = translate_rreg (SD_, RD2);
+
+ temp = ((signed32)(State.regs[srcreg1] & 0xffff)
+ * (signed32)(State.regs[srcreg1] & 0xffff));
+ State.regs[dstreg2] = temp;
+ temp = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)((State.regs[srcreg1] >>16) & 0xffff));
+ State.regs[dstreg1] = temp;
+}
+
+// 1111 1011 1001 1111 Rm Rn Rd1 Rd2; dmulhu Rm,Rn,Rd1,Rd2
+8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulhu
+"dmulhu"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ signed long long temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg1 = translate_rreg (SD_, RD0);
+ dstreg2 = translate_rreg (SD_, RD2);
+
+ temp = ((unsigned32)(State.regs[srcreg1] & 0xffff)
+ * (unsigned32)(State.regs[srcreg1] & 0xffff));
+ State.regs[dstreg2] = temp;
+ temp = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (unsigned32)((State.regs[srcreg1] >>16) & 0xffff));
+ State.regs[dstreg1] = temp;
+}
+
+// 1111 1011 1010 1111 Rm Rn; sat24 Rm,Rn
+8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
+"sat24"
+*am33
+{
+ int srcreg, dstreg;
+ int value, n, z;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+
+ value = State.regs[srcreg];
+
+ if (value >= 0x7fffff)
+ State.regs[dstreg] = 0x7fffff;
+ else if (value <= 0xff800000)
+ State.regs[dstreg] = 0xff800000;
+ else
+ State.regs[dstreg] = value;
+
+ n = (State.regs[dstreg] & 0x800000) != 0;
+ z = (State.regs[dstreg] == 0);
+ PSW &= ~(PSW_Z | PSW_N);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1011 1111 1111 Rm Rn Rd1; bsch Rm,Rn,Rd1
+8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
+"bsch"
+*am33
+{
+ int temp, c, i;
+ int srcreg1, srcreg2, dstreg;
+ int start;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
+
+ temp = State.regs[srcreg1];
+ start = (State.regs[srcreg2] & 0x1f) - 1;
+ if (start == -1)
+ start = 31;
+
+ for (i = start; i >= 0; i--)
+ {
+ if (temp & (1 << i))
+ {
+ c = 1;
+ State.regs[dstreg] = i;
+ break;
+ }
+ }
+
+ if (i < 0)
+ {
+ c = 0;
+ State.regs[dstreg] = 0;
+ }
+ PSW &= ~(PSW_C);
+ PSW |= (c ? PSW_C : 0);
+}
+
+// 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn
+8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
+"mov"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
+}
+
+// 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn
+8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
+"movu"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
+}
+
+// 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn
+8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
+"add"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ genericAdd (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
+}
+
+// 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn
+8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
+"addc"
+*am33
+{
+ int dstreg, z, n, c, v;
+ unsigned long sum, imm, reg2;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
+ reg2 = State.regs[dstreg];
+ sum = imm + reg2 + ((PSW & PSW_C) != 0);
+ State.regs[dstreg] = sum;
+
+ z = ((PSW & PSW_Z) != 0) && (sum == 0);
+ n = (sum & 0x80000000);
+ c = (sum < imm) || (sum < reg2);
+ v = ((reg2 & 0x80000000) == (imm & 0x80000000)
+ && (reg2 & 0x80000000) != (sum & 0x80000000));
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
+ | (c ? PSW_C : 0) | (v ? PSW_V : 0));
+}
+
+// 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn
+8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
+"sub"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ genericSub (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
+}
+
+// 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn
+8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
+"subc"
+*am33
+{
+ int dstreg, z, n, c, v;
+ unsigned long difference, imm, reg2;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
+ reg2 = State.regs[dstreg];
+ difference = reg2 - imm - ((PSW & PSW_C) != 0);
+ State.regs[dstreg] = difference;
+
+ z = ((PSW & PSW_Z) != 0) && (difference == 0);
+ n = (difference & 0x80000000);
+ c = (imm > reg2);
+ v = ((reg2 & 0x80000000) == (imm & 0x80000000)
+ && (reg2 & 0x80000000) != (difference & 0x80000000));
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
+ | (c ? PSW_C : 0) | (v ? PSW_V : 0));
+}
+
+// 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn
+8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
+"cmp"
+*am33
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN0);
+ genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]);
+}
+
+// 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn
+8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
+"mov"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_xreg (SD_, XRN0);
+
+ State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
+}
+
+// 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
+8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
+"and"
+*am33
+{
+ int dstreg;
+ int z,n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn
+8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
+"or"
+*am33
+{
+ int dstreg;
+ int z,n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn
+8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
+"xor"
+*am33
+{
+ int dstreg;
+ int z,n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn
+8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
+"asr"
+*am33
+{
+ int dstreg;
+ long temp;
+ int c, z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = State.regs[dstreg];
+ c = temp & 1;
+ temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
+ State.regs[dstreg] = temp;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
+}
+
+
+// 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn
+8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
+"lsr"
+*am33
+{
+ int dstreg;
+ int z, n, c;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ c = State.regs[dstreg] & 1;
+ State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
+}
+
+// 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn
+8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
+"asl"
+*am33
+{
+ int srcreg, dstreg;
+ int z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C));
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1101 1010 1001 Rn Rn IMM24; mul imm24,Rn
+8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
+"mul"
+*am33
+{
+ int dstreg;
+ unsigned long long temp;
+ int z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = ((signed64)(signed32)State.regs[dstreg]
+ * (signed64)(signed32)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
+ State.regs[dstreg] = temp & 0xffffffff;
+ State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1101 1011 1001 Rn Rn IMM24; mulu imm24,Rn
+8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
+"mulu"
+*am33
+{
+ int dstreg;
+ unsigned long long temp;
+ int z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = ((unsigned64)State.regs[dstreg]
+ * (unsigned64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
+ State.regs[dstreg] = temp & 0xffffffff;
+ State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn
+8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
+"btst"
+*am33
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN0);
+ genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
+}
+
+// 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn
+8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
+"mov"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (State.regs[srcreg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+}
+
+// 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn)
+8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
+"mov"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_word (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
+ State.regs[srcreg]);
+}
+
+// 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn
+8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
+"movbu"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_byte (State.regs[srcreg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+}
+
+// 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn)
+8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
+"movbu"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_byte (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
+ State.regs[srcreg]);
+}
+
+// 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn
+8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
+"movhu"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (State.regs[srcreg]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+}
+
+// 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn)
+8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
+"movhu"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_half (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
+ State.regs[srcreg]);
+}
+
+// 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn
+8.0xfd+8.0x6a+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
+"mov"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
+}
+
+// 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+)
+8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
+"mov"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_word (State.regs[dstreg], State.regs[srcreg]);
+ State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
+}
+
+
+// 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn
+8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
+"mov"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (State.regs[REG_SP]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+}
+
+// 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp)
+8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
+"mov"
+*am33
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_word (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
+ State.regs[srcreg]);
+}
+
+// 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,Rm),Rn
+8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
+"movbu"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_byte (State.regs[REG_SP]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+}
+
+// 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp)
+8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
+"movbu"
+*am33
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_byte (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
+ State.regs[srcreg]);
+}
+
+// 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn
+8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
+"movhu"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (State.regs[REG_SP]
+ + EXTEND24 (FETCH24 (IMM24A,
+ IMM24B, IMM24C)));
+}
+
+// 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp)
+8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
+"movhu"
+*am33
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_half (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
+ State.regs[srcreg]);
+}
+
+// 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn
+8.0xfd+8.0xea+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
+"movhu"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (State.regs[srcreg]);
+ State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
+}
+
+// 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+)
+8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
+"movhu"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_half (State.regs[dstreg], State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
+}
+
+// 1111 1101 0000 1011 Rn IMM24; mac imm24,Rn
+8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
+"mac"
+*am33
+{
+ int srcreg;
+ long long temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN2);
+
+ temp = ((signed64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C))
+ * (signed64)State.regs[srcreg]);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1101 0001 1011 Rn IMM24; macu imm24,Rn
+8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
+"macu"
+*am33
+{
+ int srcreg;
+ long long temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN2);
+
+ temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
+ * (unsigned64)State.regs[srcreg]);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1101 0010 1011 Rn IMM24; macb imm24,Rn
+8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
+"macb"
+*am33
+{
+ int srcreg;
+ long long temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN2);
+
+ temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
+ * (signed64)State.regs[srcreg] & 0xff);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1101 0011 1011 Rn IMM24; macbu imm24,Rn
+8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
+"macbu"
+*am33
+{
+ int srcreg;
+ long long temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN2);
+
+ temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
+ * (unsigned64)State.regs[srcreg] & 0xff);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1101 0100 1011 Rn IMM24; mach imm24,Rn
+8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
+"mach"
+*am33
+{
+ int srcreg;
+ long long temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN2);
+
+ temp = ((signed64)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C))
+ * (signed64)State.regs[srcreg] & 0xffff);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1101 0101 1011 Rn IMM24; machu imm24,Rn
+8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
+"machu"
+*am33
+{
+ int srcreg;
+ long long temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN2);
+
+ temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff)
+ * (unsigned64)State.regs[srcreg] & 0xffff);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn
+8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
+"mov"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C));
+}
+
+// 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24)
+8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
+"mov"
+*am33
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
+}
+
+
+// 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn
+8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
+"movbu"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C));
+}
+
+// 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24)
+8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
+"movbu"
+*am33
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
+}
+
+
+// 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn
+8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
+"movhu"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C));
+}
+
+// 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24)
+8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
+"movhu"
+*am33
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
+}
+
+
+// 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn
+8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
+"mov"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
+}
+
+// 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn
+8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
+"movu"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
+}
+
+// 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn
+8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
+"add"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
+}
+
+// 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn
+8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
+"addc"
+*am33
+{
+ int dstreg;
+ unsigned int imm, reg2, sum;
+ int z, n, c, v;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+ reg2 = State.regs[dstreg];
+ sum = imm + reg2 + ((PSW & PSW_C) != 0);
+ State.regs[dstreg] = sum;
+
+ z = ((PSW & PSW_Z) != 0) && (sum == 0);
+ n = (sum & 0x80000000);
+ c = (sum < imm) || (sum < reg2);
+ v = ((reg2 & 0x80000000) == (imm & 0x80000000)
+ && (reg2 & 0x80000000) != (sum & 0x80000000));
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
+ | (c ? PSW_C : 0) | (v ? PSW_V : 0));
+}
+
+// 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn
+8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
+"sub"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
+}
+
+// 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn
+8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
+"subc"
+*am33
+{
+ int dstreg;
+ unsigned int imm, reg2, difference;
+ int z, n, c, v;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+ reg2 = State.regs[dstreg];
+ difference = reg2 - imm - ((PSW & PSW_C) != 0);
+ State.regs[dstreg] = difference;
+
+ z = ((PSW & PSW_Z) != 0) && (difference == 0);
+ n = (difference & 0x80000000);
+ c = (imm > reg2);
+ v = ((reg2 & 0x80000000) == (imm & 0x80000000)
+ && (reg2 & 0x80000000) != (difference & 0x80000000));
+
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
+ | (c ? PSW_C : 0) | (v ? PSW_V : 0));
+}
+
+// 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn
+8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
+"cmp"
+*am33
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN0);
+ genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
+}
+
+// 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn
+8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
+"mov"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_xreg (SD_, XRN0);
+
+ State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
+}
+
+// 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn
+8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
+"and"
+*am33
+{
+ int dstreg;
+ int z,n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn
+8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
+"or"
+*am33
+{
+ int dstreg;
+ int z,n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn
+8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
+"xor"
+*am33
+{
+ int dstreg;
+ int z,n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn
+8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
+"asr"
+*am33
+{
+ int dstreg;
+ long temp;
+ int c, z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = State.regs[dstreg];
+ c = temp & 1;
+ temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+ State.regs[dstreg] = temp;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
+}
+
+// 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn
+8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
+"lsr"
+*am33
+{
+ int dstreg;
+ int z, n, c;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ c = State.regs[dstreg] & 1;
+ State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
+}
+
+// 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn
+8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
+"asl"
+*am33
+{
+ int srcreg, dstreg;
+ int z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1110 1010 1001 Rn Rn IMM32; mul imm32,Rn
+8.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul
+"mul"
+*am33
+{
+ int dstreg;
+ unsigned long long temp;
+ int z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = ((signed64)(signed32)State.regs[dstreg]
+ * (signed64)(signed32)(FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
+ State.regs[dstreg] = temp & 0xffffffff;
+ State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1110 1011 1001 Rn Rn IMM32; mulu imm32,Rn
+8.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu
+"mulu"
+*am33
+{
+ int dstreg;
+ unsigned long long temp;
+ int z, n;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+
+ temp = ((unsigned64)State.regs[dstreg]
+ * (unsigned64) (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
+ State.regs[dstreg] = temp & 0xffffffff;
+ State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
+ z = (State.regs[dstreg] == 0);
+ n = (State.regs[dstreg] & 0x80000000) != 0;
+ PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
+ PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
+}
+
+// 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn
+8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
+"btst"
+*am33
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN0);
+ genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
+}
+
+// 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn
+8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
+"mov"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (State.regs[srcreg]
+ + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn)
+8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
+"mov"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
+ State.regs[srcreg]);
+}
+
+// 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn
+8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
+"movbu"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_byte (State.regs[srcreg]
+ + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn)
+8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
+"movbu"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
+ State.regs[srcreg]);
+}
+
+// 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn
+8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
+"movhu"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (State.regs[srcreg]
+ + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn)
+8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
+"movhu"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
+ State.regs[srcreg]);
+}
+
+// 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn
+8.0xfe+8.0x6a+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
+"mov"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+}
+
+// 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+)
+8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
+"mov"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_word (State.regs[dstreg], State.regs[srcreg]);
+ State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+}
+
+
+// 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn
+8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
+"mov"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (State.regs[REG_SP]
+ + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp)
+8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
+"mov"
+*am33
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
+ State.regs[srcreg]);
+}
+
+// 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn
+8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
+"movbu"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_byte (State.regs[REG_SP]
+ + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp)
+8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
+"movbu"
+*am33
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
+ State.regs[srcreg]);
+}
+
+// 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn
+8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
+"movhu"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (State.regs[REG_SP]
+ + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp)
+8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
+"movhu"
+*am33
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
+ State.regs[srcreg]);
+}
+
+
+// 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn
+8.0xfe+8.0xea+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
+"movhu"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (State.regs[srcreg]);
+ State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+}
+
+// 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+)
+8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
+"movhu"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
+ store_half (State.regs[dstreg], State.regs[srcreg]);
+ State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+}
+
+
+// 1111 1110 0000 1011 Rn Rn IMM32; mac imm32,Rn
+8.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac
+"mac"
+*am33
+{
+ int srcreg, imm;
+ long long temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN0);
+ imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ temp = ((signed64)(signed32)State.regs[srcreg]
+ * (signed64)(signed32)imm);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1110 0001 1011 Rn Rn IMM32; macu imm32,Rn
+8.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu
+"macu"
+*am33
+{
+ int srcreg, imm;
+ long long temp, sum;
+ int c, v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN0);
+ imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ temp = ((unsigned64)State.regs[srcreg]
+ * (unsigned64)imm);
+ sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+ c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+ State.regs[REG_MCRL] = sum;
+ temp >>= 32;
+ temp &= 0xffffffff;
+ sum = State.regs[REG_MCRH] + temp + c;
+ v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRH] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1110 0010 1011 Rn Rn IMM32; macb imm32,Rn
+8.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb
+"macb"
+*am33
+{
+ int srcreg, imm;
+ long temp, sum;
+ int v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN0);
+ imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ temp = ((signed32)(signed8)(State.regs[srcreg] & 0xff)
+ * (signed32)(signed8)(imm & 0xff));
+ sum = State.regs[REG_MCRL] + temp;
+ v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRL] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1110 0011 1011 Rn Rn IMM32; macbu imm32,Rn
+8.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu
+"macbu"
+*am33
+{
+ int srcreg, imm;
+ long temp, sum;
+ int v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN0);
+ imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ temp = ((unsigned32)(State.regs[srcreg] & 0xff)
+ * (unsigned32)(imm & 0xff));
+ sum = State.regs[REG_MCRL] + temp;
+ v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRL] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1110 0100 1011 Rn Rn IMM32; mach imm32,Rn
+8.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach
+"mach"
+*am33
+{
+ int srcreg, imm;
+ long temp, sum;
+ int v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN0);
+ imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
+ * (signed32)(signed16)(imm & 0xffff));
+ sum = State.regs[REG_MCRL] + temp;
+ v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRL] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1110 0101 1011 Rn Rn IMM32; machu imm32,Rn
+8.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu
+"machu"
+*am33
+{
+ int srcreg, imm;
+ long temp, sum;
+ int v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN0);
+ imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
+ * (unsigned32)(imm & 0xffff));
+ sum = State.regs[REG_MCRL] + temp;
+ v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRL] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1110 0110 1011 Rn Rn IMM32; dmach imm32,Rn
+8.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach
+"dmach"
+*am33
+{
+ int srcreg, imm;
+ long temp, temp2, sum;
+ int v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN0);
+ imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
+ * (signed32)(signed16)(imm & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg] >> 16) & 0xffff)
+ * (signed32)(signed16)((imm >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+ v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRL] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1110 0111 1011 Rn Rn IMM32; dmachu imm32,Rn
+8.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu
+"dmachu"
+*am33
+{
+ int srcreg, imm;
+ long temp, temp2, sum;
+ int v;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RN0);
+ imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
+ * (unsigned32)(imm & 0xffff));
+ temp2 = ((unsigned32)((State.regs[srcreg] >> 16) & 0xffff)
+ * (unsigned32)((imm >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+ v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+ && (temp & 0x80000000) != (sum & 0x80000000));
+ State.regs[REG_MCRL] = sum;
+ if (v)
+ State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1110 1000 1011 Rn Rn IMM32; dmulh imm32,Rn
+8.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh
+"dmulh"
+*am33
+{
+ int imm, dstreg;
+ long temp;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
+ * (signed32)(signed16)(imm & 0xffff));
+ State.regs[REG_MDRQ] = temp;
+ temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
+ * (signed32)(signed16)((imm>>16) & 0xffff));
+ State.regs[dstreg] = temp;
+}
+
+// 1111 1110 1001 1011 Rn Rn IMM32; dmulhu imm32,Rn
+8.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu
+"dmulhu"
+*am33
+{
+ int imm, dstreg;
+ long temp;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN0);
+ imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+ temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
+ * (unsigned32)(imm & 0xffff));
+ State.regs[REG_MDRQ] = temp;
+ temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
+ * (unsigned32)((imm >>16) & 0xffff));
+ State.regs[dstreg] = temp;
+}
+
+// 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
+8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
+"mov"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
+8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
+"mov"
+*am33
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
+}
+
+// 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
+8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
+"movbu"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
+8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
+"movbu"
+*am33
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
+}
+
+// 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
+8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
+"movhu"
+*am33
+{
+ int dstreg;
+
+ PC = cia;
+ dstreg = translate_rreg (SD_, RN2);
+ State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
+}
+
+// 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
+8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
+"movhu"
+*am33
+{
+ int srcreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
+}
+
+// 1111 0111 0000 0000 Rm1 Rn1 Rm2 Rn2; add_add Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_add
+"add_add"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + State.regs[srcreg1];
+ State.regs[dstreg2] += State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0001 0000 Rm1 Rn1 imm4 Rn2; add_add Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_add
+"add_add"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + State.regs[srcreg1];
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0010 0000 Rm1 Rn1 Rm2 Rn2; add_sub Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_sub
+"add_sub"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + State.regs[srcreg1];
+ State.regs[dstreg2] -= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0011 0000 Rm1 Rn1 imm4 Rn2; add_sub Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_sub
+"add_sub"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + State.regs[srcreg1];
+ State.regs[dstreg2] -= EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0100 0000 Rm1 Rn1 Rm2 Rn2; add_cmp Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_cmp
+"add_cmp"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+ State.regs[dstreg1] += State.regs[srcreg1];
+}
+
+// 1111 0111 0101 0000 Rm1 Rn1 imm4 Rn2; add_cmp Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_cmp
+"add_cmp"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+ State.regs[dstreg1] += State.regs[srcreg1];
+}
+
+// 1111 0111 0110 0000 Rm1 Rn1 Rm2 Rn2; add_mov Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_mov
+"add_mov"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + State.regs[srcreg1];
+ State.regs[dstreg2] = State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0111 0000 Rm1 Rn1 imm4 Rn2; add_mov Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_mov
+"add_mov"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + State.regs[srcreg1];
+ State.regs[dstreg2] = EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1000 0000 Rm1 Rn1 Rm2 Rn2; add_asr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asr
+"add_asr"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + State.regs[srcreg1];
+ temp = State.regs[dstreg2];
+ temp >>= State.regs[srcreg2];
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1001 0000 Rm1 Rn1 imm4 Rn2; add_asr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asr
+"add_asr"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + State.regs[srcreg1];
+ temp = State.regs[dstreg2];
+ temp >>= IMM4;
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1010 0000 Rm1 Rn1 Rm2 Rn2; add_lsr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_lsr
+"add_lsr"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + State.regs[srcreg1];
+ State.regs[dstreg2] >>= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1011 0000 Rm1 Rn1 imm4 Rn2; add_lsr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_lsr
+"add_lsr"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + State.regs[srcreg1];
+ State.regs[dstreg2] >>= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+
+// 1111 0111 1100 0000 Rm1 Rn1 Rm2 Rn2; add_asl Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asl
+"add_asl"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + State.regs[srcreg1];
+ State.regs[dstreg2] <<= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1101 0000 Rm1 Rn1 imm4 Rn2; add_asl Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asl
+"add_asl"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + State.regs[srcreg1];
+ State.regs[dstreg2] <<= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0000 0001 Rm1 Rn1 Rm2 Rn2; cmp_add Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_add
+"cmp_add"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
+ State.regs[dstreg2] += State.regs[srcreg2];
+}
+
+// 1111 0111 0001 0001 Rm1 Rn1 imm4 Rn2; cmp_add Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_add
+"cmp_add"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+}
+
+// 1111 0111 0010 0001 Rm1 Rn1 Rm2 Rn2; cmp_sub Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_sub
+"cmp_sub"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
+ State.regs[dstreg2] -= State.regs[srcreg2];
+}
+
+// 1111 0111 0011 0001 Rm1 Rn1 imm4 Rn2; cmp_sub Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_sub
+"cmp_sub"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
+ State.regs[dstreg2] -= EXTEND4 (IMM4);
+}
+
+// 1111 0111 0110 0001 Rm1 Rn1 Rm2 Rn2; cmp_mov Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_mov
+"cmp_mov"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
+ State.regs[dstreg2] = State.regs[srcreg2];
+}
+
+// 1111 0111 0111 0001 Rm1 Rn1 imm4 Rn2; cmp_mov Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_mov
+"cmp_mov"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
+ State.regs[dstreg2] = EXTEND4 (IMM4);
+}
+
+// 1111 0111 1000 0001 Rm1 Rn1 Rm2 Rn2; cmp_asr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asr
+"cmp_asr"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
+ temp = State.regs[dstreg2];
+ temp >>= State.regs[srcreg2];
+ State.regs[dstreg2] = temp;
+}
+
+// 1111 0111 1001 0001 Rm1 Rn1 imm4 Rn2; cmp_asr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asr
+"cmp_asr"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
+ temp = State.regs[dstreg2];
+ temp >>= IMM4;
+ State.regs[dstreg2] = temp;
+}
+
+// 1111 0111 1010 0001 Rm1 Rn1 Rm2 Rn2; cmp_lsr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_lsr
+"cmp_lsr"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
+ State.regs[dstreg2] >>= State.regs[srcreg2];
+}
+
+// 1111 0111 1011 0001 Rm1 Rn1 imm4 Rn2; cmp_lsr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_lsr
+"cmp_lsr"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
+ State.regs[dstreg2] >>= IMM4;
+}
+
+
+// 1111 0111 1100 0001 Rm1 Rn1 Rm2 Rn2; cmp_asl Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asl
+"cmp_asl"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
+ State.regs[dstreg2] <<= State.regs[srcreg2];
+}
+
+// 1111 0111 1101 0001 Rm1 Rn1 imm4 Rn2; cmp_asl Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asl
+"cmp_asl"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
+ State.regs[dstreg2] <<= IMM4;
+}
+
+// 1111 0111 0000 0010 Rm1 Rn1 Rm2 Rn2; sub_add Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_add
+"sub_add"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - State.regs[srcreg1];
+ State.regs[dstreg2] += State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0001 0010 Rm1 Rn1 imm4 Rn2; sub_add Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_add
+"sub_add"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - State.regs[srcreg1];
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0010 0010 Rm1 Rn1 Rm2 Rn2; sub_sub Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_sub
+"sub_sub"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - State.regs[srcreg1];
+ State.regs[dstreg2] -= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0011 0010 Rm1 Rn1 imm4 Rn2; sub_sub Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_sub
+"sub_sub"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - State.regs[srcreg1];
+ State.regs[dstreg2] -= EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0100 0010 Rm1 Rn1 Rm2 Rn2; sub_cmp Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_cmp
+"sub_cmp"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+ State.regs[dstreg1] -= State.regs[srcreg1];
+}
+
+// 1111 0111 0101 0010 Rm1 Rn1 imm4 Rn2; sub_cmp Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_cmp
+"sub_cmp"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+ State.regs[dstreg1] -= State.regs[srcreg1];
+}
+
+// 1111 0111 0110 0010 Rm1 Rn1 Rm2 Rn2; sub_mov Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_mov
+"sub_mov"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - State.regs[srcreg1];
+ State.regs[dstreg2] = State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0111 0010 Rm1 Rn1 imm4 Rn2; sub_mov Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_mov
+"sub_mov"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - State.regs[srcreg1];
+ State.regs[dstreg2] = EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1000 0010 Rm1 Rn1 Rm2 Rn2; sub_asr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asr
+"sub_asr"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - State.regs[srcreg1];
+ temp = State.regs[dstreg2];
+ temp >>= State.regs[srcreg2];
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1001 0010 Rm1 Rn1 imm4 Rn2; sub_asr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asr
+"sub_asr"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - State.regs[srcreg1];
+ temp = State.regs[dstreg2];
+ temp >>= IMM4;
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1010 0010 Rm1 Rn1 Rm2 Rn2; sub_lsr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_lsr
+"sub_lsr"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - State.regs[srcreg1];
+ State.regs[dstreg2] >>= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1011 0010 Rm1 Rn1 imm4 Rn2; sub_lsr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_lsr
+"sub_lsr"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - State.regs[srcreg1];
+ State.regs[dstreg2] >>= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+
+// 1111 0111 1100 0010 Rm1 Rn1 Rm2 Rn2; sub_asl Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asl
+"sub_asl"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - State.regs[srcreg1];
+ State.regs[dstreg2] <<= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1101 0010 Rm1 Rn1 imm4 Rn2; sub_asl Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asl
+"sub_asl"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - State.regs[srcreg1];
+ State.regs[dstreg2] <<= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0000 0011 Rm1 Rn1 Rm2 Rn2; mov_add Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_add
+"mov_add"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[srcreg1];
+ State.regs[dstreg2] += State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0001 0011 Rm1 Rn1 imm4 Rn2; mov_add Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_add
+"mov_add"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[srcreg1];
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0010 0011 Rm1 Rn1 Rm2 Rn2; mov_sub Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_sub
+"mov_sub"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[srcreg1];
+ State.regs[dstreg2] -= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0011 0011 Rm1 Rn1 imm4 Rn2; mov_sub Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_sub
+"mov_sub"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[srcreg1];
+ State.regs[dstreg2] -= EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0100 0011 Rm1 Rn1 Rm2 Rn2; mov_cmp Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_cmp
+"mov_cmp"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+ State.regs[dstreg1] = State.regs[srcreg1];
+}
+
+// 1111 0111 0101 0011 Rm1 Rn1 imm4 Rn2; mov_cmp Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_cmp
+"mov_cmp"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+ State.regs[dstreg1] = State.regs[srcreg1];
+}
+
+// 1111 0111 0110 0011 Rm1 Rn1 Rm2 Rn2; mov_mov Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_mov
+"mov_mov"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[srcreg1];
+ State.regs[dstreg2] = State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0111 0011 Rm1 Rn1 imm4 Rn2; mov_mov Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_mov
+"mov_mov"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[srcreg1];
+ State.regs[dstreg2] = EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1000 0011 Rm1 Rn1 Rm2 Rn2; mov_asr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asr
+"mov_asr"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[srcreg1];
+ temp = State.regs[dstreg2];
+ temp >>= State.regs[srcreg2];
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1001 0011 Rm1 Rn1 imm4 Rn2; mov_asr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asr
+"mov_asr"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[srcreg1];
+ temp = State.regs[dstreg2];
+ temp >>= IMM4;
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1010 0011 Rm1 Rn1 Rm2 Rn2; mov_lsr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_lsr
+"mov_lsr"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[srcreg1];
+ State.regs[dstreg2] >>= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1011 0011 Rm1 Rn1 imm4 Rn2; mov_lsr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_lsr
+"mov_lsr"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[srcreg1];
+ State.regs[dstreg2] >>= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+
+// 1111 0111 1100 0011 Rm1 Rn1 Rm2 Rn2; mov_asl Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asl
+"mov_asl"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[srcreg1];
+ State.regs[dstreg2] <<= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1101 0011 Rm1 Rn1 imm4 Rn2; mov_asl Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asl
+"mov_asl"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[srcreg1];
+ State.regs[dstreg2] <<= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0000 0100 imm4 Rn1 Rm2 Rn2; add_add imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_add
+"add_add"
+*am33
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
+ State.regs[dstreg2] += State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0001 0100 imm4 Rn1 imm4 Rn2; add_add imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_add
+"add_add"
+*am33
+{
+ int dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0010 0100 imm4 Rn1 Rm2 Rn2; add_sub imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_sub
+"add_sub"
+*am33
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
+ State.regs[dstreg2] -= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0011 0100 imm4 Rn1 imm4 Rn2; add_sub imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_sub
+"add_sub"
+*am33
+{
+ int dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
+ State.regs[dstreg2] -= EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0100 0100 imm4 Rn1 Rm2 Rn2; add_cmp imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_cmp
+"add_cmp"
+*am33
+{
+ int srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+ State.regs[dstreg1] += EXTEND4 (IMM4A);
+}
+
+// 1111 0111 0101 0100 imm4 Rn1 imm4 Rn2; add_cmp imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_cmp
+"add_cmp"
+*am33
+{
+ int dstreg1, dstreg2;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+ State.regs[dstreg1] += EXTEND4 (IMM4A);
+}
+
+// 1111 0111 0110 0100 imm4 Rn1 Rm2 Rn2; add_mov imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_mov
+"add_mov"
+*am33
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
+ State.regs[dstreg2] = State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0111 0100 imm4 Rn1 imm4 Rn2; add_mov imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_mov
+"add_mov"
+*am33
+{
+ int dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
+ State.regs[dstreg2] = EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1000 0100 imm4 Rn1 Rm2 Rn2; add_asr imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asr
+"add_asr"
+*am33
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
+ temp = State.regs[dstreg2];
+ temp >>= State.regs[srcreg2];
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1001 0100 imm4 Rn1 imm4 Rn2; add_asr imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asr
+"add_asr"
+*am33
+{
+ int dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
+ temp = State.regs[dstreg2];
+ temp >>= IMM4;
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1010 0100 imm4 Rn1 Rm2 Rn2; add_lsr imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_lsr
+"add_lsr"
+*am33
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
+ State.regs[dstreg2] >>= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1011 0100 imm4 Rn1 imm4 Rn2; add_lsr imm4, Rn1, imm4, Rn2
+8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_lsr
+"add_lsr"
+*am33
+{
+ int dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
+ State.regs[dstreg2] >>= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+
+// 1111 0111 1100 0100 imm4 Rn1 Rm2 Rn2; add_asl imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asl
+"add_asl"
+*am33
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
+ State.regs[dstreg2] <<= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1101 0100 imm4 Rn1 imm4 Rn2; add_asl imm4, Rn1, imm4, Rn2
+8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asl
+"add_asl"
+*am33
+{
+ int dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
+ State.regs[dstreg2] <<= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0000 0101 imm4 Rn1 Rm2 Rn2; cmp_add imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_add
+"cmp_add"
+*am33
+{
+ int srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
+ State.regs[dstreg2] += State.regs[srcreg2];
+}
+
+// 1111 0111 0001 0101 imm4 Rn1 imm4 Rn2; cmp_add imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_add
+"cmp_add"
+*am33
+{
+ int dstreg1, dstreg2;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+}
+
+// 1111 0111 0010 0101 imm4 Rn1 Rm2 Rn2; cmp_sub imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_sub
+"cmp_sub"
+*am33
+{
+ int srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
+ State.regs[dstreg2] -= State.regs[srcreg2];
+}
+
+// 1111 0111 0011 0101 imm4 Rn1 imm4 Rn2; cmp_sub imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_sub
+"cmp_sub"
+*am33
+{
+ int dstreg1, dstreg2;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
+ State.regs[dstreg2] -= EXTEND4 (IMM4);
+}
+
+// 1111 0111 0110 0101 imm4 Rn1 Rm2 Rn2; cmp_mov imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_mov
+"cmp_mov"
+*am33
+{
+ int srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
+ State.regs[dstreg2] = State.regs[srcreg2];
+}
+
+// 1111 0111 0111 0101 imm4 Rn1 imm4 Rn2; cmp_mov imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_mov
+"cmp_mov"
+*am33
+{
+ int dstreg1, dstreg2;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
+ State.regs[dstreg2] = EXTEND4 (IMM4);
+}
+
+// 1111 0111 1000 0101 imm4 Rn1 Rm2 Rn2; cmp_asr imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asr
+"cmp_asr"
+*am33
+{
+ int srcreg2, dstreg1, dstreg2;
+ signed int temp;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
+ temp = State.regs[dstreg2];
+ temp >>= State.regs[srcreg2];
+ State.regs[dstreg2] = temp;
+}
+
+// 1111 0111 1001 0101 imm4 Rn1 imm4 Rn2; cmp_asr imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asr
+"cmp_asr"
+*am33
+{
+ int dstreg1, dstreg2;
+ signed int temp;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
+ temp = State.regs[dstreg2];
+ temp >>= IMM4;
+ State.regs[dstreg2] = temp;
+}
+
+// 1111 0111 1010 0101 imm4 Rn1 Rm2 Rn2; cmp_lsr imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_lsr
+"cmp_lsr"
+*am33
+{
+ int srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
+ State.regs[dstreg2] >>= State.regs[srcreg2];
+}
+
+// 1111 0111 1011 0101 imm4 Rn1 imm4 Rn2; cmp_lsr imm4, Rn1, imm4, Rn2
+8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_lsr
+"cmp_lsr"
+*am33
+{
+ int dstreg1, dstreg2;
+ signed int temp;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
+ State.regs[dstreg2] >>= IMM4;
+}
+
+
+// 1111 0111 1100 0101 imm4 Rn1 Rm2 Rn2; cmp_asl imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asl
+"cmp_asl"
+*am33
+{
+ int srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
+ State.regs[dstreg2] <<= State.regs[srcreg2];
+}
+
+// 1111 0111 1101 0101 imm4 Rn1 imm4 Rn2; cmp_asl imm4, Rn1, imm4, Rn2
+8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asl
+"cmp_asl"
+*am33
+{
+ int dstreg1, dstreg2;
+ signed int temp;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
+ State.regs[dstreg2] <<= IMM4;
+}
+
+// 1111 0111 0000 0110 imm4 Rn1 Rm2 Rn2; sub_add imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_add
+"sub_add"
+*am33
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
+ State.regs[dstreg2] += State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0001 0110 imm4 Rn1 imm4 Rn2; sub_add imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_add
+"sub_add"
+*am33
+{
+ int dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0010 0110 imm4 Rn1 Rm2 Rn2; sub_sub imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_sub
+"sub_sub"
+*am33
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
+ State.regs[dstreg2] -= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0011 0110 imm4 Rn1 imm4 Rn2; sub_sub imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_sub
+"sub_sub"
+*am33
+{
+ int dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
+ State.regs[dstreg2] -= EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0100 0110 imm4 Rn1 Rm2 Rn2; sub_cmp imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_cmp
+"sub_cmp"
+*am33
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+ State.regs[dstreg1] -= EXTEND4 (IMM4A);
+}
+
+// 1111 0111 0101 0110 imm4 Rn1 imm4 Rn2; sub_cmp imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_cmp
+"sub_cmp"
+*am33
+{
+ int dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+ State.regs[dstreg1] -= EXTEND4 (IMM4A);
+}
+
+// 1111 0111 0110 0110 imm4 Rn1 Rm2 Rn2; sub_mov imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_mov
+"sub_mov"
+*am33
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
+ State.regs[dstreg2] = State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0111 0110 imm4 Rn1 imm4 Rn2; sub_mov imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_mov
+"sub_mov"
+*am33
+{
+ int dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
+ State.regs[dstreg2] = EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1000 0110 imm4 Rn1 Rm2 Rn2; sub_asr imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asr
+"sub_asr"
+*am33
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
+ temp = State.regs[dstreg2];
+ temp >>= State.regs[srcreg2];
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1001 0110 imm4 Rn1 imm4 Rn2; sub_asr imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asr
+"sub_asr"
+*am33
+{
+ int dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
+ temp = State.regs[dstreg2];
+ temp >>= IMM4;
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1010 0110 imm4 Rn1 Rm2 Rn2; sub_lsr imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_lsr
+"sub_lsr"
+*am33
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
+ State.regs[dstreg2] >>= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1011 0110 imm4 Rn1 imm4 Rn2; sub_lsr imm4, Rn1, imm4, Rn2
+8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_lsr
+"sub_lsr"
+*am33
+{
+ int dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
+ State.regs[dstreg2] >>= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+
+// 1111 0111 1100 0110 imm4 Rn1 Rm2 Rn2; sub_asl imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asl
+"sub_asl"
+*am33
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
+ State.regs[dstreg2] <<= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1101 0110 imm4 Rn1 imm4 Rn2; sub_asl imm4, Rn1, imm4, Rn2
+8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asl
+"sub_asl"
+*am33
+{
+ int dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
+ State.regs[dstreg2] <<= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0000 0111 imm4 Rn1 Rm2 Rn2; mov_add imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_add
+"mov_add"
+*am33
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = EXTEND4 (IMM4A);
+ State.regs[dstreg2] += State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0001 0111 imm4 Rn1 imm4 Rn2; mov_add imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_add
+"mov_add"
+*am33
+{
+ int dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = EXTEND4 (IMM4A);
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0010 0111 imm4 Rn1 Rm2 Rn2; mov_sub imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_sub
+"mov_sub"
+*am33
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = EXTEND4 (IMM4A);
+ State.regs[dstreg2] -= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0011 0111 imm4 Rn1 imm4 Rn2; mov_sub imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_sub
+"mov_sub"
+*am33
+{
+ int dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = EXTEND4 (IMM4A);
+ State.regs[dstreg2] -= EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0100 0111 imm4 Rn1 Rm2 Rn2; mov_cmp imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_cmp
+"mov_cmp"
+*am33
+{
+ int srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+ State.regs[dstreg1] = EXTEND4 (IMM4A);
+}
+
+// 1111 0111 0101 0111 imm4 Rn1 imm4 Rn2; mov_cmp imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_cmp
+"mov_cmp"
+*am33
+{
+ int dstreg1, dstreg2;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+ State.regs[dstreg1] = EXTEND4 (IMM4A);
+}
+
+// 1111 0111 0110 0111 imm4 Rn1 Rm2 Rn2; mov_mov imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_mov
+"mov_mov"
+*am33
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = EXTEND4 (IMM4A);
+ State.regs[dstreg2] = State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0111 0111 imm4 Rn1 imm4 Rn2; mov_mov imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_mov
+"mov_mov"
+*am33
+{
+ int dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = EXTEND4 (IMM4A);
+ State.regs[dstreg2] = EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1000 0111 imm4 Rn1 Rm2 Rn2; mov_asr imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asr
+"mov_asr"
+*am33
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = EXTEND4 (IMM4A);
+ temp = State.regs[dstreg2];
+ temp >>= State.regs[srcreg2];
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1001 0111 imm4 Rn1 imm4 Rn2; mov_asr imm4, Rn1, imm4, Rn2
+8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asr
+"mov_asr"
+*am33
+{
+ int dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = EXTEND4 (IMM4A);
+ temp = State.regs[dstreg2];
+ temp >>= IMM4;
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1010 0111 imm4 Rn1 Rm2 Rn2; mov_lsr imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_lsr
+"mov_lsr"
+*am33
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = EXTEND4 (IMM4A);
+ State.regs[dstreg2] >>= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1011 0111 imm4 Rn1 imm4 Rn2; mov_lsr imm4, Rn1, imm4, Rn2
+8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_lsr
+"mov_lsr"
+*am33
+{
+ int dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = EXTEND4 (IMM4A);
+ State.regs[dstreg2] >>= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+
+// 1111 0111 1100 0111 imm4 Rn1 Rm2 Rn2; mov_asl imm4, Rn1, Rm2, Rn2
+8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asl
+"mov_asl"
+*am33
+{
+ int srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = EXTEND4 (IMM4A);
+ State.regs[dstreg2] <<= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1101 0111 imm4 Rn1 imm4 Rn2; mov_asl imm4, Rn1, imm4, Rn2
+8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asl
+"mov_asl"
+*am33
+{
+ int dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = EXTEND4 (IMM4A);
+ State.regs[dstreg2] <<= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0000 1000 Rm1 Rn1 Rm2 Rn2; and_add Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_add
+"and_add"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] & State.regs[srcreg1];
+ State.regs[dstreg2] += State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0001 1000 Rm1 Rn1 imm4 Rn2; and_add Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_add
+"and_add"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] & State.regs[srcreg1];
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0010 1000 Rm1 Rn1 Rm2 Rn2; and_sub Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_sub
+"and_sub"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] & State.regs[srcreg1];
+ State.regs[dstreg2] -= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0011 1000 Rm1 Rn1 imm4 Rn2; and_sub Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_sub
+"and_sub"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] & State.regs[srcreg1];
+ State.regs[dstreg2] -= EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0100 1000 Rm1 Rn1 Rm2 Rn2; and_cmp Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_cmp
+"and_cmp"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+ State.regs[dstreg1] &= State.regs[srcreg1];
+}
+
+// 1111 0111 0101 1000 Rm1 Rn1 imm4 Rn2; and_cmp Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_cmp
+"and_cmp"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+ State.regs[dstreg1] &= State.regs[srcreg1];
+}
+
+// 1111 0111 0110 1000 Rm1 Rn1 Rm2 Rn2; and_mov Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_mov
+"and_mov"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] & State.regs[srcreg1];
+ State.regs[dstreg2] = State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0111 1000 Rm1 Rn1 imm4 Rn2; and_mov Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_mov
+"and_mov"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] & State.regs[srcreg1];
+ State.regs[dstreg2] = EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1000 1000 Rm1 Rn1 Rm2 Rn2; and_asr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asr
+"and_asr"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] & State.regs[srcreg1];
+ temp = State.regs[dstreg2];
+ temp >>= State.regs[srcreg2];
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1001 1000 Rm1 Rn1 imm4 Rn2; and_asr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asr
+"and_asr"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] & State.regs[srcreg1];
+ temp = State.regs[dstreg2];
+ temp >>= IMM4;
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1010 1000 Rm1 Rn1 Rm2 Rn2; and_lsr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_lsr
+"and_lsr"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] & State.regs[srcreg1];
+ State.regs[dstreg2] >>= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1011 1000 Rm1 Rn1 imm4 Rn2; and_lsr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_lsr
+"and_lsr"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] & State.regs[srcreg1];
+ State.regs[dstreg2] >>= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+
+// 1111 0111 1100 1000 Rm1 Rn1 Rm2 Rn2; and_asl Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asl
+"and_asl"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] & State.regs[srcreg1];
+ State.regs[dstreg2] <<= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1101 1000 Rm1 Rn1 imm4 Rn2; and_asl Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asl
+"and_asl"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] & State.regs[srcreg1];
+ State.regs[dstreg2] <<= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0000 1001 Rm1 Rn1 Rm2 Rn2; dmach_add Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_add
+"dmach_add"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ long temp, temp2, sum;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+
+ State.regs[dstreg2] += State.regs[srcreg2];
+ State.regs[dstreg1] = sum;
+}
+
+// 1111 0111 0001 1001 Rm1 Rn1 imm4 Rn2; dmach_add Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_add
+"dmach_add"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ long temp, temp2, sum;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+ State.regs[dstreg1] = sum;
+}
+
+// 1111 0111 0010 1001 Rm1 Rn1 Rm2 Rn2; dmach_sub Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_sub
+"dmach_sub"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ long temp, temp2, sum;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+
+ State.regs[dstreg2] -= State.regs[srcreg2];
+ State.regs[dstreg1] = sum;
+}
+
+// 1111 0111 0011 1001 Rm1 Rn1 imm4 Rn2; dmach_sub Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_sub
+"dmach_sub"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ long temp, temp2, sum;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+
+ State.regs[dstreg2] -= EXTEND4 (IMM4);
+ State.regs[dstreg1] = sum;
+}
+
+// 1111 0111 0100 1001 Rm1 Rn1 Rm2 Rn2; dmach_cmp Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_cmp
+"dmach_cmp"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ long temp, temp2, sum;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+
+ genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+ State.regs[dstreg1] = sum;
+}
+
+// 1111 0111 0101 1001 Rm1 Rn1 imm4 Rn2; dmach_cmp Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_cmp
+"dmach_cmp"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ long temp, temp2, sum;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+
+ genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+ State.regs[dstreg1] = sum;
+}
+
+// 1111 0111 0110 1001 Rm1 Rn1 Rm2 Rn2; dmach_mov Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_mov
+"dmach_mov"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ long temp, temp2, sum;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+
+ State.regs[dstreg2] = State.regs[srcreg2];
+ State.regs[dstreg1] = sum;
+}
+
+// 1111 0111 0111 1001 Rm1 Rn1 imm4 Rn2; dmach_mov Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_mov
+"dmach_mov"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ long temp, temp2, sum;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+
+ State.regs[dstreg2] = EXTEND4 (IMM4);
+ State.regs[dstreg1] = sum;
+}
+
+// 1111 0111 1000 1001 Rm1 Rn1 Rm2 Rn2; dmach_asr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asr
+"dmach_asr"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ long temp, temp2, sum;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+
+ temp = State.regs[dstreg2];
+ temp >>= State.regs[srcreg2];
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = sum;
+}
+
+// 1111 0111 1001 1001 Rm1 Rn1 imm4 Rn2; dmach_asr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asr
+"dmach_asr"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ long temp, temp2, sum;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+
+ temp = State.regs[dstreg2];
+ temp >>= IMM4;
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = sum;
+}
+
+// 1111 0111 1010 1001 Rm1 Rn1 Rm2 Rn2; dmach_lsr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_lsr
+"dmach_lsr"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ long temp, temp2, sum;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+
+ State.regs[dstreg2] >>= State.regs[srcreg2];
+ State.regs[dstreg1] = sum;
+}
+
+// 1111 0111 1011 1001 Rm1 Rn1 imm4 Rn2; dmach_lsr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_lsr
+"dmach_lsr"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ long temp, temp2, sum;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+
+ State.regs[dstreg2] >>= IMM4;
+ State.regs[dstreg1] = sum;
+}
+
+
+// 1111 0111 1100 1001 Rm1 Rn1 Rm2 Rn2; dmach_asl Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asl
+"dmach_asl"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ long temp, temp2, sum;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+
+ State.regs[dstreg2] <<= State.regs[srcreg2];
+ State.regs[dstreg1] = sum;
+}
+
+// 1111 0111 1101 1001 Rm1 Rn1 imm4 Rn2; dmach_asl Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asl
+"dmach_asl"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ long temp, temp2, sum;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+ * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+ temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+ * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+ sum = temp + temp2 + State.regs[REG_MCRL];
+
+ State.regs[dstreg2] <<= IMM4;
+ State.regs[dstreg1] = sum;
+}
+
+// 1111 0111 0000 1010 Rm1 Rn1 Rm2 Rn2; xor_add Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_add
+"xor_add"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
+ State.regs[dstreg2] += State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0001 1010 Rm1 Rn1 imm4 Rn2; xor_add Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_add
+"xor_add"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0010 1010 Rm1 Rn1 Rm2 Rn2; xor_sub Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_sub
+"xor_sub"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
+ State.regs[dstreg2] -= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0011 1010 Rm1 Rn1 imm4 Rn2; xor_sub Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_sub
+"xor_sub"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
+ State.regs[dstreg2] -= EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0100 1010 Rm1 Rn1 Rm2 Rn2; xor_cmp Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_cmp
+"xor_cmp"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+ State.regs[dstreg1] ^= State.regs[srcreg1];
+}
+
+// 1111 0111 0101 1010 Rm1 Rn1 imm4 Rn2; xor_cmp Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_cmp
+"xor_cmp"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+ State.regs[dstreg1] ^= State.regs[srcreg1];
+}
+
+// 1111 0111 0110 1010 Rm1 Rn1 Rm2 Rn2; xor_mov Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_mov
+"xor_mov"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
+ State.regs[dstreg2] = State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0111 1010 Rm1 Rn1 imm4 Rn2; xor_mov Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_mov
+"xor_mov"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
+ State.regs[dstreg2] = EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1000 1010 Rm1 Rn1 Rm2 Rn2; xor_asr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asr
+"xor_asr"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
+ temp = State.regs[dstreg2];
+ temp >>= State.regs[srcreg2];
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1001 1010 Rm1 Rn1 imm4 Rn2; xor_asr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asr
+"xor_asr"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
+ temp = State.regs[dstreg2];
+ temp >>= IMM4;
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1010 1010 Rm1 Rn1 Rm2 Rn2; xor_lsr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_lsr
+"xor_lsr"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
+ State.regs[dstreg2] >>= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1011 1010 Rm1 Rn1 imm4 Rn2; xor_lsr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_lsr
+"xor_lsr"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
+ State.regs[dstreg2] >>= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+
+// 1111 0111 1100 1010 Rm1 Rn1 Rm2 Rn2; xor_asl Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asl
+"xor_asl"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
+ State.regs[dstreg2] <<= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1101 1010 Rm1 Rn1 imm4 Rn2; xor_asl Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asl
+"xor_asl"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
+ State.regs[dstreg2] <<= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0000 1011 Rm1 Rn1 Rm2 Rn2; swhw_add Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_add
+"swhw_add"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
+ State.regs[dstreg2] += State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0001 1011 Rm1 Rn1 imm4 Rn2; swhw_add Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_add
+"swhw_add"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+ | ((State.regs[srcreg1] >> 16) & 0xffff));
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0010 1011 Rm1 Rn1 Rm2 Rn2; swhw_sub Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_sub
+"swhw_sub"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+ | ((State.regs[srcreg1] >> 16) & 0xffff));
+ State.regs[dstreg2] -= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0011 1011 Rm1 Rn1 imm4 Rn2; swhw_sub Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_sub
+"swhw_sub"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+ | ((State.regs[srcreg1] >> 16) & 0xffff));
+ State.regs[dstreg2] -= EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0100 1011 Rm1 Rn1 Rm2 Rn2; swhw_cmp Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_cmp
+"swhw_cmp"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+ State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
+ | ((State.regs[srcreg1] >> 16) & 0xffff));
+}
+
+// 1111 0111 0101 1011 Rm1 Rn1 imm4 Rn2; swhw_cmp Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_cmp
+"swhw_cmp"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+ State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
+ | ((State.regs[srcreg1] >> 16) & 0xffff));
+}
+
+// 1111 0111 0110 1011 Rm1 Rn1 Rm2 Rn2; swhw_mov Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_mov
+"swhw_mov"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+ | ((State.regs[srcreg1] >> 16) & 0xffff));
+ State.regs[dstreg2] = State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0111 1011 Rm1 Rn1 imm4 Rn2; swhw_mov Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_mov
+"swhw_mov"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+ | ((State.regs[srcreg1] >> 16) & 0xffff));
+ State.regs[dstreg2] = EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1000 1011 Rm1 Rn1 Rm2 Rn2; swhw_asr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asr
+"swhw_asr"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+ | ((State.regs[srcreg1] >> 16) & 0xffff));
+ temp = State.regs[dstreg2];
+ temp >>= State.regs[srcreg2];
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1001 1011 Rm1 Rn1 imm4 Rn2; swhw_asr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asr
+"swhw_asr"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+ | ((State.regs[srcreg1] >> 16) & 0xffff));
+ temp = State.regs[dstreg2];
+ temp >>= IMM4;
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1010 1011 Rm1 Rn1 Rm2 Rn2; swhw_lsr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_lsr
+"swhw_lsr"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+ | ((State.regs[srcreg1] >> 16) & 0xffff));
+ State.regs[dstreg2] >>= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1011 1011 Rm1 Rn1 imm4 Rn2; swhw_lsr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_lsr
+"swhw_lsr"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+ | ((State.regs[srcreg1] >> 16) & 0xffff));
+ State.regs[dstreg2] >>= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+
+// 1111 0111 1100 1011 Rm1 Rn1 Rm2 Rn2; swhw_asl Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asl
+"swhw_asl"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+ | ((State.regs[srcreg1] >> 16) & 0xffff));
+ State.regs[dstreg2] <<= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1101 1011 Rm1 Rn1 imm4 Rn2; swhw_asl Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asl
+"swhw_asl"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+ | ((State.regs[srcreg1] >> 16) & 0xffff));
+ State.regs[dstreg2] <<= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0000 1100 Rm1 Rn1 Rm2 Rn2; or_add Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_add
+"or_add"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] | State.regs[srcreg1];
+ State.regs[dstreg2] += State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0001 1100 Rm1 Rn1 imm4 Rn2; or_add Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_add
+"or_add"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] | State.regs[srcreg1];
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0010 1100 Rm1 Rn1 Rm2 Rn2; or_sub Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_sub
+"or_sub"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] | State.regs[srcreg1];
+ State.regs[dstreg2] -= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0011 1100 Rm1 Rn1 imm4 Rn2; or_sub Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_sub
+"or_sub"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] | State.regs[srcreg1];
+ State.regs[dstreg2] -= EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0100 1100 Rm1 Rn1 Rm2 Rn2; or_cmp Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_cmp
+"or_cmp"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+ State.regs[dstreg1] |= State.regs[srcreg1];
+}
+
+// 1111 0111 0101 1100 Rm1 Rn1 imm4 Rn2; or_cmp Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_cmp
+"or_cmp"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+ State.regs[dstreg1] |= State.regs[srcreg1];
+}
+
+// 1111 0111 0110 1100 Rm1 Rn1 Rm2 Rn2; or_mov Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_mov
+"or_mov"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] | State.regs[srcreg1];
+ State.regs[dstreg2] = State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0111 1100 Rm1 Rn1 imm4 Rn2; or_mov Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_mov
+"or_mov"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] | State.regs[srcreg1];
+ State.regs[dstreg2] = EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1000 1100 Rm1 Rn1 Rm2 Rn2; or_asr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asr
+"or_asr"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] | State.regs[srcreg1];
+ temp = State.regs[dstreg2];
+ temp >>= State.regs[srcreg2];
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1001 1100 Rm1 Rn1 imm4 Rn2; or_asr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asr
+"or_asr"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] | State.regs[srcreg1];
+ temp = State.regs[dstreg2];
+ temp >>= IMM4;
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1010 1100 Rm1 Rn1 Rm2 Rn2; or_lsr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_lsr
+"or_lsr"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] | State.regs[srcreg1];
+ State.regs[dstreg2] >>= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1011 1100 Rm1 Rn1 imm4 Rn2; or_lsr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_lsr
+"or_lsr"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] | State.regs[srcreg1];
+ State.regs[dstreg2] >>= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+
+// 1111 0111 1100 1100 Rm1 Rn1 Rm2 Rn2; or_asl Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asl
+"or_asl"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] | State.regs[srcreg1];
+ State.regs[dstreg2] <<= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1101 1100 Rm1 Rn1 imm4 Rn2; or_asl Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asl
+"or_asl"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ result1 = State.regs[dstreg1] | State.regs[srcreg1];
+ State.regs[dstreg2] <<= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0000 1101 Rm1 Rn1 Rm2 Rn2; sat16_add Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_add
+"sat16_add"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ if (State.regs[srcreg1] >= 0x7fff)
+ result1 = 0x7fff;
+ else if (State.regs[srcreg1] <= 0xffff8000)
+ result1 = 0xffff8000;
+ else
+ result1 = State.regs[srcreg1];
+
+ State.regs[dstreg2] += State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0001 1101 Rm1 Rn1 imm4 Rn2; sat16_add Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_add
+"sat16_add"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ if (State.regs[srcreg1] >= 0x7fff)
+ result1 = 0x7fff;
+ else if (State.regs[srcreg1] <= 0xffff8000)
+ result1 = 0xffff8000;
+ else
+ result1 = State.regs[srcreg1];
+
+ State.regs[dstreg2] += EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0010 1101 Rm1 Rn1 Rm2 Rn2; sat16_sub Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_sub
+"sat16_sub"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ if (State.regs[srcreg1] >= 0x7fff)
+ result1 = 0x7fff;
+ else if (State.regs[srcreg1] <= 0xffff8000)
+ result1 = 0xffff8000;
+ else
+ result1 = State.regs[srcreg1];
+
+ State.regs[dstreg2] -= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0011 1101 Rm1 Rn1 imm4 Rn2; sat16_sub Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_sub
+"sat16_sub"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ if (State.regs[srcreg1] >= 0x7fff)
+ result1 = 0x7fff;
+ else if (State.regs[srcreg1] <= 0xffff8000)
+ result1 = 0xffff8000;
+ else
+ result1 = State.regs[srcreg1];
+
+ State.regs[dstreg2] -= EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0100 1101 Rm1 Rn1 Rm2 Rn2; sat16_cmp Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_cmp
+"sat16_cmp"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ State.regs[dstreg1] = result1;
+ if (State.regs[srcreg1] >= 0x7fff)
+ State.regs[dstreg1] = 0x7fff;
+ else if (State.regs[srcreg1] <= 0xffff8000)
+ State.regs[dstreg1] = 0xffff8000;
+ else
+ State.regs[dstreg1] = State.regs[srcreg1];
+}
+
+// 1111 0111 0101 1101 Rm1 Rn1 imm4 Rn2; sat16_cmp Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_cmp
+"sat16_cmp"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+ if (State.regs[srcreg1] >= 0x7fff)
+ State.regs[dstreg1] = 0x7fff;
+ else if (State.regs[srcreg1] <= 0xffff8000)
+ State.regs[dstreg1] = 0xffff8000;
+ else
+ State.regs[dstreg1] = State.regs[srcreg1];
+}
+
+// 1111 0111 0110 1101 Rm1 Rn1 Rm2 Rn2; sat16_mov Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_mov
+"sat16_mov"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ if (State.regs[srcreg1] >= 0x7fff)
+ result1 = 0x7fff;
+ else if (State.regs[srcreg1] <= 0xffff8000)
+ result1 = 0xffff8000;
+ else
+ result1 = State.regs[srcreg1];
+
+ State.regs[dstreg2] = State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 0111 1101 Rm1 Rn1 imm4 Rn2; sat16_mov Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_mov
+"sat16_mov"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ if (State.regs[srcreg1] >= 0x7fff)
+ result1 = 0x7fff;
+ else if (State.regs[srcreg1] <= 0xffff8000)
+ result1 = 0xffff8000;
+ else
+ result1 = State.regs[srcreg1];
+
+ State.regs[dstreg2] = EXTEND4 (IMM4);
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1000 1101 Rm1 Rn1 Rm2 Rn2; sat16_asr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asr
+"sat16_asr"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ if (State.regs[srcreg1] >= 0x7fff)
+ result1 = 0x7fff;
+ else if (State.regs[srcreg1] <= 0xffff8000)
+ result1 = 0xffff8000;
+ else
+ result1 = State.regs[srcreg1];
+
+ temp = State.regs[dstreg2];
+ temp >>= State.regs[srcreg2];
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1001 1101 Rm1 Rn1 imm4 Rn2; sat16_asr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asr
+"sat16_asr"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ if (State.regs[srcreg1] >= 0x7fff)
+ result1 = 0x7fff;
+ else if (State.regs[srcreg1] <= 0xffff8000)
+ result1 = 0xffff8000;
+ else
+ result1 = State.regs[srcreg1];
+
+ temp = State.regs[dstreg2];
+ temp >>= IMM4;
+ State.regs[dstreg2] = temp;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1010 1101 Rm1 Rn1 Rm2 Rn2; sat16_lsr Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_lsr
+"sat16_lsr"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ if (State.regs[srcreg1] >= 0x7fff)
+ result1 = 0x7fff;
+ else if (State.regs[srcreg1] <= 0xffff8000)
+ result1 = 0xffff8000;
+ else
+ result1 = State.regs[srcreg1];
+
+ State.regs[dstreg2] >>= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1011 1101 Rm1 Rn1 imm4 Rn2; sat16_lsr Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_lsr
+"sat16_lsr"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ if (State.regs[srcreg1] >= 0x7fff)
+ result1 = 0x7fff;
+ else if (State.regs[srcreg1] <= 0xffff8000)
+ result1 = 0xffff8000;
+ else
+ result1 = State.regs[srcreg1];
+
+ State.regs[dstreg2] >>= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+
+// 1111 0111 1100 1101 Rm1 Rn1 Rm2 Rn2; sat16_asl Rm1, Rn1, Rm2, Rn2
+8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asl
+"sat16_asl"
+*am33
+{
+ int srcreg1, srcreg2, dstreg1, dstreg2;
+ int result1;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ srcreg2 = translate_rreg (SD_, RM2);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ if (State.regs[srcreg1] >= 0x7fff)
+ result1 = 0x7fff;
+ else if (State.regs[srcreg1] <= 0xffff8000)
+ result1 = 0xffff8000;
+ else
+ result1 = State.regs[srcreg1];
+
+ State.regs[dstreg2] <<= State.regs[srcreg2];
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1101 1101 Rm1 Rn1 imm4 Rn2; sat16_asl Rm1, Rn1, imm4, Rn2
+8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asl
+"sat16_asl"
+*am33
+{
+ int srcreg1, dstreg1, dstreg2;
+ int result1;
+ signed int temp;
+
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM1);
+ dstreg1 = translate_rreg (SD_, RN1);
+ dstreg2 = translate_rreg (SD_, RN2);
+
+ if (State.regs[srcreg1] >= 0x7fff)
+ result1 = 0x7fff;
+ else if (State.regs[srcreg1] <= 0xffff8000)
+ result1 = 0xffff8000;
+ else
+ result1 = State.regs[srcreg1];
+
+ State.regs[dstreg2] <<= IMM4;
+ State.regs[dstreg1] = result1;
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0000; mov_llt (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x0:D2:::mov_llt
+"mov_llt"
+*am33
+{
+ int srcreg, dstreg;
+ int result1;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM);
+ dstreg = translate_rreg (SD_, RN);
+
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND4 (IMM4);
+
+ if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+ State.regs[dstreg] = result1;
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0001; mov_lgt (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x1:D2:::mov_lgt
+"mov_lgt"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM);
+ dstreg = translate_rreg (SD_, RN);
+
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND4 (IMM4);
+
+ if (!((PSW & PSW_Z)
+ || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0010; mov_lge (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x2:D2:::mov_lge
+"mov_lge"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM);
+ dstreg = translate_rreg (SD_, RN);
+
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND4 (IMM4);
+
+ if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0011; mov_lle (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x3:D2:::mov_lle
+"mov_lle"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM);
+ dstreg = translate_rreg (SD_, RN);
+
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND4 (IMM4);
+
+ if ((PSW & PSW_Z)
+ || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0100; mov_lcs (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x4:D2:::mov_lcs
+"mov_lcs"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM);
+ dstreg = translate_rreg (SD_, RN);
+
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND4 (IMM4);
+
+ if (PSW & PSW_C)
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0101; mov_lhi (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x5:D2:::mov_lhi
+"mov_lhi"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM);
+ dstreg = translate_rreg (SD_, RN);
+
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND4 (IMM4);
+
+ if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0110; mov_lcc (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x6:D2:::mov_lcc
+"mov_lcc"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM);
+ dstreg = translate_rreg (SD_, RN);
+
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND4 (IMM4);
+
+ if (!(PSW & PSW_C))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0111; mov_lls (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x7:D2:::mov_lls
+"mov_lls"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM);
+ dstreg = translate_rreg (SD_, RN);
+
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND4 (IMM4);
+
+ if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 1000; mov_leq (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x8:D2:::mov_leq
+"mov_leq"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM);
+ dstreg = translate_rreg (SD_, RN);
+
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND4 (IMM4);
+
+ if (PSW & PSW_Z)
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 1001; mov_lne (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x9:D2:::mov_lne
+"mov_lne"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM);
+ dstreg = translate_rreg (SD_, RN);
+
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND4 (IMM4);
+
+ if (!(PSW & PSW_Z))
+ {
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+ }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 1010; mov_lra (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0xa:D2:::mov_lra
+"mov_lra"
+*am33
+{
+ int srcreg, dstreg;
+
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM);
+ dstreg = translate_rreg (SD_, RN);
+
+ State.regs[dstreg] = load_word (State.regs[srcreg]);
+ State.regs[srcreg] += EXTEND4 (IMM4);
+
+ State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+ nia = PC;
+}
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