New Cell SPU port.

32 files changed, 3648 insertions, 438 deletions

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 0dd9d97d758..38f0e8c9b53 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,24 @@
+2006-10-25  Alan Modra  <amodra@bigpond.net.au>
+	    Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
+	    Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
+	    Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
+	    Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
+
+	* cpu-spu.c: New file.
+	* elf32-spu.c: New file.
+	* elf32-spu.h: New file.
+	* archures.c: Add SPU support.
+	* config.bfd: Likewise.
+	* configure.in: Likewise.
+	* reloc.c: Likewise.
+	* targets.c: Likewise.
+	* Makefile.am: Likewise.  Run "make dep-am".
+	* libbfd.h: Regenerate.
+	* bfd-in2.h: Regenerate.
+	* Makefile.in: Regenerate.
+	* configure: Regenerate.
+	* po/SRC-POTFILES.in: Regenerate.
+
 2006-10-23  Alan Modra  <amodra@bigpond.net.au>
 
 	* elf64-ppc.c (ppc64_elf_edit_opd): Clarify comment.
diff --git a/bfd/Makefile.am b/bfd/Makefile.am
index df9b2a9da54..435b30b3c35 100644
--- a/bfd/Makefile.am
+++ b/bfd/Makefile.am
@@ -106,6 +106,7 @@ ALL_MACHINES = \
 	cpu-score.lo \
 	cpu-sh.lo \
 	cpu-sparc.lo \
+	cpu-spu.lo \
 	cpu-tic30.lo \
 	cpu-tic4x.lo \
 	cpu-tic54x.lo \
@@ -169,6 +170,7 @@ ALL_MACHINES_CFILES = \
 	cpu-score.c \
 	cpu-sh.c \
 	cpu-sparc.c \
+	cpu-spu.c \
 	cpu-tic30.c \
 	cpu-tic4x.c \
 	cpu-tic54x.c \
@@ -280,6 +282,7 @@ BFD32_BACKENDS = \
 	elf32-sh64-com.lo \
 	elfxx-sparc.lo \
 	elf32-sparc.lo \
+	elf32-spu.lo \
 	elf32-v850.lo \
 	elf32-vax.lo \
 	elf32-xstormy16.lo \
@@ -455,6 +458,7 @@ BFD32_BACKENDS_CFILES = \
 	elf32-sh-symbian.c \
 	elfxx-sparc.c \
 	elf32-sparc.c \
+	elf32-spu.c \
 	elf32-v850.c \
 	elf32-vax.c \
 	elf32-xstormy16.c \
@@ -1074,11 +1078,12 @@ cpu-pj.lo: cpu-pj.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
 cpu-powerpc.lo: cpu-powerpc.c $(INCDIR)/filenames.h \
   $(INCDIR)/hashtab.h
 cpu-rs6000.lo: cpu-rs6000.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
-cpu-score.lo: cpu-score.c $(INCDIR)/filenames.h
 cpu-s390.lo: cpu-s390.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
+cpu-score.lo: cpu-score.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
 cpu-sh.lo: cpu-sh.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
   $(srcdir)/../opcodes/sh-opc.h
 cpu-sparc.lo: cpu-sparc.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
+cpu-spu.lo: cpu-spu.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
 cpu-tic30.lo: cpu-tic30.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
 cpu-tic4x.lo: cpu-tic4x.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
 cpu-tic54x.lo: cpu-tic54x.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
@@ -1453,14 +1458,15 @@ elf32-sh64-com.lo: elf32-sh64-com.c $(INCDIR)/filenames.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h elf32-sh64.h \
   $(srcdir)/../opcodes/sh64-opc.h
-elf32-score.lo: elf32-score.c $(INCDIR)/filenames.h \
-  elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/elf/score.h \
-  $(INCDIR)/elf/reloc-macros.h elf32-target.h
 elf32-s390.lo: elf32-s390.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/s390.h \
   $(INCDIR)/elf/reloc-macros.h elf32-target.h
+elf32-score.lo: elf32-score.c $(INCDIR)/filenames.h \
+  $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/elf/score.h $(INCDIR)/elf/reloc-macros.h \
+  elf32-target.h
 elf32-sh.lo: elf32-sh.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h elf-vxworks.h \
@@ -1482,6 +1488,10 @@ elf32-sparc.lo: elf32-sparc.c $(INCDIR)/filenames.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/sparc.h \
   $(INCDIR)/elf/reloc-macros.h $(INCDIR)/opcode/sparc.h \
   elfxx-sparc.h elf-vxworks.h elf32-target.h
+elf32-spu.lo: elf32-spu.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \
+  $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/spu.h \
+  $(INCDIR)/elf/reloc-macros.h elf32-spu.h elf32-target.h
 elf32-v850.lo: elf32-v850.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/v850.h \
@@ -1845,6 +1855,21 @@ nlm32-alpha.lo: nlm32-alpha.c $(INCDIR)/filenames.h \
 nlm64.lo: nlm64.c nlmcode.h $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
   libnlm.h $(INCDIR)/nlm/common.h $(INCDIR)/nlm/internal.h \
   $(INCDIR)/nlm/external.h
+coff-x86_64.lo: coff-x86_64.c $(INCDIR)/filenames.h \
+  $(INCDIR)/hashtab.h $(INCDIR)/coff/x86_64.h $(INCDIR)/coff/external.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/pe.h libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/libiberty.h coffcode.h \
+  coffswap.h
+pe-x86_64.lo: pe-x86_64.c $(INCDIR)/filenames.h coff-x86_64.c \
+  $(INCDIR)/hashtab.h $(INCDIR)/coff/x86_64.h $(INCDIR)/coff/external.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/pe.h libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/libiberty.h coffcode.h \
+  peicode.h libpei.h
+pei-x86_64.lo: pei-x86_64.c $(INCDIR)/filenames.h coff-x86_64.c \
+  $(INCDIR)/hashtab.h $(INCDIR)/coff/x86_64.h $(INCDIR)/coff/external.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/pe.h libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/libiberty.h coffcode.h \
+  peicode.h libpei.h
 aix386-core.lo: aix386-core.c $(INCDIR)/filenames.h \
   $(INCDIR)/hashtab.h $(INCDIR)/coff/i386.h $(INCDIR)/coff/external.h \
   $(INCDIR)/coff/internal.h libcoff.h $(INCDIR)/bfdlink.h
diff --git a/bfd/Makefile.in b/bfd/Makefile.in
index 312b7308dee..5bde689339e 100644
--- a/bfd/Makefile.in
+++ b/bfd/Makefile.in
@@ -337,6 +337,7 @@ ALL_MACHINES = \
 	cpu-score.lo \
 	cpu-sh.lo \
 	cpu-sparc.lo \
+	cpu-spu.lo \
 	cpu-tic30.lo \
 	cpu-tic4x.lo \
 	cpu-tic54x.lo \
@@ -400,6 +401,7 @@ ALL_MACHINES_CFILES = \
 	cpu-score.c \
 	cpu-sh.c \
 	cpu-sparc.c \
+	cpu-spu.c \
 	cpu-tic30.c \
 	cpu-tic4x.c \
 	cpu-tic54x.c \
@@ -512,6 +514,7 @@ BFD32_BACKENDS = \
 	elf32-sh64-com.lo \
 	elfxx-sparc.lo \
 	elf32-sparc.lo \
+	elf32-spu.lo \
 	elf32-v850.lo \
 	elf32-vax.lo \
 	elf32-xstormy16.lo \
@@ -687,6 +690,7 @@ BFD32_BACKENDS_CFILES = \
 	elf32-sh-symbian.c \
 	elfxx-sparc.c \
 	elf32-sparc.c \
+	elf32-spu.c \
 	elf32-v850.c \
 	elf32-vax.c \
 	elf32-xstormy16.c \
@@ -1635,11 +1639,12 @@ cpu-pj.lo: cpu-pj.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
 cpu-powerpc.lo: cpu-powerpc.c $(INCDIR)/filenames.h \
   $(INCDIR)/hashtab.h
 cpu-rs6000.lo: cpu-rs6000.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
-cpu-score.lo: cpu-score.c $(INCDIR)/filenames.h
 cpu-s390.lo: cpu-s390.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
+cpu-score.lo: cpu-score.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
 cpu-sh.lo: cpu-sh.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
   $(srcdir)/../opcodes/sh-opc.h
 cpu-sparc.lo: cpu-sparc.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
+cpu-spu.lo: cpu-spu.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
 cpu-tic30.lo: cpu-tic30.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
 cpu-tic4x.lo: cpu-tic4x.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
 cpu-tic54x.lo: cpu-tic54x.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h
@@ -2014,14 +2019,15 @@ elf32-sh64-com.lo: elf32-sh64-com.c $(INCDIR)/filenames.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h elf32-sh64.h \
   $(srcdir)/../opcodes/sh64-opc.h
-elf32-score.lo: elf32-score.c $(INCDIR)/filenames.h \
-  elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/elf/score.h \
-  $(INCDIR)/elf/reloc-macros.h elf32-target.h
 elf32-s390.lo: elf32-s390.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/s390.h \
   $(INCDIR)/elf/reloc-macros.h elf32-target.h
+elf32-score.lo: elf32-score.c $(INCDIR)/filenames.h \
+  $(INCDIR)/hashtab.h $(INCDIR)/libiberty.h elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/elf/score.h $(INCDIR)/elf/reloc-macros.h \
+  elf32-target.h
 elf32-sh.lo: elf32-sh.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h elf-vxworks.h \
@@ -2043,6 +2049,10 @@ elf32-sparc.lo: elf32-sparc.c $(INCDIR)/filenames.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/sparc.h \
   $(INCDIR)/elf/reloc-macros.h $(INCDIR)/opcode/sparc.h \
   elfxx-sparc.h elf-vxworks.h elf32-target.h
+elf32-spu.lo: elf32-spu.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \
+  $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/spu.h \
+  $(INCDIR)/elf/reloc-macros.h elf32-spu.h elf32-target.h
 elf32-v850.lo: elf32-v850.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/v850.h \
@@ -2406,6 +2416,21 @@ nlm32-alpha.lo: nlm32-alpha.c $(INCDIR)/filenames.h \
 nlm64.lo: nlm64.c nlmcode.h $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \
   libnlm.h $(INCDIR)/nlm/common.h $(INCDIR)/nlm/internal.h \
   $(INCDIR)/nlm/external.h
+coff-x86_64.lo: coff-x86_64.c $(INCDIR)/filenames.h \
+  $(INCDIR)/hashtab.h $(INCDIR)/coff/x86_64.h $(INCDIR)/coff/external.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/pe.h libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/libiberty.h coffcode.h \
+  coffswap.h
+pe-x86_64.lo: pe-x86_64.c $(INCDIR)/filenames.h coff-x86_64.c \
+  $(INCDIR)/hashtab.h $(INCDIR)/coff/x86_64.h $(INCDIR)/coff/external.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/pe.h libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/libiberty.h coffcode.h \
+  peicode.h libpei.h
+pei-x86_64.lo: pei-x86_64.c $(INCDIR)/filenames.h coff-x86_64.c \
+  $(INCDIR)/hashtab.h $(INCDIR)/coff/x86_64.h $(INCDIR)/coff/external.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/pe.h libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/libiberty.h coffcode.h \
+  peicode.h libpei.h
 aix386-core.lo: aix386-core.c $(INCDIR)/filenames.h \
   $(INCDIR)/hashtab.h $(INCDIR)/coff/i386.h $(INCDIR)/coff/external.h \
   $(INCDIR)/coff/internal.h libcoff.h $(INCDIR)/bfdlink.h
diff --git a/bfd/archures.c b/bfd/archures.c
index eb3831f311c..5029cb03f80 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -136,6 +136,8 @@ DESCRIPTION
 .{* Nonzero if MACH is a 64 bit sparc architecture.  *}
 .#define bfd_mach_sparc_64bit_p(mach) \
 .  ((mach) >= bfd_mach_sparc_v9 && (mach) != bfd_mach_sparc_v8plusb)
+.  bfd_arch_spu,       {* PowerPC SPU *}
+.#define bfd_mach_spu		256 
 .  bfd_arch_mips,      {* MIPS Rxxxx *}
 .#define bfd_mach_mips3000		3000
 .#define bfd_mach_mips3900		3900
@@ -471,6 +473,7 @@ extern const bfd_arch_info_type bfd_s390_arch;
 extern const bfd_arch_info_type bfd_score_arch;
 extern const bfd_arch_info_type bfd_sh_arch;
 extern const bfd_arch_info_type bfd_sparc_arch;
+extern const bfd_arch_info_type bfd_spu_arch;
 extern const bfd_arch_info_type bfd_tic30_arch;
 extern const bfd_arch_info_type bfd_tic4x_arch;
 extern const bfd_arch_info_type bfd_tic54x_arch;
@@ -537,6 +540,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] =
     &bfd_score_arch,
     &bfd_sh_arch,
     &bfd_sparc_arch,
+    &bfd_spu_arch,
     &bfd_tic30_arch,
     &bfd_tic4x_arch,
     &bfd_tic54x_arch,
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 0fc6232de57..882f61ad969 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1761,6 +1761,8 @@ enum bfd_architecture
 /* Nonzero if MACH is a 64 bit sparc architecture.  */
 #define bfd_mach_sparc_64bit_p(mach) \
   ((mach) >= bfd_mach_sparc_v9 && (mach) != bfd_mach_sparc_v8plusb)
+  bfd_arch_spu,       /* PowerPC SPU */
+#define bfd_mach_spu           256 
   bfd_arch_mips,      /* MIPS Rxxxx */
 #define bfd_mach_mips3000              3000
 #define bfd_mach_mips3900              3900
@@ -2452,6 +2454,20 @@ relocation types already defined.  */
   BFD_RELOC_SPARC_TLS_TPOFF32,
   BFD_RELOC_SPARC_TLS_TPOFF64,
 
+/* SPU Relocations.  */
+  BFD_RELOC_SPU_IMM7,
+  BFD_RELOC_SPU_IMM8,
+  BFD_RELOC_SPU_IMM10,
+  BFD_RELOC_SPU_IMM10W,
+  BFD_RELOC_SPU_IMM16,
+  BFD_RELOC_SPU_IMM16W,
+  BFD_RELOC_SPU_IMM18,
+  BFD_RELOC_SPU_PCREL9a,
+  BFD_RELOC_SPU_PCREL9b,
+  BFD_RELOC_SPU_PCREL16,
+  BFD_RELOC_SPU_LO16,
+  BFD_RELOC_SPU_HI16,
+
 /* Alpha ECOFF and ELF relocations.  Some of these treat the symbol or
 "addend" in some special way.
 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
diff --git a/bfd/config.bfd b/bfd/config.bfd
index 31dbf0e9fae..41bbda9c0eb 100644
--- a/bfd/config.bfd
+++ b/bfd/config.bfd
@@ -95,6 +95,7 @@ rs6000)		 targ_archs="bfd_rs6000_arch bfd_powerpc_arch" ;;
 s390*)		 targ_archs=bfd_s390_arch ;;
 sh*)		 targ_archs=bfd_sh_arch ;;
 sparc*)		 targ_archs=bfd_sparc_arch ;;
+spu*)            targ_archs=bfd_spu_arch ;;
 strongarm*)	 targ_archs=bfd_arm_arch ;;
 thumb*)		 targ_archs=bfd_arm_arch ;;
 v850*)		 targ_archs=bfd_v850_arch ;;
@@ -1382,6 +1383,11 @@ case "${targ}" in
     targ_underscore=yes
     ;;
 
+  spu-*-elf)
+    targ_defvec=bfd_elf32_spu_vec
+    targ_selvecs="bfd_elf32_powerpc_vec bfd_elf64_powerpc_vec"
+    ;;
+
 #if HAVE_host_aout_vec
   tahoe-*-*)
     targ_defvec=host_aout_vec
diff --git a/bfd/configure b/bfd/configure
index fa61beedffd..bc138ff93ad 100755
--- a/bfd/configure
+++ b/bfd/configure
@@ -10895,6 +10895,7 @@ do
     bfd_elf32_shvxworks_vec)	tb="$tb elf32-sh.lo elf-vxworks.lo elf32.lo $elf coff-sh.lo" ;;
     bfd_elf32_sparc_vec)	tb="$tb elf32-sparc.lo elfxx-sparc.lo elf-vxworks.lo elf32.lo $elf" ;;
     bfd_elf32_sparc_vxworks_vec) tb="$tb elf32-sparc.lo elfxx-sparc.lo elf-vxworks.lo elf32.lo $elf" ;;
+    bfd_elf32_spu_vec)		tb="$tb elf32-spu.lo elf32.lo $elf" ;;
     bfd_elf32_tradbigmips_vec)  tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
     bfd_elf32_tradlittlemips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
     bfd_elf32_us_cris_vec)	tb="$tb elf32-cris.lo elf32.lo $elf" ;;
diff --git a/bfd/configure.in b/bfd/configure.in
index 05324348335..fa0d50f7d15 100644
--- a/bfd/configure.in
+++ b/bfd/configure.in
@@ -685,6 +685,7 @@ do
     bfd_elf32_shvxworks_vec)	tb="$tb elf32-sh.lo elf-vxworks.lo elf32.lo $elf coff-sh.lo" ;;
     bfd_elf32_sparc_vec)	tb="$tb elf32-sparc.lo elfxx-sparc.lo elf-vxworks.lo elf32.lo $elf" ;;
     bfd_elf32_sparc_vxworks_vec) tb="$tb elf32-sparc.lo elfxx-sparc.lo elf-vxworks.lo elf32.lo $elf" ;;
+    bfd_elf32_spu_vec)		tb="$tb elf32-spu.lo elf32.lo $elf" ;;
     bfd_elf32_tradbigmips_vec)  tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
     bfd_elf32_tradlittlemips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
     bfd_elf32_us_cris_vec)	tb="$tb elf32-cris.lo elf32.lo $elf" ;;
diff --git a/bfd/cpu-spu.c b/bfd/cpu-spu.c
new file mode 100644
index 00000000000..25127f47791
--- /dev/null
+++ b/bfd/cpu-spu.c
@@ -0,0 +1,54 @@
+/* Copyright 2006 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#include "bfd.h"
+#include "sysdep.h"
+#include "libbfd.h"
+
+
+static const bfd_arch_info_type *
+spu_compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b)
+{
+  BFD_ASSERT (a->arch == bfd_arch_spu);
+  switch (b->arch)
+    {
+    default:
+      return NULL;
+    case bfd_arch_spu:
+      return bfd_default_compatible (a, b);
+    }
+  /*NOTREACHED*/
+}
+
+const bfd_arch_info_type bfd_spu_arch[] =
+{
+  {
+    32,	/* 32 bits in a word */
+    32,	/* 32 bits in an address */
+    8,	/* 8 bits in a byte */
+    bfd_arch_spu,	/* architecture */
+    bfd_mach_spu,	/* machine */
+    "spu",		/* architecture name */
+    "spu:256K",		/* printable name */
+    3,			/* aligned power */
+    TRUE, 		/* the default machine for the architecture */
+    spu_compatible,	/* the spu is only compatible with itself, see above */
+    bfd_default_scan,
+    0,			/* next -- there are none! */
+  }
+};
diff --git a/bfd/elf32-spu.c b/bfd/elf32-spu.c
new file mode 100644
index 00000000000..5eb0f0523a5
--- /dev/null
+++ b/bfd/elf32-spu.c
@@ -0,0 +1,1749 @@
+/* SPU specific support for 32-bit ELF
+
+   Copyright 2006 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#include "bfd.h"
+#include "sysdep.h"
+#include "bfdlink.h"
+#include "libbfd.h"
+#include "elf-bfd.h"
+#include "elf/spu.h"
+#include "elf32-spu.h"
+
+/* We use RELA style relocs.  Don't define USE_REL.  */
+
+static bfd_reloc_status_type spu_elf_rel9 (bfd *, arelent *, asymbol *,
+					   void *, asection *,
+					   bfd *, char **);
+
+/* Values of type 'enum elf_spu_reloc_type' are used to index this
+   array, so it must be declared in the order of that type.  */
+
+static reloc_howto_type elf_howto_table[] = {
+  HOWTO (R_SPU_NONE,       0, 0,  0, FALSE,  0, complain_overflow_dont,
+	 bfd_elf_generic_reloc, "SPU_NONE",
+	 FALSE, 0, 0x00000000, FALSE),
+  HOWTO (R_SPU_ADDR10,     4, 2, 10, FALSE, 14, complain_overflow_bitfield,
+	 bfd_elf_generic_reloc, "SPU_ADDR10",
+	 FALSE, 0, 0x00ffc000, FALSE),
+  HOWTO (R_SPU_ADDR16,     2, 2, 16, FALSE,  7, complain_overflow_bitfield,
+	 bfd_elf_generic_reloc, "SPU_ADDR16",
+	 FALSE, 0, 0x007fff80, FALSE),
+  HOWTO (R_SPU_ADDR16_HI, 16, 2, 16, FALSE,  7, complain_overflow_bitfield,
+	 bfd_elf_generic_reloc, "SPU_ADDR16_HI",
+	 FALSE, 0, 0x007fff80, FALSE),
+  HOWTO (R_SPU_ADDR16_LO,  0, 2, 16, FALSE,  7, complain_overflow_dont,
+	 bfd_elf_generic_reloc, "SPU_ADDR16_LO",
+	 FALSE, 0, 0x007fff80, FALSE),
+  HOWTO (R_SPU_ADDR18,     0, 2, 18, FALSE,  7, complain_overflow_bitfield,
+	 bfd_elf_generic_reloc, "SPU_ADDR18",
+	 FALSE, 0, 0x01ffff80, FALSE),
+  HOWTO (R_SPU_ADDR32,   0, 2, 32, FALSE,  0, complain_overflow_dont,
+	 bfd_elf_generic_reloc, "SPU_ADDR32",
+	 FALSE, 0, 0xffffffff, FALSE),
+  HOWTO (R_SPU_REL16,      2, 2, 16,  TRUE,  7, complain_overflow_bitfield,
+	 bfd_elf_generic_reloc, "SPU_REL16",
+	 FALSE, 0, 0x007fff80, TRUE),
+  HOWTO (R_SPU_ADDR7,      0, 2,  7, FALSE, 14, complain_overflow_dont,
+	 bfd_elf_generic_reloc, "SPU_ADDR7",
+	 FALSE, 0, 0x001fc000, FALSE),
+  HOWTO (R_SPU_REL9,       2, 2,  9,  TRUE,  0, complain_overflow_signed,
+	 spu_elf_rel9,          "SPU_REL9",
+	 FALSE, 0, 0x0180007f, TRUE),
+  HOWTO (R_SPU_REL9I,      2, 2,  9,  TRUE,  0, complain_overflow_signed,
+	 spu_elf_rel9,          "SPU_REL9I",
+	 FALSE, 0, 0x0000c07f, TRUE),
+  HOWTO (R_SPU_ADDR10I,    0, 2, 10, FALSE, 14, complain_overflow_signed,
+	 bfd_elf_generic_reloc, "SPU_ADDR10I",
+	 FALSE, 0, 0x00ffc000, FALSE),
+  HOWTO (R_SPU_ADDR16I,    0, 2, 16, FALSE,  7, complain_overflow_signed,
+	 bfd_elf_generic_reloc, "SPU_ADDR16I",
+	 FALSE, 0, 0x007fff80, FALSE),
+  HOWTO (R_SPU_REL32,   0, 2, 32, TRUE,  0, complain_overflow_dont,
+	 bfd_elf_generic_reloc, "SPU_REL32",
+	 FALSE, 0, 0xffffffff, TRUE),
+};
+
+static struct bfd_elf_special_section const spu_elf_special_sections[] = {
+  { ".toe", 4, 0, SHT_NOBITS, SHF_ALLOC },
+  { NULL, 0, 0, 0, 0 }
+};
+
+static enum elf_spu_reloc_type
+spu_elf_bfd_to_reloc_type (bfd_reloc_code_real_type code)
+{
+  switch (code)
+    {
+    default:
+      return R_SPU_NONE;
+    case BFD_RELOC_SPU_IMM10W:
+      return R_SPU_ADDR10;
+    case BFD_RELOC_SPU_IMM16W:
+      return R_SPU_ADDR16;
+    case BFD_RELOC_SPU_LO16:
+      return R_SPU_ADDR16_LO;
+    case BFD_RELOC_SPU_HI16:
+      return R_SPU_ADDR16_HI;
+    case BFD_RELOC_SPU_IMM18:
+      return R_SPU_ADDR18;
+    case BFD_RELOC_SPU_PCREL16:
+      return R_SPU_REL16;
+    case BFD_RELOC_SPU_IMM7:
+      return R_SPU_ADDR7;
+    case BFD_RELOC_SPU_IMM8:
+      return R_SPU_NONE;
+    case BFD_RELOC_SPU_PCREL9a:
+      return R_SPU_REL9;
+    case BFD_RELOC_SPU_PCREL9b:
+      return R_SPU_REL9I;
+    case BFD_RELOC_SPU_IMM10:
+      return R_SPU_ADDR10I;
+    case BFD_RELOC_SPU_IMM16:
+      return R_SPU_ADDR16I;
+    case BFD_RELOC_32:
+      return R_SPU_ADDR32;
+    case BFD_RELOC_32_PCREL:
+      return R_SPU_REL32;
+    }
+}
+
+static void
+spu_elf_info_to_howto (bfd *abfd ATTRIBUTE_UNUSED,
+		       arelent *cache_ptr,
+		       Elf_Internal_Rela *dst)
+{
+  enum elf_spu_reloc_type r_type;
+
+  r_type = (enum elf_spu_reloc_type) ELF32_R_TYPE (dst->r_info);
+  BFD_ASSERT (r_type < R_SPU_max);
+  cache_ptr->howto = &elf_howto_table[(int) r_type];
+}
+
+static reloc_howto_type *
+spu_elf_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
+			   bfd_reloc_code_real_type code)
+{
+  return elf_howto_table + spu_elf_bfd_to_reloc_type (code);
+}
+
+/* Apply R_SPU_REL9 and R_SPU_REL9I relocs.  */
+
+static bfd_reloc_status_type
+spu_elf_rel9 (bfd *abfd, arelent *reloc_entry, asymbol *symbol,
+	      void *data, asection *input_section,
+	      bfd *output_bfd, char **error_message)
+{
+  bfd_size_type octets;
+  bfd_vma val;
+  long insn;
+
+  /* If this is a relocatable link (output_bfd test tells us), just
+     call the generic function.  Any adjustment will be done at final
+     link time.  */
+  if (output_bfd != NULL)
+    return bfd_elf_generic_reloc (abfd, reloc_entry, symbol, data,
+				  input_section, output_bfd, error_message);
+
+  if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
+    return bfd_reloc_outofrange;
+  octets = reloc_entry->address * bfd_octets_per_byte (abfd);
+
+  /* Get symbol value.  */
+  val = 0;
+  if (!bfd_is_com_section (symbol->section))
+    val = symbol->value;
+  if (symbol->section->output_section)
+    val += symbol->section->output_section->vma;
+
+  val += reloc_entry->addend;
+
+  /* Make it pc-relative.  */
+  val -= input_section->output_section->vma + input_section->output_offset;
+
+  val >>= 2;
+  if (val + 256 >= 512)
+    return bfd_reloc_overflow;
+
+  insn = bfd_get_32 (abfd, (bfd_byte *) data + octets);
+
+  /* Move two high bits of value to REL9I and REL9 position.
+     The mask will take care of selecting the right field.  */
+  val = (val & 0x7f) | ((val & 0x180) << 7) | ((val & 0x180) << 16);
+  insn &= ~reloc_entry->howto->dst_mask;
+  insn |= val & reloc_entry->howto->dst_mask;
+  bfd_put_32 (abfd, insn, (bfd_byte *) data + octets);
+  return bfd_reloc_ok;
+}
+
+static bfd_boolean
+spu_elf_new_section_hook (bfd *abfd, asection *sec)
+{
+  if (!sec->used_by_bfd)
+    {
+      struct _spu_elf_section_data *sdata;
+
+      sdata = bfd_zalloc (abfd, sizeof (*sdata));
+      if (sdata == NULL)
+	return FALSE;
+      sec->used_by_bfd = sdata;
+    }
+
+  return _bfd_elf_new_section_hook (abfd, sec);
+}
+
+/* Specially mark defined symbols named _EAR_* with BSF_KEEP so that
+   strip --strip-unneeded will not remove them.  */
+
+static void
+spu_elf_backend_symbol_processing (bfd *abfd ATTRIBUTE_UNUSED, asymbol *sym)
+{
+  if (sym->name != NULL
+      && sym->section != bfd_abs_section_ptr
+      && strncmp (sym->name, "_EAR_", 5) == 0)
+    sym->flags |= BSF_KEEP;
+}
+
+/* SPU ELF linker hash table.  */
+
+struct spu_link_hash_table
+{
+  struct elf_link_hash_table elf;
+
+  /* The stub hash table.  */
+  struct bfd_hash_table stub_hash_table;
+
+  /* Shortcuts to overlay sections.  */
+  asection *stub;
+  asection *ovtab;
+
+  struct elf_link_hash_entry *ovly_load;
+
+  /* An array of two output sections per overlay region, chosen such that
+     the first section vma is the overlay buffer vma (ie. the section has
+     the lowest vma in the group that occupy the region), and the second
+     section vma+size specifies the end of the region.  We keep pointers
+     to sections like this because section vmas may change when laying
+     them out.  */
+  asection **ovl_region;
+
+  /* Number of overlay buffers.  */
+  unsigned int num_buf;
+
+  /* Total number of overlays.  */
+  unsigned int num_overlays;
+
+  /* Set if we should emit symbols for stubs.  */
+  unsigned int emit_stub_syms:1;
+
+  /* Set if we want stubs on calls out of overlay regions to
+     non-overlay regions.  */
+  unsigned int non_overlay_stubs : 1;
+
+  /* Set on error.  */
+  unsigned int stub_overflow : 1;
+};
+
+#define spu_hash_table(p) \
+  ((struct spu_link_hash_table *) ((p)->hash))
+
+struct spu_stub_hash_entry
+{
+  struct bfd_hash_entry root;
+
+  /* Destination of this stub.  */
+  asection *target_section;
+  bfd_vma target_off;
+
+  /* Offset of entry in stub section.  */
+  bfd_vma off;
+
+  /* Offset from this stub to stub that loads the overlay index.  */
+  bfd_vma delta;
+};
+
+/* Create an entry in a spu stub hash table.  */
+
+static struct bfd_hash_entry *
+stub_hash_newfunc (struct bfd_hash_entry *entry,
+		   struct bfd_hash_table *table,
+		   const char *string)
+{
+  /* Allocate the structure if it has not already been allocated by a
+     subclass.  */
+  if (entry == NULL)
+    {
+      entry = bfd_hash_allocate (table, sizeof (struct spu_stub_hash_entry));
+      if (entry == NULL)
+	return entry;
+    }
+
+  /* Call the allocation method of the superclass.  */
+  entry = bfd_hash_newfunc (entry, table, string);
+  if (entry != NULL)
+    {
+      struct spu_stub_hash_entry *sh = (struct spu_stub_hash_entry *) entry;
+
+      sh->target_section = NULL;
+      sh->target_off = 0;
+      sh->off = 0;
+      sh->delta = 0;
+    }
+
+  return entry;
+}
+
+/* Create a spu ELF linker hash table.  */
+
+static struct bfd_link_hash_table *
+spu_elf_link_hash_table_create (bfd *abfd)
+{
+  struct spu_link_hash_table *htab;
+
+  htab = bfd_malloc (sizeof (*htab));
+  if (htab == NULL)
+    return NULL;
+
+  if (!_bfd_elf_link_hash_table_init (&htab->elf, abfd,
+				      _bfd_elf_link_hash_newfunc,
+				      sizeof (struct elf_link_hash_entry)))
+    {
+      free (htab);
+      return NULL;
+    }
+
+  /* Init the stub hash table too.  */
+  if (!bfd_hash_table_init (&htab->stub_hash_table, stub_hash_newfunc,
+			    sizeof (struct spu_stub_hash_entry)))
+    return NULL;
+
+  memset (&htab->stub, 0,
+	  sizeof (*htab) - offsetof (struct spu_link_hash_table, stub));
+
+  return &htab->elf.root;
+}
+
+/* Free the derived linker hash table.  */
+
+static void
+spu_elf_link_hash_table_free (struct bfd_link_hash_table *hash)
+{
+  struct spu_link_hash_table *ret = (struct spu_link_hash_table *) hash;
+
+  bfd_hash_table_free (&ret->stub_hash_table);
+  _bfd_generic_link_hash_table_free (hash);
+}
+
+/* Find the symbol for the given R_SYMNDX in IBFD and set *HP and *SYMP
+   to (hash, NULL) for global symbols, and (NULL, sym) for locals.  Set
+   *SYMSECP to the symbol's section.  *LOCSYMSP caches local syms.  */
+
+static bfd_boolean
+get_sym_h (struct elf_link_hash_entry **hp,
+	   Elf_Internal_Sym **symp,
+	   asection **symsecp,
+	   Elf_Internal_Sym **locsymsp,
+	   unsigned long r_symndx,
+	   bfd *ibfd)
+{
+  Elf_Internal_Shdr *symtab_hdr = &elf_tdata (ibfd)->symtab_hdr;
+
+  if (r_symndx >= symtab_hdr->sh_info)
+    {
+      struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (ibfd);
+      struct elf_link_hash_entry *h;
+
+      h = sym_hashes[r_symndx - symtab_hdr->sh_info];
+      while (h->root.type == bfd_link_hash_indirect
+	     || h->root.type == bfd_link_hash_warning)
+	h = (struct elf_link_hash_entry *) h->root.u.i.link;
+
+      if (hp != NULL)
+	*hp = h;
+
+      if (symp != NULL)
+	*symp = NULL;
+
+      if (symsecp != NULL)
+	{
+	  asection *symsec = NULL;
+	  if (h->root.type == bfd_link_hash_defined
+	      || h->root.type == bfd_link_hash_defweak)
+	    symsec = h->root.u.def.section;
+	  *symsecp = symsec;
+	}
+    }
+  else
+    {
+      Elf_Internal_Sym *sym;
+      Elf_Internal_Sym *locsyms = *locsymsp;
+
+      if (locsyms == NULL)
+	{
+	  locsyms = (Elf_Internal_Sym *) symtab_hdr->contents;
+	  if (locsyms == NULL)
+	    locsyms = bfd_elf_get_elf_syms (ibfd, symtab_hdr,
+					    symtab_hdr->sh_info,
+					    0, NULL, NULL, NULL);
+	  if (locsyms == NULL)
+	    return FALSE;
+	  *locsymsp = locsyms;
+	}
+      sym = locsyms + r_symndx;
+
+      if (hp != NULL)
+	*hp = NULL;
+
+      if (symp != NULL)
+	*symp = sym;
+
+      if (symsecp != NULL)
+	{
+	  asection *symsec = NULL;
+	  if ((sym->st_shndx != SHN_UNDEF
+	       && sym->st_shndx < SHN_LORESERVE)
+	      || sym->st_shndx > SHN_HIRESERVE)
+	    symsec = bfd_section_from_elf_index (ibfd, sym->st_shndx);
+	  *symsecp = symsec;
+	}
+    }
+  return TRUE;
+}
+
+/* Build a name for an entry in the stub hash table.  The input section
+   id isn't really necessary but we add that in for consistency with
+   ppc32 and ppc64 stub names.  We can't use a local symbol name
+   because ld -r might generate duplicate local symbols.  */
+
+static char *
+spu_stub_name (const asection *input_sec,
+	       const asection *sym_sec,
+	       const struct elf_link_hash_entry *h,
+	       const Elf_Internal_Rela *rel)
+{
+  char *stub_name;
+  bfd_size_type len;
+
+  if (h)
+    {
+      len = 8 + 1 + strlen (h->root.root.string) + 1 + 8 + 1;
+      stub_name = bfd_malloc (len);
+      if (stub_name == NULL)
+	return stub_name;
+
+      sprintf (stub_name, "%08x.%s+%x",
+	       input_sec->id & 0xffffffff,
+	       h->root.root.string,
+	       (int) rel->r_addend & 0xffffffff);
+      len -= 8;
+    }
+  else
+    {
+      len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1;
+      stub_name = bfd_malloc (len);
+      if (stub_name == NULL)
+	return stub_name;
+
+      sprintf (stub_name, "%08x.%x:%x+%x",
+	       input_sec->id & 0xffffffff,
+	       sym_sec->id & 0xffffffff,
+	       (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
+	       (int) rel->r_addend & 0xffffffff);
+      len = strlen (stub_name);
+    }
+
+  if (stub_name[len - 2] == '+'
+      && stub_name[len - 1] == '0'
+      && stub_name[len] == 0)
+    stub_name[len - 2] = 0;
+
+  return stub_name;
+}
+
+/* Create the note section if not already present.  This is done early so
+   that the linker maps the sections to the right place in the output.  */
+
+bfd_boolean
+spu_elf_create_sections (bfd *output_bfd, struct bfd_link_info *info)
+{
+  bfd *ibfd;
+
+  for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->next)
+    if (bfd_get_section_by_name (ibfd, SPU_PTNOTE_SPUNAME) != NULL)
+      break;
+
+  if (ibfd == NULL)
+    {
+      /* Make SPU_PTNOTE_SPUNAME section.  */
+      asection *s;
+      size_t name_len;
+      size_t size;
+      bfd_byte *data;
+      flagword flags;
+
+      ibfd = info->input_bfds;
+      flags = SEC_LOAD | SEC_READONLY | SEC_HAS_CONTENTS | SEC_IN_MEMORY;
+      s = bfd_make_section_anyway_with_flags (ibfd, SPU_PTNOTE_SPUNAME, flags);
+      if (s == NULL
+	  || !bfd_set_section_alignment (ibfd, s, 4))
+	return FALSE;
+
+      name_len = strlen (bfd_get_filename (output_bfd)) + 1;
+      size = 12 + ((sizeof (SPU_PLUGIN_NAME) + 3) & -4);
+      size += (name_len + 3) & -4;
+
+      if (!bfd_set_section_size (ibfd, s, size))
+	return FALSE;
+
+      data = bfd_zalloc (ibfd, size);
+      if (data == NULL)
+	return FALSE;
+
+      bfd_put_32 (ibfd, sizeof (SPU_PLUGIN_NAME), data + 0);
+      bfd_put_32 (ibfd, name_len, data + 4);
+      bfd_put_32 (ibfd, 1, data + 8);
+      memcpy (data + 12, SPU_PLUGIN_NAME, sizeof (SPU_PLUGIN_NAME));
+      memcpy (data + 12 + ((sizeof (SPU_PLUGIN_NAME) + 3) & -4),
+	      bfd_get_filename (output_bfd), name_len);
+      s->contents = data;
+    }
+
+  return TRUE;
+}
+
+/* Return the section that should be marked against GC for a given
+   relocation.  */
+
+static asection *
+spu_elf_gc_mark_hook (asection *sec,
+		      struct bfd_link_info *info ATTRIBUTE_UNUSED,
+		      Elf_Internal_Rela *rel ATTRIBUTE_UNUSED,
+		      struct elf_link_hash_entry *h,
+		      Elf_Internal_Sym *sym)
+{
+  if (h != NULL)
+    {
+      switch (h->root.type)
+	{
+	case bfd_link_hash_defined:
+	case bfd_link_hash_defweak:
+	  return h->root.u.def.section;
+
+	case bfd_link_hash_common:
+	  return h->root.u.c.p->section;
+
+	default:
+	  break;
+	}
+    }
+  else
+    return bfd_section_from_elf_index (sec->owner, sym->st_shndx);
+
+  return NULL;
+}
+
+/* qsort predicate to sort sections by vma.  */
+
+static int
+sort_sections (const void *a, const void *b)
+{
+  const asection *const *s1 = a;
+  const asection *const *s2 = b;
+  bfd_signed_vma delta = (*s1)->vma - (*s2)->vma;
+
+  if (delta != 0)
+    return delta < 0 ? -1 : 1;
+
+  return (*s1)->index - (*s2)->index;
+}
+
+/* Identify overlays in the output bfd, and number them.  */
+
+bfd_boolean
+spu_elf_find_overlays (bfd *output_bfd, struct bfd_link_info *info)
+{
+  struct spu_link_hash_table *htab = spu_hash_table (info);
+  asection **alloc_sec;
+  unsigned int i, n, ovl_index, num_buf;
+  asection *s;
+  bfd_vma ovl_end;
+
+  if (output_bfd->section_count < 2)
+    return FALSE;
+
+  alloc_sec = bfd_malloc (output_bfd->section_count * sizeof (*alloc_sec));
+  if (alloc_sec == NULL)
+    return FALSE;
+
+  /* Pick out all the alloced sections.  */
+  for (n = 0, s = output_bfd->sections; s != NULL; s = s->next)
+    if ((s->flags & SEC_ALLOC) != 0
+	&& (s->flags & (SEC_LOAD | SEC_THREAD_LOCAL)) != SEC_THREAD_LOCAL
+	&& s->size != 0)
+      alloc_sec[n++] = s;
+
+  if (n == 0)
+    {
+      free (alloc_sec);
+      return FALSE;
+    }
+
+  /* Sort them by vma.  */
+  qsort (alloc_sec, n, sizeof (*alloc_sec), sort_sections);
+
+  /* Look for overlapping vmas.  Any with overlap must be overlays.
+     Count them.  Also count the number of overlay regions and for
+     each region save a section from that region with the lowest vma
+     and another section with the highest end vma.  */
+  ovl_end = alloc_sec[0]->vma + alloc_sec[0]->size;
+  for (ovl_index = 0, num_buf = 0, i = 1; i < n; i++)
+    {
+      s = alloc_sec[i];
+      if (s->vma < ovl_end)
+	{
+	  asection *s0 = alloc_sec[i - 1];
+
+	  if (spu_elf_section_data (s0)->ovl_index == 0)
+	    {
+	      spu_elf_section_data (s0)->ovl_index = ++ovl_index;
+	      alloc_sec[num_buf * 2] = s0;
+	      alloc_sec[num_buf * 2 + 1] = s0;
+	      num_buf++;
+	    }
+	  spu_elf_section_data (s)->ovl_index = ++ovl_index;
+	  if (ovl_end < s->vma + s->size)
+	    {
+	      ovl_end = s->vma + s->size;
+	      alloc_sec[num_buf * 2 - 1] = s;
+	    }
+	}
+      else
+	ovl_end = s->vma + s->size;
+    }
+
+  htab->num_overlays = ovl_index;
+  htab->num_buf = num_buf;
+  if (ovl_index == 0)
+    {
+      free (alloc_sec);
+      return FALSE;
+    }
+
+  alloc_sec = bfd_realloc (alloc_sec, num_buf * 2 * sizeof (*alloc_sec));
+  if (alloc_sec == NULL)
+    return FALSE;
+
+  htab->ovl_region = alloc_sec;
+  return TRUE;
+}
+
+/* One of these per stub.  */
+#define SIZEOF_STUB1 8
+#define ILA_79	0x4200004f		/* ila $79,function_address */
+#define BR	0x32000000		/* br stub2 */
+
+/* One of these per overlay.  */
+#define SIZEOF_STUB2 8
+#define ILA_78	0x4200004e		/* ila $78,overlay_number */
+					/* br __ovly_load */
+#define NOP	0x40200000
+
+/* Return true for all relative and absolute branch and hint instructions.
+   bra   00110000 0..
+   brasl 00110001 0..
+   br    00110010 0..
+   brsl  00110011 0..
+   brz   00100000 0..
+   brnz  00100001 0..
+   brhz  00100010 0..
+   brhnz 00100011 0..
+   hbra  0001000..
+   hbrr  0001001..  */
+
+static bfd_boolean
+is_branch (const unsigned char *insn)
+{
+  return (((insn[0] & 0xec) == 0x20 && (insn[1] & 0x80) == 0)
+	  || (insn[0] & 0xfc) == 0x10);
+}
+
+struct stubarr {
+  struct spu_stub_hash_entry **sh;
+  unsigned int count;
+};
+
+/* Called via bfd_hash_traverse to set up pointers to all symbols
+   in the stub hash table.  */
+
+static bfd_boolean
+populate_stubs (struct bfd_hash_entry *bh, void *inf)
+{
+  struct stubarr *stubs = inf;
+
+  stubs->sh[--stubs->count] = (struct spu_stub_hash_entry *) bh;
+  return TRUE;
+}
+
+/* qsort predicate to sort stubs by overlay number.  */
+
+static int
+sort_stubs (const void *a, const void *b)
+{
+  const struct spu_stub_hash_entry *const *sa = a;
+  const struct spu_stub_hash_entry *const *sb = b;
+  int i;
+  bfd_signed_vma d;
+
+  i = spu_elf_section_data ((*sa)->target_section->output_section)->ovl_index;
+  i -= spu_elf_section_data ((*sb)->target_section->output_section)->ovl_index;
+  if (i != 0)
+    return i;
+
+  d = ((*sa)->target_section->output_section->vma
+       + (*sa)->target_section->output_offset
+       + (*sa)->target_off
+       - (*sb)->target_section->output_section->vma
+       - (*sb)->target_section->output_offset
+       - (*sb)->target_off);
+  if (d != 0)
+    return d < 0 ? -1 : 1;
+
+  /* Two functions at the same address.  Aliases perhaps.  */
+  i = strcmp ((*sb)->root.string, (*sa)->root.string);
+  BFD_ASSERT (i != 0);
+  return i;
+}
+
+/* Allocate space for overlay call and return stubs.  */
+
+bfd_boolean
+spu_elf_size_stubs (bfd *output_bfd,
+		    struct bfd_link_info *info,
+		    int non_overlay_stubs,
+		    asection **stub,
+		    asection **ovtab,
+		    asection **toe)
+{
+  struct spu_link_hash_table *htab = spu_hash_table (info);
+  bfd *ibfd;
+  struct stubarr stubs;
+  unsigned i, group;
+  flagword flags;
+
+  htab->non_overlay_stubs = non_overlay_stubs;
+  stubs.count = 0;
+  for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link_next)
+    {
+      extern const bfd_target bfd_elf32_spu_vec;
+      Elf_Internal_Shdr *symtab_hdr;
+      asection *section;
+      Elf_Internal_Sym *local_syms = NULL;
+
+      if (ibfd->xvec != &bfd_elf32_spu_vec)
+	continue;
+
+      /* We'll need the symbol table in a second.  */
+      symtab_hdr = &elf_tdata (ibfd)->symtab_hdr;
+      if (symtab_hdr->sh_info == 0)
+	continue;
+
+      /* Walk over each section attached to the input bfd.  */
+      for (section = ibfd->sections; section != NULL; section = section->next)
+	{
+	  Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
+
+	  /* If there aren't any relocs, then there's nothing more to do.  */
+	  if ((section->flags & SEC_RELOC) == 0
+	      || (section->flags & SEC_ALLOC) == 0
+	      || (section->flags & SEC_LOAD) == 0
+	      || section->reloc_count == 0)
+	    continue;
+
+	  /* If this section is a link-once section that will be
+	     discarded, then don't create any stubs.  */
+	  if (section->output_section == NULL
+	      || section->output_section->owner != output_bfd)
+	    continue;
+
+	  /* Get the relocs.  */
+	  internal_relocs
+	    = _bfd_elf_link_read_relocs (ibfd, section, NULL, NULL,
+					 info->keep_memory);
+	  if (internal_relocs == NULL)
+	    goto error_ret_free_local;
+
+	  /* Now examine each relocation.  */
+	  irela = internal_relocs;
+	  irelaend = irela + section->reloc_count;
+	  for (; irela < irelaend; irela++)
+	    {
+	      enum elf_spu_reloc_type r_type;
+	      unsigned int r_indx;
+	      asection *sym_sec;
+	      Elf_Internal_Sym *sym;
+	      struct elf_link_hash_entry *h;
+	      char *stub_name;
+	      struct spu_stub_hash_entry *sh;
+	      unsigned int sym_type;
+	      enum _insn_type { non_branch, branch, call } insn_type;
+
+	      r_type = ELF32_R_TYPE (irela->r_info);
+	      r_indx = ELF32_R_SYM (irela->r_info);
+
+	      if (r_type >= R_SPU_max)
+		{
+		  bfd_set_error (bfd_error_bad_value);
+		  goto error_ret_free_internal;
+		}
+
+	      /* Determine the reloc target section.  */
+	      if (!get_sym_h (&h, &sym, &sym_sec, &local_syms, r_indx, ibfd))
+		goto error_ret_free_internal;
+
+	      if (sym_sec == NULL
+		  || sym_sec->output_section == NULL
+		  || sym_sec->output_section->owner != output_bfd)
+		continue;
+
+	      /* Ensure no stubs for user supplied overlay manager syms.  */
+	      if (h != NULL
+		  && (strcmp (h->root.root.string, "__ovly_load") == 0
+		      || strcmp (h->root.root.string, "__ovly_return") == 0))
+		continue;
+
+	      insn_type = non_branch;
+	      if (r_type == R_SPU_REL16
+		  || r_type == R_SPU_ADDR16)
+		{
+		  unsigned char insn[4];
+
+		  if (!bfd_get_section_contents (ibfd, section, insn,
+						 irela->r_offset, 4))
+		    goto error_ret_free_internal;
+
+		  if (is_branch (insn))
+		    {
+		      insn_type = branch;
+		      if ((insn[0] & 0xfd) == 0x31)
+			insn_type = call;
+		    }
+		}
+
+	      /* We are only interested in function symbols.  */
+	      if (h != NULL)
+		sym_type = h->type;
+	      else
+		sym_type = ELF_ST_TYPE (sym->st_info);
+	      if (sym_type != STT_FUNC)
+		{
+		  /* It's common for people to write assembly and forget
+		     to give function symbols the right type.  Handle
+		     calls to such symbols, but warn so that (hopefully)
+		     people will fix their code.  We need the symbol
+		     type to be correct to distinguish function pointer
+		     initialisation from other pointer initialisation.  */
+		  if (insn_type == call)
+		    {
+		      const char *sym_name;
+
+		      if (h != NULL)
+			sym_name = h->root.root.string;
+		      else
+			sym_name = bfd_elf_sym_name (sym_sec->owner,
+						     symtab_hdr,
+						     sym,
+						     sym_sec);
+
+		      (*_bfd_error_handler) (_("warning: call to non-function"
+					       " symbol %s defined in %B"),
+					     sym_name, sym_sec->owner);
+		    }
+		  else
+		    continue;
+		}
+
+	      /* Usually, non-overlay sections don't need stubs.  */
+	      if (!spu_elf_section_data (sym_sec->output_section)->ovl_index
+		  && !non_overlay_stubs)
+		continue;
+
+	      /* We need a reference from some other section before
+		 we consider that a symbol might need an overlay stub.  */
+	      if (spu_elf_section_data (sym_sec->output_section)->ovl_index
+		  == spu_elf_section_data (section->output_section)->ovl_index)
+		{
+		  /* Or we need this to *not* be a branch.  ie. We are
+		     possibly taking the address of a function and
+		     passing it out somehow.  */
+		  if (insn_type != non_branch)
+		    continue;
+		}
+
+	      stub_name = spu_stub_name (section, sym_sec, h, irela);
+	      if (stub_name == NULL)
+		goto error_ret_free_internal;
+
+	      sh = (struct spu_stub_hash_entry *)
+		bfd_hash_lookup (&htab->stub_hash_table, stub_name,
+				 TRUE, FALSE);
+	      if (sh == NULL)
+		{
+		  free (stub_name);
+		error_ret_free_internal:
+		  if (elf_section_data (section)->relocs != internal_relocs)
+		    free (internal_relocs);
+		error_ret_free_local:
+		  if (local_syms != NULL
+		      && (symtab_hdr->contents
+			  != (unsigned char *) local_syms))
+		    free (local_syms);
+		  return FALSE;
+		}
+
+	      /* If this entry isn't new, we already have a stub.  */
+	      if (sh->target_section != NULL)
+		{
+		  free (stub_name);
+		  continue;
+		}
+
+	      sh->target_section = sym_sec;
+	      if (h != NULL)
+		sh->target_off = h->root.u.def.value;
+	      else
+		sh->target_off = sym->st_value;
+	      sh->target_off += irela->r_addend;
+
+	      stubs.count += 1;
+	    }
+
+	  /* We're done with the internal relocs, free them.  */
+	  if (elf_section_data (section)->relocs != internal_relocs)
+	    free (internal_relocs);
+	}
+
+      if (local_syms != NULL
+	  && symtab_hdr->contents != (unsigned char *) local_syms)
+	{
+	  if (!info->keep_memory)
+	    free (local_syms);
+	  else
+	    symtab_hdr->contents = (unsigned char *) local_syms;
+	}
+    }
+
+  *stub = NULL;
+  if (stubs.count == 0)
+    return TRUE;
+
+  ibfd = info->input_bfds;
+  flags = (SEC_ALLOC | SEC_LOAD | SEC_CODE | SEC_READONLY
+	   | SEC_HAS_CONTENTS | SEC_IN_MEMORY);
+  htab->stub = bfd_make_section_anyway_with_flags (ibfd, ".stub", flags);
+  *stub = htab->stub;
+  if (htab->stub == NULL
+      || !bfd_set_section_alignment (ibfd, htab->stub, 2))
+    return FALSE;
+
+  flags = (SEC_ALLOC | SEC_LOAD
+	   | SEC_HAS_CONTENTS | SEC_IN_MEMORY);
+  htab->ovtab = bfd_make_section_anyway_with_flags (ibfd, ".ovtab", flags);
+  *ovtab = htab->ovtab;
+  if (htab->ovtab == NULL
+      || !bfd_set_section_alignment (ibfd, htab->stub, 4))
+    return FALSE;
+
+  *toe = bfd_make_section_anyway_with_flags (ibfd, ".toe", SEC_ALLOC);
+  if (*toe == NULL
+      || !bfd_set_section_alignment (ibfd, *toe, 4))
+    return FALSE;
+  (*toe)->size = 16;
+
+  /* Retrieve all the stubs and sort.  */
+  stubs.sh = bfd_malloc (stubs.count * sizeof (*stubs.sh));
+  if (stubs.sh == NULL)
+    return FALSE;
+  i = stubs.count;
+  bfd_hash_traverse (&htab->stub_hash_table, populate_stubs, &stubs);
+  BFD_ASSERT (stubs.count == 0);
+
+  stubs.count = i;
+  qsort (stubs.sh, stubs.count, sizeof (*stubs.sh), sort_stubs);
+
+  /* Now that the stubs are sorted, place them in the stub section.
+     Stubs are grouped per overlay
+     .	    ila $79,func1
+     .	    br 1f
+     .	    ila $79,func2
+     .	    br 1f
+     .
+     .
+     .	    ila $79,funcn
+     .	    nop
+     .	1:
+     .	    ila $78,ovl_index
+     .	    br __ovly_load  */
+
+  group = 0;
+  for (i = 0; i < stubs.count; i++)
+    {
+      if (spu_elf_section_data (stubs.sh[group]->target_section
+				->output_section)->ovl_index
+	  != spu_elf_section_data (stubs.sh[i]->target_section
+				   ->output_section)->ovl_index)
+	{
+	  htab->stub->size += SIZEOF_STUB2;
+	  for (; group != i; group++)
+	    stubs.sh[group]->delta
+	      = stubs.sh[i - 1]->off - stubs.sh[group]->off;
+	}
+      if (group == i
+	  || ((stubs.sh[i - 1]->target_section->output_section->vma
+	       + stubs.sh[i - 1]->target_section->output_offset
+	       + stubs.sh[i - 1]->target_off)
+	      != (stubs.sh[i]->target_section->output_section->vma
+		  + stubs.sh[i]->target_section->output_offset
+		  + stubs.sh[i]->target_off)))
+	{
+	  stubs.sh[i]->off = htab->stub->size;
+	  htab->stub->size += SIZEOF_STUB1;
+	}
+      else
+	stubs.sh[i]->off = stubs.sh[i - 1]->off;
+    }
+  if (group != i)
+    htab->stub->size += SIZEOF_STUB2;
+  for (; group != i; group++)
+    stubs.sh[group]->delta = stubs.sh[i - 1]->off - stubs.sh[group]->off;
+
+ /* htab->ovtab consists of two arrays.
+    .	struct {
+    .	  u32 vma;
+    .	  u32 size;
+    .	  u32 file_off;
+    .	  u32 buf;
+    .	} _ovly_table[];
+    .
+    .	struct {
+    .	  u32 mapped;
+    .	} _ovly_buf_table[];  */
+
+  htab->ovtab->alignment_power = 4;
+  htab->ovtab->size = htab->num_overlays * 16 + htab->num_buf * 4;
+
+  return TRUE;
+}
+
+/* Functions to handle embedded spu_ovl.o object.  */
+
+static void *
+ovl_mgr_open (struct bfd *nbfd ATTRIBUTE_UNUSED, void *stream)
+{
+  return stream;
+}
+
+static file_ptr
+ovl_mgr_pread (struct bfd *abfd ATTRIBUTE_UNUSED,
+	       void *stream,
+	       void *buf,
+	       file_ptr nbytes,
+	       file_ptr offset)
+{
+  struct _ovl_stream *os;
+  size_t count;
+  size_t max;
+
+  os = (struct _ovl_stream *) stream;
+  max = (char *) os->end - (char *) os->start;
+
+  if ((ufile_ptr) offset >= max)
+    return 0;
+
+  count = nbytes;
+  if (count > max - offset)
+    count = max - offset;
+
+  memcpy (buf, (char *) os->start + offset, count);
+  return count;
+}
+
+bfd_boolean
+spu_elf_open_builtin_lib (bfd **ovl_bfd, const struct _ovl_stream *stream)
+{
+  *ovl_bfd = bfd_openr_iovec ("builtin ovl_mgr",
+			      "elf32-spu",
+			      ovl_mgr_open,
+			      (void *) stream,
+			      ovl_mgr_pread,
+			      NULL);
+  return *ovl_bfd != NULL;
+}
+
+/* Fill in the ila and br for a stub.  On the last stub for a group,
+   write the stub that sets the overlay number too.  */
+
+static bfd_boolean
+write_one_stub (struct bfd_hash_entry *bh, void *inf)
+{
+  struct spu_stub_hash_entry *ent = (struct spu_stub_hash_entry *) bh;
+  struct spu_link_hash_table *htab = inf;
+  asection *sec = htab->stub;
+  asection *s = ent->target_section;
+  unsigned int ovl;
+  bfd_vma val;
+
+  val = ent->target_off + s->output_offset + s->output_section->vma;
+  bfd_put_32 (sec->owner, ILA_79 + ((val << 7) & 0x01ffff80),
+	      sec->contents + ent->off);
+  val = ent->delta + 4;
+  bfd_put_32 (sec->owner, BR + ((val << 5) & 0x007fff80),
+	      sec->contents + ent->off + 4);
+
+  /* If this is the last stub of this group, write stub2.  */
+  if (ent->delta == 0)
+    {
+      bfd_put_32 (sec->owner, NOP,
+		  sec->contents + ent->off + 4);
+
+      ovl = spu_elf_section_data (s->output_section)->ovl_index;
+      bfd_put_32 (sec->owner, ILA_78 + ((ovl << 7) & 0x01ffff80),
+		  sec->contents + ent->off + 8);
+
+      val = (htab->ovly_load->root.u.def.section->output_section->vma
+	     + htab->ovly_load->root.u.def.section->output_offset
+	     + htab->ovly_load->root.u.def.value
+	     - (sec->output_section->vma
+		+ sec->output_offset
+		+ ent->off + 12));
+
+      if (val + 0x20000 >= 0x40000)
+	htab->stub_overflow = TRUE;
+
+      bfd_put_32 (sec->owner, BR + ((val << 5) & 0x007fff80),
+		  sec->contents + ent->off + 12);
+    }
+
+  if (htab->emit_stub_syms)
+    {
+      struct elf_link_hash_entry *h;
+      size_t len1, len2;
+      char *name;
+
+      len1 = sizeof ("ovl_call.") - 1;
+      len2 = strlen (ent->root.string);
+      name = bfd_malloc (len1 + len2 + 1);
+      if (name == NULL)
+	return FALSE;
+      memcpy (name, ent->root.string, 9);
+      memcpy (name + 9, "ovl_call.", len1);
+      memcpy (name + 9 + len1, ent->root.string + 9, len2 - 9 + 1);
+      h = elf_link_hash_lookup (&htab->elf, name, TRUE, FALSE, FALSE);
+      if (h == NULL)
+	return FALSE;
+      if (h->root.type == bfd_link_hash_new)
+	{
+	  h->root.type = bfd_link_hash_defined;
+	  h->root.u.def.section = sec;
+	  h->root.u.def.value = ent->off;
+	  h->size = (ent->delta == 0
+		     ? SIZEOF_STUB1 + SIZEOF_STUB2 : SIZEOF_STUB1);
+	  h->type = STT_FUNC;
+	  h->ref_regular = 1;
+	  h->def_regular = 1;
+	  h->ref_regular_nonweak = 1;
+	  h->forced_local = 1;
+	  h->non_elf = 0;
+	}
+    }
+
+  return TRUE;
+}
+
+/* Define an STT_OBJECT symbol.  */
+
+static struct elf_link_hash_entry *
+define_ovtab_symbol (struct spu_link_hash_table *htab, const char *name)
+{
+  struct elf_link_hash_entry *h;
+
+  h = elf_link_hash_lookup (&htab->elf, name, TRUE, FALSE, FALSE);
+  if (h == NULL)
+    return NULL;
+
+  if (h->root.type != bfd_link_hash_defined
+      || !h->def_regular)
+    {
+      h->root.type = bfd_link_hash_defined;
+      h->root.u.def.section = htab->ovtab;
+      h->type = STT_OBJECT;
+      h->ref_regular = 1;
+      h->def_regular = 1;
+      h->ref_regular_nonweak = 1;
+      h->non_elf = 0;
+    }
+  else
+    {
+      (*_bfd_error_handler) (_("%B is not allowed to define %s"),
+			     h->root.u.def.section->owner,
+			     h->root.root.string);
+      bfd_set_error (bfd_error_bad_value);
+      return NULL;
+    }
+
+  return h;
+}
+
+/* Fill in all stubs and the overlay tables.  */
+
+bfd_boolean
+spu_elf_build_stubs (struct bfd_link_info *info, int emit_syms, asection *toe)
+{
+  struct spu_link_hash_table *htab = spu_hash_table (info);
+  struct elf_link_hash_entry *h;
+  bfd_byte *p;
+  asection *s;
+  bfd *obfd;
+  unsigned int i;
+
+  htab->emit_stub_syms = emit_syms;
+  htab->stub->contents = bfd_zalloc (htab->stub->owner, htab->stub->size);
+  if (htab->stub->contents == NULL)
+    return FALSE;
+
+  h = elf_link_hash_lookup (&htab->elf, "__ovly_load", FALSE, FALSE, FALSE);
+  htab->ovly_load = h;
+  BFD_ASSERT (h != NULL
+	      && (h->root.type == bfd_link_hash_defined
+		  || h->root.type == bfd_link_hash_defweak)
+	      && h->def_regular);
+
+  s = h->root.u.def.section->output_section;
+  if (spu_elf_section_data (s)->ovl_index)
+    {
+      (*_bfd_error_handler) (_("%s in overlay section"),
+			     h->root.u.def.section->owner);
+      bfd_set_error (bfd_error_bad_value);
+      return FALSE;
+    }
+
+  /* Write out all the stubs.  */
+  bfd_hash_traverse (&htab->stub_hash_table, write_one_stub, htab);
+
+  if (htab->stub_overflow)
+    {
+      (*_bfd_error_handler) (_("overlay stub relocation overflow"));
+      bfd_set_error (bfd_error_bad_value);
+      return FALSE;
+    }
+
+  htab->ovtab->contents = bfd_zalloc (htab->ovtab->owner, htab->ovtab->size);
+  if (htab->ovtab->contents == NULL)
+    return FALSE;
+
+  /* Write out _ovly_table.  */
+  p = htab->ovtab->contents;
+  obfd = htab->ovtab->output_section->owner;
+  for (s = obfd->sections; s != NULL; s = s->next)
+    {
+      unsigned int ovl_index = spu_elf_section_data (s)->ovl_index;
+
+      if (ovl_index != 0)
+	{
+	  unsigned int lo, hi, mid;
+	  unsigned long off = (ovl_index - 1) * 16;
+	  bfd_put_32 (htab->ovtab->owner, s->vma, p + off);
+	  bfd_put_32 (htab->ovtab->owner, (s->size + 15) & -16, p + off + 4);
+	  /* file_off written later in spu_elf_modify_program_headers.  */
+
+	  lo = 0;
+	  hi = htab->num_buf;
+	  while (lo < hi)
+	    {
+	      mid = (lo + hi) >> 1;
+	      if (htab->ovl_region[2 * mid + 1]->vma
+		  + htab->ovl_region[2 * mid + 1]->size <= s->vma)
+		lo = mid + 1;
+	      else if (htab->ovl_region[2 * mid]->vma > s->vma)
+		hi = mid;
+	      else
+		{
+		  bfd_put_32 (htab->ovtab->owner, mid + 1, p + off + 12);
+		  break;
+		}
+	    }
+	  BFD_ASSERT (lo < hi);
+	}
+    }
+
+  /* Write out _ovly_buf_table.  */
+  p = htab->ovtab->contents + htab->num_overlays * 16;
+  for (i = 0; i < htab->num_buf; i++)
+    {
+      bfd_put_32 (htab->ovtab->owner, 0, p);
+      p += 4;
+    }
+
+  h = define_ovtab_symbol (htab, "_ovly_table");
+  if (h == NULL)
+    return FALSE;
+  h->root.u.def.value = 0;
+  h->size = htab->num_overlays * 16;
+
+  h = define_ovtab_symbol (htab, "_ovly_table_end");
+  if (h == NULL)
+    return FALSE;
+  h->root.u.def.value = htab->num_overlays * 16;
+  h->size = 0;
+
+  h = define_ovtab_symbol (htab, "_ovly_buf_table");
+  if (h == NULL)
+    return FALSE;
+  h->root.u.def.value = htab->num_overlays * 16;
+  h->size = htab->num_buf * 4;
+
+  h = define_ovtab_symbol (htab, "_ovly_buf_table_end");
+  if (h == NULL)
+    return FALSE;
+  h->root.u.def.value = htab->num_overlays * 16 + htab->num_buf * 4;
+  h->size = 0;
+
+  h = define_ovtab_symbol (htab, "_EAR_");
+  if (h == NULL)
+    return FALSE;
+  h->root.u.def.section = toe;
+  h->root.u.def.value = 0;
+  h->size = 16;
+
+  return TRUE;
+}
+
+/* Apply RELOCS to CONTENTS of INPUT_SECTION from INPUT_BFD.  */
+
+static bfd_boolean
+spu_elf_relocate_section (bfd *output_bfd,
+			  struct bfd_link_info *info,
+			  bfd *input_bfd,
+			  asection *input_section,
+			  bfd_byte *contents,
+			  Elf_Internal_Rela *relocs,
+			  Elf_Internal_Sym *local_syms,
+			  asection **local_sections)
+{
+  Elf_Internal_Shdr *symtab_hdr;
+  struct elf_link_hash_entry **sym_hashes;
+  Elf_Internal_Rela *rel, *relend;
+  struct spu_link_hash_table *htab;
+  bfd_boolean ret = TRUE;
+
+  if (info->relocatable)
+    return TRUE;
+
+  htab = spu_hash_table (info);
+  symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
+  sym_hashes = (struct elf_link_hash_entry **) (elf_sym_hashes (input_bfd));
+
+  rel = relocs;
+  relend = relocs + input_section->reloc_count;
+  for (; rel < relend; rel++)
+    {
+      int r_type;
+      reloc_howto_type *howto;
+      unsigned long r_symndx;
+      Elf_Internal_Sym *sym;
+      asection *sec;
+      struct elf_link_hash_entry *h;
+      const char *sym_name;
+      bfd_vma relocation;
+      bfd_vma addend;
+      bfd_reloc_status_type r;
+      bfd_boolean unresolved_reloc;
+      bfd_boolean warned;
+
+      r_symndx = ELF32_R_SYM (rel->r_info);
+      r_type = ELF32_R_TYPE (rel->r_info);
+      howto = elf_howto_table + r_type;
+      unresolved_reloc = FALSE;
+      warned = FALSE;
+
+      h = NULL;
+      sym = NULL;
+      sec = NULL;
+      if (r_symndx < symtab_hdr->sh_info)
+	{
+	  sym = local_syms + r_symndx;
+	  sec = local_sections[r_symndx];
+	  sym_name = bfd_elf_sym_name (input_bfd, symtab_hdr, sym, sec);
+	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	}
+      else
+	{
+	  RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
+				   r_symndx, symtab_hdr, sym_hashes,
+				   h, sec, relocation,
+				   unresolved_reloc, warned);
+	  sym_name = h->root.root.string;
+	}
+
+      if (unresolved_reloc)
+	{
+	  (*_bfd_error_handler)
+	    (_("%B(%s+0x%lx): unresolvable %s relocation against symbol `%s'"),
+	     input_bfd,
+	     bfd_get_section_name (input_bfd, input_section),
+	     (long) rel->r_offset,
+	     howto->name,
+	     sym_name);
+	  ret = FALSE;
+	}
+
+      /* If this symbol is in an overlay area, we may need to relocate
+	 to the overlay stub.  */
+      addend = rel->r_addend;
+      if (sec != NULL
+	  && sec->output_section != NULL
+	  && sec->output_section->owner == output_bfd
+	  && (spu_elf_section_data (sec->output_section)->ovl_index != 0
+	      || htab->non_overlay_stubs)
+	  && !(sec == input_section
+	       && is_branch (contents + rel->r_offset)))
+	{
+	  char *stub_name;
+	  struct spu_stub_hash_entry *sh;
+
+	  stub_name = spu_stub_name (input_section, sec, h, rel);
+	  if (stub_name == NULL)
+	    return FALSE;
+
+	  sh = (struct spu_stub_hash_entry *)
+	    bfd_hash_lookup (&htab->stub_hash_table, stub_name, FALSE, FALSE);
+	  if (sh != NULL)
+	    {
+	      relocation = (htab->stub->output_section->vma
+			    + htab->stub->output_offset
+			    + sh->off);
+	      addend = 0;
+	    }
+	  free (stub_name);
+	}
+
+      r = _bfd_final_link_relocate (howto,
+				    input_bfd,
+				    input_section,
+				    contents,
+				    rel->r_offset, relocation, addend);
+
+      if (r != bfd_reloc_ok)
+	{
+	  const char *msg = (const char *) 0;
+
+	  switch (r)
+	    {
+	    case bfd_reloc_overflow:
+	      if (!((*info->callbacks->reloc_overflow)
+		    (info, (h ? &h->root : NULL), sym_name, howto->name,
+		     (bfd_vma) 0, input_bfd, input_section, rel->r_offset)))
+		return FALSE;
+	      break;
+
+	    case bfd_reloc_undefined:
+	      if (!((*info->callbacks->undefined_symbol)
+		    (info, sym_name, input_bfd, input_section,
+		     rel->r_offset, TRUE)))
+		return FALSE;
+	      break;
+
+	    case bfd_reloc_outofrange:
+	      msg = _("internal error: out of range error");
+	      goto common_error;
+
+	    case bfd_reloc_notsupported:
+	      msg = _("internal error: unsupported relocation error");
+	      goto common_error;
+
+	    case bfd_reloc_dangerous:
+	      msg = _("internal error: dangerous error");
+	      goto common_error;
+
+	    default:
+	      msg = _("internal error: unknown error");
+	      /* fall through */
+
+	    common_error:
+	      if (!((*info->callbacks->warning)
+		    (info, msg, sym_name, input_bfd, input_section,
+		     rel->r_offset)))
+		return FALSE;
+	      break;
+	    }
+	}
+    }
+
+  return ret;
+}
+
+static int spu_plugin = 0;
+
+void
+spu_elf_plugin (int val)
+{
+  spu_plugin = val;
+}
+
+/* Set ELF header e_type for plugins.  */
+
+static void
+spu_elf_post_process_headers (bfd *abfd,
+			      struct bfd_link_info *info ATTRIBUTE_UNUSED)
+{
+  if (spu_plugin)
+    {
+      Elf_Internal_Ehdr *i_ehdrp = elf_elfheader (abfd);
+
+      i_ehdrp->e_type = ET_DYN;
+    }
+}
+
+/* We may add an extra PT_LOAD segment for .toe.  We also need extra
+   segments for overlays.  */
+
+static int
+spu_elf_additional_program_headers (bfd *abfd, struct bfd_link_info *info)
+{
+  struct spu_link_hash_table *htab = spu_hash_table (info);
+  int extra = htab->num_overlays;
+  asection *sec;
+
+  if (extra)
+    ++extra;
+
+  sec = bfd_get_section_by_name (abfd, ".toe");
+  if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
+    ++extra;
+
+  return extra;
+}
+
+/* Remove .toe section from other PT_LOAD segments and put it in
+   a segment of its own.  Put overlays in separate segments too.  */
+
+static bfd_boolean
+spu_elf_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
+{
+  asection *toe, *s;
+  struct elf_segment_map *m;
+  unsigned int i;
+
+  if (info == NULL)
+    return TRUE;
+
+  toe = bfd_get_section_by_name (abfd, ".toe");
+  for (m = elf_tdata (abfd)->segment_map; m != NULL; m = m->next)
+    if (m->p_type == PT_LOAD && m->count > 1)
+      for (i = 0; i < m->count; i++)
+	if ((s = m->sections[i]) == toe
+	    || spu_elf_section_data (s)->ovl_index != 0)
+	  {
+	    struct elf_segment_map *m2;
+	    bfd_vma amt;
+
+	    if (i + 1 < m->count)
+	      {
+		amt = sizeof (struct elf_segment_map);
+		amt += (m->count - (i + 2)) * sizeof (m->sections[0]);
+		m2 = bfd_zalloc (abfd, amt);
+		if (m2 == NULL)
+		  return FALSE;
+		m2->count = m->count - (i + 1);
+		memcpy (m2->sections, m->sections + i + 1,
+			m2->count * sizeof (m->sections[0]));
+		m2->p_type = PT_LOAD;
+		m2->next = m->next;
+		m->next = m2;
+	      }
+	    m->count = 1;
+	    if (i != 0)
+	      {
+		m->count = i;
+		amt = sizeof (struct elf_segment_map);
+		m2 = bfd_zalloc (abfd, amt);
+		if (m2 == NULL)
+		  return FALSE;
+		m2->p_type = PT_LOAD;
+		m2->count = 1;
+		m2->sections[0] = s;
+		m2->next = m->next;
+		m->next = m2;
+	      }
+	    break;
+	  }
+
+  return TRUE;
+}
+
+/* Check that all loadable section VMAs lie in the range
+   LO .. HI inclusive.  */
+
+asection *
+spu_elf_check_vma (bfd *abfd, bfd_vma lo, bfd_vma hi)
+{
+  struct elf_segment_map *m;
+  unsigned int i;
+
+  for (m = elf_tdata (abfd)->segment_map; m != NULL; m = m->next)
+    if (m->p_type == PT_LOAD)
+      for (i = 0; i < m->count; i++)
+	if (m->sections[i]->size != 0
+	    && (m->sections[i]->vma < lo
+		|| m->sections[i]->vma > hi
+		|| m->sections[i]->vma + m->sections[i]->size - 1 > hi))
+	  return m->sections[i];
+
+  return NULL;
+}
+
+/* Tweak phdrs before writing them out.  */
+
+static int
+spu_elf_modify_program_headers (bfd *abfd, struct bfd_link_info *info)
+{
+  const struct elf_backend_data *bed;
+  struct elf_obj_tdata *tdata;
+  Elf_Internal_Phdr *phdr, *last;
+  struct spu_link_hash_table *htab;
+  unsigned int count;
+  unsigned int i;
+
+  if (info == NULL)
+    return TRUE;
+
+  bed = get_elf_backend_data (abfd);
+  tdata = elf_tdata (abfd);
+  phdr = tdata->phdr;
+  count = tdata->program_header_size / bed->s->sizeof_phdr;
+  htab = spu_hash_table (info);
+  if (htab->num_overlays != 0)
+    {
+      struct elf_segment_map *m;
+      unsigned int o;
+
+      for (i = 0, m = elf_tdata (abfd)->segment_map; m; ++i, m = m->next)
+	if (m->count != 0
+	    && (o = spu_elf_section_data (m->sections[0])->ovl_index) != 0)
+	  {
+	    /* Mark this as an overlay header.  */
+	    phdr[i].p_flags |= PF_OVERLAY;
+
+	    if (htab->ovtab != NULL && htab->ovtab->size != 0)
+	      {
+		bfd_byte *p = htab->ovtab->contents;
+		unsigned int off = (o - 1) * 16 + 8;
+
+		/* Write file_off into _ovly_table.  */
+		bfd_put_32 (htab->ovtab->owner, phdr[i].p_offset, p + off);
+	      }
+	  }
+    }
+
+  /* Round up p_filesz and p_memsz of PT_LOAD segments to multiples
+     of 16.  This should always be possible when using the standard
+     linker scripts, but don't create overlapping segments if
+     someone is playing games with linker scripts.  */
+  last = NULL;
+  for (i = count; i-- != 0; )
+    if (phdr[i].p_type == PT_LOAD)
+      {
+	unsigned adjust;
+
+	adjust = -phdr[i].p_filesz & 15;
+	if (adjust != 0
+	    && last != NULL
+	    && phdr[i].p_offset + phdr[i].p_filesz > last->p_offset - adjust)
+	  break;
+
+	adjust = -phdr[i].p_memsz & 15;
+	if (adjust != 0
+	    && last != NULL
+	    && phdr[i].p_filesz != 0
+	    && phdr[i].p_vaddr + phdr[i].p_memsz > last->p_vaddr - adjust
+	    && phdr[i].p_vaddr + phdr[i].p_memsz <= last->p_vaddr)
+	  break;
+
+	if (phdr[i].p_filesz != 0)
+	  last = &phdr[i];
+      }
+
+  if (i == (unsigned int) -1)
+    for (i = count; i-- != 0; )
+      if (phdr[i].p_type == PT_LOAD)
+	{
+	unsigned adjust;
+
+	adjust = -phdr[i].p_filesz & 15;
+	phdr[i].p_filesz += adjust;
+
+	adjust = -phdr[i].p_memsz & 15;
+	phdr[i].p_memsz += adjust;
+      }
+
+  return TRUE;
+}
+
+/* Arrange for our linker created section to be output.  */
+
+static bfd_boolean
+spu_elf_section_processing (bfd *abfd ATTRIBUTE_UNUSED,
+			    Elf_Internal_Shdr *i_shdrp)
+{
+  asection *sec;
+
+  sec = i_shdrp->bfd_section;
+  if (sec != NULL
+      && (sec->flags & SEC_LINKER_CREATED) != 0
+      && sec->name != NULL
+      && strcmp (sec->name, SPU_PTNOTE_SPUNAME) == 0)
+    i_shdrp->contents = sec->contents;
+
+  return TRUE;
+}
+
+#define TARGET_BIG_SYM		bfd_elf32_spu_vec
+#define TARGET_BIG_NAME		"elf32-spu"
+#define ELF_ARCH		bfd_arch_spu
+#define ELF_MACHINE_CODE	EM_SPU
+/* This matches the alignment need for DMA.  */
+#define ELF_MAXPAGESIZE		0x80
+#define elf_backend_rela_normal         1
+#define elf_backend_can_gc_sections	1
+
+#define bfd_elf32_bfd_reloc_type_lookup		spu_elf_reloc_type_lookup
+#define elf_info_to_howto			spu_elf_info_to_howto
+#define elf_backend_gc_mark_hook		spu_elf_gc_mark_hook
+#define elf_backend_relocate_section		spu_elf_relocate_section
+#define elf_backend_symbol_processing		spu_elf_backend_symbol_processing
+#define bfd_elf32_new_section_hook		spu_elf_new_section_hook
+#define bfd_elf32_bfd_link_hash_table_create	spu_elf_link_hash_table_create
+#define bfd_elf32_bfd_link_hash_table_free	spu_elf_link_hash_table_free
+
+#define elf_backend_additional_program_headers	spu_elf_additional_program_headers
+#define elf_backend_modify_segment_map		spu_elf_modify_segment_map
+#define elf_backend_modify_program_headers	spu_elf_modify_program_headers
+#define elf_backend_post_process_headers        spu_elf_post_process_headers
+#define elf_backend_section_processing		spu_elf_section_processing
+#define elf_backend_special_sections		spu_elf_special_sections
+
+#include "elf32-target.h"
diff --git a/bfd/elf32-spu.h b/bfd/elf32-spu.h
new file mode 100644
index 00000000000..2d6eaf3c634
--- /dev/null
+++ b/bfd/elf32-spu.h
@@ -0,0 +1,51 @@
+/* SPU specific support for 32-bit ELF.
+
+   Copyright 2006 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+/* Extra info kept for SPU sections.  */
+
+struct _spu_elf_section_data
+{
+  struct bfd_elf_section_data elf;
+
+  /* Non-zero for overlay output sections.  */
+  unsigned int ovl_index;
+};
+
+#define spu_elf_section_data(sec) \
+  ((struct _spu_elf_section_data *) elf_section_data (sec))
+
+struct _ovl_stream
+{
+  void *start;
+  void *end;
+};
+
+extern void spu_elf_plugin (int);
+extern bfd_boolean spu_elf_open_builtin_lib (bfd **,
+					     const struct _ovl_stream *);
+extern bfd_boolean spu_elf_create_sections (bfd *,
+					    struct bfd_link_info *);
+extern bfd_boolean spu_elf_find_overlays (bfd *, struct bfd_link_info *);
+extern bfd_boolean spu_elf_size_stubs (bfd *, struct bfd_link_info *, int,
+				       asection **, asection **,
+				       asection **);
+extern bfd_boolean spu_elf_build_stubs (struct bfd_link_info *, int,
+					asection *);
+extern asection *spu_elf_check_vma (bfd *, bfd_vma, bfd_vma);
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index 40e9182475c..a4c4f011e27 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -902,6 +902,18 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
   "BFD_RELOC_SPARC_TLS_DTPOFF64",
   "BFD_RELOC_SPARC_TLS_TPOFF32",
   "BFD_RELOC_SPARC_TLS_TPOFF64",
+  "BFD_RELOC_SPU_IMM7",
+  "BFD_RELOC_SPU_IMM8",
+  "BFD_RELOC_SPU_IMM10",
+  "BFD_RELOC_SPU_IMM10W",
+  "BFD_RELOC_SPU_IMM16",
+  "BFD_RELOC_SPU_IMM16W",
+  "BFD_RELOC_SPU_IMM18",
+  "BFD_RELOC_SPU_PCREL9a",
+  "BFD_RELOC_SPU_PCREL9b",
+  "BFD_RELOC_SPU_PCREL16",
+  "BFD_RELOC_SPU_LO16",
+  "BFD_RELOC_SPU_HI16",
   "BFD_RELOC_ALPHA_GPDISP_HI16",
   "BFD_RELOC_ALPHA_GPDISP_LO16",
   "BFD_RELOC_ALPHA_GPDISP",
diff --git a/bfd/po/SRC-POTFILES.in b/bfd/po/SRC-POTFILES.in
index 7e96f28c96e..a8dd4e8ff78 100644
--- a/bfd/po/SRC-POTFILES.in
+++ b/bfd/po/SRC-POTFILES.in
@@ -109,6 +109,7 @@ cpu-s390.c
 cpu-score.c
 cpu-sh.c
 cpu-sparc.c
+cpu-spu.c
 cpu-tic30.c
 cpu-tic4x.c
 cpu-tic54x.c
@@ -176,6 +177,7 @@ elf32-sh64-com.c
 elf32-sh.c
 elf32-sh-symbian.c
 elf32-sparc.c
+elf32-spu.c
 elf32-v850.c
 elf32-vax.c
 elf32-xc16x.c
diff --git a/bfd/reloc.c b/bfd/reloc.c
index 56eebcf791a..3d40730d6e3 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -1884,6 +1884,33 @@ ENUMDOC
   SPARC TLS relocations
 
 ENUM
+  BFD_RELOC_SPU_IMM7
+ENUMX
+  BFD_RELOC_SPU_IMM8
+ENUMX
+  BFD_RELOC_SPU_IMM10
+ENUMX
+  BFD_RELOC_SPU_IMM10W
+ENUMX
+  BFD_RELOC_SPU_IMM16
+ENUMX
+  BFD_RELOC_SPU_IMM16W
+ENUMX
+  BFD_RELOC_SPU_IMM18
+ENUMX
+  BFD_RELOC_SPU_PCREL9a
+ENUMX
+  BFD_RELOC_SPU_PCREL9b
+ENUMX
+  BFD_RELOC_SPU_PCREL16
+ENUMX
+  BFD_RELOC_SPU_LO16
+ENUMX
+  BFD_RELOC_SPU_HI16
+ENUMDOC
+  SPU Relocations.
+
+ENUM
   BFD_RELOC_ALPHA_GPDISP_HI16
 ENUMDOC
   Alpha ECOFF and ELF relocations.  Some of these treat the symbol or
diff --git a/bfd/targets.c b/bfd/targets.c
index 96fab096f9d..d8d3709a542 100644
--- a/bfd/targets.c
+++ b/bfd/targets.c
@@ -643,6 +643,7 @@ extern const bfd_target bfd_elf32_shnbsd_vec;
 extern const bfd_target bfd_elf32_shvxworks_vec;
 extern const bfd_target bfd_elf32_sparc_vec;
 extern const bfd_target bfd_elf32_sparc_vxworks_vec;
+extern const bfd_target bfd_elf32_spu_vec;
 extern const bfd_target bfd_elf32_tradbigmips_vec;
 extern const bfd_target bfd_elf32_tradlittlemips_vec;
 extern const bfd_target bfd_elf32_us_cris_vec;
@@ -971,6 +972,7 @@ static const bfd_target * const _bfd_target_vector[] =
 #endif
 	&bfd_elf32_sparc_vec,
 	&bfd_elf32_sparc_vxworks_vec,
+	&bfd_elf32_spu_vec,
 	&bfd_elf32_tradbigmips_vec,
 	&bfd_elf32_tradlittlemips_vec,
 	&bfd_elf32_us_cris_vec,
diff --git a/include/ChangeLog b/include/ChangeLog
index 564efeaec79..23841a58692 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,11 @@
+2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
+	    Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
+	    Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
+	    Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
+	    Alan Modra  <amodra@bigpond.net.au>
+
+	* dis-asm.h (print_insn_spu): Declare.
+
 2006-10-17  Mark Shinwell  <shinwell@codesourcery.com>
 
 	* elf/arm.h: Define TAG_CPU_ARCH_* constants.
diff --git a/include/dis-asm.h b/include/dis-asm.h
index d6f0374b561..cb8039bf35e 100644
--- a/include/dis-asm.h
+++ b/include/dis-asm.h
@@ -260,6 +260,7 @@ extern int print_insn_sh		(bfd_vma, disassemble_info *);
 extern int print_insn_sh64		(bfd_vma, disassemble_info *);
 extern int print_insn_sh64x_media	(bfd_vma, disassemble_info *);
 extern int print_insn_sparc		(bfd_vma, disassemble_info *);
+extern int print_insn_spu		(bfd_vma, disassemble_info *);
 extern int print_insn_tic30		(bfd_vma, disassemble_info *);
 extern int print_insn_tic4x		(bfd_vma, disassemble_info *);
 extern int print_insn_tic54x		(bfd_vma, disassemble_info *);
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index c737b67dd5e..9799f458222 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,12 @@
+2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
+	    Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
+	    Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
+	    Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
+	    Alan Modra  <amodra@bigpond.net.au>
+
+	* common.h (EM_SPU): Define.
+	* spu.h: New file.
+
 2006-10-19  Mei Ligang  <ligang@sunnorth.com.cn>
 
 	* score.h (EF_SCORE_PIC): Redefine EF_SCORE_PIC as 0x80000000.
diff --git a/include/elf/common.h b/include/elf/common.h
index f041ecb870b..b418d3f8087 100644
--- a/include/elf/common.h
+++ b/include/elf/common.h
@@ -118,6 +118,7 @@
 #define EM_PPC		 20	/* PowerPC */
 #define EM_PPC64	 21	/* 64-bit PowerPC */
 #define EM_S390		 22	/* IBM S/390 */
+#define EM_SPU		 23	/* Sony/Toshiba/IBM SPU */
 
 #define EM_V800		 36	/* NEC V800 series */
 #define EM_FR20		 37	/* Fujitsu FR20 */
diff --git a/include/elf/spu.h b/include/elf/spu.h
new file mode 100644
index 00000000000..2e3f0500d1e
--- /dev/null
+++ b/include/elf/spu.h
@@ -0,0 +1,57 @@
+/* SPU ELF support for BFD.
+
+   Copyright 2006 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_SPU_H
+#define _ELF_SPU_H
+
+#include "elf/reloc-macros.h"
+
+/* elf32-spu.c depends on these being consecutive. */
+START_RELOC_NUMBERS (elf_spu_reloc_type)
+     RELOC_NUMBER (R_SPU_NONE,		 0)
+     RELOC_NUMBER (R_SPU_ADDR10,	 1)
+     RELOC_NUMBER (R_SPU_ADDR16,	 2)
+     RELOC_NUMBER (R_SPU_ADDR16_HI,	 3)
+     RELOC_NUMBER (R_SPU_ADDR16_LO,	 4)
+     RELOC_NUMBER (R_SPU_ADDR18,	 5)
+     RELOC_NUMBER (R_SPU_ADDR32,	 6)
+     RELOC_NUMBER (R_SPU_REL16,		 7)
+     RELOC_NUMBER (R_SPU_ADDR7,		 8)
+     RELOC_NUMBER (R_SPU_REL9,		 9)
+     RELOC_NUMBER (R_SPU_REL9I,		10)
+     RELOC_NUMBER (R_SPU_ADDR10I,	11)
+     RELOC_NUMBER (R_SPU_ADDR16I,	12)
+     RELOC_NUMBER (R_SPU_REL32,		13)
+END_RELOC_NUMBERS (R_SPU_max)
+
+/* Program header extensions */
+
+/* Mark a PT_LOAD segment as containing an overlay which should not
+   initially be loaded.  */
+#define PF_OVERLAY		(1 << 27)
+
+/* SPU Dynamic Object Information.  */
+#define PT_SPU_INFO             0x70000000
+
+/* SPU plugin information */
+#define SPU_PLUGIN_NAME         "SPUNAME"
+#define SPU_PTNOTE_SPUNAME	".note.spu_name"
+
+#endif /* _ELF_SPU_H */
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 33a22688ab4..8951e1e2097 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,12 @@
+2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
+	    Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
+	    Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
+	    Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
+	    Alan Modra  <amodra@bigpond.net.au>
+
+	* spu-insns.h: New file.
+	* spu.h: New file.
+
 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 
 	* ppc.h (PPC_OPCODE_CELL): Define.
diff --git a/include/opcode/spu-insns.h b/include/opcode/spu-insns.h
new file mode 100644
index 00000000000..99dc452821a
--- /dev/null
+++ b/include/opcode/spu-insns.h
@@ -0,0 +1,410 @@
+/* SPU ELF support for BFD.
+
+   Copyright 2006 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+/* SPU Opcode Table
+
+-=-=-= FORMAT =-=-=-
+                                             		                                             
+       +----+-------+-------+-------+-------+  		       +------------+-------+-------+-------+
+RRR    | op |  RC   |  RB   |  RA   |  RT   |		RI7    | op         |  I7   |  RA   |  RT   |
+       +----+-------+-------+-------+-------+		       +------------+-------+-------+-------+
+        0  3       1       1       2       3		        0          1       1       2       3 
+                   0       7       4       1		                   0       7       4       1 
+
+       +-----------+--------+-------+-------+		       +---------+----------+-------+-------+
+RI8    | op        |   I8   |  RA   |  RT   |		RI10   | op      |   I10    |  RA   |  RT   |
+       +-----------+--------+-------+-------+		       +---------+----------+-------+-------+
+        0         9        1       2       3		        0       7          1       2       3 
+                           7       4       1		                           7       4       1 
+
+       +----------+-----------------+-------+		       +--------+-------------------+-------+
+RI16   | op       |       I16       |  RT   |		RI18   | op     |       I18         |  RT   |
+       +----------+-----------------+-------+		       +--------+-------------------+-------+
+        0        8                 2       3		        0      6                   2       3 
+                                   4       1		                                   4       1 
+
+       +------------+-------+-------+-------+		       +-------+--+-----------------+-------+
+RR     | op         |  RB   |  RA   |  RT   |		LBT    | op    |RO|       I16       |  RO   |
+       +------------+-------+-------+-------+		       +-------+--+-----------------+-------+
+        0          1       1       2       3		        0     6  8                 2       3 
+                   0       7       4       1		                                   4       1 
+
+							       +------------+----+--+-------+-------+
+							LBTI   | op         | // |RO|  RA   |  RO   |
+							       +------------+----+--+-------+-------+
+							        0          1    1  1       2       3
+							                   0    5  7       4       1
+
+-=-=-= OPCODE =-=-=-
+
+OPCODE field specifies the most significant 11bit of the instruction. Some formats don't have 11bits for opcode field, and in this
+case, bit field other than op are defined as 0s. For example, opcode of fma instruction which is RRR format is defined as 0x700,
+since 0x700 -> 11'b11100000000, this means opcode is 4'b1110, and other 7bits are defined as 7'b0000000.
+
+-=-=-= ASM_FORMAT =-=-=-
+
+RRR category						RI7 category                               
+	ASM_RRR		mnemonic RC, RA, RB, RT		        ASM_RI4         mnemonic RT, RA, I4
+							        ASM_RI7         mnemonic RT, RA, I7
+
+RI8 category						RI10 category                               
+	ASM_RUI8	mnemonic RT, RA, UI8		        ASM_AI10        mnemonic RA, I10    
+							        ASM_RI10        mnemonic RT, RA, R10
+							        ASM_RI10IDX     mnemonic RT, I10(RA)
+
+RI16 category						RI18 category                           
+	ASM_I16W	mnemonic I16W			        ASM_RI18        mnemonic RT, I18
+	ASM_RI16	mnemonic RT, I16
+	ASM_RI16W	mnemonic RT, I16W
+
+RR category						LBT category                                    
+	ASM_MFSPR	mnemonic RT, SA			        ASM_LBT         mnemonic brinst, brtarg 
+	ASM_MTSPR	mnemonic SA, RT			                                                
+	ASM_NOOP	mnemonic			LBTI category                                   
+	ASM_RA		mnemonic RA			        ASM_LBTI        mnemonic brinst, RA     
+	ASM_RAB		mnemonic RA, RB
+	ASM_RDCH	mnemonic RT, CA
+	ASM_RR		mnemonic RT, RA, RB
+	ASM_RT		mnemonic RT
+	ASM_RTA		mnemonic RT, RA
+	ASM_WRCH	mnemonic CA, RT
+
+Note that RRR instructions have the names for RC and RT reversed from
+what's in the ISA, in order to put RT in the same position it appears
+for other formats.
+
+-=-=-= DEPENDENCY =-=-=-
+
+DEPENDENCY filed consists of 5 digits. This represents which register is used as source and which register is used as target.
+The first(most significant) digit is always 0. Then it is followd by RC, RB, RA and RT digits.
+If the digit is 0, this means the corresponding register is not used in the instruction.
+If the digit is 1, this means the corresponding register is used as a source in the instruction.
+If the digit is 2, this means the corresponding register is used as a target in the instruction.
+If the digit is 3, this means the corresponding register is used as both source and target in the instruction.
+For example, fms instruction has 00113 as the DEPENDENCY field. This means RC is not used in this operation, RB and RA are
+used as sources and RT is the target.
+
+-=-=-= PIPE =-=-=-
+
+This field shows which execution pipe is used for the instruction
+
+pipe0 execution pipelines:
+	FP6	SP floating pipeline
+	FP7	integer operations executed in SP floating pipeline
+	FPD	DP floating pipeline
+	FX2	FXU pipeline
+	FX3	Rotate/Shift pipeline
+	FXB	Byte pipeline
+	NOP	No pipeline
+
+pipe1 execution pipelines:
+	BR	Branch pipeline
+	LNOP	No pipeline
+	LS	Load/Store pipeline
+	SHUF	Shuffle pipeline
+	SPR	SPR/CH pipeline
+
+*/
+
+#define _A0() {0}
+#define _A1(a) {1,a}
+#define _A2(a,b) {2,a,b}
+#define _A3(a,b,c) {3,a,b,c}
+#define _A4(a,b,c,d) {4,a,b,c,d}
+
+/*    TAG		FORMAT	OPCODE	MNEMONIC	ASM_FORMAT	DEPENDENCY	PIPE	COMMENT				*/
+/*									0[RC][RB][RA][RT]					*/
+/*									1:src, 2:target						*/
+
+APUOP(M_BR,		RI16,	0x190,	"br",		_A1(A_R18),	00000,	BR)	/* BRel          IP<-IP+I16 */
+APUOP(M_BRSL,		RI16,	0x198,	"brsl",		_A2(A_T,A_R18),	00002,	BR)	/* BRelSetLink   RT,IP<-IP,IP+I16 */
+APUOP(M_BRA,		RI16,	0x180,	"bra",		_A1(A_S18),	00000,	BR)	/* BRAbs         IP<-I16 */
+APUOP(M_BRASL,		RI16,	0x188,	"brasl",	_A2(A_T,A_S18),	00002,	BR)	/* BRAbsSetLink  RT,IP<-IP,I16 */
+APUOP(M_FSMBI,		RI16,	0x194,	"fsmbi",	_A2(A_T,A_X16),	00002,	SHUF)	/* FormSelMask%I RT<-fsm(I16) */
+APUOP(M_LQA,		RI16,	0x184,	"lqa",		_A2(A_T,A_S18),	00002,	LS)	/* LoadQAbs      RT<-M[I16] */
+APUOP(M_LQR,		RI16,	0x19C,	"lqr",		_A2(A_T,A_R18),	00002,	LS)	/* LoadQRel      RT<-M[IP+I16] */
+APUOP(M_STOP,		RR,	0x000,	"stop",		_A0(),		00000,	BR)	/* STOP          stop */
+APUOP(M_STOP2,		RR,	0x000,	"stop",		_A1(A_U14),	00000,	BR)	/* STOP          stop */
+APUOP(M_STOPD,		RR,	0x140,	"stopd",	_A3(A_T,A_A,A_B),         00111,	BR)	/* STOPD         stop (with register dependencies) */
+APUOP(M_LNOP,		RR,	0x001,	"lnop",		_A0(),		00000,	LNOP)	/* LNOP          no_operation */
+APUOP(M_SYNC,		RR,	0x002,	"sync",		_A0(),		00000,	BR)	/* SYNC          flush_pipe */
+APUOP(M_DSYNC,		RR,	0x003,	"dsync",	_A0(),		00000,	BR)	/* DSYNC         flush_store_queue */
+APUOP(M_MFSPR,		RR,	0x00c,	"mfspr",	_A2(A_T,A_S),	00002,	SPR)	/* MFSPR         RT<-SA */
+APUOP(M_RDCH,		RR,	0x00d,	"rdch",		_A2(A_T,A_H),	00002,	SPR)	/* ReaDCHannel   RT<-CA:data */
+APUOP(M_RCHCNT,		RR,	0x00f,	"rchcnt",	_A2(A_T,A_H),	00002,	SPR)	/* ReaDCHanCouNT RT<-CA:count */
+APUOP(M_HBRA,		LBT,	0x080,	"hbra",		_A2(A_S11,A_S18),	00000,	LS)	/* HBRA          BTB[B9]<-M[I16] */
+APUOP(M_HBRR,		LBT,	0x090,	"hbrr",		_A2(A_S11,A_R18),	00000,	LS)	/* HBRR          BTB[B9]<-M[IP+I16] */
+APUOP(M_BRZ,		RI16,	0x100,	"brz",		_A2(A_T,A_R18),	00001,	BR)	/* BRZ           IP<-IP+I16_if(RT) */
+APUOP(M_BRNZ,		RI16,	0x108,	"brnz",		_A2(A_T,A_R18),	00001,	BR)	/* BRNZ          IP<-IP+I16_if(RT) */
+APUOP(M_BRHZ,		RI16,	0x110,	"brhz",		_A2(A_T,A_R18),	00001,	BR)	/* BRHZ          IP<-IP+I16_if(RT) */
+APUOP(M_BRHNZ,		RI16,	0x118,	"brhnz",	_A2(A_T,A_R18),	00001,	BR)	/* BRHNZ         IP<-IP+I16_if(RT) */
+APUOP(M_STQA,		RI16,	0x104,	"stqa",		_A2(A_T,A_S18),	00001,	LS)	/* SToreQAbs     M[I16]<-RT */
+APUOP(M_STQR,		RI16,	0x11C,	"stqr",		_A2(A_T,A_R18),	00001,	LS)	/* SToreQRel     M[IP+I16]<-RT */
+APUOP(M_MTSPR,		RR,	0x10c,	"mtspr",	_A2(A_S,A_T),	00001,	SPR)	/* MTSPR         SA<-RT */
+APUOP(M_WRCH,		RR,	0x10d,	"wrch",		_A2(A_H,A_T),	00001,	SPR)	/* ChanWRite     CA<-RT */
+APUOP(M_LQD,		RI10,	0x1a0,	"lqd",		_A4(A_T,A_S14,A_P,A_A),	00012,	LS)	/* LoadQDisp     RT<-M[Ra+I10] */
+APUOP(M_BI,		RR,	0x1a8,	"bi",		_A1(A_A),		00010,	BR)	/* BI            IP<-RA */
+APUOP(M_BISL,		RR,	0x1a9,	"bisl",		_A2(A_T,A_A),	00012,	BR)	/* BISL          RT,IP<-IP,RA */
+APUOP(M_IRET,  		RR,	0x1aa,	"iret",	        _A1(A_A), 	00010,	BR)	/* IRET          IP<-SRR0 */
+APUOP(M_IRET2, 		RR,	0x1aa,	"iret",	        _A0(),	 	00010,	BR)	/* IRET          IP<-SRR0 */
+APUOP(M_BISLED,		RR,	0x1ab,	"bisled",	_A2(A_T,A_A),	00012,	BR)	/* BISLED        RT,IP<-IP,RA_if(ext) */
+APUOP(M_HBR,		LBTI,	0x1ac,	"hbr",		_A2(A_S11I,A_A),	00010,	LS)	/* HBR           BTB[B9]<-M[Ra] */
+APUOP(M_FREST,		RR,	0x1b8,	"frest",	_A2(A_T,A_A),	00012,	SHUF)	/* FREST         RT<-recip(RA) */
+APUOP(M_FRSQEST,	RR,	0x1b9,	"frsqest",	_A2(A_T,A_A),	00012,	SHUF)	/* FRSQEST       RT<-rsqrt(RA) */
+APUOP(M_FSM,		RR,	0x1b4,	"fsm",		_A2(A_T,A_A),	00012,	SHUF)	/* FormSelMask%  RT<-expand(Ra) */
+APUOP(M_FSMH,		RR,	0x1b5,	"fsmh",		_A2(A_T,A_A),	00012,	SHUF)	/* FormSelMask%  RT<-expand(Ra) */
+APUOP(M_FSMB,		RR,	0x1b6,	"fsmb",		_A2(A_T,A_A),	00012,	SHUF)	/* FormSelMask%  RT<-expand(Ra) */
+APUOP(M_GB,		RR,	0x1b0,	"gb",		_A2(A_T,A_A),	00012,	SHUF)	/* GatherBits%   RT<-gather(RA) */
+APUOP(M_GBH,		RR,	0x1b1,	"gbh",		_A2(A_T,A_A),	00012,	SHUF)	/* GatherBits%   RT<-gather(RA) */
+APUOP(M_GBB,		RR,	0x1b2,	"gbb",		_A2(A_T,A_A),	00012,	SHUF)	/* GatherBits%   RT<-gather(RA) */
+APUOP(M_CBD,		RI7,	0x1f4,	"cbd",		_A4(A_T,A_U7,A_P,A_A),	00012,	SHUF)	/* genCtl%%insD  RT<-sta(Ra+I4,siz) */
+APUOP(M_CHD,		RI7,	0x1f5,	"chd",		_A4(A_T,A_U7,A_P,A_A),	00012,	SHUF)	/* genCtl%%insD  RT<-sta(Ra+I4,siz) */
+APUOP(M_CWD,		RI7,	0x1f6,	"cwd",		_A4(A_T,A_U7,A_P,A_A),	00012,	SHUF)	/* genCtl%%insD  RT<-sta(Ra+I4,siz) */
+APUOP(M_CDD,		RI7,	0x1f7,	"cdd",		_A4(A_T,A_U7,A_P,A_A),	00012,	SHUF)	/* genCtl%%insD  RT<-sta(Ra+I4,siz) */
+APUOP(M_ROTQBII,	RI7,	0x1f8,	"rotqbii",	_A3(A_T,A_A,A_U3),	00012,	SHUF)	/* ROTQBII       RT<-RA<<<I7 */
+APUOP(M_ROTQBYI,	RI7,	0x1fc,	"rotqbyi",	_A3(A_T,A_A,A_S7N),	00012,	SHUF)	/* ROTQBYI       RT<-RA<<<(I7*8) */
+APUOP(M_ROTQMBII,	RI7,	0x1f9,	"rotqmbii",	_A3(A_T,A_A,A_S3),	00012,	SHUF)	/* ROTQMBII      RT<-RA<<I7 */
+APUOP(M_ROTQMBYI,	RI7,	0x1fd,	"rotqmbyi",	_A3(A_T,A_A,A_S6),	00012,	SHUF)	/* ROTQMBYI      RT<-RA<<I7 */
+APUOP(M_SHLQBII,	RI7,	0x1fb,	"shlqbii",	_A3(A_T,A_A,A_U3),	00012,	SHUF)	/* SHLQBII       RT<-RA<<I7 */
+APUOP(M_SHLQBYI,	RI7,	0x1ff,	"shlqbyi",	_A3(A_T,A_A,A_U5),	00012,	SHUF)	/* SHLQBYI       RT<-RA<<I7 */
+APUOP(M_STQD,		RI10,	0x120,	"stqd",		_A4(A_T,A_S14,A_P,A_A),	00011,	LS)	/* SToreQDisp    M[Ra+I10]<-RT */
+APUOP(M_BIHNZ,		RR,	0x12b,	"bihnz",	_A2(A_T,A_A),	00011,	BR)	/* BIHNZ         IP<-RA_if(RT) */
+APUOP(M_BIHZ,		RR,	0x12a,	"bihz",		_A2(A_T,A_A),	00011,	BR)	/* BIHZ          IP<-RA_if(RT) */
+APUOP(M_BINZ,		RR,	0x129,	"binz",		_A2(A_T,A_A),	00011,	BR)	/* BINZ          IP<-RA_if(RT) */
+APUOP(M_BIZ,		RR,	0x128,	"biz",		_A2(A_T,A_A),	00011,	BR)	/* BIZ           IP<-RA_if(RT) */
+APUOP(M_CBX,		RR,	0x1d4,	"cbx",		_A3(A_T,A_A,A_B),		00112,	SHUF)	/* genCtl%%insX  RT<-sta(Ra+Rb,siz) */
+APUOP(M_CHX,		RR,	0x1d5,	"chx",		_A3(A_T,A_A,A_B),		00112,	SHUF)	/* genCtl%%insX  RT<-sta(Ra+Rb,siz) */
+APUOP(M_CWX,		RR,	0x1d6,	"cwx",		_A3(A_T,A_A,A_B),		00112,	SHUF)	/* genCtl%%insX  RT<-sta(Ra+Rb,siz) */
+APUOP(M_CDX,		RR,	0x1d7,	"cdx",		_A3(A_T,A_A,A_B),		00112,	SHUF)	/* genCtl%%insX  RT<-sta(Ra+Rb,siz) */
+APUOP(M_LQX,		RR,	0x1c4,	"lqx",		_A3(A_T,A_A,A_B),		00112,	LS)	/* LoadQindeX    RT<-M[Ra+Rb] */
+APUOP(M_ROTQBI,		RR,	0x1d8,	"rotqbi",	_A3(A_T,A_A,A_B),		00112,	SHUF)	/* ROTQBI        RT<-RA<<<Rb */
+APUOP(M_ROTQMBI,	RR,	0x1d9,	"rotqmbi",	_A3(A_T,A_A,A_B),		00112,	SHUF)	/* ROTQMBI       RT<-RA<<Rb */
+APUOP(M_SHLQBI,		RR,	0x1db,	"shlqbi",	_A3(A_T,A_A,A_B),		00112,	SHUF)	/* SHLQBI        RT<-RA<<Rb */
+APUOP(M_ROTQBY,		RR,	0x1dc,	"rotqby",	_A3(A_T,A_A,A_B),		00112,		SHUF)	/* ROTQBY        RT<-RA<<<(Rb*8) */
+APUOP(M_ROTQMBY,	RR,	0x1dd,	"rotqmby",	_A3(A_T,A_A,A_B),		00112,		SHUF)	/* ROTQMBY       RT<-RA<<Rb */
+APUOP(M_SHLQBY,		RR,	0x1df,	"shlqby",	_A3(A_T,A_A,A_B),		00112,	SHUF)	/* SHLQBY        RT<-RA<<Rb */
+APUOP(M_ROTQBYBI,	RR,	0x1cc,	"rotqbybi",	_A3(A_T,A_A,A_B),		00112,		SHUF)	/* ROTQBYBI      RT<-RA<<Rb */
+APUOP(M_ROTQMBYBI,	RR,	0x1cd,	"rotqmbybi",	_A3(A_T,A_A,A_B),		00112,		SHUF)	/* ROTQMBYBI     RT<-RA<<Rb */
+APUOP(M_SHLQBYBI,	RR,	0x1cf,	"shlqbybi",	_A3(A_T,A_A,A_B),		00112,	SHUF)	/* SHLQBYBI      RT<-RA<<Rb */
+APUOP(M_STQX,		RR,	0x144,	"stqx",		_A3(A_T,A_A,A_B),		00111,	LS)	/* SToreQindeX   M[Ra+Rb]<-RT */
+APUOP(M_SHUFB,		RRR,	0x580,	"shufb",	_A4(A_C,A_A,A_B,A_T),	02111,	SHUF)	/* SHUFfleBytes  RC<-f(RA,RB,RT) */
+APUOP(M_IL,		RI16,	0x204,	"il",		_A2(A_T,A_S16),	00002,	FX2)	/* ImmLoad       RT<-sxt(I16) */
+APUOP(M_ILH,		RI16,	0x20c,	"ilh",		_A2(A_T,A_X16),	00002,	FX2)	/* ImmLoadH      RT<-I16 */
+APUOP(M_ILHU,		RI16,	0x208,	"ilhu",		_A2(A_T,A_X16),	00002,	FX2)	/* ImmLoadHUpper RT<-I16<<16 */
+APUOP(M_ILA,		RI18,	0x210,	"ila",		_A2(A_T,A_U18),	00002,	FX2)	/* ImmLoadAddr   RT<-zxt(I18) */
+APUOP(M_NOP,		RR,	0x201,	"nop",		_A1(A_T),		00000,	NOP)	/* XNOP          no_operation */
+APUOP(M_NOP2,		RR,	0x201,	"nop",		_A0(),		00000,	NOP)	/* XNOP          no_operation */
+APUOP(M_IOHL,		RI16,	0x304,	"iohl",		_A2(A_T,A_X16),	00003,	FX2)	/* AddImmeXt     RT<-RT+sxt(I16) */
+APUOP(M_ANDBI,		RI10,	0x0b0,	"andbi",	_A3(A_T,A_A,A_S10B),	00012,	FX2)	/* AND%I         RT<-RA&I10 */
+APUOP(M_ANDHI,		RI10,	0x0a8,	"andhi",	_A3(A_T,A_A,A_S10),	00012,	FX2)	/* AND%I         RT<-RA&I10 */
+APUOP(M_ANDI,		RI10,	0x0a0,	"andi",		_A3(A_T,A_A,A_S10),	00012,	FX2)	/* AND%I         RT<-RA&I10 */
+APUOP(M_ORBI,		RI10,	0x030,	"orbi",		_A3(A_T,A_A,A_S10B),	00012,	FX2)	/* OR%I          RT<-RA|I10 */
+APUOP(M_ORHI,		RI10,	0x028,	"orhi",		_A3(A_T,A_A,A_S10),	00012,	FX2)	/* OR%I          RT<-RA|I10 */
+APUOP(M_ORI,		RI10,	0x020,	"ori",		_A3(A_T,A_A,A_S10),	00012,	FX2)	/* OR%I          RT<-RA|I10 */
+APUOP(M_ORX,		RR,	0x1f0,	"orx",		_A2(A_T,A_A),		00012,	BR)	/* ORX           RT<-RA.w0|RA.w1|RA.w2|RA.w3 */
+APUOP(M_XORBI,		RI10,	0x230,	"xorbi",	_A3(A_T,A_A,A_S10B),	00012,	FX2)	/* XOR%I         RT<-RA^I10 */
+APUOP(M_XORHI,		RI10,	0x228,	"xorhi",	_A3(A_T,A_A,A_S10),	00012,	FX2)	/* XOR%I         RT<-RA^I10 */
+APUOP(M_XORI,		RI10,	0x220,	"xori",		_A3(A_T,A_A,A_S10),	00012,	FX2)	/* XOR%I         RT<-RA^I10 */
+APUOP(M_AHI,		RI10,	0x0e8,	"ahi",		_A3(A_T,A_A,A_S10),	00012,	FX2)	/* Add%Immed     RT<-RA+I10 */
+APUOP(M_AI,		RI10,	0x0e0,	"ai",		_A3(A_T,A_A,A_S10),	00012,	FX2)	/* Add%Immed     RT<-RA+I10 */
+APUOP(M_SFHI,		RI10,	0x068,	"sfhi",		_A3(A_T,A_A,A_S10),	00012,	FX2)	/* SubFrom%Imm   RT<-I10-RA */
+APUOP(M_SFI,		RI10,	0x060,	"sfi",		_A3(A_T,A_A,A_S10),	00012,	FX2)	/* SubFrom%Imm   RT<-I10-RA */
+APUOP(M_CGTBI,		RI10,	0x270,	"cgtbi",	_A3(A_T,A_A,A_S10B),	00012,	FX2)	/* CGT%I         RT<-(RA>I10) */
+APUOP(M_CGTHI,		RI10,	0x268,	"cgthi",	_A3(A_T,A_A,A_S10),	00012,	FX2)	/* CGT%I         RT<-(RA>I10) */
+APUOP(M_CGTI,		RI10,	0x260,	"cgti",		_A3(A_T,A_A,A_S10),	00012,	FX2)	/* CGT%I         RT<-(RA>I10) */
+APUOP(M_CLGTBI,		RI10,	0x2f0,	"clgtbi",	_A3(A_T,A_A,A_S10B),	00012,	FX2)	/* CLGT%I        RT<-(RA>I10) */
+APUOP(M_CLGTHI,		RI10,	0x2e8,	"clgthi",	_A3(A_T,A_A,A_S10),	00012,	FX2)	/* CLGT%I        RT<-(RA>I10) */
+APUOP(M_CLGTI,		RI10,	0x2e0,	"clgti",	_A3(A_T,A_A,A_S10),	00012,	FX2)	/* CLGT%I        RT<-(RA>I10) */
+APUOP(M_CEQBI,		RI10,	0x3f0,	"ceqbi",	_A3(A_T,A_A,A_S10B),	00012,	FX2)	/* CEQ%I         RT<-(RA=I10) */
+APUOP(M_CEQHI,		RI10,	0x3e8,	"ceqhi",	_A3(A_T,A_A,A_S10),	00012,	FX2)	/* CEQ%I         RT<-(RA=I10) */
+APUOP(M_CEQI,		RI10,	0x3e0,	"ceqi",		_A3(A_T,A_A,A_S10),	00012,	FX2)	/* CEQ%I         RT<-(RA=I10) */
+APUOP(M_HGTI,		RI10,	0x278,	"hgti",		_A3(A_T,A_A,A_S10),	00010,	FX2)	/* HaltGTI       halt_if(RA>I10) */
+APUOP(M_HGTI2,		RI10,	0x278,	"hgti",		_A2(A_A,A_S10),	00010,	FX2)	/* HaltGTI       halt_if(RA>I10) */
+APUOP(M_HLGTI,		RI10,	0x2f8,	"hlgti",	_A3(A_T,A_A,A_S10),	00010,	FX2)	/* HaltLGTI      halt_if(RA>I10) */
+APUOP(M_HLGTI2,		RI10,	0x2f8,	"hlgti",	_A2(A_A,A_S10),	00010,	FX2)	/* HaltLGTI      halt_if(RA>I10) */
+APUOP(M_HEQI,		RI10,	0x3f8,	"heqi",		_A3(A_T,A_A,A_S10),	00010,	FX2)	/* HaltEQImm     halt_if(RA=I10) */
+APUOP(M_HEQI2,		RI10,	0x3f8,	"heqi",		_A2(A_A,A_S10),	00010,	FX2)	/* HaltEQImm     halt_if(RA=I10) */
+APUOP(M_MPYI,		RI10,	0x3a0,	"mpyi",		_A3(A_T,A_A,A_S10),	00012,	FP7)	/* MPYI          RT<-RA*I10 */
+APUOP(M_MPYUI,		RI10,	0x3a8,	"mpyui",	_A3(A_T,A_A,A_S10),	00012,	FP7)	/* MPYUI         RT<-RA*I10 */
+APUOP(M_CFLTS,		RI8,	0x3b0,	"cflts",	_A3(A_T,A_A,A_U7A),	00012,	FP7)	/* CFLTS         RT<-int(RA,I8) */
+APUOP(M_CFLTU,		RI8,	0x3b2,	"cfltu",	_A3(A_T,A_A,A_U7A),	00012,	FP7)	/* CFLTU         RT<-int(RA,I8) */
+APUOP(M_CSFLT,		RI8,	0x3b4,	"csflt",	_A3(A_T,A_A,A_U7B),	00012,	FP7)	/* CSFLT         RT<-flt(RA,I8) */
+APUOP(M_CUFLT,		RI8,	0x3b6,	"cuflt",	_A3(A_T,A_A,A_U7B),	00012,	FP7)	/* CUFLT         RT<-flt(RA,I8) */
+APUOP(M_FESD,		RR,	0x3b8,	"fesd",		_A2(A_T,A_A),	00012,	FPD)	/* FESD          RT<-double(RA) */
+APUOP(M_FRDS,		RR,	0x3b9,	"frds",		_A2(A_T,A_A),	00012,	FPD)	/* FRDS          RT<-single(RA) */
+APUOP(M_FSCRRD,		RR,	0x398,	"fscrrd",	_A1(A_T),		00002,	FPD)	/* FSCRRD        RT<-FP_status */
+APUOP(M_FSCRWR,		RR,	0x3ba,	"fscrwr",	_A2(A_T,A_A),	00010,	FP7)	/* FSCRWR        FP_status<-RA */
+APUOP(M_FSCRWR2,	RR,	0x3ba,	"fscrwr",	_A1(A_A),		00010,	FP7)	/* FSCRWR        FP_status<-RA */
+APUOP(M_CLZ,		RR,	0x2a5,	"clz",		_A2(A_T,A_A),	00012,	FX2)	/* CLZ           RT<-clz(RA) */
+APUOP(M_CNTB,		RR,	0x2b4,	"cntb",		_A2(A_T,A_A),	00012,	FXB)	/* CNT           RT<-pop(RA) */
+APUOP(M_XSBH,		RR,	0x2b6,	"xsbh",		_A2(A_T,A_A),	00012,	FX2)	/* eXtSignBtoH   RT<-sign_ext(RA) */
+APUOP(M_XSHW,		RR,	0x2ae,	"xshw",		_A2(A_T,A_A),	00012,	FX2)	/* eXtSignHtoW   RT<-sign_ext(RA) */
+APUOP(M_XSWD,		RR,	0x2a6,	"xswd",		_A2(A_T,A_A),	00012,	FX2)	/* eXtSignWtoD   RT<-sign_ext(RA) */
+APUOP(M_ROTI,		RI7,	0x078,	"roti",		_A3(A_T,A_A,A_S7N),	00012,	FX3)	/* ROT%I         RT<-RA<<<I7 */
+APUOP(M_ROTMI,		RI7,	0x079,	"rotmi",	_A3(A_T,A_A,A_S7),	00012,	FX3)	/* ROT%MI        RT<-RA<<I7 */
+APUOP(M_ROTMAI,		RI7,	0x07a,	"rotmai",	_A3(A_T,A_A,A_S7),	00012,	FX3)	/* ROTMA%I       RT<-RA<<I7 */
+APUOP(M_SHLI,		RI7,	0x07b,	"shli",		_A3(A_T,A_A,A_U6),	00012,	FX3)	/* SHL%I         RT<-RA<<I7 */
+APUOP(M_ROTHI,		RI7,	0x07c,	"rothi",	_A3(A_T,A_A,A_S7N),	00012,	FX3)	/* ROT%I         RT<-RA<<<I7 */
+APUOP(M_ROTHMI,		RI7,	0x07d,	"rothmi",	_A3(A_T,A_A,A_S6),	00012,	FX3)	/* ROT%MI        RT<-RA<<I7 */
+APUOP(M_ROTMAHI,	RI7,	0x07e,	"rotmahi",	_A3(A_T,A_A,A_S6),	00012,	FX3)	/* ROTMA%I       RT<-RA<<I7 */
+APUOP(M_SHLHI,		RI7,	0x07f,	"shlhi",	_A3(A_T,A_A,A_U5),	00012,	FX3)	/* SHL%I         RT<-RA<<I7 */
+APUOP(M_A,		RR,	0x0c0,	"a",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* Add%          RT<-RA+RB */
+APUOP(M_AH,		RR,	0x0c8,	"ah",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* Add%          RT<-RA+RB */
+APUOP(M_SF,		RR,	0x040,	"sf",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* SubFrom%      RT<-RB-RA */
+APUOP(M_SFH,		RR,	0x048,	"sfh",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* SubFrom%      RT<-RB-RA */
+APUOP(M_CGT,		RR,	0x240,	"cgt",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* CGT%          RT<-(RA>RB) */
+APUOP(M_CGTB,		RR,	0x250,	"cgtb",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* CGT%          RT<-(RA>RB) */
+APUOP(M_CGTH,		RR,	0x248,	"cgth",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* CGT%          RT<-(RA>RB) */
+APUOP(M_CLGT,		RR,	0x2c0,	"clgt",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* CLGT%         RT<-(RA>RB) */
+APUOP(M_CLGTB,		RR,	0x2d0,	"clgtb",	_A3(A_T,A_A,A_B),		00112,	FX2)	/* CLGT%         RT<-(RA>RB) */
+APUOP(M_CLGTH,		RR,	0x2c8,	"clgth",	_A3(A_T,A_A,A_B),		00112,	FX2)	/* CLGT%         RT<-(RA>RB) */
+APUOP(M_CEQ,		RR,	0x3c0,	"ceq",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* CEQ%          RT<-(RA=RB) */
+APUOP(M_CEQB,		RR,	0x3d0,	"ceqb",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* CEQ%          RT<-(RA=RB) */
+APUOP(M_CEQH,		RR,	0x3c8,	"ceqh",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* CEQ%          RT<-(RA=RB) */
+APUOP(M_HGT,		RR,	0x258,	"hgt",		_A3(A_T,A_A,A_B),		00110,	FX2)	/* HaltGT        halt_if(RA>RB) */
+APUOP(M_HGT2,		RR,	0x258,	"hgt",		_A2(A_A,A_B),	00110,	FX2)	/* HaltGT        halt_if(RA>RB) */
+APUOP(M_HLGT,		RR,	0x2d8,	"hlgt",		_A3(A_T,A_A,A_B),		00110,	FX2)	/* HaltLGT       halt_if(RA>RB) */
+APUOP(M_HLGT2,		RR,	0x2d8,	"hlgt",		_A2(A_A,A_B),	00110,	FX2)	/* HaltLGT       halt_if(RA>RB) */
+APUOP(M_HEQ,		RR,	0x3d8,	"heq",		_A3(A_T,A_A,A_B),		00110,	FX2)	/* HaltEQ        halt_if(RA=RB) */
+APUOP(M_HEQ2,		RR,	0x3d8,	"heq",		_A2(A_A,A_B),	00110,	FX2)	/* HaltEQ        halt_if(RA=RB) */
+APUOP(M_FCEQ,		RR,	0x3c2,	"fceq",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* FCEQ          RT<-(RA=RB) */
+APUOP(M_FCMEQ,		RR,	0x3ca,	"fcmeq",	_A3(A_T,A_A,A_B),		00112,	FX2)	/* FCMEQ         RT<-(|RA|=|RB|) */
+APUOP(M_FCGT,		RR,	0x2c2,	"fcgt",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* FCGT          RT<-(RA<RB) */
+APUOP(M_FCMGT,		RR,	0x2ca,	"fcmgt",	_A3(A_T,A_A,A_B),		00112,	FX2)	/* FCMGT         RT<-(|RA|<|RB|) */
+APUOP(M_AND,		RR,	0x0c1,	"and",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* AND           RT<-RA&RB */
+APUOP(M_NAND,		RR,	0x0c9,	"nand",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* NAND          RT<-!(RA&RB) */
+APUOP(M_OR,		RR,	0x041,	"or",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* OR            RT<-RA|RB */
+APUOP(M_NOR,		RR,	0x049,	"nor",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* NOR           RT<-!(RA&RB) */
+APUOP(M_XOR,		RR,	0x241,	"xor",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* XOR           RT<-RA^RB */
+APUOP(M_EQV,		RR,	0x249,	"eqv",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* EQuiValent    RT<-!(RA^RB) */
+APUOP(M_ANDC,		RR,	0x2c1,	"andc",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* ANDComplement RT<-RA&!RB */
+APUOP(M_ORC,		RR,	0x2c9,	"orc",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* ORComplement  RT<-RA|!RB */
+APUOP(M_ABSDB,		RR,	0x053,	"absdb",	_A3(A_T,A_A,A_B),		00112,	FXB)	/* ABSoluteDiff  RT<-|RA-RB| */
+APUOP(M_AVGB,		RR,	0x0d3,	"avgb",		_A3(A_T,A_A,A_B),		00112,	FXB)	/* AVG%          RT<-(RA+RB+1)/2 */
+APUOP(M_SUMB,		RR,	0x253,	"sumb",		_A3(A_T,A_A,A_B),		00112,	FXB)	/* SUM%          RT<-f(RA,RB) */
+APUOP(M_DFA,		RR,	0x2cc,	"dfa",		_A3(A_T,A_A,A_B),		00112,	FPD)	/* DFAdd         RT<-RA+RB */
+APUOP(M_DFM,		RR,	0x2ce,	"dfm",		_A3(A_T,A_A,A_B),		00112,	FPD)	/* DFMul         RT<-RA*RB */
+APUOP(M_DFS,		RR,	0x2cd,	"dfs",		_A3(A_T,A_A,A_B),		00112,	FPD)	/* DFSub         RT<-RA-RB */
+APUOP(M_FA,		RR,	0x2c4,	"fa",		_A3(A_T,A_A,A_B),		00112,	FP6)	/* FAdd          RT<-RA+RB */
+APUOP(M_FM,		RR,	0x2c6,	"fm",		_A3(A_T,A_A,A_B),		00112,	FP6)	/* FMul          RT<-RA*RB */
+APUOP(M_FS,		RR,	0x2c5,	"fs",		_A3(A_T,A_A,A_B),		00112,	FP6)	/* FSub          RT<-RA-RB */
+APUOP(M_MPY,		RR,	0x3c4,	"mpy",		_A3(A_T,A_A,A_B),		00112,	FP7)	/* MPY           RT<-RA*RB */
+APUOP(M_MPYH,		RR,	0x3c5,	"mpyh",		_A3(A_T,A_A,A_B),		00112,	FP7)	/* MPYH          RT<-(RAh*RB)<<16 */
+APUOP(M_MPYHH,		RR,	0x3c6,	"mpyhh",	_A3(A_T,A_A,A_B),		00112,	FP7)	/* MPYHH         RT<-RAh*RBh */
+APUOP(M_MPYHHU,		RR,	0x3ce,	"mpyhhu",	_A3(A_T,A_A,A_B),		00112,	FP7)	/* MPYHHU        RT<-RAh*RBh */
+APUOP(M_MPYS,		RR,	0x3c7,	"mpys",		_A3(A_T,A_A,A_B),		00112,	FP7)	/* MPYS          RT<-(RA*RB)>>16 */
+APUOP(M_MPYU,		RR,	0x3cc,	"mpyu",		_A3(A_T,A_A,A_B),		00112,	FP7)	/* MPYU          RT<-RA*RB */
+APUOP(M_FI,		RR,	0x3d4,	"fi",		_A3(A_T,A_A,A_B),		00112,	FP7)	/* FInterpolate  RT<-f(RA,RB) */
+APUOP(M_ROT,		RR,	0x058,	"rot",		_A3(A_T,A_A,A_B),		00112,	FX3)	/* ROT%          RT<-RA<<<RB */
+APUOP(M_ROTM,		RR,	0x059,	"rotm",		_A3(A_T,A_A,A_B),		00112,	FX3)	/* ROT%M         RT<-RA<<Rb */
+APUOP(M_ROTMA,		RR,	0x05a,	"rotma",	_A3(A_T,A_A,A_B),		00112,	FX3)	/* ROTMA%        RT<-RA<<Rb */
+APUOP(M_SHL,		RR,	0x05b,	"shl",		_A3(A_T,A_A,A_B),		00112,	FX3)	/* SHL%          RT<-RA<<Rb */
+APUOP(M_ROTH,		RR,	0x05c,	"roth",		_A3(A_T,A_A,A_B),		00112,	FX3)	/* ROT%          RT<-RA<<<RB */
+APUOP(M_ROTHM,		RR,	0x05d,	"rothm",	_A3(A_T,A_A,A_B),		00112,	FX3)	/* ROT%M         RT<-RA<<Rb */
+APUOP(M_ROTMAH,		RR,	0x05e,	"rotmah",	_A3(A_T,A_A,A_B),		00112,	FX3)	/* ROTMA%        RT<-RA<<Rb */
+APUOP(M_SHLH,		RR,	0x05f,	"shlh",		_A3(A_T,A_A,A_B),		00112,	FX3)	/* SHL%          RT<-RA<<Rb */
+APUOP(M_MPYHHA,		RR,	0x346,	"mpyhha",	_A3(A_T,A_A,A_B),		00113,	FP7)	/* MPYHHA        RT<-RAh*RBh+RT */
+APUOP(M_MPYHHAU,	RR,	0x34e,	"mpyhhau",	_A3(A_T,A_A,A_B),		00113,	FP7)	/* MPYHHAU       RT<-RAh*RBh+RT */
+APUOP(M_DFMA,		RR,	0x35c,	"dfma",		_A3(A_T,A_A,A_B),		00113,	FPD)	/* DFMAdd        RT<-RT+RA*RB */
+APUOP(M_DFMS,		RR,	0x35d,	"dfms",		_A3(A_T,A_A,A_B),		00113,	FPD)	/* DFMSub        RT<-RA*RB-RT */
+APUOP(M_DFNMS,		RR,	0x35e,	"dfnms",	_A3(A_T,A_A,A_B),		00113,	FPD)	/* DFNMSub       RT<-RT-RA*RB */
+APUOP(M_DFNMA,		RR,	0x35f,	"dfnma",	_A3(A_T,A_A,A_B),		00113,	FPD)	/* DFNMAdd       RT<-(-RT)-RA*RB */
+APUOP(M_FMA,		RRR,	0x700,	"fma",		_A4(A_C,A_A,A_B,A_T),	02111,	FP6)	/* FMAdd         RC<-RT+RA*RB */
+APUOP(M_FMS,		RRR,	0x780,	"fms",		_A4(A_C,A_A,A_B,A_T),	02111,	FP6)	/* FMSub         RC<-RA*RB-RT */
+APUOP(M_FNMS,		RRR,	0x680,	"fnms",		_A4(A_C,A_A,A_B,A_T),	02111,	FP6)	/* FNMSub        RC<-RT-RA*RB */
+APUOP(M_MPYA,		RRR,	0x600,	"mpya",		_A4(A_C,A_A,A_B,A_T),	02111,	FP7)	/* MPYA          RC<-RA*RB+RT */
+APUOP(M_SELB,		RRR,	0x400,	"selb",		_A4(A_C,A_A,A_B,A_T),	02111,	FX2)	/* SELectBits    RC<-RA&RT|RB&!RT */
+/* for system function call, this uses op-code of mtspr */
+APUOP(M_SYSCALL,	RI7,    0x10c,	"syscall",      _A3(A_T,A_A,A_S7N),	00002,	SPR)        /* System Call */
+/*
+pseudo instruction:
+system call
+value of I9	operation
+0	halt
+1		rt[0] = open(MEM[ra[0]],	ra[1])
+2		rt[0] = close(ra[0])
+3		rt[0] = read(ra[0],	MEM[ra[1]],	ra[2])
+4		rt[0] = write(ra[0],	MEM[ra[1]],	ra[2])
+5		printf(MEM[ra[0]],	ra[1],	ra[2],	ra[3])
+42		rt[0] = clock()
+52		rt[0] = lseek(ra0,	ra1,	ra2)
+
+*/
+
+
+/* new multiprecision add/sub */
+APUOP(M_ADDX,		RR,	0x340,	"addx",		_A3(A_T,A_A,A_B),		00113,		FX2)	/* Add_eXtended  RT<-RA+RB+RT */
+APUOP(M_CG,		RR,	0x0c2,	"cg",		_A3(A_T,A_A,A_B),		00112,		FX2)	/* CarryGenerate RT<-cout(RA+RB) */
+APUOP(M_CGX,		RR,	0x342,	"cgx",		_A3(A_T,A_A,A_B),		00113,		FX2)	/* CarryGen_eXtd RT<-cout(RA+RB+RT) */
+APUOP(M_SFX,		RR,	0x341,	"sfx",		_A3(A_T,A_A,A_B),		00113,		FX2)	/* Add_eXtended  RT<-RA+RB+RT */
+APUOP(M_BG,		RR,	0x042,	"bg",		_A3(A_T,A_A,A_B),		00112,		FX2)	/* CarryGenerate RT<-cout(RA+RB) */
+APUOP(M_BGX,		RR,	0x343,	"bgx",		_A3(A_T,A_A,A_B),		00113,		FX2)	/* CarryGen_eXtd RT<-cout(RA+RB+RT) */
+
+/*
+
+The following ops are a subset of above except with feature bits set.
+Feature bits are bits 11-17 of the instruction:
+
+  11 - C & P feature bit
+  12 - disable interrupts
+  13 - enable interrupts
+
+*/
+APUOPFB(M_BID,		RR,	0x1a8,	0x20,	"bid",		_A1(A_A),		00010,	BR)	/* BI            IP<-RA */
+APUOPFB(M_BIE,		RR,	0x1a8,	0x10,	"bie",		_A1(A_A),		00010,	BR)	/* BI            IP<-RA */
+APUOPFB(M_BISLD,	RR,	0x1a9,	0x20,	"bisld",	_A2(A_T,A_A),	00012,	BR)	/* BISL          RT,IP<-IP,RA */
+APUOPFB(M_BISLE,	RR,	0x1a9,	0x10,	"bisle",	_A2(A_T,A_A),	00012,	BR)	/* BISL          RT,IP<-IP,RA */
+APUOPFB(M_IRETD,  	RR,	0x1aa,	0x20,	"iretd",	_A1(A_A), 	00010,	BR)	/* IRET          IP<-SRR0 */
+APUOPFB(M_IRETD2,  	RR,	0x1aa,	0x20,	"iretd",	_A0(),	 	00010,	BR)	/* IRET          IP<-SRR0 */
+APUOPFB(M_IRETE,  	RR,	0x1aa,	0x10,	"irete",	_A1(A_A), 	00010,	BR)	/* IRET          IP<-SRR0 */
+APUOPFB(M_IRETE2,  	RR,	0x1aa,	0x10,	"irete",	_A0(),	 	00010,	BR)	/* IRET          IP<-SRR0 */
+APUOPFB(M_BISLEDD,	RR,	0x1ab,	0x20,	"bisledd",	_A2(A_T,A_A),	00012,	BR)	/* BISLED        RT,IP<-IP,RA_if(ext) */
+APUOPFB(M_BISLEDE,	RR,	0x1ab,	0x10,	"bislede",	_A2(A_T,A_A),	00012,	BR)	/* BISLED        RT,IP<-IP,RA_if(ext) */
+APUOPFB(M_BIHNZD,	RR,	0x12b,	0x20,	"bihnzd",	_A2(A_T,A_A),	00011,	BR)	/* BIHNZ         IP<-RA_if(RT) */
+APUOPFB(M_BIHNZE,	RR,	0x12b,	0x10,	"bihnze",	_A2(A_T,A_A),	00011,	BR)	/* BIHNZ         IP<-RA_if(RT) */
+APUOPFB(M_BIHZD,	RR,	0x12a,	0x20,	"bihzd",	_A2(A_T,A_A),	00011,	BR)	/* BIHZ          IP<-RA_if(RT) */
+APUOPFB(M_BIHZE,	RR,	0x12a,	0x10,	"bihze",	_A2(A_T,A_A),	00011,	BR)	/* BIHZ          IP<-RA_if(RT) */
+APUOPFB(M_BINZD,	RR,	0x129,	0x20,	"binzd",	_A2(A_T,A_A),	00011,	BR)	/* BINZ          IP<-RA_if(RT) */
+APUOPFB(M_BINZE,	RR,	0x129,	0x10,	"binze",	_A2(A_T,A_A),	00011,	BR)	/* BINZ          IP<-RA_if(RT) */
+APUOPFB(M_BIZD,		RR,	0x128,	0x20,	"bizd",		_A2(A_T,A_A),	00011,	BR)	/* BIZ           IP<-RA_if(RT) */
+APUOPFB(M_BIZE,		RR,	0x128,	0x10,	"bize",		_A2(A_T,A_A),	00011,	BR)	/* BIZ           IP<-RA_if(RT) */
+APUOPFB(M_SYNCC,	RR,	0x002,	0x40,	"syncc",	_A0(),		00000,	BR)	/* SYNCC          flush_pipe */
+APUOPFB(M_HBRP,		LBTI,	0x1ac,	0x40,	"hbrp",		_A0(),	        00010,	LS)	/* HBR           BTB[B9]<-M[Ra] */
+
+/* Synonyms required by the AS manual. */
+APUOP(M_LR,		RI10,	0x020,	"lr",		_A2(A_T,A_A),	00012,	FX2)	/* OR%I          RT<-RA|I10 */
+APUOP(M_BIHT,		RR,	0x12b,	"biht", 	_A2(A_T,A_A),	00011,	BR)	/* BIHNZ         IP<-RA_if(RT) */
+APUOP(M_BIHF,		RR,	0x12a,	"bihf",		_A2(A_T,A_A),	00011,	BR)	/* BIHZ          IP<-RA_if(RT) */
+APUOP(M_BIT,		RR,	0x129,	"bit",		_A2(A_T,A_A),	00011,	BR)	/* BINZ          IP<-RA_if(RT) */
+APUOP(M_BIF,		RR,	0x128,	"bif",		_A2(A_T,A_A),	00011,	BR)	/* BIZ           IP<-RA_if(RT) */
+APUOPFB(M_BIHTD,	RR,	0x12b,	0x20,	"bihtd",	_A2(A_T,A_A),	00011,	BR)	/* BIHNF         IP<-RA_if(RT) */
+APUOPFB(M_BIHTE,	RR,	0x12b,	0x10,	"bihte",	_A2(A_T,A_A),	00011,	BR)	/* BIHNF         IP<-RA_if(RT) */
+APUOPFB(M_BIHFD,	RR,	0x12a,	0x20,	"bihfd",	_A2(A_T,A_A),	00011,	BR)	/* BIHZ          IP<-RA_if(RT) */
+APUOPFB(M_BIHFE,	RR,	0x12a,	0x10,	"bihfe",	_A2(A_T,A_A),	00011,	BR)	/* BIHZ          IP<-RA_if(RT) */
+APUOPFB(M_BITD, 	RR,	0x129,	0x20,	"bitd", 	_A2(A_T,A_A),	00011,	BR)	/* BINF          IP<-RA_if(RT) */
+APUOPFB(M_BITE, 	RR,	0x129,	0x10,	"bite", 	_A2(A_T,A_A),	00011,	BR)	/* BINF          IP<-RA_if(RT) */
+APUOPFB(M_BIFD,		RR,	0x128,	0x20,	"bifd",		_A2(A_T,A_A),	00011,	BR)	/* BIZ           IP<-RA_if(RT) */
+APUOPFB(M_BIFE,		RR,	0x128,	0x10,	"bife",		_A2(A_T,A_A),	00011,	BR)	/* BIZ           IP<-RA_if(RT) */
+
+#undef _A0
+#undef _A1
+#undef _A2
+#undef _A3
+#undef _A4
diff --git a/include/opcode/spu.h b/include/opcode/spu.h
new file mode 100644
index 00000000000..975b1fdde4b
--- /dev/null
+++ b/include/opcode/spu.h
@@ -0,0 +1,126 @@
+/* SPU ELF support for BFD.
+
+   Copyright 2006 Free Software Foundation, Inc.
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+
+/* These two enums are from rel_apu/common/spu_asm_format.h */
+/* definition of instruction format */
+typedef enum {
+  RRR,
+  RI18,
+  RI16,
+  RI10,
+  RI8,
+  RI7,
+  RR,
+  LBT,
+  LBTI,
+  IDATA,
+  UNKNOWN_IFORMAT
+} spu_iformat;
+
+/* These values describe assembly instruction arguments.  They indicate
+ * how to encode, range checking and which relocation to use. */
+typedef enum {
+  A_T,  /* register at pos 0 */
+  A_A,  /* register at pos 7 */
+  A_B,  /* register at pos 14 */
+  A_C,  /* register at pos 21 */
+  A_S,  /* special purpose register at pos 7 */
+  A_H,  /* channel register at pos 7 */
+  A_P,  /* parenthesis, this has to separate regs from immediates */
+  A_S3,
+  A_S6,
+  A_S7N,
+  A_S7,
+  A_U7A,
+  A_U7B,
+  A_S10B,
+  A_S10,
+  A_S11,
+  A_S11I,
+  A_S14,
+  A_S16,
+  A_S18,
+  A_R18,
+  A_U3,
+  A_U5,
+  A_U6,
+  A_U7,
+  A_U14,
+  A_X16,
+  A_U18,
+  A_MAX
+} spu_aformat;
+
+enum spu_insns {
+#define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
+	TAG,
+#define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
+	TAG,
+#include "opcode/spu-insns.h"
+#undef APUOP
+#undef APUOPFB
+        M_SPU_MAX
+};
+
+struct spu_opcode
+{
+   spu_iformat insn_type;
+   unsigned int opcode;
+   char *mnemonic;
+   int arg[5];
+};
+
+#define SIGNED_EXTRACT(insn,size,pos) (((int)((insn) << (32-size-pos))) >> (32-size))
+#define UNSIGNED_EXTRACT(insn,size,pos) (((insn) >> pos) & ((1 << size)-1))
+
+#define DECODE_INSN_RT(insn) (insn & 0x7f)
+#define DECODE_INSN_RA(insn) ((insn >> 7) & 0x7f)
+#define DECODE_INSN_RB(insn) ((insn >> 14) & 0x7f)
+#define DECODE_INSN_RC(insn) ((insn >> 21) & 0x7f)
+
+#define DECODE_INSN_I10(insn) SIGNED_EXTRACT(insn,10,14)
+#define DECODE_INSN_U10(insn) UNSIGNED_EXTRACT(insn,10,14)
+
+/* For branching, immediate loads, hbr and  lqa/stqa. */
+#define DECODE_INSN_I16(insn) SIGNED_EXTRACT(insn,16,7)
+#define DECODE_INSN_U16(insn) UNSIGNED_EXTRACT(insn,16,7)
+
+/* for stop */
+#define DECODE_INSN_U14(insn) UNSIGNED_EXTRACT(insn,14,0)
+
+/* For ila */
+#define DECODE_INSN_I18(insn) SIGNED_EXTRACT(insn,18,7)
+#define DECODE_INSN_U18(insn) UNSIGNED_EXTRACT(insn,18,7)
+
+/* For rotate and shift and generate control mask */
+#define DECODE_INSN_I7(insn) SIGNED_EXTRACT(insn,7,14)
+#define DECODE_INSN_U7(insn) UNSIGNED_EXTRACT(insn,7,14)
+
+/* For float <-> int conversion */
+#define DECODE_INSN_I8(insn)  SIGNED_EXTRACT(insn,8,14)
+#define DECODE_INSN_U8(insn) UNSIGNED_EXTRACT(insn,8,14)
+
+/* For hbr  */
+#define DECODE_INSN_I9a(insn) ((SIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0))
+#define DECODE_INSN_I9b(insn) ((SIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0))
+#define DECODE_INSN_U9a(insn) ((UNSIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0))
+#define DECODE_INSN_U9b(insn) ((UNSIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0))
+
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 7f17d757d43..016292ef707 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,18 @@
+2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
+	    Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
+	    Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
+	    Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
+	    Alan Modra  <amodra@bigpond.net.au>
+
+	* spu-dis.c: New file.
+	* spu-opc.c: New file.
+	* configure.in: Add SPU support.
+	* disassemble.c: Likewise.
+	* Makefile.am: Likewise.  Run "make dep-am".
+	* Makefile.in: Regenerate.
+	* configure: Regenerate.
+	* po/POTFILES.in: Regenerate.
+
 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 
 	* ppc-opc.c (CELL): New define.
diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am
index 3bf38e9d201..ebd252fb7bf 100644
--- a/opcodes/Makefile.am
+++ b/opcodes/Makefile.am
@@ -169,6 +169,8 @@ CFILES = \
 	sh64-opc.c \
 	sparc-dis.c \
 	sparc-opc.c \
+	spu-dis.c \
+	spu-opc.c \
 	tic30-dis.c \
 	tic4x-dis.c \
 	tic54x-dis.c \
@@ -301,6 +303,8 @@ ALL_MACHINES = \
 	sh64-opc.lo \
 	sparc-dis.lo \
 	sparc-opc.lo \
+	spu-dis.lo \
+	spu-opc.lo \
 	tic30-dis.lo \
 	tic4x-dis.lo \
 	tic54x-dis.lo \
@@ -604,131 +608,164 @@ dep-am: DEP
 # DO NOT DELETE THIS LINE -- mkdep uses it.
 # DO NOT PUT ANYTHING AFTER THIS LINE, IT WILL GO AWAY.
 alpha-dis.lo: alpha-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/alpha.h
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(INCDIR)/opcode/alpha.h
 alpha-opc.lo: alpha-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/opcode/alpha.h $(BFD_H) $(INCDIR)/symcat.h \
-  opintl.h
+  $(INCDIR)/opcode/alpha.h $(BFD_H) $(INCDIR)/ansidecl.h \
+  $(INCDIR)/symcat.h opintl.h
 arc-dis.lo: arc-dis.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h \
-  $(INCDIR)/elf/reloc-macros.h opintl.h arc-dis.h arc-ext.h
+  $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h \
+  opintl.h arc-dis.h arc-ext.h
 arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h \
   opintl.h
 arc-ext.lo: arc-ext.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(BFD_H) $(INCDIR)/symcat.h arc-ext.h $(INCDIR)/libiberty.h
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h arc-ext.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
 arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/arm.h \
-  opintl.h $(INCDIR)/safe-ctype.h $(INCDIR)/floatformat.h \
-  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(INCDIR)/opcode/arm.h opintl.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/floatformat.h $(INCDIR)/ansidecl.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/elf/internal.h $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h
 avr-dis.lo: avr-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h \
-  $(INCDIR)/libiberty.h $(INCDIR)/opcode/avr.h
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/avr.h
 bfin-dis.lo: bfin-dis.c $(INCDIR)/opcode/bfin.h $(INCDIR)/dis-asm.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
 cgen-asm.lo: cgen-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h $(BFD_H) \
-  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
   opintl.h
 cgen-bitset.lo: cgen-bitset.c $(INCDIR)/libiberty.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/opcode/cgen-bitset.h
 cgen-dis.lo: cgen-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/libiberty.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h \
-  $(INCDIR)/opcode/cgen-bitset.h
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(BFD_H) \
+  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h
 cgen-opc.lo: cgen-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h $(BFD_H) \
-  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h $(INCDIR)/opcode/cgen-bitset.h
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h
 cris-dis.lo: cris-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \
-  $(INCDIR)/opcode/cris.h $(INCDIR)/libiberty.h
+  $(INCDIR)/ansidecl.h $(INCDIR)/opcode/cris.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/ansidecl.h
 cris-opc.lo: cris-opc.c $(INCDIR)/opcode/cris.h
 crx-dis.lo: crx-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \
-  $(INCDIR)/opcode/crx.h
+  $(INCDIR)/ansidecl.h $(INCDIR)/opcode/crx.h
 crx-opc.lo: crx-opc.c $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h $(INCDIR)/opcode/crx.h
 d10v-dis.lo: d10v-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/d10v.h $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/symcat.h
+  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
 d10v-opc.lo: d10v-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/d10v.h
 d30v-dis.lo: d30v-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/d30v.h $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/symcat.h opintl.h
+  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h opintl.h
 d30v-opc.lo: d30v-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/d30v.h
 dlx-dis.lo: dlx-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/dlx.h
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(INCDIR)/opcode/dlx.h
 dis-buf.lo: dis-buf.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  opintl.h
 dis-init.lo: dis-init.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(BFD_H)
 disassemble.lo: disassemble.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
 fr30-asm.lo: fr30-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h $(INCDIR)/xregex.h \
-  $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h fr30-opc.h \
+  opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
 fr30-desc.lo: fr30-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h $(INCDIR)/libiberty.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h fr30-opc.h \
+  opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
 fr30-dis.lo: fr30-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
   fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  fr30-opc.h opintl.h
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h fr30-opc.h \
+  opintl.h
 fr30-ibld.lo: fr30-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h \
-  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
   fr30-opc.h opintl.h $(INCDIR)/safe-ctype.h
 fr30-opc.lo: fr30-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h fr30-opc.h $(INCDIR)/libiberty.h
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h fr30-opc.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
 frv-asm.lo: frv-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(BFD_H) $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h $(INCDIR)/xregex.h \
-  $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  frv-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h frv-opc.h \
+  opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
 frv-desc.lo: frv-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(BFD_H) $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h $(INCDIR)/libiberty.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  frv-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h frv-opc.h \
+  opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
 frv-dis.lo: frv-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
   frv-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  frv-opc.h opintl.h
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h frv-opc.h \
+  opintl.h
 frv-ibld.lo: frv-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h frv-desc.h \
-  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(BFD_H) $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
   frv-opc.h opintl.h $(INCDIR)/safe-ctype.h
 frv-opc.lo: frv-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(BFD_H) $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h frv-opc.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/elf/frv.h $(INCDIR)/elf/reloc-macros.h
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  frv-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h frv-opc.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/elf/frv.h \
+  $(INCDIR)/elf/reloc-macros.h
 h8300-dis.lo: h8300-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/h8300.h $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/symcat.h opintl.h $(INCDIR)/libiberty.h
+  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h opintl.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/ansidecl.h
 h8500-dis.lo: h8500-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  h8500-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \
-  opintl.h
+  h8500-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
+  $(INCDIR)/symcat.h opintl.h
 hppa-dis.lo: hppa-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(BFDDIR)/libhppa.h \
-  $(INCDIR)/opcode/hppa.h
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(BFDDIR)/libhppa.h $(INCDIR)/opcode/hppa.h
 i370-dis.lo: i370-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/i370.h
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(INCDIR)/opcode/i370.h
 i370-opc.lo: i370-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/i370.h
 i386-dis.lo: i386-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \
-  opintl.h
+  $(INCDIR)/ansidecl.h opintl.h
 i860-dis.lo: i860-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/i860.h
 i960-dis.lo: i960-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
 ia64-dis.lo: ia64-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/ia64.h
+  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/ia64.h \
+  $(BFD_H)
 ia64-opc-a.lo: ia64-opc-a.c ia64-opc.h $(INCDIR)/opcode/ia64.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
 ia64-opc-b.lo: ia64-opc-b.c ia64-opc.h $(INCDIR)/opcode/ia64.h \
@@ -741,295 +778,390 @@ ia64-opc-m.lo: ia64-opc-m.c ia64-opc.h $(INCDIR)/opcode/ia64.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
 ia64-opc-d.lo: ia64-opc-d.c
 ia64-opc.lo: ia64-opc.c $(INCDIR)/ansidecl.h sysdep.h \
-  config.h $(INCDIR)/libiberty.h ia64-asmtab.h $(INCDIR)/opcode/ia64.h \
-  $(BFD_H) $(INCDIR)/symcat.h ia64-asmtab.c
+  config.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+  ia64-asmtab.h $(INCDIR)/opcode/ia64.h $(BFD_H) $(INCDIR)/ansidecl.h \
+  $(INCDIR)/symcat.h ia64-asmtab.c
 ia64-gen.lo: ia64-gen.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/safe-ctype.h sysdep.h config.h $(INCDIR)/getopt.h \
-  ia64-opc.h $(INCDIR)/opcode/ia64.h $(BFD_H) $(INCDIR)/symcat.h \
-  ia64-opc-a.c ia64-opc-i.c ia64-opc-m.c ia64-opc-b.c \
-  ia64-opc-f.c ia64-opc-x.c ia64-opc-d.c
+  $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h sysdep.h \
+  config.h $(INCDIR)/getopt.h ia64-opc.h $(INCDIR)/opcode/ia64.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h ia64-opc-a.c \
+  ia64-opc-i.c ia64-opc-m.c ia64-opc-b.c ia64-opc-f.c \
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-  $(BFD_H) $(INCDIR)/symcat.h mt-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h mt-opc.h opintl.h $(INCDIR)/libiberty.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
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+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h mt-opc.h \
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-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
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+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h mt-opc.h \
+  opintl.h
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-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h mt-desc.h \
-  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(BFD_H) $(INCDIR)/symcat.h mt-desc.h $(INCDIR)/opcode/cgen-bitset.h \
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-  $(INCDIR)/opcode/cgen.h mt-opc.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/safe-ctype.h
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-  $(INCDIR)/symcat.h sysdep.h config.h $(INCDIR)/dis-asm.h \
-  $(INCDIR)/opcode/ns32k.h opintl.h
+  $(INCDIR)/symcat.h sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/ns32k.h \
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-  $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h openrisc-desc.h \
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   $(INCDIR)/opcode/pj.h $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/symcat.h
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-  $(INCDIR)/symcat.h $(INCDIR)/libiberty.h opintl.h
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   $(INCDIR)/opcode/tic80.h $(INCDIR)/dis-asm.h $(BFD_H) \
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   $(INCDIR)/opcode/v850.h $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/symcat.h opintl.h
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+  $(INCDIR)/symcat.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/ansidecl.h xstormy16-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
+  xstormy16-opc.h opintl.h
 xstormy16-ibld.lo: xstormy16-ibld.c sysdep.h config.h \
-  $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \
-  xstormy16-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  xstormy16-opc.h opintl.h $(INCDIR)/safe-ctype.h
+  $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
+  $(INCDIR)/symcat.h $(BFD_H) $(INCDIR)/symcat.h xstormy16-desc.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h xstormy16-opc.h \
+  opintl.h $(INCDIR)/safe-ctype.h
 xstormy16-opc.lo: xstormy16-opc.c sysdep.h config.h \
-  $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h xstormy16-desc.h \
+  $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/ansidecl.h \
+  $(INCDIR)/symcat.h $(INCDIR)/symcat.h xstormy16-desc.h \
   $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  xstormy16-opc.h $(INCDIR)/libiberty.h
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h xstormy16-opc.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
 xtensa-dis.lo: xtensa-dis.c $(INCDIR)/xtensa-isa.h \
-  $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h sysdep.h \
-  config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h
+  $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+  sysdep.h config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
+  $(INCDIR)/symcat.h
 z80-dis.lo: z80-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
 z8k-dis.lo: z8k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h z8k-opc.h
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  z8k-opc.h
 z8kgen.lo: z8kgen.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/libiberty.h
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
 # IF YOU PUT ANYTHING HERE IT WILL GO AWAY
diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in
index 6d3275fd65d..85003e61a0e 100644
--- a/opcodes/Makefile.in
+++ b/opcodes/Makefile.in
@@ -383,6 +383,8 @@ CFILES = \
 	sh64-opc.c \
 	sparc-dis.c \
 	sparc-opc.c \
+	spu-dis.c \
+	spu-opc.c \
 	tic30-dis.c \
 	tic4x-dis.c \
 	tic54x-dis.c \
@@ -515,6 +517,8 @@ ALL_MACHINES = \
 	sh64-opc.lo \
 	sparc-dis.lo \
 	sparc-opc.lo \
+	spu-dis.lo \
+	spu-opc.lo \
 	tic30-dis.lo \
 	tic4x-dis.lo \
 	tic54x-dis.lo \
@@ -1141,131 +1145,164 @@ dep-am: DEP
 # DO NOT DELETE THIS LINE -- mkdep uses it.
 # DO NOT PUT ANYTHING AFTER THIS LINE, IT WILL GO AWAY.
 alpha-dis.lo: alpha-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/alpha.h
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(INCDIR)/opcode/alpha.h
 alpha-opc.lo: alpha-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/opcode/alpha.h $(BFD_H) $(INCDIR)/symcat.h \
-  opintl.h
+  $(INCDIR)/opcode/alpha.h $(BFD_H) $(INCDIR)/ansidecl.h \
+  $(INCDIR)/symcat.h opintl.h
 arc-dis.lo: arc-dis.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h \
-  $(INCDIR)/elf/reloc-macros.h opintl.h arc-dis.h arc-ext.h
+  $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h \
+  opintl.h arc-dis.h arc-ext.h
 arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h \
   opintl.h
 arc-ext.lo: arc-ext.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(BFD_H) $(INCDIR)/symcat.h arc-ext.h $(INCDIR)/libiberty.h
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h arc-ext.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
 arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/arm.h \
-  opintl.h $(INCDIR)/safe-ctype.h $(INCDIR)/floatformat.h \
-  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(INCDIR)/opcode/arm.h opintl.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/floatformat.h $(INCDIR)/ansidecl.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/elf/internal.h $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h
 avr-dis.lo: avr-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h \
-  $(INCDIR)/libiberty.h $(INCDIR)/opcode/avr.h
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/opcode/avr.h
 bfin-dis.lo: bfin-dis.c $(INCDIR)/opcode/bfin.h $(INCDIR)/dis-asm.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
 cgen-asm.lo: cgen-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h $(BFD_H) \
-  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
   opintl.h
 cgen-bitset.lo: cgen-bitset.c $(INCDIR)/libiberty.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/opcode/cgen-bitset.h
 cgen-dis.lo: cgen-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/libiberty.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h \
-  $(INCDIR)/opcode/cgen-bitset.h
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(BFD_H) \
+  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h
 cgen-opc.lo: cgen-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h $(BFD_H) \
-  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h $(INCDIR)/opcode/cgen-bitset.h
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h
 cris-dis.lo: cris-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \
-  $(INCDIR)/opcode/cris.h $(INCDIR)/libiberty.h
+  $(INCDIR)/ansidecl.h $(INCDIR)/opcode/cris.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/ansidecl.h
 cris-opc.lo: cris-opc.c $(INCDIR)/opcode/cris.h
 crx-dis.lo: crx-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \
-  $(INCDIR)/opcode/crx.h
+  $(INCDIR)/ansidecl.h $(INCDIR)/opcode/crx.h
 crx-opc.lo: crx-opc.c $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/symcat.h $(INCDIR)/opcode/crx.h
 d10v-dis.lo: d10v-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/d10v.h $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/symcat.h
+  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
 d10v-opc.lo: d10v-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/d10v.h
 d30v-dis.lo: d30v-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/d30v.h $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/symcat.h opintl.h
+  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h opintl.h
 d30v-opc.lo: d30v-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/d30v.h
 dlx-dis.lo: dlx-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/dlx.h
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(INCDIR)/opcode/dlx.h
 dis-buf.lo: dis-buf.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  opintl.h
 dis-init.lo: dis-init.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(BFD_H)
 disassemble.lo: disassemble.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
 fr30-asm.lo: fr30-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h $(INCDIR)/xregex.h \
-  $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h fr30-opc.h \
+  opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
 fr30-desc.lo: fr30-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h $(INCDIR)/libiberty.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h fr30-opc.h \
+  opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
 fr30-dis.lo: fr30-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
   fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  fr30-opc.h opintl.h
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h fr30-opc.h \
+  opintl.h
 fr30-ibld.lo: fr30-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h \
-  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
   fr30-opc.h opintl.h $(INCDIR)/safe-ctype.h
 fr30-opc.lo: fr30-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h fr30-opc.h $(INCDIR)/libiberty.h
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h fr30-opc.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
 frv-asm.lo: frv-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(BFD_H) $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h $(INCDIR)/xregex.h \
-  $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  frv-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h frv-opc.h \
+  opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
 frv-desc.lo: frv-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(BFD_H) $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h $(INCDIR)/libiberty.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  frv-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h frv-opc.h \
+  opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
 frv-dis.lo: frv-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
   frv-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  frv-opc.h opintl.h
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h frv-opc.h \
+  opintl.h
 frv-ibld.lo: frv-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h frv-desc.h \
-  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(BFD_H) $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
   frv-opc.h opintl.h $(INCDIR)/safe-ctype.h
 frv-opc.lo: frv-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(BFD_H) $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h frv-opc.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/elf/frv.h $(INCDIR)/elf/reloc-macros.h
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  frv-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h frv-opc.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/elf/frv.h \
+  $(INCDIR)/elf/reloc-macros.h
 h8300-dis.lo: h8300-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/h8300.h $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/symcat.h opintl.h $(INCDIR)/libiberty.h
+  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h opintl.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/ansidecl.h
 h8500-dis.lo: h8500-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  h8500-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \
-  opintl.h
+  h8500-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
+  $(INCDIR)/symcat.h opintl.h
 hppa-dis.lo: hppa-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(BFDDIR)/libhppa.h \
-  $(INCDIR)/opcode/hppa.h
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(BFDDIR)/libhppa.h $(INCDIR)/opcode/hppa.h
 i370-dis.lo: i370-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/i370.h
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(INCDIR)/opcode/i370.h
 i370-opc.lo: i370-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/i370.h
 i386-dis.lo: i386-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \
-  opintl.h
+  $(INCDIR)/ansidecl.h opintl.h
 i860-dis.lo: i860-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/i860.h
 i960-dis.lo: i960-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
 ia64-dis.lo: ia64-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/ia64.h
+  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/ia64.h \
+  $(BFD_H)
 ia64-opc-a.lo: ia64-opc-a.c ia64-opc.h $(INCDIR)/opcode/ia64.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
 ia64-opc-b.lo: ia64-opc-b.c ia64-opc.h $(INCDIR)/opcode/ia64.h \
@@ -1278,297 +1315,392 @@ ia64-opc-m.lo: ia64-opc-m.c ia64-opc.h $(INCDIR)/opcode/ia64.h \
   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
 ia64-opc-d.lo: ia64-opc-d.c
 ia64-opc.lo: ia64-opc.c $(INCDIR)/ansidecl.h sysdep.h \
-  config.h $(INCDIR)/libiberty.h ia64-asmtab.h $(INCDIR)/opcode/ia64.h \
-  $(BFD_H) $(INCDIR)/symcat.h ia64-asmtab.c
+  config.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+  ia64-asmtab.h $(INCDIR)/opcode/ia64.h $(BFD_H) $(INCDIR)/ansidecl.h \
+  $(INCDIR)/symcat.h ia64-asmtab.c
 ia64-gen.lo: ia64-gen.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/safe-ctype.h sysdep.h config.h $(INCDIR)/getopt.h \
-  ia64-opc.h $(INCDIR)/opcode/ia64.h $(BFD_H) $(INCDIR)/symcat.h \
-  ia64-opc-a.c ia64-opc-i.c ia64-opc-m.c ia64-opc-b.c \
-  ia64-opc-f.c ia64-opc-x.c ia64-opc-d.c
+  $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h sysdep.h \
+  config.h $(INCDIR)/getopt.h ia64-opc.h $(INCDIR)/opcode/ia64.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h ia64-opc-a.c \
+  ia64-opc-i.c ia64-opc-m.c ia64-opc-b.c ia64-opc-f.c \
+  ia64-opc-x.c ia64-opc-d.c
 ia64-asmtab.lo: ia64-asmtab.c
 ip2k-asm.lo: ip2k-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h ip2k-opc.h opintl.h $(INCDIR)/xregex.h \
-  $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  ip2k-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ip2k-opc.h \
+  opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
 ip2k-desc.lo: ip2k-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h ip2k-opc.h opintl.h $(INCDIR)/libiberty.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  ip2k-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ip2k-opc.h \
+  opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
 ip2k-dis.lo: ip2k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
   ip2k-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  ip2k-opc.h opintl.h
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ip2k-opc.h \
+  opintl.h
 ip2k-ibld.lo: ip2k-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h \
-  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
   ip2k-opc.h opintl.h $(INCDIR)/safe-ctype.h
 ip2k-opc.lo: ip2k-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h ip2k-opc.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/safe-ctype.h
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  ip2k-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h ip2k-opc.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
 iq2000-asm.lo: iq2000-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(BFD_H) $(INCDIR)/symcat.h iq2000-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h iq2000-opc.h opintl.h $(INCDIR)/xregex.h \
-  $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  iq2000-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h iq2000-opc.h \
+  opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
 iq2000-desc.lo: iq2000-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(BFD_H) $(INCDIR)/symcat.h iq2000-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h iq2000-opc.h opintl.h $(INCDIR)/libiberty.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  iq2000-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h iq2000-opc.h \
+  opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
 iq2000-dis.lo: iq2000-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
   iq2000-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  iq2000-opc.h opintl.h
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h iq2000-opc.h \
+  opintl.h
 iq2000-ibld.lo: iq2000-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h iq2000-desc.h \
-  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(BFD_H) $(INCDIR)/symcat.h iq2000-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
   iq2000-opc.h opintl.h $(INCDIR)/safe-ctype.h
 iq2000-opc.lo: iq2000-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(BFD_H) $(INCDIR)/symcat.h iq2000-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h iq2000-opc.h $(INCDIR)/libiberty.h
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  iq2000-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h iq2000-opc.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
 m32c-asm.lo: m32c-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(BFD_H) $(INCDIR)/symcat.h m32c-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h m32c-opc.h cgen-types.h cgen-ops.h \
-  opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  m32c-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h m32c-opc.h \
+  cgen-types.h cgen-ops.h opintl.h $(INCDIR)/xregex.h \
+  $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/safe-ctype.h
 m32c-desc.lo: m32c-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(BFD_H) $(INCDIR)/symcat.h m32c-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h m32c-opc.h cgen-types.h cgen-ops.h \
-  opintl.h $(INCDIR)/libiberty.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  m32c-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h m32c-opc.h \
+  cgen-types.h cgen-ops.h opintl.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/ansidecl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
 m32c-dis.lo: m32c-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
   m32c-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  m32c-opc.h cgen-types.h cgen-ops.h opintl.h $(INCDIR)/elf/m32c.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h m32c-opc.h \
+  cgen-types.h cgen-ops.h opintl.h $(INCDIR)/elf/m32c.h \
   $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h
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-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h m32c-desc.h \
-  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(BFD_H) $(INCDIR)/symcat.h m32c-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
   m32c-opc.h cgen-types.h cgen-ops.h opintl.h $(INCDIR)/safe-ctype.h
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-  $(BFD_H) $(INCDIR)/symcat.h m32c-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h m32c-opc.h cgen-types.h cgen-ops.h \
-  $(INCDIR)/libiberty.h
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
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-  $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen-bitset.h \
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-  $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h
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-  $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h m32r-opc.h opintl.h $(INCDIR)/libiberty.h \
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   $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
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-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \
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   m32r-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  m32r-opc.h opintl.h
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h m32r-opc.h \
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-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h \
-  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
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   m32r-opc.h opintl.h $(INCDIR)/safe-ctype.h
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-  $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h m32r-opc.h $(INCDIR)/libiberty.h
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-  $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h m32r-opc.h
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   $(INCDIR)/opcode/m68hc11.h $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/symcat.h
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-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/floatformat.h \
-  $(INCDIR)/libiberty.h opintl.h $(INCDIR)/opcode/m68k.h
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-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/m88k.h \
-  opintl.h $(INCDIR)/libiberty.h
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-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/maxq.h
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-  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/opcode/mips.h \
+  opintl.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
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   $(INCDIR)/opcode/mips.h
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   $(INCDIR)/opcode/mips.h
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   $(INCDIR)/opcode/mn10200.h $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/symcat.h opintl.h
+  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h opintl.h
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   $(INCDIR)/opcode/mn10200.h
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   $(INCDIR)/opcode/mn10300.h $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/symcat.h opintl.h
+  $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h opintl.h
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   $(INCDIR)/opcode/mn10300.h
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   $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \
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+  $(INCDIR)/ansidecl.h $(BFD_H) opintl.h
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-  $(BFD_H) $(INCDIR)/symcat.h mt-desc.h $(INCDIR)/opcode/cgen-bitset.h \
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-  $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
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+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h mt-opc.h \
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-  $(INCDIR)/opcode/cgen.h mt-opc.h opintl.h $(INCDIR)/libiberty.h \
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+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h mt-opc.h \
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-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \
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+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h mt-opc.h \
+  opintl.h
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-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h mt-desc.h \
-  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  $(BFD_H) $(INCDIR)/symcat.h mt-desc.h $(INCDIR)/opcode/cgen-bitset.h \
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-  $(INCDIR)/opcode/cgen.h mt-opc.h $(INCDIR)/libiberty.h \
-  $(INCDIR)/safe-ctype.h
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-  $(INCDIR)/symcat.h sysdep.h config.h $(INCDIR)/dis-asm.h \
-  $(INCDIR)/opcode/ns32k.h opintl.h
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+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/ns32k.h \
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-  $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h openrisc-desc.h \
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   $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/or32.h \
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   $(INCDIR)/opcode/pj.h $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/symcat.h
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-  $(BFDDIR)/elf32-sh64.h
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-  $(INCDIR)/opcode/sparc.h $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/symcat.h $(INCDIR)/libiberty.h opintl.h
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-  $(INCDIR)/opcode/sparc.h
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   $(INCDIR)/opcode/tic80.h $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/symcat.h
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   $(INCDIR)/opcode/v850.h $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/symcat.h opintl.h
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   $(INCDIR)/opcode/vax.h $(INCDIR)/dis-asm.h $(BFD_H) \
-  $(INCDIR)/symcat.h
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+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
   xc16x-opc.h opintl.h $(INCDIR)/safe-ctype.h
 xc16x-opc.lo: xc16x-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(BFD_H) $(INCDIR)/symcat.h xc16x-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h xc16x-opc.h $(INCDIR)/libiberty.h
+  $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
+  xc16x-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h xc16x-opc.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
 xstormy16-asm.lo: xstormy16-asm.c sysdep.h config.h \
-  $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h xstormy16-desc.h \
+  $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/ansidecl.h \
+  $(INCDIR)/symcat.h $(INCDIR)/symcat.h xstormy16-desc.h \
   $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  xstormy16-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \
-  $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h xstormy16-opc.h \
+  opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h
 xstormy16-desc.lo: xstormy16-desc.c sysdep.h config.h \
-  $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h xstormy16-desc.h \
+  $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/ansidecl.h \
+  $(INCDIR)/symcat.h $(INCDIR)/symcat.h xstormy16-desc.h \
   $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  xstormy16-opc.h opintl.h $(INCDIR)/libiberty.h $(INCDIR)/xregex.h \
-  $(INCDIR)/xregex2.h
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h xstormy16-opc.h \
+  opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
 xstormy16-dis.lo: xstormy16-dis.c sysdep.h config.h \
-  $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \
-  $(INCDIR)/libiberty.h xstormy16-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h xstormy16-opc.h opintl.h
+  $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
+  $(INCDIR)/symcat.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \
+  $(INCDIR)/ansidecl.h xstormy16-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \
+  xstormy16-opc.h opintl.h
 xstormy16-ibld.lo: xstormy16-ibld.c sysdep.h config.h \
-  $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \
-  xstormy16-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  xstormy16-opc.h opintl.h $(INCDIR)/safe-ctype.h
+  $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
+  $(INCDIR)/symcat.h $(BFD_H) $(INCDIR)/symcat.h xstormy16-desc.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h xstormy16-opc.h \
+  opintl.h $(INCDIR)/safe-ctype.h
 xstormy16-opc.lo: xstormy16-opc.c sysdep.h config.h \
-  $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h xstormy16-desc.h \
+  $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/ansidecl.h \
+  $(INCDIR)/symcat.h $(INCDIR)/symcat.h xstormy16-desc.h \
   $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  xstormy16-opc.h $(INCDIR)/libiberty.h
+  $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h xstormy16-opc.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
 xtensa-dis.lo: xtensa-dis.c $(INCDIR)/xtensa-isa.h \
-  $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h sysdep.h \
-  config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h
+  $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+  sysdep.h config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \
+  $(INCDIR)/symcat.h
 z80-dis.lo: z80-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h
 z8k-dis.lo: z8k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h z8k-opc.h
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
+  z8k-opc.h
 z8kgen.lo: z8kgen.c sysdep.h config.h $(INCDIR)/ansidecl.h \
-  $(INCDIR)/libiberty.h
+  $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h
 # IF YOU PUT ANYTHING HERE IT WILL GO AWAY
 # Tell versions [3.59,3.63) of GNU make to not export all variables.
 # Otherwise a system limit (for SysV at least) may be exceeded.
diff --git a/opcodes/configure b/opcodes/configure
index ed91ecabeb7..8e3e27ea9e6 100755
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -6589,6 +6589,7 @@ if test x${all_targets} = xfalse ; then
 	  done
 				ta="$ta sh-dis.lo cgen-bitset.lo" ;;
 	bfd_sparc_arch)		ta="$ta sparc-dis.lo sparc-opc.lo" ;;
+	bfd_spu_arch)		ta="$ta spu-dis.lo spu-opc.lo" ;;
 	bfd_tahoe_arch)		;;
 	bfd_tic30_arch)		ta="$ta tic30-dis.lo" ;;
         bfd_tic4x_arch)         ta="$ta tic4x-dis.lo" ;;
diff --git a/opcodes/configure.in b/opcodes/configure.in
index b8cb7de53e4..d937784491d 100644
--- a/opcodes/configure.in
+++ b/opcodes/configure.in
@@ -218,6 +218,7 @@ if test x${all_targets} = xfalse ; then
 	  done
 				ta="$ta sh-dis.lo cgen-bitset.lo" ;;
 	bfd_sparc_arch)		ta="$ta sparc-dis.lo sparc-opc.lo" ;;
+	bfd_spu_arch)		ta="$ta spu-dis.lo spu-opc.lo" ;;
 	bfd_tahoe_arch)		;;
 	bfd_tic30_arch)		ta="$ta tic30-dis.lo" ;;
         bfd_tic4x_arch)         ta="$ta tic4x-dis.lo" ;;
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index 14f6d377593..ca28f561989 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -67,6 +67,7 @@
 #define ARCH_score
 #define ARCH_sh
 #define ARCH_sparc
+#define ARCH_spu
 #define ARCH_tic30
 #define ARCH_tic4x
 #define ARCH_tic54x
@@ -345,6 +346,11 @@ disassembler (abfd)
       disassemble = print_insn_sparc;
       break;
 #endif
+#ifdef ARCH_spu
+    case bfd_arch_spu:
+      disassemble = print_insn_spu;
+      break;
+#endif
 #ifdef ARCH_tic30
     case bfd_arch_tic30:
       disassemble = print_insn_tic30;
diff --git a/opcodes/po/POTFILES.in b/opcodes/po/POTFILES.in
index add47f5f4bb..337ec855cf7 100644
--- a/opcodes/po/POTFILES.in
+++ b/opcodes/po/POTFILES.in
@@ -140,6 +140,8 @@ sh-dis.c
 sh-opc.h
 sparc-dis.c
 sparc-opc.c
+spu-dis.c
+spu-opc.c
 sysdep.h
 tic30-dis.c
 tic4x-dis.c
diff --git a/opcodes/spu-dis.c b/opcodes/spu-dis.c
new file mode 100644
index 00000000000..a0dd1a0742e
--- /dev/null
+++ b/opcodes/spu-dis.c
@@ -0,0 +1,260 @@
+/* Disassemble SPU instructions
+
+   Copyright 2006 Free Software Foundation, Inc.
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#include <stdio.h>
+#include "sysdep.h"
+#include "dis-asm.h"
+#include "opcode/spu.h"
+
+/* This file provides a disassembler function which uses
+   the disassembler interface defined in dis-asm.h.   */
+
+extern const struct spu_opcode spu_opcodes[];
+extern const int spu_num_opcodes;
+
+static const struct spu_opcode *spu_disassemble_table[(1<<11)];
+
+static void
+init_spu_disassemble (void)
+{
+  int i;
+
+  /* If two instructions have the same opcode then we prefer the first
+   * one.  In most cases it is just an alternate mnemonic. */
+  for (i = 0; i < spu_num_opcodes; i++)
+    {
+      int o = spu_opcodes[i].opcode;
+      if (o >= (1 << 11))
+	abort ();
+      if (spu_disassemble_table[o] == 0)
+	spu_disassemble_table[o] = &spu_opcodes[i];
+    }
+}
+
+/* Determine the instruction from the 10 least significant bits. */
+static const struct spu_opcode *
+get_index_for_opcode (unsigned int insn)
+{
+  const struct spu_opcode *index;
+  unsigned int opcode = insn >> (32-11);
+
+  /* Init the table.  This assumes that element 0/opcode 0 (currently
+   * NOP) is always used */
+  if (spu_disassemble_table[0] == 0)
+    init_spu_disassemble ();
+
+  if ((index = spu_disassemble_table[opcode & 0x780]) != 0
+      && index->insn_type == RRR)
+    return index;
+
+  if ((index = spu_disassemble_table[opcode & 0x7f0]) != 0
+      && (index->insn_type == RI18 || index->insn_type == LBT))
+    return index;
+
+  if ((index = spu_disassemble_table[opcode & 0x7f8]) != 0
+      && index->insn_type == RI10)
+    return index;
+
+  if ((index = spu_disassemble_table[opcode & 0x7fc]) != 0
+      && (index->insn_type == RI16))
+    return index;
+
+  if ((index = spu_disassemble_table[opcode & 0x7fe]) != 0
+      && (index->insn_type == RI8))
+    return index;
+
+  if ((index = spu_disassemble_table[opcode & 0x7ff]) != 0)
+    return index;
+
+  return 0;
+}
+
+/* Print a Spu instruction.  */
+
+int
+print_insn_spu (bfd_vma memaddr, struct disassemble_info *info)
+{
+  bfd_byte buffer[4];
+  int value;
+  int hex_value;
+  int status;
+  unsigned int insn;
+  const struct spu_opcode *index;
+  enum spu_insns tag;
+
+  status = (*info->read_memory_func) (memaddr, buffer, 4, info);
+  if (status != 0)
+    {
+      (*info->memory_error_func) (status, memaddr, info);
+      return -1;
+    }
+
+  insn = bfd_getb32 (buffer);
+
+  index = get_index_for_opcode (insn);
+
+  if (index == 0)
+    {
+      (*info->fprintf_func) (info->stream, ".long 0x%x", insn);
+    }
+  else
+    {
+      int i;
+      int paren = 0;
+      tag = (enum spu_insns)(index - spu_opcodes);
+      (*info->fprintf_func) (info->stream, "%s", index->mnemonic);
+      if (tag == M_BI || tag == M_BISL || tag == M_IRET || tag == M_BISLED
+	  || tag == M_BIHNZ || tag == M_BIHZ || tag == M_BINZ || tag == M_BIZ
+          || tag == M_SYNC || tag == M_HBR)
+	{
+	  int fb = (insn >> (32-18)) & 0x7f;
+	  if (fb & 0x40)
+	    (*info->fprintf_func) (info->stream, tag == M_SYNC ? "c" : "p");
+	  if (fb & 0x20)
+	    (*info->fprintf_func) (info->stream, "d");
+	  if (fb & 0x10)
+	    (*info->fprintf_func) (info->stream, "e");
+	}
+      if (index->arg[0] != 0)
+	(*info->fprintf_func) (info->stream, "\t");
+      hex_value = 0;
+      for (i = 1;  i <= index->arg[0]; i++)
+	{
+	  int arg = index->arg[i];
+	  if (arg != A_P && !paren && i > 1)
+	    (*info->fprintf_func) (info->stream, ",");
+
+	  switch (arg)
+	    {
+	    case A_T:
+	      (*info->fprintf_func) (info->stream, "$%d",
+				     DECODE_INSN_RT (insn));
+	      break;
+	    case A_A:
+	      (*info->fprintf_func) (info->stream, "$%d",
+				     DECODE_INSN_RA (insn));
+	      break;
+	    case A_B:
+	      (*info->fprintf_func) (info->stream, "$%d",
+				     DECODE_INSN_RB (insn));
+	      break;
+	    case A_C:
+	      (*info->fprintf_func) (info->stream, "$%d",
+				     DECODE_INSN_RC (insn));
+	      break;
+	    case A_S:
+	      (*info->fprintf_func) (info->stream, "$sp%d",
+				     DECODE_INSN_RA (insn));
+	      break;
+	    case A_H:
+	      (*info->fprintf_func) (info->stream, "$ch%d",
+				     DECODE_INSN_RA (insn));
+	      break;
+	    case A_P:
+	      paren++;
+	      (*info->fprintf_func) (info->stream, "(");
+	      break;
+	    case A_U7A:
+	      (*info->fprintf_func) (info->stream, "%d",
+				     173 - DECODE_INSN_U8 (insn));
+	      break;
+	    case A_U7B:
+	      (*info->fprintf_func) (info->stream, "%d",
+				     155 - DECODE_INSN_U8 (insn));
+	      break;
+	    case A_S3:
+	    case A_S6:
+	    case A_S7:
+	    case A_S7N:
+	    case A_U3:
+	    case A_U5:
+	    case A_U6:
+	    case A_U7:
+	      hex_value = DECODE_INSN_I7 (insn);
+	      (*info->fprintf_func) (info->stream, "%d", hex_value);
+	      break;
+	    case A_S11:
+	      (*info->print_address_func) (memaddr + DECODE_INSN_I9a (insn) * 4,
+					   info);
+	      break;
+	    case A_S11I:
+	      (*info->print_address_func) (memaddr + DECODE_INSN_I9b (insn) * 4,
+					   info);
+	      break;
+	    case A_S10:
+	    case A_S10B:
+	      hex_value = DECODE_INSN_I10 (insn);
+	      (*info->fprintf_func) (info->stream, "%d", hex_value);
+	      break;
+	    case A_S14:
+	      hex_value = DECODE_INSN_I10 (insn) * 16;
+	      (*info->fprintf_func) (info->stream, "%d", hex_value);
+	      break;
+	    case A_S16:
+	      hex_value = DECODE_INSN_I16 (insn);
+	      (*info->fprintf_func) (info->stream, "%d", hex_value);
+	      break;
+	    case A_X16:
+	      hex_value = DECODE_INSN_U16 (insn);
+	      (*info->fprintf_func) (info->stream, "%u", hex_value);
+	      break;
+	    case A_R18:
+	      value = DECODE_INSN_I16 (insn) * 4;
+	      if (value == 0)
+		(*info->fprintf_func) (info->stream, "%d", value);
+	      else
+		{
+		  hex_value = memaddr + value;
+		  (*info->print_address_func) (hex_value & 0x3ffff, info);
+		}
+	      break;
+	    case A_S18:
+	      value = DECODE_INSN_U16 (insn) * 4;
+	      if (value == 0)
+		(*info->fprintf_func) (info->stream, "%d", value);
+	      else
+		(*info->print_address_func) (value, info);
+	      break;
+	    case A_U18:
+	      value = DECODE_INSN_U18 (insn);
+	      if (value == 0 || !(*info->symbol_at_address_func)(0, info))
+		{
+		  hex_value = value;
+		  (*info->fprintf_func) (info->stream, "%u", value);
+		}
+	      else
+		(*info->print_address_func) (value, info);
+	      break;
+	    case A_U14:
+	      hex_value = DECODE_INSN_U14 (insn);
+	      (*info->fprintf_func) (info->stream, "%u", hex_value);
+	      break;
+	    }
+	  if (arg != A_P && paren)
+	    {
+	      (*info->fprintf_func) (info->stream, ")");
+	      paren--;
+	    }
+	}
+      if (hex_value > 16)
+	(*info->fprintf_func) (info->stream, "\t# %x", hex_value);
+    }
+  return 4;
+}
diff --git a/opcodes/spu-opc.c b/opcodes/spu-opc.c
new file mode 100644
index 00000000000..683f96f5de9
--- /dev/null
+++ b/opcodes/spu-opc.c
@@ -0,0 +1,44 @@
+/* SPU opcode list
+
+   Copyright 2006 Free Software Foundation, Inc.
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#include "opcode/spu.h"
+
+/* This file holds the Spu opcode table */
+
+
+/*
+   Example contents of spu-insn.h
+      id_tag	mode	mode	type	opcode	mnemonic	asmtype	    dependency		FPU	L/S?	branch?	instruction   
+                QUAD	WORD                                               (0,RC,RB,RA,RT)    latency  			              		
+   APUOP(M_LQD,	1,	0,	RI9,	0x1f8,	"lqd",		ASM_RI9IDX,	00012,		FXU,	1,	0)	Load Quadword d-form 
+ */
+
+const struct spu_opcode spu_opcodes[] = {
+#define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
+	{ MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
+#define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
+	{ MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
+#include "opcode/spu-insns.h"
+#undef APUOP
+#undef APUOPFB
+};
+
+const int spu_num_opcodes =
+  sizeof (spu_opcodes) / sizeof (spu_opcodes[0]);