gdb/ChangeLog:

2004-08-25  Jim Blandy  <jimb@redhat.com>

	Merge changes from trunk:

	2004-08-09  Jim Blandy  <jimb@redhat.com>

	* rs6000-tdep.c (set_sim_regno, init_sim_regno_table,
	rs6000_register_sim_regno): Doc fixes.

	2004-08-04  Jim Blandy  <jimb@redhat.com>

	* ppc-linux-nat.c (fetch_register): Replace 'gdb_assert (0)' with
	a call to 'internal_error', with a more helpful error message.
	* rs6000-tdep.c (e500_pseudo_register_read,
	e500_pseudo_register_write, rs6000_store_return_value): Same.

	Change the layout of the PowerPC E500 raw register cache to allow
	the lower 32-bit halves of the GPRS to be their own raw registers,
	not pseudoregisters.
	* ppc-tdep.h (struct gdbarch_tdep): Remove ppc_gprs_pseudo_p flag;
	add ppc_ev0_upper_regnum flag.
	* rs6000-tdep.c: #include "reggroups.h".
	(spe_register_p): Recognize the ev upper half registers as SPE
	registers.
	(init_sim_regno_table): Build gdb->sim mappings for the upper-half
	registers.
	(e500_move_ev_register): New function.
	(e500_pseudo_register_read, e500_pseudo_register_write): The 'ev'
	vector registers are the pseudo-registers now, formed by splicing
	together the gprs and the upper-half registers.
	(e500_register_reggroup_p): New function.
	(P): Macro deleted.
	(P8, A4): New macro.
	(PPC_EV_REGS, PPC_GPRS_PSEUDO_REGS): Macros deleted.
	(PPC_SPE_GP_REGS, PPC_SPE_UPPER_GP_REGS, PPC_EV_PSEUDO_REGS): New
	macros.
	(registers_e500): Rearrange register set so that the raw register
	set contains 32-bit GPRs and upper-half registers, and the SPE
	vector registers become pseudo-registers.
	(rs6000_gdbarch_init): Don't initialize tdep->ppc_gprs_pseudo_p;
	it has been deleted.  Initialize ppc_ev0_upper_regnum.  Many other
	register numbers are now the same for the E500 as they are for
	other PowerPC variants.  Register e500_register_reggroup_p as the
	register group function for the E500.
	* Makefile.in (rs6000-tdep.o): Update dependencies.

	Adapt PPC E500 native support to the new raw regcache layout.
	* ppc-linux-nat.c (struct gdb_evrregset_t): Doc fixes.
	(read_spliced_spe_reg, write_spliced_spe_reg): Deleted.
	(fetch_spe_register, store_spe_register): Handle fetching/storing
	all the SPE registers at once, if regno == -1.  These now take
	over the job of fetch_spe_registers and store_spe_registers.
	(fetch_spe_registers, store_spe_registers): Deleted.
	(fetch_ppc_registers, store_ppc_registers): Fetch/store gprs
	unconditionally; they're always raw.  Fetch/store SPE upper half
	registers, if present, instead of ev registers.
	(fetch_register, store_register): Remove sanity checks: gprs are
	never pseudo-registers now, so we never need to even mention any
	registers that are ever pseudoregisters.

	Use a fixed register numbering when communicating with the PowerPC
	simulator.
	* ppc-tdep.h (struct gdbarch_tdep): New member: 'sim_regno'.
	* rs6000-tdep.c: #include "sim-regno.h" and "gdb/sim-ppc.h".
	(set_sim_regno, init_sim_regno_table, rs6000_register_sim_regno):
	New functions.
	(rs6000_gdbarch_init): Register rs6000_register_sim_regno.  Call
	init_sim_regno_table.
	* Makefile.in (gdb_sim_ppc_h): New variable.
	(rs6000-tdep.o): Update dependencies.

	2004-08-02  Andrew Cagney  <cagney@gnu.org>

	Replace DEPRECATED_REGISTER_RAW_SIZE with register_size.
	* rs6000-tdep.c (rs6000_push_dummy_call)
	(rs6000_extract_return_value): Use register_size.
	...
	* ppc-linux-nat.c (fetch_altivec_register, fetch_register)
	(supply_vrregset, store_altivec_register, fill_vrregset): Ditto.

	2004-07-20  Jim Blandy  <jimb@redhat.com>

	* rs6000-tdep.c (rs6000_gdbarch_init): The register set used for
	bfd_mach_ppc has no segment registers.

	Include PowerPC SPR numbers for special-purpose registers.
	* rs6000-tdep.c (struct reg): Add new member, 'spr_num'.
	(R, R4, R8, R16, F, P, R32, R64, R0): Include value for
	new member in initializer.
	(S, S4, SN4, S64): New macros for defining special-purpose
	registers.
	(PPC_UISA_SPRS, PPC_UISA_NOFP_SPRS, PPC_OEA_SPRS, registers_power,
	registers_403, registers_403GC, registers_505, registers_860,
	registers_601, registers_602, registers_603, registers_604,
	registers_750, registers_e500): Use them.

	* rs6000-tdep.c (rs6000_gdbarch_init): Delete variable 'power';
	replace references with expression used to initialize variable.

	2004-07-16  Jim Blandy  <jimb@redhat.com>

	* ppc-tdep.h (ppc_spr_asr): Add missing OEA SPR.
        (ppc_spr_mi_dbcam, ppc_spr_mi_dbram0, ppc_spr_mi_dbram1)
	(ppc_spr_md_cam, ppc_spr_md_ram0, ppc_spr_md_ram1): Add
	missing MPC823 SPRs.
	(ppc_spr_m_twb): Renamed from ppc_spr_md_twb; the old name was
	incorrect.  (This was corrected in GDB's register name tables on
	2004-07-14.)

	* rs6000-tdep.c (registers_602): Correct register name: "esassr"
	should be "esasrr" ("ESA Save and Restore Register").

	2004-07-15  Jim Blandy  <jimb@redhat.com>

	* ppc-tdep.h (struct gdbarch_tdep): New member: ppc_sr0_regnum.
	* rs6000-tdep.c (rs6000_gdbarch_init): Initialize it.

	2004-07-14  Jim Blandy  <jimb@redhat.com>

	* rs6000-tdep.c (COMMON_UISA_NOFP_REGS): Delete; unused.

	* ppc-tdep.h (ppc_num_vrs): New enum constant.

	* ppc-tdep.h (ppc_num_srs): New enum constant.

	* ppc-tdep.h (ppc_spr_mq, ppc_spr_xer, ppc_spr_rtcu, ppc_spr_rtcl)
	(ppc_spr_lr, ppc_spr_ctr, ppc_spr_cnt, ppc_spr_dsisr, ppc_spr_dar)
	(ppc_spr_dec, ppc_spr_sdr1, ppc_spr_srr0, ppc_spr_srr1)
	(ppc_spr_eie, ppc_spr_eid, ppc_spr_nri, ppc_spr_sp, ppc_spr_cmpa)
	(ppc_spr_cmpb, ppc_spr_cmpc, ppc_spr_cmpd, ppc_spr_icr)
	(ppc_spr_der, ppc_spr_counta, ppc_spr_countb, ppc_spr_cmpe)
	(ppc_spr_cmpf, ppc_spr_cmpg, ppc_spr_cmph, ppc_spr_lctrl1)
	(ppc_spr_lctrl2, ppc_spr_ictrl, ppc_spr_bar, ppc_spr_vrsave)
	(ppc_spr_sprg0, ppc_spr_sprg1, ppc_spr_sprg2, ppc_spr_sprg3)
	(ppc_spr_ear, ppc_spr_tbl, ppc_spr_tbu, ppc_spr_pvr)
	(ppc_spr_spefscr, ppc_spr_ibat0u, ppc_spr_ibat0l, ppc_spr_ibat1u)
	(ppc_spr_ibat1l, ppc_spr_ibat2u, ppc_spr_ibat2l, ppc_spr_ibat3u)
	(ppc_spr_ibat3l, ppc_spr_dbat0u, ppc_spr_dbat0l, ppc_spr_dbat1u)
	(ppc_spr_dbat1l, ppc_spr_dbat2u, ppc_spr_dbat2l, ppc_spr_dbat3u)
	(ppc_spr_dbat3l, ppc_spr_ic_cst, ppc_spr_ic_adr, ppc_spr_ic_dat)
	(ppc_spr_dc_cst, ppc_spr_dc_adr, ppc_spr_dc_dat, ppc_spr_dpdr)
	(ppc_spr_dpir, ppc_spr_immr, ppc_spr_mi_ctr, ppc_spr_mi_ap)
	(ppc_spr_mi_epn, ppc_spr_mi_twc, ppc_spr_mi_rpn, ppc_spr_mi_cam)
	(ppc_spr_mi_ram0, ppc_spr_mi_ram1, ppc_spr_md_ctr, ppc_spr_m_casid)
	(ppc_spr_md_ap, ppc_spr_md_epn, ppc_spr_md_twb, ppc_spr_md_twc)
	(ppc_spr_md_rpn, ppc_spr_m_tw, ppc_spr_md_dbcam, ppc_spr_md_dbram0)
	(ppc_spr_md_dbram1, ppc_spr_ummcr0, ppc_spr_upmc1, ppc_spr_upmc2)
	(ppc_spr_usia, ppc_spr_ummcr1, ppc_spr_upmc3, ppc_spr_upmc4)
	(ppc_spr_zpr, ppc_spr_pid, ppc_spr_mmcr0, ppc_spr_pmc1)
	(ppc_spr_sgr, ppc_spr_pmc2, ppc_spr_dcwr, ppc_spr_sia)
	(ppc_spr_mmcr1, ppc_spr_pmc3, ppc_spr_pmc4, ppc_spr_sda)
	(ppc_spr_tbhu, ppc_spr_tblu, ppc_spr_dmiss, ppc_spr_dcmp)
	(ppc_spr_hash1, ppc_spr_hash2, ppc_spr_icdbdr, ppc_spr_imiss)
	(ppc_spr_esr, ppc_spr_icmp, ppc_spr_dear, ppc_spr_rpa)
	(ppc_spr_evpr, ppc_spr_cdbcr, ppc_spr_tsr, ppc_spr_602_tcr)
	(ppc_spr_403_tcr, ppc_spr_ibr, ppc_spr_pit, ppc_spr_esasrr)
	(ppc_spr_tbhi, ppc_spr_tblo, ppc_spr_srr2, ppc_spr_sebr)
	(ppc_spr_srr3, ppc_spr_ser, ppc_spr_hid0, ppc_spr_dbsr)
	(ppc_spr_hid1, ppc_spr_iabr, ppc_spr_dbcr, ppc_spr_iac1)
	(ppc_spr_dabr, ppc_spr_iac2, ppc_spr_dac1, ppc_spr_dac2)
	(ppc_spr_l2cr, ppc_spr_dccr, ppc_spr_ictc, ppc_spr_iccr)
	(ppc_spr_thrm1, ppc_spr_pbl1, ppc_spr_thrm2, ppc_spr_pbu1)
	(ppc_spr_thrm3, ppc_spr_pbl2, ppc_spr_fpecr, ppc_spr_lt)
	(ppc_spr_pir, ppc_spr_pbu2): New enum constants for PowerPC
	special-purpose register numbers.

	* rs6000-tdep.c (registers_860): Correct register name.  (No PPC
	manual mentions 'md_twb', but many mention 'm_twb', and at that
	point in the register list.)

include/gdb/ChangeLog:
2004-08-04  Andrew Cagney  <cagney@gnu.org>

	* sim-ppc.h: Add extern "C" wrapper.
	(enum sim_ppc_regnum): Add full list of SPRs.

2004-08-04  Jim Blandy  <jimb@redhat.com>

	* sim-ppc.h: New file.

sim/ppc/ChangeLog:
2004-08-04  Andrew Cagney  <cagney@gnu.org>
	    Jim Blandy <jimb@redhat.com>

	* sim_callbacks.h (simulator): Declare.
	* Makefile.in (gdb-sim.o): New rule.
	(MAIN_SRC, GDB_OBJ): Add gdb-sim.o, gdb-sim.c.
	(DEFS_H): Delete.
	(GDB_SIM_PPC_H): Define.
	* gdb-sim.c: New file.
	* sim_calls.c: Do not include "defs.h".
	(simulator): Drop static.
	(sim_store_register, sim_fetch_register): Delete.

8 files changed, 8900 insertions, 73 deletions

diff --git a/gdb/Makefile.in b/gdb/Makefile.in
new file mode 100644
index 00000000000..a81fe9f790b
--- /dev/null
+++ b/gdb/Makefile.in
@@ -0,0 +1,2973 @@
+# Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
+# 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation,
+# Inc.
+
+# This file is part of GDB.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+prefix = @prefix@
+exec_prefix = @exec_prefix@
+
+host_alias = @host_alias@
+target_alias = @target_alias@
+program_transform_name = @program_transform_name@
+bindir = @bindir@
+libdir = @libdir@
+tooldir = $(libdir)/$(target_alias)
+
+datadir = @datadir@
+mandir = @mandir@
+man1dir = $(mandir)/man1
+man2dir = $(mandir)/man2
+man3dir = $(mandir)/man3
+man4dir = $(mandir)/man4
+man5dir = $(mandir)/man5
+man6dir = $(mandir)/man6
+man7dir = $(mandir)/man7
+man8dir = $(mandir)/man8
+man9dir = $(mandir)/man9
+infodir = @infodir@
+htmldir = $(prefix)/html
+includedir = @includedir@
+
+# This can be referenced by `INTLDEPS' as computed by CY_GNU_GETTEXT.
+top_builddir = .
+
+SHELL = @SHELL@
+EXEEXT = @EXEEXT@
+
+AWK = @AWK@
+LN_S = @LN_S@
+
+INSTALL = @INSTALL@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_DATA = @INSTALL_DATA@
+
+DESTDIR =
+
+AR = @AR@
+AR_FLAGS = qv
+RANLIB = @RANLIB@
+DLLTOOL = @DLLTOOL@
+WINDRES = @WINDRES@
+MIG = @MIG@
+
+# If you are compiling with GCC, make sure that either 1) You have the
+# fixed include files where GCC can reach them, or 2) You use the
+# -traditional flag.  Otherwise the ioctl calls in inflow.c
+# will be incorrectly compiled.  The "fixincludes" script in the gcc
+# distribution will fix your include files up.
+CC=@CC@
+
+# Directory containing source files.
+srcdir = @srcdir@
+VPATH = @srcdir@
+
+YACC=@YACC@
+
+# This is used to rebuild ada-lex.c from ada-lex.l.  If the program is
+# not defined, but ada-lex.c is present, compilation will continue,
+# possibly with a warning.
+FLEX = flex
+
+YLWRAP = $(srcdir)/../ylwrap
+
+# where to find makeinfo, preferably one designed for texinfo-2
+MAKEINFO=makeinfo
+
+MAKEHTML = texi2html
+
+MAKEHTMLFLAGS = -glossary -menu -split_chapter
+
+# Set this up with gcc if you have gnu ld and the loader will print out
+# line numbers for undefined references.
+#CC_LD=gcc -static
+CC_LD=$(CC)
+
+# Where is our "include" directory?  Typically $(srcdir)/../include.
+# This is essentially the header file directory for the library
+# routines in libiberty.
+INCLUDE_DIR =  $(srcdir)/../include
+INCLUDE_CFLAGS = -I$(INCLUDE_DIR)
+
+# Where is the "-liberty" library?  Typically in ../libiberty.
+LIBIBERTY = ../libiberty/libiberty.a
+
+# Where is the BFD library?  Typically in ../bfd.
+BFD_DIR = ../bfd
+BFD = $(BFD_DIR)/libbfd.a
+BFD_SRC = $(srcdir)/$(BFD_DIR)
+BFD_CFLAGS = -I$(BFD_DIR) -I$(BFD_SRC)
+
+# Where is the READLINE library?  Typically in ../readline.
+READLINE_DIR = ../readline
+READLINE = $(READLINE_DIR)/libreadline.a
+READLINE_SRC = $(srcdir)/$(READLINE_DIR)
+READLINE_CFLAGS = -I$(READLINE_SRC)/..
+
+WARN_CFLAGS = @WARN_CFLAGS@
+WERROR_CFLAGS = @WERROR_CFLAGS@
+GDB_WARN_CFLAGS = $(WARN_CFLAGS)
+GDB_WERROR_CFLAGS = $(WERROR_CFLAGS)
+
+# Where is the INTL library?  Typically in ../intl.
+INTL_DIR = ../intl
+INTL = @INTLLIBS@
+INTL_DEPS = @INTLDEPS@
+INTL_SRC = $(srcdir)/$(INTL_DIR)
+INTL_CFLAGS = -I$(INTL_DIR) -I$(INTL_SRC)
+
+# Where is the ICONV library?  This can be empty if libc has iconv.
+LIBICONV = @LIBICONV@
+
+# Did the user give us a --with-sysroot option?
+TARGET_SYSTEM_ROOT = @TARGET_SYSTEM_ROOT@
+TARGET_SYSTEM_ROOT_DEFINE = @TARGET_SYSTEM_ROOT_DEFINE@
+
+#
+# CLI sub directory definitons
+#
+SUBDIR_CLI_OBS = \
+	cli-dump.o \
+	cli-decode.o cli-script.o cli-cmds.o cli-setshow.o cli-utils.o \
+	cli-logging.o \
+	cli-interp.o
+SUBDIR_CLI_SRCS = \
+	cli/cli-dump.c \
+	cli/cli-decode.c cli/cli-script.c cli/cli-cmds.c cli/cli-setshow.c \
+	cli/cli-logging.c \
+	cli/cli-interp.c \
+	cli/cli-utils.c
+SUBDIR_CLI_DEPS =
+SUBDIR_CLI_LDFLAGS=
+SUBDIR_CLI_CFLAGS=
+
+#
+# MI sub directory definitons
+#
+SUBDIR_MI_OBS = \
+	mi-out.o mi-console.o \
+	mi-cmds.o mi-cmd-env.o mi-cmd-var.o mi-cmd-break.o mi-cmd-stack.o \
+	mi-cmd-file.o mi-cmd-disas.o mi-symbol-cmds.o \
+	mi-interp.o \
+	mi-main.o mi-parse.o mi-getopt.o
+SUBDIR_MI_SRCS = \
+	mi/mi-out.c mi/mi-console.c \
+	mi/mi-cmds.c mi/mi-cmd-env.c \
+	mi/mi-cmd-var.c mi/mi-cmd-break.c mi/mi-cmd-stack.c \
+	mi/mi-cmd-file.c mi/mi-cmd-disas.c mi/mi-symbol-cmds.c \
+	mi/mi-interp.c \
+	mi/mi-main.c mi/mi-parse.c mi/mi-getopt.c
+SUBDIR_MI_DEPS =
+SUBDIR_MI_LDFLAGS=
+SUBDIR_MI_CFLAGS= \
+	-DMI_OUT=1
+
+#
+# TUI sub directory definitions
+#
+
+# Name of the TUI program
+TUI=gdbtui
+
+SUBDIR_TUI_OBS = \
+	tui-command.o \
+	tui-data.o \
+	tui-disasm.o \
+	tui-file.o tui.o \
+	tui-hooks.o \
+	tui-interp.o \
+	tui-io.o \
+	tui-layout.o \
+	tui-out.o \
+	tui-regs.o \
+	tui-source.o \
+	tui-stack.o \
+	tui-win.o \
+	tui-windata.o \
+	tui-wingeneral.o \
+	tui-winsource.o
+SUBDIR_TUI_SRCS = \
+	tui/tui-command.c \
+	tui/tui-data.c \
+	tui/tui-disasm.c \
+	tui/tui-file.c \
+	tui/tui-hooks.c \
+	tui/tui-interp.c \
+	tui/tui-io.c \
+	tui/tui-layout.c \
+	tui/tui-out.c \
+	tui/tui-regs.c \
+	tui/tui-source.c \
+	tui/tui-stack.c \
+	tui/tui-win.c \
+	tui/tui-windata.c \
+	tui/tui-wingeneral.c \
+	tui/tui-winsource.c \
+	tui/tui.c
+SUBDIR_TUI_DEPS =
+SUBDIR_TUI_LDFLAGS=
+SUBDIR_TUI_CFLAGS= \
+	-DTUI=1
+
+
+# Opcodes currently live in one of two places.  Either they are in the
+# opcode library, typically ../opcodes, or they are in a header file
+# in INCLUDE_DIR.
+# Where is the "-lopcodes" library, with (some of) the opcode tables and
+# disassemblers?
+OPCODES_DIR = ../opcodes
+OPCODES_SRC = $(srcdir)/$(OPCODES_DIR)
+OPCODES = $(OPCODES_DIR)/libopcodes.a
+# Where are the other opcode tables which only have header file
+# versions?
+OP_INCLUDE = $(INCLUDE_DIR)/opcode
+OPCODES_CFLAGS = -I$(OP_INCLUDE)
+
+# The simulator is usually nonexistent; targets that include one
+# should set this to list all the .o or .a files to be linked in.
+SIM =
+
+WIN32LIBS = @WIN32LIBS@
+
+# Where is the TCL library?  Typically in ../tcl.
+LIB_INSTALL_DIR = $(libdir)
+# This variable is needed when doing dynamic linking.
+LIB_RUNTIME_DIR = $(libdir)
+TCL = @TCL_CC_SEARCH_FLAGS@ @TCL_BUILD_LIB_SPEC@
+TCL_CFLAGS = @TCLHDIR@
+GDBTKLIBS = @GDBTKLIBS@
+# Extra flags that the GDBTK files need:
+GDBTK_CFLAGS = @GDBTK_CFLAGS@
+
+# Where is the TK library?  Typically in ../tk.
+TK = @TK_BUILD_LIB_SPEC@
+TK_CFLAGS = @TKHDIR@ @TK_BUILD_INCLUDES@
+
+# Where is Itcl?  Typically in ../itcl/itcl.
+ITCL_CFLAGS = @ITCLHDIR@
+ITCL = @ITCLLIB@
+
+# Where is Itk?  Typically in ../itcl/itk.
+ITK_CFLAGS = @ITKHDIR@
+ITK = @ITKLIB@
+
+X11_CFLAGS = @TK_XINCLUDES@
+X11_LDFLAGS =
+X11_LIBS =
+
+WIN32LDAPP = @WIN32LDAPP@
+
+LIBGUI = @LIBGUI@
+GUI_CFLAGS_X = @GUI_CFLAGS_X@
+IDE_CFLAGS=$(GUI_CFLAGS_X) $(IDE_CFLAGS_X)
+
+# The version of gdbtk we're building. This should be kept
+# in sync with GDBTK_VERSION and friends in gdbtk.h.
+GDBTK_VERSION = 1.0
+GDBTK_LIBRARY = $(datadir)/insight$(GDBTK_VERSION)
+
+# Gdbtk requires an absolute path to the source directory or
+# the testsuite won't run properly.
+GDBTK_SRC_DIR = @GDBTK_SRC_DIR@
+
+SUBDIR_GDBTK_OBS = \
+	gdbtk.o gdbtk-bp.o gdbtk-cmds.o gdbtk-hooks.o gdbtk-interp.o \
+	gdbtk-register.o gdbtk-stack.o gdbtk-varobj.o gdbtk-wrapper.o
+SUBDIR_GDBTK_SRCS = \
+	gdbtk/generic/gdbtk.c gdbtk/generic/gdbtk-bp.c \
+	gdbtk/generic/gdbtk-cmds.c gdbtk/generic/gdbtk-hooks.c \
+	gdbtk/generic/gdbtk-interp.c \
+	gdbtk/generic/gdbtk-register.c gdbtk/generic/gdbtk-stack.c \
+	gdbtk/generic/gdbtk-varobj.c gdbtk/generic/gdbtk-wrapper.c \
+	gdbtk/generic/gdbtk-main.c
+SUBDIR_GDBTK_DEPS = \
+	$(LIBGUI) $(ITCL_DEPS) $(ITK_DEPS) $(TK_DEPS) $(TCL_DEPS)
+SUBDIR_GDBTK_LDFLAGS=
+SUBDIR_GDBTK_CFLAGS= -DGDBTK
+
+CONFIG_OBS= @CONFIG_OBS@
+CONFIG_SRCS= @CONFIG_SRCS@
+CONFIG_DEPS= @CONFIG_DEPS@
+CONFIG_LDFLAGS = @CONFIG_LDFLAGS@
+ENABLE_CFLAGS= @ENABLE_CFLAGS@
+CONFIG_ALL= @CONFIG_ALL@
+CONFIG_CLEAN= @CONFIG_CLEAN@
+CONFIG_CLEAN= @CONFIG_CLEAN@
+CONFIG_INSTALL = @CONFIG_INSTALL@
+CONFIG_UNINSTALL = @CONFIG_UNINSTALL@
+
+# -I. for config files.
+# -I$(srcdir) for gdb internal headers.
+# -I$(srcdir)/config for more generic config files.
+
+# It is also possible that you will need to add -I/usr/include/sys if
+# your system doesn't have fcntl.h in /usr/include (which is where it
+# should be according to Posix).
+DEFS = @DEFS@
+GDB_CFLAGS = -I. -I$(srcdir) -I$(srcdir)/config -DLOCALEDIR="\"$(prefix)/share/locale\"" $(DEFS)
+
+# M{H,T}_CFLAGS, if defined, have host- and target-dependent CFLAGS
+# from the config directory.
+GLOBAL_CFLAGS = $(MT_CFLAGS) $(MH_CFLAGS)
+
+PROFILE_CFLAGS = @PROFILE_CFLAGS@
+
+# CFLAGS is specifically reserved for setting from the command line
+# when running make.  I.E.  "make CFLAGS=-Wmissing-prototypes".
+CFLAGS = @CFLAGS@
+
+# Need to pass this to testsuite for "make check".  Probably should be
+# consistent with top-level Makefile.in and gdb/testsuite/Makefile.in
+# so "make check" has the same result no matter where it is run.
+CXXFLAGS = -g -O
+
+# INTERNAL_CFLAGS is the aggregate of all other *CFLAGS macros.
+INTERNAL_WARN_CFLAGS = \
+	$(CFLAGS) $(GLOBAL_CFLAGS) $(PROFILE_CFLAGS) \
+	$(GDB_CFLAGS) $(OPCODES_CFLAGS) $(READLINE_CFLAGS) \
+	$(BFD_CFLAGS) $(INCLUDE_CFLAGS) \
+	$(INTL_CFLAGS) $(ENABLE_CFLAGS) \
+	$(GDB_WARN_CFLAGS)
+INTERNAL_CFLAGS = $(INTERNAL_WARN_CFLAGS) $(GDB_WERROR_CFLAGS)
+
+# LDFLAGS is specifically reserved for setting from the command line
+# when running make.
+LDFLAGS = @LDFLAGS@
+
+# Profiling options need to go here to work.
+# I think it's perfectly reasonable for a user to set -pg in CFLAGS
+# and have it work; that's why CFLAGS is here.
+# PROFILE_CFLAGS is _not_ included, however, because we use monstartup.
+INTERNAL_LDFLAGS = $(CFLAGS) $(GLOBAL_CFLAGS) $(MH_LDFLAGS) $(LDFLAGS) $(CONFIG_LDFLAGS)
+
+# If your system is missing alloca(), or, more likely, it's there but
+# it doesn't work, then refer to libiberty.
+
+# Libraries and corresponding dependencies for compiling gdb.
+# {X,T}M_CLIBS, defined in *config files, have host- and target-dependent libs.
+# LIBIBERTY appears twice on purpose.
+# If you have the Cygnus libraries installed,
+# you can use 'CLIBS=$(INSTALLED_LIBS)' 'CDEPS='
+INSTALLED_LIBS=-lbfd -lreadline -lopcodes -liberty \
+	$(XM_CLIBS) $(TM_CLIBS) $(NAT_CLIBS) $(GDBTKLIBS) @LIBS@ \
+	-lintl -liberty
+CLIBS = $(SIM) $(BFD) $(READLINE) $(OPCODES) $(INTL) $(LIBIBERTY) \
+	$(XM_CLIBS) $(TM_CLIBS) $(NAT_CLIBS) $(GDBTKLIBS) @LIBS@ \
+	$(LIBICONV) \
+	$(LIBIBERTY) $(WIN32LIBS)
+CDEPS = $(XM_CDEPS) $(TM_CDEPS) $(NAT_CDEPS) $(SIM) $(BFD) $(READLINE) \
+	$(OPCODES) $(INTL_DEPS) $(LIBIBERTY) $(CONFIG_DEPS)
+
+ADD_FILES = $(XM_ADD_FILES) $(TM_ADD_FILES) $(NAT_ADD_FILES)
+ADD_DEPS = $(XM_ADD_FILES) $(TM_ADD_FILES) $(NAT_ADD_FILES)
+
+DIST=gdb
+
+LINT=/usr/5bin/lint
+LINTFLAGS= $(GDB_CFLAGS) $(OPCODES_CFLAGS) $(READLINE_CFLAGS) \
+	$(BFD_CFLAGS) $(INCLUDE_CFLAGS) \
+	$(INTL_CFLAGS)
+
+RUNTEST = `if [ -f $${rootsrc}/../dejagnu/runtest ] ; then \
+		echo $${rootsrc}/../dejagnu/runtest ; else echo runtest; \
+	   fi`
+
+RUNTESTFLAGS=
+
+# This is ser-unix.o for any system which supports a v7/BSD/SYSV/POSIX
+# interface to the serial port.  Hopefully if get ported to OS/2, VMS,
+# etc., then there will be (as part of the C library or perhaps as
+# part of libiberty) a POSIX interface.  But at least for now the
+# host-dependent makefile fragment might need to use something else
+# besides ser-unix.o
+SER_HARDWIRE = @SER_HARDWIRE@
+
+# The `remote' debugging target is supported for most architectures,
+# but not all (e.g. 960)
+REMOTE_OBS = remote.o dcache.o remote-utils.o tracepoint.o ax-general.o ax-gdb.o remote-fileio.o
+
+# This is remote-sim.o if a simulator is to be linked in.
+SIM_OBS =
+
+# Host and target-dependent makefile fragments come in here.
+@host_makefile_frag@
+@target_makefile_frag@
+# End of host and target-dependent makefile fragments
+
+# Possibly ignore the simulator.  If the simulator is being ignored,
+# these expand into SIM= and SIM_OBJ=, overriding the entries from
+# target_makefile_frag
+#
+@IGNORE_SIM@
+@IGNORE_SIM_OBS@
+
+FLAGS_TO_PASS = \
+	"prefix=$(prefix)" \
+	"exec_prefix=$(exec_prefix)" \
+	"infodir=$(infodir)" \
+	"libdir=$(libdir)" \
+	"mandir=$(mandir)" \
+	"datadir=$(datadir)" \
+	"includedir=$(includedir)" \
+	"against=$(against)" \
+	"DESTDIR=$(DESTDIR)" \
+	"AR=$(AR)" \
+	"AR_FLAGS=$(AR_FLAGS)" \
+	"CC=$(CC)" \
+	"CFLAGS=$(CFLAGS)" \
+	"CXX=$(CXX)" \
+	"CXXFLAGS=$(CXXFLAGS)" \
+	"DLLTOOL=$(DLLTOOL)" \
+	"LDFLAGS=$(LDFLAGS)" \
+	"RANLIB=$(RANLIB)" \
+	"MAKEINFO=$(MAKEINFO)" \
+	"MAKEHTML=$(MAKEHTML)" \
+	"MAKEHTMLFLAGS=$(MAKEHTMLFLAGS)" \
+	"INSTALL=$(INSTALL)" \
+	"INSTALL_PROGRAM=$(INSTALL_PROGRAM)" \
+	"INSTALL_DATA=$(INSTALL_DATA)" \
+	"RUNTEST=$(RUNTEST)" \
+	"RUNTESTFLAGS=$(RUNTESTFLAGS)"
+
+# Flags that we pass when building the testsuite.
+
+# empty for native, $(target_alias)/ for cross
+target_subdir = @target_subdir@
+
+CC_FOR_TARGET = ` \
+  if [ -f $${rootme}/../gcc/xgcc ] ; then \
+    if [ -f $${rootme}/../$(target_subdir)newlib/Makefile ] ; then \
+      echo $${rootme}/../gcc/xgcc -B$${rootme}/../gcc/ -idirafter $${rootme}/$(target_subdir)newlib/targ-include -idirafter $${rootsrc}/../$(target_subdir)newlib/libc/include -nostdinc -B$${rootme}/../$(target_subdir)newlib/; \
+    else \
+      echo $${rootme}/../gcc/xgcc -B$${rootme}/../gcc/; \
+    fi; \
+  else \
+    if [ "$(host_canonical)" = "$(target_canonical)" ] ; then \
+      echo $(CC); \
+    else \
+      t='$(program_transform_name)'; echo gcc | sed -e '' $$t; \
+    fi; \
+  fi`
+
+CXX = gcc
+CXX_FOR_TARGET = ` \
+  if [ -f $${rootme}/../gcc/xgcc ] ; then \
+    if [ -f $${rootme}/../$(target_subdir)newlib/Makefile ] ; then \
+      echo $${rootme}/../gcc/xgcc -B$${rootme}/../gcc/ -idirafter $${rootme}/$(target_subdir)newlib/targ-include -idirafter $${rootsrc}/../$(target_subdir)newlib/libc/include -nostdinc -B$${rootme}/../$(target_subdir)newlib/; \
+    else \
+      echo $${rootme}/../gcc/xgcc -B$${rootme}/../gcc/; \
+    fi; \
+  else \
+    if [ "$(host_canonical)" = "$(target_canonical)" ] ; then \
+      echo $(CXX); \
+    else \
+      t='$(program_transform_name)'; echo gcc | sed -e '' $$t; \
+    fi; \
+  fi`
+
+# The use of $$(x_FOR_TARGET) reduces the command line length by not
+# duplicating the lengthy definition.
+TARGET_FLAGS_TO_PASS = \
+	"prefix=$(prefix)" \
+	"exec_prefix=$(exec_prefix)" \
+	"against=$(against)" \
+	'CC=$$(CC_FOR_TARGET)' \
+	"CC_FOR_TARGET=$(CC_FOR_TARGET)" \
+	"CFLAGS=$(CFLAGS)" \
+	'CXX=$$(CXX_FOR_TARGET)' \
+	"CXX_FOR_TARGET=$(CXX_FOR_TARGET)" \
+	"CXXFLAGS=$(CXXFLAGS)" \
+	"INSTALL=$(INSTALL)" \
+	"INSTALL_PROGRAM=$(INSTALL_PROGRAM)" \
+	"INSTALL_DATA=$(INSTALL_DATA)" \
+	"MAKEINFO=$(MAKEINFO)" \
+	"MAKEHTML=$(MAKEHTML)" \
+	"RUNTEST=$(RUNTEST)" \
+	"RUNTESTFLAGS=$(RUNTESTFLAGS)"
+
+# All source files that go into linking GDB.
+# Links made at configuration time should not be specified here, since
+# SFILES is used in building the distribution archive.
+
+SFILES = ada-exp.y ada-lang.c ada-typeprint.c ada-valprint.c ada-tasks.c \
+	ax-general.c ax-gdb.c \
+	bcache.c \
+	bfd-target.c \
+	block.c blockframe.c breakpoint.c buildsym.c \
+	c-exp.y c-lang.c c-typeprint.c c-valprint.c \
+	charset.c cli-out.c coffread.c coff-pe-read.c \
+	complaints.c completer.c corefile.c \
+	cp-abi.c cp-support.c cp-namespace.c cp-valprint.c \
+	dbxread.c demangle.c dictionary.c disasm.c doublest.c dummy-frame.c \
+	dwarfread.c dwarf2expr.c dwarf2loc.c dwarf2read.c dwarf2-frame.c \
+	elfread.c environ.c eval.c event-loop.c event-top.c expprint.c \
+	f-exp.y f-lang.c f-typeprint.c f-valprint.c findvar.c frame.c \
+	frame-base.c \
+	frame-unwind.c \
+	gdbarch.c arch-utils.c gdbtypes.c gnu-v2-abi.c gnu-v3-abi.c \
+	hpacc-abi.c \
+	inf-loop.c \
+	infcall.c \
+	infcmd.c inflow.c infrun.c \
+	interps.c \
+	jv-exp.y jv-lang.c jv-valprint.c jv-typeprint.c \
+	kod.c kod-cisco.c \
+	language.c linespec.c \
+	m2-exp.y m2-lang.c m2-typeprint.c m2-valprint.c \
+	macrotab.c macroexp.c macrocmd.c macroscope.c main.c maint.c \
+	mdebugread.c memattr.c mem-break.c minsyms.c mipsread.c \
+	nlmread.c \
+	objc-exp.y objc-lang.c \
+	objfiles.c osabi.c observer.c \
+	p-exp.y p-lang.c p-typeprint.c p-valprint.c parse.c printcmd.c \
+	regcache.c reggroups.c remote.c remote-fileio.c \
+	scm-exp.c scm-lang.c scm-valprint.c \
+	sentinel-frame.c \
+	serial.c ser-unix.c source.c \
+	stabsread.c stack.c std-regs.c symfile.c symfile-mem.c symmisc.c \
+	symtab.c \
+	target.c thread.c top.c tracepoint.c \
+	trad-frame.c \
+	tramp-frame.c \
+	typeprint.c \
+	ui-out.c utils.c ui-file.h ui-file.c \
+	user-regs.c \
+	valarith.c valops.c valprint.c values.c varobj.c \
+	wrapper.c
+
+LINTFILES = $(SFILES) $(YYFILES) $(CONFIG_SRCS) init.c
+
+# "system" headers.  Using these in dependencies is a rather personal
+# choice. (-rich, summer 1993)
+# (Why would we not want to depend on them?  If one of these changes in a
+# non-binary-compatible way, it is a real pain to remake the right stuff
+# without these dependencies -kingdon, 13 Mar 1994)
+aout_aout64_h =	$(INCLUDE_DIR)/aout/aout64.h
+aout_stabs_gnu_h =	$(INCLUDE_DIR)/aout/stabs_gnu.h
+getopt_h =	$(INCLUDE_DIR)/getopt.h
+floatformat_h =	$(INCLUDE_DIR)/floatformat.h
+bfd_h =		$(BFD_DIR)/bfd.h
+coff_sym_h =	$(INCLUDE_DIR)/coff/sym.h
+coff_symconst_h =	$(INCLUDE_DIR)/coff/symconst.h
+coff_ecoff_h =	$(INCLUDE_DIR)/coff/ecoff.h
+coff_internal_h =	$(INCLUDE_DIR)/coff/internal.h
+dis_asm_h =	$(INCLUDE_DIR)/dis-asm.h $(bfd_h)
+elf_reloc_macros_h =	$(INCLUDE_DIR)/elf/reloc-macros.h
+elf_sh_h =	$(INCLUDE_DIR)/elf/sh.h
+elf_arm_h =	$(INCLUDE_DIR)/elf/arm.h $(elf_reloc_macros_h)
+elf_bfd_h =	$(BFD_SRC)/elf-bfd.h
+elf_frv_h =	$(INCLUDE_DIR)/elf/frv.h $(elf_reloc_macros_h)
+libaout_h =	$(BFD_SRC)/libaout.h
+libbfd_h =	$(BFD_SRC)/libbfd.h
+remote_sim_h =	$(INCLUDE_DIR)/gdb/remote-sim.h
+demangle_h =    $(INCLUDE_DIR)/demangle.h
+obstack_h =     $(INCLUDE_DIR)/obstack.h
+opcode_m68hc11_h = $(INCLUDE_DIR)/opcode/m68hc11.h
+readline_h = 	$(READLINE_SRC)/readline.h
+readline_tilde_h =	$(READLINE_SRC)/tilde.h
+readline_history_h =	$(READLINE_SRC)/history.h
+frv_desc_h =	$(OPCODES_SRC)/frv-desc.h
+sh_opc_h = 	$(OPCODES_SRC)/sh-opc.h
+gdb_callback_h = $(INCLUDE_DIR)/gdb/callback.h
+gdb_sim_arm_h =	$(INCLUDE_DIR)/gdb/sim-arm.h
+gdb_sim_d10v_h = $(INCLUDE_DIR)/gdb/sim-d10v.h
+gdb_sim_frv_h = $(INCLUDE_DIR)/gdb/sim-frv.h
+gdb_sim_ppc_h =	$(INCLUDE_DIR)/gdb/sim-ppc.h
+gdb_sim_sh_h =	$(INCLUDE_DIR)/gdb/sim-sh.h
+splay_tree_h =  $(INCLUDE_DIR)/splay-tree.h
+hashtab_h =	$(INCLUDE_DIR)/hashtab.h
+
+#
+# $BUILD/ headers
+#
+
+config_h = config.h
+exc_request_U_h = exc_request_U.h
+exc_request_S_h = exc_request_S.h
+msg_reply_S_h = msg_reply_S.h
+msg_U_h = msg_U.h
+notify_S_h = notify_S.h
+observer_h = observer.h
+observer_inc = observer.inc
+process_reply_S_h = process_reply_S.h
+
+#
+# config/ headers
+#
+
+xm_h =		@xm_h@
+tm_h =		@tm_h@
+nm_h =		@nm_h@
+
+#
+# gdb/ headers
+#
+
+ada_lang_h = ada-lang.h $(value_h) $(gdbtypes_h)
+alphabsd_tdep_h = alphabsd-tdep.h
+alpha_tdep_h = alpha-tdep.h
+amd64_nat_h = amd64-nat.h
+amd64_tdep_h = amd64-tdep.h $(i386_tdep_h)
+annotate_h = annotate.h $(symtab_h) $(gdbtypes_h)
+arch_utils_h = arch-utils.h
+arm_tdep_h = arm-tdep.h
+auxv_h = auxv.h
+ax_gdb_h = ax-gdb.h
+ax_h = ax.h $(doublest_h)
+bcache_h = bcache.h
+bfd_target_h = bfd-target.h
+block_h = block.h
+breakpoint_h = breakpoint.h $(frame_h) $(value_h) $(gdb_events_h)
+bsd_kvm_h = bsd-kvm.h
+buildsym_h = buildsym.h
+call_cmds_h = call-cmds.h
+charset_h = charset.h
+c_lang_h = c-lang.h $(value_h) $(macroexp_h)
+cli_out_h = cli-out.h
+coff_pe_read_h = coff-pe-read.h
+coff_solib_h = coff-solib.h
+command_h = command.h
+complaints_h = complaints.h
+completer_h = completer.h
+cp_abi_h = cp-abi.h
+cp_support_h = cp-support.h $(symtab_h)
+dcache_h = dcache.h
+defs_h = defs.h $(config_h) $(ansidecl_h) $(gdb_locale_h) $(gdb_signals_h) \
+	$(libiberty_h) $(bfd_h) $(ui_file_h) $(xm_h) $(nm_h) $(tm_h) \
+	$(fopen_same_h) $(gdbarch_h)
+dictionary_h = dictionary.h
+disasm_h = disasm.h
+doublest_h = doublest.h $(floatformat_h)
+dummy_frame_h = dummy-frame.h
+dwarf2expr_h = dwarf2expr.h
+dwarf2_frame_h = dwarf2-frame.h
+dwarf2loc_h = dwarf2loc.h
+environ_h = environ.h
+event_loop_h = event-loop.h
+event_top_h = event-top.h
+exec_h = exec.h $(target_h)
+expression_h = expression.h $(symtab_h) $(doublest_h)
+f_lang_h = f-lang.h
+frame_base_h = frame-base.h
+frame_h = frame.h
+frame_unwind_h = frame-unwind.h $(frame_h)
+frv_tdep_h = frv-tdep.h
+gdbarch_h = gdbarch.h
+gdb_assert_h = gdb_assert.h
+gdbcmd_h = gdbcmd.h $(command_h) $(ui_out_h)
+gdbcore_h = gdbcore.h $(bfd_h)
+gdb_curses_h = gdb_curses.h
+gdb_dirent_h = gdb_dirent.h
+gdb_events_h = gdb-events.h
+gdb_h = gdb.h
+gdb_locale_h = gdb_locale.h
+gdb_obstack_h = gdb_obstack.h $(obstack_h)
+gdb_proc_service_h = gdb_proc_service.h $(gregset_h)
+gdb_regex_h = gdb_regex.h $(xregex_h)
+gdb_stabs_h = gdb-stabs.h
+gdb_stat_h = gdb_stat.h
+gdb_string_h = gdb_string.h
+gdb_thread_db_h = gdb_thread_db.h
+gdbthread_h = gdbthread.h $(breakpoint_h) $(frame_h)
+gdbtypes_h = gdbtypes.h
+gdb_vfork_h = gdb_vfork.h
+gdb_wait_h = gdb_wait.h
+glibc_tdep_h = glibc-tdep.h
+gnu_nat_h = gnu-nat.h
+gregset_h = gregset.h
+hppa_tdep_h = hppa-tdep.h
+i386_linux_tdep_h = i386-linux-tdep.h
+i386_tdep_h = i386-tdep.h
+i387_tdep_h = i387-tdep.h
+ia64_tdep_h = ia64-tdep.h
+infcall_h = infcall.h
+inferior_h = inferior.h $(breakpoint_h) $(target_h) $(frame_h)
+inf_loop_h = inf-loop.h
+inflow_h = inflow.h $(terminal_h)
+infttrace_h = infttrace.h $(target_h)
+interps_h = interps.h
+jv_lang_h = jv-lang.h
+kod_h = kod.h
+language_h = language.h
+libunwind_frame_h = libunwind-frame.h $(libunwind_h)
+linespec_h = linespec.h
+linux_nat_h = linux-nat.h $(target_h)
+m2_lang_h = m2-lang.h
+m68k_tdep_h = m68k-tdep.h
+m88k_tdep_h = m88k-tdep.h
+macroexp_h = macroexp.h
+macroscope_h = macroscope.h $(macrotab_h) $(symtab_h)
+macrotab_h = macrotab.h
+main_h = main.h
+memattr_h = memattr.h
+minimon_h = minimon.h
+mipsnbsd_tdep_h = mipsnbsd-tdep.h
+mips_tdep_h = mips-tdep.h
+monitor_h = monitor.h
+nbsd_tdep_h = nbsd-tdep.h
+ns32k_tdep_h = ns32k-tdep.h
+nto_tdep_h = nto-tdep.h $(defs_h) $(solist_h)
+objc_lang_h = objc-lang.h
+objfiles_h = objfiles.h $(gdb_obstack_h) $(symfile_h)
+ocd_h = ocd.h
+osabi_h = osabi.h
+pa64solib_h = pa64solib.h
+parser_defs_h = parser-defs.h $(doublest_h)
+p_lang_h = p-lang.h
+ppcnbsd_tdep_h = ppcnbsd-tdep.h
+ppc_tdep_h = ppc-tdep.h
+proc_utils_h = proc-utils.h
+regcache_h = regcache.h
+reggroups_h = reggroups.h
+regset_h = regset.h
+remote_fileio_h = remote-fileio.h
+remote_h = remote.h
+remote_utils_h = remote-utils.h $(target_h)
+s390_tdep_h = s390-tdep.h
+scm_lang_h = scm-lang.h $(scm_tags_h)
+scm_tags_h = scm-tags.h
+sentinel_frame_h = sentinel-frame.h
+serial_h = serial.h
+ser_unix_h = ser-unix.h
+shnbsd_tdep_h = shnbsd-tdep.h
+sh_tdep_h = sh-tdep.h
+sim_regno_h = sim-regno.h
+solib_h = solib.h
+solib_svr4_h = solib-svr4.h
+solist_h = solist.h
+somsolib_h = somsolib.h
+source_h = source.h
+sparc64_tdep_h = sparc64-tdep.h $(sparc_tdep_h)
+sparc_nat_h = sparc-nat.h
+sparc_tdep_h = sparc-tdep.h
+srec_h = srec.h
+stabsread_h = stabsread.h
+stack_h = stack.h
+symfile_h = symfile.h
+symtab_h = symtab.h
+target_h = target.h $(bfd_h) $(symtab_h) $(dcache_h) $(memattr_h)
+terminal_h = terminal.h
+top_h = top.h
+tracepoint_h = tracepoint.h
+trad_frame_h = trad-frame.h $(frame_h)
+tramp_frame_h = tramp-frame.h
+typeprint_h = typeprint.h
+ui_file_h = ui-file.h
+ui_out_h = ui-out.h
+user_regs_h = user-regs.h
+valprint_h = valprint.h
+value_h = value.h $(doublest_h) $(frame_h) $(symtab_h) $(gdbtypes_h) \
+	$(expression_h)
+varobj_h = varobj.h $(symtab_h) $(gdbtypes_h)
+vax_tdep_h = vax-tdep.h
+version_h = version.h
+wince_stub_h = wince-stub.h
+wrapper_h = wrapper.h $(gdb_h)
+xcoffsolib_h = xcoffsolib.h
+
+#
+# gdb/cli/ headers
+#
+
+cli_cmds_h = $(srcdir)/cli/cli-cmds.h
+cli_decode_h = $(srcdir)/cli/cli-decode.h $(command_h)
+cli_dump_h = $(srcdir)/cli/cli-dump.h
+cli_script_h = $(srcdir)/cli/cli-script.h
+cli_setshow_h = $(srcdir)/cli/cli-setshow.h
+cli_utils_h = $(srcdir)/cli/cli-utils.h
+
+#
+# gdb/mi/ headers
+#
+
+mi_cmds_h = $(srcdir)/mi/mi-cmds.h
+mi_console_h = $(srcdir)/mi/mi-console.h
+mi_getopt_h = $(srcdir)/mi/mi-getopt.h
+mi_main_h = $(srcdir)/mi/mi-main.h
+mi_out_h = $(srcdir)/mi/mi-out.h
+mi_parse_h = $(srcdir)/mi/mi-parse.h
+
+#
+# gdb/tui/ headers
+#
+
+tui_command_h = $(srcdir)/tui/tui-command.h
+tui_data_h = $(srcdir)/tui/tui-data.h $(tui_h) $(gdb_curses_h)
+tui_disasm_h = $(srcdir)/tui/tui-disasm.h $(tui_h) $(tui_data_h)
+tui_file_h = $(srcdir)/tui/tui-file.h
+tui_h = $(srcdir)/tui/tui.h
+tui_hooks_h = $(srcdir)/tui/tui-hooks.h
+tui_io_h = $(srcdir)/tui/tui-io.h
+tui_layout_h = $(srcdir)/tui/tui-layout.h $(tui_h) $(tui_data_h)
+tui_regs_h = $(srcdir)/tui/tui-regs.h $(tui_data_h)
+tui_source_h = $(srcdir)/tui/tui-source.h $(tui_data_h)
+tui_stack_h = $(srcdir)/tui/tui-stack.h
+tui_windata_h = $(srcdir)/tui/tui-windata.h $(tui_data_h)
+tui_wingeneral_h = $(srcdir)/tui/tui-wingeneral.h
+tui_win_h = $(srcdir)/tui/tui-win.h $(tui_data_h)
+tui_winsource_h = $(srcdir)/tui/tui-winsource.h $(tui_data_h)
+
+# Header files that need to have srcdir added.  Note that in the cases
+# where we use a macro like $(gdbcmd_h), things are carefully arranged
+# so that each .h file is listed exactly once (M-x tags-search works
+# wrong if TAGS has files twice).  Because this is tricky to get
+# right, it is probably easiest just to list .h files here directly.
+
+HFILES_NO_SRCDIR = bcache.h buildsym.h call-cmds.h coff-solib.h defs.h \
+	environ.h $(gdbcmd_h) gdb.h gdbcore.h \
+	gdb-stabs.h $(inferior_h) language.h minimon.h monitor.h \
+	objfiles.h parser-defs.h serial.h solib.h \
+	symfile.h symfile-mem.h stabsread.h target.h terminal.h typeprint.h \
+	xcoffsolib.h \
+	macrotab.h macroexp.h macroscope.h \
+	c-lang.h f-lang.h \
+	jv-lang.h \
+	m2-lang.h  p-lang.h \
+	complaints.h valprint.h \
+	vx-share/dbgRpcLib.h vx-share/ptrace.h vx-share/vxTypes.h \
+	vx-share/vxWorks.h vx-share/wait.h vx-share/xdr_ld.h \
+	vx-share/xdr_ptrace.h vx-share/xdr_rdb.h gdbthread.h \
+	dcache.h remote-utils.h top.h somsolib.h
+
+# Header files that already have srcdir in them, or which are in objdir.
+
+HFILES_WITH_SRCDIR = ../bfd/bfd.h
+
+
+# GDB "info" files, which should be included in their entirety
+INFOFILES = gdb.info*
+
+REMOTE_EXAMPLES = m68k-stub.c i386-stub.c sparc-stub.c rem-multi.shar
+
+# {X,T,NAT}DEPFILES are something of a pain in that it's hard to
+# default their values the way we do for SER_HARDWIRE; in the future
+# maybe much of the stuff now in {X,T,NAT}DEPFILES will go into other
+# variables analogous to SER_HARDWIRE which get defaulted in this
+# Makefile.in
+
+DEPFILES = $(TDEPFILES) $(SER_HARDWIRE) $(NATDEPFILES) \
+	   $(REMOTE_OBS) $(SIM_OBS) $(CONFIG_OBS)
+
+SOURCES = $(SFILES) $(ALLDEPFILES) $(YYFILES) $(CONFIG_SRCS)
+# Don't include YYFILES (*.c) because we already include *.y in SFILES,
+# and it's more useful to see it in the .y file.
+TAGFILES_NO_SRCDIR = $(SFILES) $(HFILES_NO_SRCDIR) $(ALLDEPFILES) \
+	$(SUBDIR_CLI_SRCS)
+TAGFILES_WITH_SRCDIR = $(HFILES_WITH_SRCDIR)
+
+COMMON_OBS = $(DEPFILES) $(YYOBJ) \
+	version.o \
+	annotate.o \
+	auxv.o \
+	bfd-target.o \
+	blockframe.o breakpoint.o findvar.o regcache.o \
+	charset.o disasm.o dummy-frame.o \
+	source.o values.o eval.o valops.o valarith.o valprint.o printcmd.o \
+	block.o symtab.o symfile.o symmisc.o linespec.o dictionary.o \
+	infcall.o \
+	infcmd.o infrun.o \
+	expprint.o environ.o stack.o thread.o \
+	interps.o \
+	main.o \
+	macrotab.o macrocmd.o macroexp.o macroscope.o \
+	event-loop.o event-top.o inf-loop.o completer.o \
+	gdbarch.o arch-utils.o gdbtypes.o osabi.o copying.o \
+	memattr.o mem-break.o target.o parse.o language.o buildsym.o \
+	std-regs.o \
+	signals.o \
+	kod.o kod-cisco.o \
+	gdb-events.o \
+	exec.o bcache.o objfiles.o observer.o minsyms.o maint.o demangle.o \
+	dbxread.o coffread.o coff-pe-read.o elfread.o \
+	dwarfread.o dwarf2read.o mipsread.o stabsread.o corefile.o \
+	dwarf2expr.o dwarf2loc.o dwarf2-frame.o \
+	c-lang.o f-lang.o objc-lang.o \
+	ui-out.o cli-out.o \
+	varobj.o wrapper.o \
+	jv-lang.o jv-valprint.o jv-typeprint.o \
+	m2-lang.o p-lang.o p-typeprint.o p-valprint.o \
+	scm-exp.o scm-lang.o scm-valprint.o \
+	sentinel-frame.o \
+	complaints.o typeprint.o \
+	c-typeprint.o f-typeprint.o m2-typeprint.o \
+	c-valprint.o cp-valprint.o f-valprint.o m2-valprint.o \
+	nlmread.o serial.o mdebugread.o top.o utils.o \
+	ui-file.o \
+	user-regs.o \
+	frame.o frame-unwind.o doublest.o \
+	frame-base.o \
+	gnu-v2-abi.o gnu-v3-abi.o hpacc-abi.o cp-abi.o cp-support.o \
+	cp-namespace.o \
+	reggroups.o regset.o \
+	trad-frame.o \
+	tramp-frame.o
+
+TSOBS = inflow.o
+
+SUBDIRS = @subdirs@
+
+# For now, shortcut the "configure GDB for fewer languages" stuff.
+YYFILES = c-exp.c \
+	objc-exp.c \
+	ada-exp.c \
+	jv-exp.c \
+	f-exp.c m2-exp.c p-exp.c
+YYOBJ = c-exp.o \
+	objc-exp.o \
+	jv-exp.o \
+	f-exp.o m2-exp.o p-exp.o
+
+# Things which need to be built when making a distribution.
+
+DISTSTUFF = $(YYFILES)
+
+# Prevent Sun make from putting in the machine type.  Setting
+# TARGET_ARCH to nothing works for SunOS 3, 4.0, but not for 4.1.
+.c.o:
+	$(CC) -c $(INTERNAL_CFLAGS) $<
+
+all: gdb$(EXEEXT) $(CONFIG_ALL)
+	@$(MAKE) $(FLAGS_TO_PASS) DO=all "DODIRS=`echo $(SUBDIRS) | sed 's/testsuite//'`" subdir_do
+.PHONY: all-tui
+all-tui: $(TUI)$(EXEEXT)
+
+installcheck:
+
+# The check target can not use subdir_do, because subdir_do does not
+# use TARGET_FLAGS_TO_PASS.
+check: force
+	@if [ -f testsuite/Makefile ]; then \
+	  rootme=`pwd`; export rootme; \
+	  rootsrc=`cd $(srcdir); pwd`; export rootsrc; \
+	  cd testsuite; \
+	  $(MAKE) $(TARGET_FLAGS_TO_PASS) check; \
+	else true; fi
+
+# The idea is to parallelize testing of multilibs, for example:
+#   make -j3 check//sh-hms-sim/{-m1,-m2,-m3,-m3e,-m4}/{,-nofpu}
+# will run 3 concurrent sessions of check, eventually testing all 10
+# combinations.  GNU make is required for the % pattern to work, as is
+# a shell that expands alternations within braces.  If GNU make is not
+# used, this rule will harmlessly fail to match.
+check//%: force
+	@if [ -f testsuite/config.status ]; then \
+	  rootme=`pwd`; export rootme; \
+	  rootsrc=`cd $(srcdir); pwd`; export rootsrc; \
+	  target=`echo "$@" | sed 's,//.*,,'`; \
+	  variant=`echo "$@" | sed 's,^[^/]*//,,'`; \
+	  vardots=`echo "$$variant" | sed 's,/,.,g'`; \
+	  testdir=testsuite.$$vardots; \
+	  if [ ! -f $$testdir/Makefile ]; then \
+	    (cd testsuite && find . -name config.status) | \
+	    sed s,/config.status$$,, | sort | while read subdir; do \
+	      $(SHELL) $(srcdir)/../mkinstalldirs $$testdir/$$subdir && \
+	      (cd $$testdir/$$subdir && \
+	       $(SHELL) $$rootme/testsuite/$$subdir/config.status \
+		 --recheck && \
+	       $(SHELL) ./config.status); done; \
+	  else :; fi && cd $$testdir && \
+	  $(MAKE) $(TARGET_FLAGS_TO_PASS) \
+	    RUNTESTFLAGS="--target_board=$$variant $(RUNTESTFLAGS)" \
+	    "$$target"; \
+	else true; fi
+
+info dvi install-info clean-info html install-html: force
+	@$(MAKE) $(FLAGS_TO_PASS) DO=$@ "DODIRS=$(SUBDIRS)" subdir_do
+
+gdb.z:gdb.1
+	nroff -man $(srcdir)/gdb.1 | col -b > gdb.t
+	pack gdb.t ; rm -f gdb.t
+	mv gdb.t.z gdb.z
+
+# Traditionally "install" depends on "all".  But it may be useful
+# not to; for example, if the user has made some trivial change to a
+# source file and doesn't care about rebuilding or just wants to save the
+# time it takes for make to check that all is up to date.
+# install-only is intended to address that need.
+install: all install-only
+install-only: $(CONFIG_INSTALL)
+	transformed_name=`t='$(program_transform_name)'; \
+			  echo gdb | sed -e "$$t"` ; \
+		if test "x$$transformed_name" = x; then \
+		  transformed_name=gdb ; \
+		else \
+		  true ; \
+		fi ; \
+		$(SHELL) $(srcdir)/../mkinstalldirs $(DESTDIR)$(bindir) ; \
+		$(INSTALL_PROGRAM) gdb$(EXEEXT) \
+			$(DESTDIR)$(bindir)/$$transformed_name$(EXEEXT) ; \
+		$(SHELL) $(srcdir)/../mkinstalldirs \
+			$(DESTDIR)$(man1dir) ; \
+		$(INSTALL_DATA) $(srcdir)/gdb.1 \
+			$(DESTDIR)$(man1dir)/$$transformed_name.1
+	@$(MAKE) DO=install "DODIRS=$(SUBDIRS)" $(FLAGS_TO_PASS) subdir_do
+.PHONY: install-tui
+install-tui:
+	transformed_name=`t='$(program_transform_name)'; \
+			  echo $(TUI) | sed -e "$$t"` ; \
+		if test "x$$transformed_name" = x; then \
+		  transformed_name=$(TUI) ; \
+		else \
+		  true ; \
+		fi ; \
+		$(SHELL) $(srcdir)/../mkinstalldirs $(DESTDIR)$(bindir) ; \
+		$(INSTALL_PROGRAM) $(TUI)$(EXEEXT) \
+			$(DESTDIR)$(bindir)/$$transformed_name$(EXEEXT) ; \
+		$(SHELL) $(srcdir)/../mkinstalldirs \
+			$(DESTDIR)$(man1dir) ; \
+		$(INSTALL_DATA) $(srcdir)/gdb.1 \
+			$(DESTDIR)$(man1dir)/$$transformed_name.1
+
+
+uninstall: force $(CONFIG_UNINSTALL)
+	transformed_name=`t='$(program_transform_name)'; \
+			  echo gdb | sed -e $$t` ; \
+		if test "x$$transformed_name" = x; then \
+		  transformed_name=gdb ; \
+		else \
+		  true ; \
+		fi ; \
+		rm -f $(DESTDIR)$(bindir)/$$transformed_name$(EXEEXT) \
+		      $(DESTDIR)$(man1dir)/$$transformed_name.1
+	@$(MAKE) DO=uninstall "DODIRS=$(SUBDIRS)" $(FLAGS_TO_PASS) subdir_do
+.PHONY: uninstall-tui
+uninstall-tui:
+	transformed_name=`t='$(program_transform_name)'; \
+			  echo $(TUI) | sed -e $$t` ; \
+		if test "x$$transformed_name" = x; then \
+		  transformed_name=$(TUI) ; \
+		else \
+		  true ; \
+		fi ; \
+		rm -f $(DESTDIR)$(bindir)/$$transformed_name$(EXEEXT) \
+		      $(DESTDIR)$(man1dir)/$$transformed_name.1
+
+# We do this by grepping through sources.  If that turns out to be too slow,
+# maybe we could just require every .o file to have an initialization routine
+# of a given name (top.o -> _initialize_top, etc.).
+#
+# Formatting conventions:  The name of the _initialize_* routines must start
+# in column zero, and must not be inside #if.
+#
+# Note that the set of files with init functions might change, or the names
+# of the functions might change, so this files needs to depend on all the
+# object files that will be linked into gdb.
+
+# FIXME: There is a problem with this approach - init.c may force
+# unnecessary files to be linked in.
+
+# FIXME: cagney/2002-06-09: gdb/564: gdb/563: Force the order so that
+# the first call is to _initialize_gdbtypes (implemented by explicitly
+# putting that function's name first in the init.l-tmp file).  This is
+# a hack to ensure that all the architecture dependant global
+# builtin_type_* variables are initialized before anything else
+# (per-architecture code is called in the same order that it is
+# registered).  The ``correct fix'' is to have all the builtin types
+# made part of the architecture and initialize them on-demand (using
+# gdbarch_data) just like everything else.  The catch is that other
+# modules still take the address of these builtin types forcing them
+# to be variables, sigh!
+
+# NOTE: cagney/2003-03-18: The sed pattern ``s|^\([^ /]...'' is
+# anchored on the first column and excludes the ``/'' character so
+# that it doesn't add the $(srcdir) prefix to any file that already
+# has an absolute path.  It turns out that $(DEC)'s True64 make
+# automatically adds the $(srcdir) prefixes when it encounters files
+# in sub-directories such as cli/ and mi/.
+
+# NOTE: cagney/2004-02-08: The ``case "$$fs" in'' eliminates
+# duplicates.  Files in the gdb/ directory can end up appearing in
+# COMMON_OBS (as a .o file) and CONFIG_SRCS (as a .c file).
+
+INIT_FILES = $(COMMON_OBS) $(TSOBS) $(CONFIG_SRCS)
+init.c: $(INIT_FILES)
+	@echo Making init.c
+	@rm -f init.c-tmp init.l-tmp
+	@touch init.c-tmp
+	@echo gdbtypes > init.l-tmp
+	@-echo $(INIT_FILES) | \
+	tr ' ' '\012' | \
+	sed \
+	    -e '/^gdbtypes.[co]$$/d' \
+	    -e '/^init.[co]$$/d' \
+	    -e '/xdr_ld.[co]$$/d' \
+	    -e '/xdr_ptrace.[co]$$/d' \
+	    -e '/xdr_rdb.[co]$$/d' \
+	    -e '/udr.[co]$$/d' \
+	    -e '/udip2soc.[co]$$/d' \
+	    -e '/udi2go32.[co]$$/d' \
+	    -e '/version.[co]$$/d' \
+	    -e '/^[a-z0-9A-Z_]*_[SU].[co]$$/d' \
+	    -e '/[a-z0-9A-Z_]*-exp.tab.[co]$$/d' \
+	    -e 's/\.[co]$$/.c/' \
+	    -e 's,signals\.c,signals/signals\.c,' \
+	    -e 's|^\([^  /][^     ]*\)|$(srcdir)/\1|g' | \
+	while read f; do \
+	    sed -n -e 's/^_initialize_\([a-z_0-9A-Z]*\).*/\1/p' $$f 2>/dev/null; \
+	done | \
+	while read f; do \
+	    case " $$fs " in \
+	        *" $$f "* ) ;; \
+	        * ) echo $$f ; fs="$$fs $$f";; \
+            esac; \
+	done >> init.l-tmp
+	@echo '/* Do not modify this file.  */' >>init.c-tmp
+	@echo '/* It is created automatically by the Makefile.  */'>>init.c-tmp
+	@echo '#include "defs.h"      /* For initialize_file_ftype.  */' >>init.c-tmp
+	@echo '#include "call-cmds.h" /* For initialize_all_files.  */' >>init.c-tmp
+	@sed -e 's/\(.*\)/extern initialize_file_ftype _initialize_\1;/' <init.l-tmp >>init.c-tmp
+	@echo 'void' >>init.c-tmp
+	@echo 'initialize_all_files (void)' >>init.c-tmp
+	@echo '{' >>init.c-tmp
+	@sed -e 's/\(.*\)/  _initialize_\1 ();/' <init.l-tmp >>init.c-tmp
+	@echo '}' >>init.c-tmp
+	@rm init.l-tmp
+	@mv init.c-tmp init.c
+
+.PRECIOUS: init.c
+
+init.o: init.c $(defs_h) $(call_cmds_h)
+
+# Removing the old gdb first works better if it is running, at least on SunOS.
+gdb$(EXEEXT): gdb.o libgdb.a $(ADD_DEPS) $(CDEPS) $(TDEPLIBS)
+	rm -f gdb$(EXEEXT)
+	$(CC_LD) $(INTERNAL_LDFLAGS) $(WIN32LDAPP) \
+		-o gdb$(EXEEXT) gdb.o libgdb.a \
+		$(TDEPLIBS) $(TUI_LIBRARY) $(CLIBS) $(LOADLIBES)
+
+$(TUI)$(EXEEXT): tui-main.o libgdb.a $(ADD_DEPS) $(CDEPS) $(TDEPLIBS)
+	rm -f $(TUI)$(EXEEXT)
+	$(CC_LD) $(INTERNAL_LDFLAGS) $(WIN32LDAPP) \
+		-o $(TUI)$(EXEEXT) tui-main.o libgdb.a \
+		$(TDEPLIBS) $(TUI_LIBRARY) $(CLIBS) $(LOADLIBES)
+
+nlm:	force
+	rootme=`pwd`; export rootme; $(MAKE) $(TARGET_FLAGS_TO_PASS) DO=all DODIRS=nlm subdir_do
+
+# Create a library of the gdb object files and build GDB by linking
+# against that.
+#
+# init.o is very important.  It pulls in the rest of GDB.
+LIBGDB_OBS= $(COMMON_OBS) $(TSOBS) $(ADD_FILES) init.o
+libgdb.a: $(LIBGDB_OBS)
+	-rm -f libgdb.a
+	$(AR) q libgdb.a $(LIBGDB_OBS)
+	$(RANLIB) libgdb.a
+
+# A Mach 3.0 program to force gdb back to command level
+
+stop-gdb: stop-gdb.o
+	${CC_LD} $(GLOBAL_CFLAGS) $(LDFLAGS) -o stop-gdb \
+	stop-gdb.o $(CLIBS) $(LOADLIBES)
+
+# This is useful when debugging GDB, because some Unix's don't let you run GDB
+# on itself without copying the executable.  So "make gdb1" will make
+# gdb and put a copy in gdb1, and you can run it with "gdb gdb1".
+# Removing gdb1 before the copy is the right thing if gdb1 is open
+# in another process.
+gdb1$(EXEEXT): gdb$(EXEEXT)
+	rm -f gdb1$(EXEEXT)
+	cp gdb$(EXEEXT) gdb1$(EXEEXT)
+
+# FIXME. These are not generated by "make depend" because they only are there
+# for some machines.
+# But these rules don't do what we want; we want to hack the foo.o: tm.h
+# dependency to do the right thing.
+xm-vaxult.h: xm-vax.h
+xm-vaxbsd.h: xm-vax.h
+
+# Put the proper machine-specific files first, so M-. on a machine
+# specific routine gets the one for the correct machine.  (FIXME: those
+# files go in twice; we should be removing them from the main list).
+
+# TAGS depends on all the files that go into it so you can rebuild TAGS
+# with `make TAGS' and not have to say `rm TAGS' first.
+
+TAGS: $(TAGFILES_NO_SRCDIR) $(TAGFILES_WITH_SRCDIR)
+	@echo Making TAGS
+	@etags $(srcdir)/$(TM_FILE) \
+	  $(srcdir)/$(XM_FILE) \
+	  $(srcdir)/$(NAT_FILE) \
+	`(for i in $(DEPFILES) $(TAGFILES_NO_SRCDIR); do \
+		echo $(srcdir)/$$i ; \
+	done ; for i in $(TAGFILES_WITH_SRCDIR); do \
+		echo $$i ; \
+	done) | sed -e 's/\.o$$/\.c/'` \
+	`find $(srcdir)/config -name '*.h' -print`
+
+tags: TAGS
+
+clean mostlyclean: $(CONFIG_CLEAN)
+	@$(MAKE) $(FLAGS_TO_PASS) DO=clean "DODIRS=$(SUBDIRS)" subdir_do
+	rm -f *.o *.a $(ADD_FILES) *~ init.c-tmp init.l-tmp version.c-tmp
+	rm -f init.c version.c
+	rm -f gdb$(EXEEXT) core make.log
+	rm -f gdb[0-9]$(EXEEXT)
+.PHONY: clean-tui
+clean-tui:
+	rm -f $(TUI)$(EXEEXT)
+
+# This used to depend on c-exp.c m2-exp.c TAGS
+# I believe this is wrong; the makefile standards for distclean just
+# describe removing files; the only sort of "re-create a distribution"
+# functionality described is if the distributed files are unmodified.
+# NB: While GDBSERVER might be configured on native systems, it isn't
+# always included in SUBDIRS.  Remove the gdbserver files explictly.
+distclean: clean
+	@$(MAKE) $(FLAGS_TO_PASS) DO=distclean "DODIRS=$(SUBDIRS)" subdir_do
+	rm -f gdbserver/config.status gdbserver/config.log
+	rm -f gdbserver/tm.h gdbserver/xm.h gdbserver/nm.h
+	rm -f gdbserver/Makefile gdbserver/config.cache
+	rm -f nm.h tm.h xm.h config.status config.h stamp-h .gdbinit
+	rm -f y.output yacc.acts yacc.tmp y.tab.h
+	rm -f config.log config.cache
+	rm -f Makefile
+
+maintainer-clean: local-maintainer-clean do-maintainer-clean distclean
+realclean: maintainer-clean
+
+local-maintainer-clean:
+	@echo "This command is intended for maintainers to use;"
+	@echo "it deletes files that may require special tools to rebuild."
+	rm -f c-exp.c \
+		ada-lex.c ada-exp.c \
+	        objc-exp.c \
+		jv-exp.tab \
+		f-exp.c m2-exp.c p-exp.c
+	rm -f TAGS $(INFOFILES)
+	rm -f $(YYFILES)
+	rm -f nm.h tm.h xm.h config.status
+
+do-maintainer-clean:
+	@$(MAKE) $(FLAGS_TO_PASS) DO=maintainer-clean "DODIRS=$(SUBDIRS)" \
+		subdir_do
+
+diststuff: $(DISTSTUFF)
+	cd doc; $(MAKE) $(MFLAGS) diststuff
+
+subdir_do: force
+	@for i in $(DODIRS); do \
+		if [ -f ./$$i/Makefile ] ; then \
+			if (cd ./$$i; \
+				$(MAKE) $(FLAGS_TO_PASS) $(DO)) ; then true ; \
+			else exit 1 ; fi ; \
+		else true ; fi ; \
+	done
+
+Makefile: Makefile.in config.status @frags@
+	$(SHELL) config.status
+
+config.h: stamp-h ; @true
+stamp-h: config.in config.status
+	CONFIG_HEADERS=config.h:config.in $(SHELL) config.status
+
+config.status: configure configure.tgt configure.host
+	$(SHELL) config.status --recheck
+
+force:
+
+# Documentation!
+# GDB QUICK REFERENCE (TeX dvi file, CM fonts)
+doc/refcard.dvi:
+	cd doc; $(MAKE) refcard.dvi $(FLAGS_TO_PASS)
+
+# GDB QUICK REFERENCE (PostScript output, common PS fonts)
+doc/refcard.ps:
+	cd doc; $(MAKE) refcard.ps $(FLAGS_TO_PASS)
+
+# GDB MANUAL: TeX dvi file
+doc/gdb.dvi:
+	cd doc; $(MAKE) gdb.dvi $(FLAGS_TO_PASS)
+
+# GDB MANUAL: info file
+doc/gdb.info:
+	cd doc; $(MAKE) gdb.info $(FLAGS_TO_PASS)
+
+# Make copying.c from COPYING
+$(srcdir)/copying.c: @MAINTAINER_MODE_TRUE@ \
+		$(srcdir)/COPYING $(srcdir)/copying.awk
+	awk -f $(srcdir)/copying.awk \
+		< $(srcdir)/COPYING > $(srcdir)/copying.tmp
+	mv $(srcdir)/copying.tmp $(srcdir)/copying.c
+
+version.c: Makefile version.in
+	rm -f version.c-tmp version.c
+	echo '#include "version.h"' >> version.c-tmp
+	echo 'const char version[] = "'"`sed q ${srcdir}/version.in`"'";' >> version.c-tmp
+	echo 'const char host_name[] = "$(host_alias)";' >> version.c-tmp
+	echo 'const char target_name[] = "$(target_alias)";' >> version.c-tmp
+	mv version.c-tmp version.c
+version.o: version.c $(version_h)
+
+observer.h: observer.sh doc/observer.texi
+	${srcdir}/observer.sh h ${srcdir}/doc/observer.texi observer.h
+
+observer.inc: observer.sh doc/observer.texi
+	${srcdir}/observer.sh inc ${srcdir}/doc/observer.texi observer.inc
+
+lint: $(LINTFILES)
+	$(LINT) $(INCLUDE_CFLAGS) $(LINTFLAGS) $(LINTFILES) \
+	   `echo $(DEPFILES) | sed 's/\.o /\.c /g'`
+
+gdb.cxref: $(SFILES)
+	cxref -I. $(SFILES) >gdb.cxref
+
+force_update:
+
+# GNU Make has an annoying habit of putting *all* the Makefile variables
+# into the environment, unless you include this target as a circumvention.
+# Rumor is that this will be fixed (and this target can be removed)
+# in GNU Make 4.0.
+.NOEXPORT:
+
+# GNU Make 3.63 has a different problem: it keeps tacking command line
+# overrides onto the definition of $(MAKE).  This variable setting
+# will remove them.
+MAKEOVERRIDES=
+
+ALLDEPFILES = \
+	aix-thread.c \
+	alpha-nat.c alphabsd-nat.c \
+	alpha-tdep.c alpha-linux-tdep.c alphabsd-tdep.c alphanbsd-tdep.c \
+	alpha-osf1-tdep.c alphafbsd-tdep.c alpha-mdebug-tdep.c \
+	amd64-nat.c amd64-tdep.c \
+	amd64bsd-nat.c amdfbsd-nat.c amd64fbsd-tdep.c \
+	amd64nbsd-nat.c amd64nbsd-tdep.c \
+	amd64obsd-nat.c amd64obsd-tdep.c \
+	amd64-linux-nat.c amd64-linux-tdep.c \
+	arm-linux-nat.c arm-linux-tdep.c arm-tdep.c \
+	armnbsd-nat.c armnbsd-tdep.c \
+	avr-tdep.c \
+	bsd-kvm.c \
+	coff-solib.c \
+	core-regset.c core-aout.c corelow.c \
+	dcache.c exec.c fork-child.c \
+	glibc-tdep.c \
+	go32-nat.c h8300-tdep.c \
+	hppa-tdep.c hppa-hpux-tdep.c \
+	hppah-nat.c hpread.c \
+	hppa-linux-tdep.c hppa-linux-nat.c \
+	hppabsd-nat.c hppabsd-tdep.c \
+	i386-tdep.c i386v-nat.c i386-linux-nat.c \
+	i386v4-nat.c i386ly-tdep.c i386-cygwin-tdep.c \
+	i386bsd-nat.c i386bsd-tdep.c i386fbsd-nat.c i386fbsd-tdep.c \
+	i386nbsd-nat.c i386nbsd-tdep.c i386obsd-nat.c i386obsd-tdep.c \
+	i387-tdep.c \
+	i386-linux-tdep.c i386-nat.c \
+	i386gnu-nat.c i386gnu-tdep.c \
+	ia64-linux-nat.c ia64-linux-tdep.c ia64-tdep.c \
+	infptrace.c inftarg.c irix4-nat.c irix5-nat.c \
+	libunwind-frame.c \
+	lynx-nat.c m3-nat.c \
+	m68hc11-tdep.c \
+	m68k-tdep.c \
+	m68kbsd-nat.c m68kbsd-tdep.c \
+	m88k-tdep.c m88kbsd-nat.c \
+	mcore-tdep.c \
+	mips-linux-nat.c mips-linux-tdep.c \
+	mips-nat.c \
+	mips-irix-tdep.c \
+	mips-tdep.c mipsm3-nat.c mipsv4-nat.c \
+	mipsnbsd-nat.c mipsnbsd-tdep.c \
+	nbsd-tdep.c \
+	ns32k-tdep.c solib-osf.c \
+	somread.c somsolib.c $(HPREAD_SOURCE) \
+	ppc-sysv-tdep.c ppc-linux-nat.c ppc-linux-tdep.c \
+	ppcnbsd-nat.c ppcnbsd-tdep.c \
+	ppcobsd-nat.c ppcobsd-tdep.c \
+	procfs.c \
+	remote-e7000.c \
+	remote-hms.c remote-m32r-sdi.c remote-mips.c \
+	remote-rdp.c remote-sim.c \
+	remote-st.c remote-utils.c dcache.c \
+	remote-vx.c \
+	rs6000-nat.c rs6000-tdep.c \
+	s390-tdep.c s390-nat.c \
+	ser-go32.c ser-pipe.c ser-tcp.c \
+	sh-tdep.c sh64-tdep.c shnbsd-tdep.c shnbsd-nat.c \
+	solib.c solib-irix.c solib-svr4.c solib-sunos.c \
+	sparc-linux-tdep.c sparc-nat.c sparc-sol2-nat.c sparc-sol2-tdep.c \
+	sparc-tdep.c sparc-sol2-nat.c sparc-sol2-tdep.c sparc64-linux-nat.c \
+	sparc64-linux-tdep.c sparc64-nat.c sparc64-sol2-tdep.c \
+	sparc64-tdep.c sparc64fbsd-nat.c sparc64fbsd-tdep.c \
+	sparc64nbsd-nat.c sparc64nbsd-tdep.c sparc64obsd-tdep.c \
+	sparcnbsd-nat.c sparcnbsd-tdep.c sparcobsd-tdep.c \
+	symm-tdep.c symm-nat.c \
+	vax-tdep.c \
+	vx-share/xdr_ld.c vx-share/xdr_ptrace.c vx-share/xdr_rdb.c \
+	win32-nat.c \
+	xcoffread.c xcoffsolib.c \
+	xstormy16-tdep.c
+
+# Some files need explict build rules (due to -Werror problems) or due
+# to sub-directory fun 'n' games.
+
+# Provide explicit rule/dependency - works for more makes.
+copying.o: $(srcdir)/copying.c
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/copying.c
+
+hpux-thread.o: $(srcdir)/hpux-thread.c
+	$(CC) -c $(INTERNAL_CFLAGS) -I$(srcdir)/osf-share \
+		-I$(srcdir)/osf-share/HP800 -I/usr/include/dce \
+		$(srcdir)/hpux-thread.c
+
+# main.o needs an explicit build rule to get TARGET_SYSTEM_ROOT and BINDIR.
+main.o: main.c
+	$(CC) -c $(INTERNAL_CFLAGS) $(TARGET_SYSTEM_ROOT_DEFINE) \
+		-DBINDIR=\"$(bindir)\" $(srcdir)/main.c
+
+# FIXME: cagney/2003-08-10: "monitor.c" gets -Wformat-nonliteral
+# errors.  It turns out that that is the least of monitor.c's
+# problems.  The function print_vsprintf appears to be using
+# va_arg(long) to extract CORE_ADDR parameters - something that
+# definitly will not work.  "monitor.c" needs to be rewritten so that
+# it doesn't use format strings and instead uses callbacks.
+monitor.o: $(srcdir)/monitor.c
+	$(CC) -c $(INTERNAL_WARN_CFLAGS) $(NO_WERROR_CFLAGS) $(srcdir)/monitor.c
+
+# FIXME: cagney/2003-08-10: Do not try to build "printcmd.c" with
+# -Wformat-nonliteral.  It needs to be overhauled so that it doesn't
+# pass user input strings as the format parameter to host printf
+# function calls.
+printcmd.o: $(srcdir)/printcmd.c
+	$(CC) -c $(INTERNAL_WARN_CFLAGS) $(NO_WERROR_CFLAGS) $(srcdir)/printcmd.c
+
+# FIXME: Procfs.o gets -Wformat errors because things like pid_t don't
+# match output format strings.
+procfs.o: $(srcdir)/procfs.c
+	$(CC) -c $(INTERNAL_WARN_CFLAGS) $(NO_WERROR_CFLAGS) $(srcdir)/procfs.c
+
+# FIXME: Thread-db.o gets warnings because the definitions of the register
+# sets are different from kernel to kernel.
+thread-db.o: $(srcdir)/thread-db.c
+	$(CC) -c $(INTERNAL_WARN_CFLAGS) $(NO_WERROR_CFLAGS) \
+		$(srcdir)/thread-db.c
+
+v850ice.o: $(srcdir)/v850ice.c
+	$(CC) -c $(INTERNAL_CFLAGS) $(IDE_CFLAGS) $(ITCL_CFLAGS) \
+		$(TCL_CFLAGS) $(TK_CFLAGS) $(X11_CFLAGS) \
+		$(GDBTK_CFLAGS) \
+		$(srcdir)/v850ice.c
+
+# FIXME: cagney/2003-08-10: Do not try to build "valprint.c" with
+# -Wformat-nonliteral.  It relies on local_hex_format et.al. and
+# that's a mess.  It needs a serious overhaul.
+valprint.o: $(srcdir)/valprint.c
+	$(CC) -c $(INTERNAL_WARN_CFLAGS) $(NO_WERROR_CFLAGS) $(srcdir)/valprint.c
+
+#
+# YACC/LEX dependencies
+#
+# LANG-exp.c is generated in objdir from LANG-exp.y if it doesn't
+# exist in srcdir, then compiled in objdir to LANG-exp.o.  If we
+# said LANG-exp.c rather than ./c-exp.c some makes would
+# sometimes re-write it into $(srcdir)/c-exp.c.  Remove bogus
+# decls for malloc/realloc/free which conflict with everything else.
+# Strictly speaking c-exp.c should therefore depend on
+# Makefile.in, but that was a pretty big annoyance.
+
+.SUFFIXES: .y .l
+.y.c: 
+	$(SHELL) $(YLWRAP) "$(YACC)" $< y.tab.c $@.tmp -- $(YFLAGS)
+	-sed -e '/extern.*malloc/d' \
+	     -e '/extern.*realloc/d' \
+	     -e '/extern.*free/d' \
+	     -e '/include.*malloc.h/d' \
+	     -e 's/malloc/xmalloc/g' \
+	     -e 's/realloc/xrealloc/g' \
+	     -e '/^#line.*y.tab.c/d' \
+	  < $@.tmp > $@.new
+	-rm $@.tmp
+	mv $@.new ./$*.c
+.l.c:
+	@if [ "$(FLEX)" ] && $(FLEX) --version >/dev/null 2>&1; then \
+	    echo $(FLEX) -Isit $< ">" $@; \
+	    $(FLEX) -Isit $< > $@; \
+	elif [ ! -f $@ -a ! -f $< ]; then \
+	    echo "ada-lex.c missing and flex not available."; \
+	    false; \
+	elif [ ! -f $@ ]; then \
+	    echo "Warning: $*.c older than $*.l and flex not available."; \
+	fi
+
+.PRECIOUS: ada-exp.c ada-lex.c
+.PRECIOUS: c-exp.c
+.PRECIOUS: f-exp.c
+.PRECIOUS: jv-exp.c
+.PRECIOUS: m2-exp.c
+.PRECIOUS: objc-exp.c
+.PRECIOUS: p-exp.c
+
+#
+# gdb/ dependencies
+#
+
+abug-rom.o: abug-rom.c $(defs_h) $(gdbcore_h) $(target_h) $(monitor_h) \
+	$(serial_h) $(regcache_h) $(m68k_tdep_h)
+ada-exp.o: ada-exp.c $(defs_h) $(expression_h) $(value_h) $(parser_defs_h) \
+	$(language_h) $(ada_lang_h) $(bfd_h) $(symfile_h) $(objfiles_h) \
+	$(frame_h) $(block_h) $(ada_lex_c)
+ada-lang.o: ada-lang.c $(gdb_string_h) $(demangle_h) $(defs_h) $(symtab_h) \
+	$(gdbtypes_h) $(gdbcmd_h) $(expression_h) $(parser_defs_h) \
+	$(language_h) $(c_lang_h) $(inferior_h) $(symfile_h) $(objfiles_h) \
+	$(breakpoint_h) $(gdbcore_h) $(ada_lang_h) $(ui_out_h) $(block_h) \
+	$(infcall_h) $(dictionary_h)
+ada-lex.o: ada-lex.c
+ada-tasks.o: ada-tasks.c $(defs_h) $(command_h) $(value_h) $(language_h) \
+	$(inferior_h) $(symtab_h) $(target_h) $(regcache_h) $(gdbcore_h) \
+	$(gregset_h) $(ada_lang_h)
+ada-typeprint.o: ada-typeprint.c $(defs_h) $(gdb_obstack_h) $(bfd_h) \
+	$(symtab_h) $(gdbtypes_h) $(expression_h) $(value_h) $(gdbcore_h) \
+	$(target_h) $(command_h) $(gdbcmd_h) $(language_h) $(demangle_h) \
+	$(c_lang_h) $(typeprint_h) $(ada_lang_h) $(gdb_string_h)
+ada-valprint.o: ada-valprint.c $(defs_h) $(symtab_h) $(gdbtypes_h) \
+	$(expression_h) $(value_h) $(demangle_h) $(valprint_h) $(language_h) \
+	$(annotate_h) $(ada_lang_h) $(c_lang_h) $(infcall_h)
+aix-thread.o: aix-thread.c $(defs_h) $(gdb_assert_h) $(gdbthread_h) \
+	$(target_h) $(inferior_h) $(regcache_h) $(gdbcmd_h) $(language_h) \
+	$(ppc_tdep_h) $(gdb_string_h)
+alphabsd-nat.o: alphabsd-nat.c $(defs_h) $(inferior_h) $(regcache_h) \
+	$(alpha_tdep_h) $(alphabsd_tdep_h) $(gregset_h)
+alphabsd-tdep.o: alphabsd-tdep.c $(defs_h) $(alpha_tdep_h) \
+	$(alphabsd_tdep_h)
+alphafbsd-tdep.o: alphafbsd-tdep.c $(defs_h) $(value_h) $(osabi_h) \
+	$(alpha_tdep_h)
+alpha-linux-tdep.o: alpha-linux-tdep.c $(defs_h) $(frame_h) $(gdb_assert_h) \
+	$(osabi_h) $(alpha_tdep_h)
+alpha-mdebug-tdep.o: alpha-mdebug-tdep.c $(defs_h) $(frame_h) \
+	$(frame_unwind_h) $(frame_base_h) $(symtab_h) $(gdbcore_h) \
+	$(block_h) $(gdb_assert_h) $(alpha_tdep_h)
+alpha-nat.o: alpha-nat.c $(defs_h) $(gdb_string_h) $(inferior_h) \
+	$(gdbcore_h) $(target_h) $(regcache_h) $(alpha_tdep_h) $(gregset_h)
+alphanbsd-tdep.o: alphanbsd-tdep.c $(defs_h) $(gdbcore_h) $(frame_h) \
+	$(regcache_h) $(value_h) $(osabi_h) $(gdb_string_h) $(alpha_tdep_h) \
+	$(alphabsd_tdep_h) $(nbsd_tdep_h) $(solib_svr4_h)
+alpha-osf1-tdep.o: alpha-osf1-tdep.c $(defs_h) $(frame_h) $(gdbcore_h) \
+	$(value_h) $(osabi_h) $(gdb_string_h) $(objfiles_h) $(alpha_tdep_h)
+alpha-tdep.o: alpha-tdep.c $(defs_h) $(doublest_h) $(frame_h) \
+	$(frame_unwind_h) $(frame_base_h) $(dwarf2_frame_h) $(inferior_h) \
+	$(symtab_h) $(value_h) $(gdbcmd_h) $(gdbcore_h) $(dis_asm_h) \
+	$(symfile_h) $(objfiles_h) $(gdb_string_h) $(linespec_h) \
+	$(regcache_h) $(reggroups_h) $(arch_utils_h) $(osabi_h) $(block_h) \
+	$(elf_bfd_h) $(infcall_h) $(alpha_tdep_h)
+amd64bsd-nat.o: amd64bsd-nat.c $(defs_h) $(inferior_h) $(regcache_h) \
+	$(gdb_assert_h) $(amd64_tdep_h) $(amd64_nat_h)
+amd64fbsd-nat.o: amd64fbsd-nat.c $(defs_h) $(inferior_h) $(regcache_h) \
+	$(gdb_assert_h) $(amd64_tdep_h) $(amd64_nat_h)
+amd64fbsd-tdep.o: amd64fbsd-tdep.c $(defs_h) $(arch_utils_h) $(frame_h) \
+	$(gdbcore_h) $(regcache_h) $(osabi_h) $(gdb_string_h) \
+	$(amd64_tdep_h) $(solib_svr4_h)
+amd64-linux-nat.o: amd64-linux-nat.c $(defs_h) $(inferior_h) $(gdbcore_h) \
+	$(regcache_h) $(linux_nat_h) $(gdb_assert_h) $(gdb_string_h) \
+	$(gdb_proc_service_h) $(gregset_h) $(amd64_tdep_h) \
+	$(i386_linux_tdep_h) $(amd64_nat_h)
+amd64-linux-tdep.o: amd64-linux-tdep.c $(defs_h) $(frame_h) $(gdbcore_h) \
+	$(regcache_h) $(osabi_h) $(symtab_h) $(gdb_string_h) \
+	$(amd64_tdep_h) $(solib_svr4_h)
+amd64-nat.o: amd64-nat.c $(defs_h) $(gdbarch_h) $(regcache_h) \
+	$(gdb_assert_h) $(gdb_string_h) $(i386_tdep_h) $(amd64_tdep_h)
+amd64nbsd-nat.o: amd64nbsd-nat.c $(defs_h) $(gdb_assert_h) $(amd64_tdep_h) \
+	$(amd64_nat_h)
+amd64nbsd-tdep.o: amd64nbsd-tdep.c $(defs_h) $(arch_utils_h) $(frame_h) \
+	$(gdbcore_h) $(osabi_h) $(symtab_h) $(gdb_assert_h) $(amd64_tdep_h) \
+	$(nbsd_tdep_h) $(solib_svr4_h)
+amd64obsd-nat.o: amd64obsd-nat.c $(defs_h) $(gdbcore_h) $(regcache_h) \
+	$(gdb_assert_h) $(amd64_tdep_h) $(amd64_nat_h) $(bsd_kvm_h)
+amd64obsd-tdep.o: amd64obsd-tdep.c $(defs_h) $(frame_h) $(gdbcore_h) \
+	$(symtab_h) $(objfiles_h) $(osabi_h) $(regset_h) $(target_h) \
+	$(gdb_assert_h) $(gdb_string_h) $(amd64_tdep_h) $(i387_tdep_h) \
+	$(solib_svr4_h)
+amd64-tdep.o: amd64-tdep.c $(defs_h) $(arch_utils_h) $(block_h) \
+	$(dummy_frame_h) $(frame_h) $(frame_base_h) $(frame_unwind_h) \
+	$(inferior_h) $(gdbcmd_h) $(gdbcore_h) $(objfiles_h) $(regcache_h) \
+	$(regset_h) $(symfile_h) $(gdb_assert_h) $(amd64_tdep_h) \
+	$(i387_tdep_h)
+annotate.o: annotate.c $(defs_h) $(annotate_h) $(value_h) $(target_h) \
+	$(gdbtypes_h) $(breakpoint_h)
+arch-utils.o: arch-utils.c $(defs_h) $(arch_utils_h) $(buildsym_h) \
+	$(gdbcmd_h) $(inferior_h) $(gdb_string_h) $(regcache_h) \
+	$(gdb_assert_h) $(sim_regno_h) $(osabi_h) $(version_h) \
+	$(floatformat_h) $(gdbcore_h)
+arm-linux-nat.o: arm-linux-nat.c $(defs_h) $(inferior_h) $(gdbcore_h) \
+	$(gdb_string_h) $(regcache_h) $(arm_tdep_h) $(gregset_h)
+arm-linux-tdep.o: arm-linux-tdep.c $(defs_h) $(target_h) $(value_h) \
+	$(gdbtypes_h) $(floatformat_h) $(gdbcore_h) $(frame_h) $(regcache_h) \
+	$(doublest_h) $(solib_svr4_h) $(osabi_h) $(arm_tdep_h) \
+	$(glibc_tdep_h)
+armnbsd-nat.o: armnbsd-nat.c $(defs_h) $(arm_tdep_h) $(inferior_h) \
+	$(regcache_h) $(gdbcore_h)
+armnbsd-tdep.o: armnbsd-tdep.c $(defs_h) $(osabi_h) $(gdb_string_h) \
+	$(arm_tdep_h) $(nbsd_tdep_h) $(solib_svr4_h)
+arm-tdep.o: arm-tdep.c $(defs_h) $(frame_h) $(inferior_h) $(gdbcmd_h) \
+	$(gdbcore_h) $(gdb_string_h) $(dis_asm_h) $(regcache_h) \
+	$(doublest_h) $(value_h) $(arch_utils_h) $(osabi_h) \
+	$(frame_unwind_h) $(frame_base_h) $(trad_frame_h) $(arm_tdep_h) \
+	$(gdb_sim_arm_h) $(elf_bfd_h) $(coff_internal_h) $(elf_arm_h) \
+	$(gdb_assert_h) $(bfd_in2_h) $(libcoff_h)
+auxv.o: auxv.c $(defs_h) $(target_h) $(gdbtypes_h) $(command_h) \
+	$(inferior_h) $(valprint_h) $(gdb_assert_h) $(auxv_h) \
+	$(elf_common_h)
+avr-tdep.o: avr-tdep.c $(defs_h) $(frame_h) $(frame_unwind_h) \
+	$(frame_base_h) $(trad_frame_h) $(gdbcmd_h) $(gdbcore_h) \
+	$(inferior_h) $(symfile_h) $(arch_utils_h) $(regcache_h) \
+	$(gdb_string_h) $(dis_asm_h)
+ax-gdb.o: ax-gdb.c $(defs_h) $(symtab_h) $(symfile_h) $(gdbtypes_h) \
+	$(value_h) $(expression_h) $(command_h) $(gdbcmd_h) $(frame_h) \
+	$(target_h) $(ax_h) $(ax_gdb_h) $(gdb_string_h) $(block_h) \
+	$(regcache_h)
+ax-general.o: ax-general.c $(defs_h) $(ax_h) $(value_h) $(gdb_string_h)
+bcache.o: bcache.c $(defs_h) $(gdb_obstack_h) $(bcache_h) $(gdb_string_h) \
+	$(gdb_assert_h)
+bfd-target.o: bfd-target.c $(defs_h) $(target_h) $(bfd_target_h) \
+	$(gdb_assert_h) $(gdb_string_h)
+block.o: block.c $(defs_h) $(block_h) $(symtab_h) $(symfile_h) \
+	$(gdb_obstack_h) $(cp_support_h)
+blockframe.o: blockframe.c $(defs_h) $(symtab_h) $(bfd_h) $(objfiles_h) \
+	$(frame_h) $(gdbcore_h) $(value_h) $(target_h) $(inferior_h) \
+	$(annotate_h) $(regcache_h) $(gdb_assert_h) $(dummy_frame_h) \
+	$(command_h) $(gdbcmd_h) $(block_h)
+breakpoint.o: breakpoint.c $(defs_h) $(symtab_h) $(frame_h) $(breakpoint_h) \
+	$(gdbtypes_h) $(expression_h) $(gdbcore_h) $(gdbcmd_h) $(value_h) \
+	$(command_h) $(inferior_h) $(gdbthread_h) $(target_h) $(language_h) \
+	$(gdb_string_h) $(demangle_h) $(annotate_h) $(symfile_h) \
+	$(objfiles_h) $(source_h) $(linespec_h) $(completer_h) $(gdb_h) \
+	$(ui_out_h) $(cli_script_h) $(gdb_assert_h) $(block_h) \
+	$(gdb_events_h)
+bsd-kvm.o: bsd-kvm.c $(defs_h) $(cli_cmds.h) $(command_h) $(value_h) \
+	$(frame_h) $(regcache_h) $(target_h) $(gdb_assert_h) $(readline_h) \
+	$(bsd_kvm_h)
+buildsym.o: buildsym.c $(defs_h) $(bfd_h) $(gdb_obstack_h) $(symtab_h) \
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+	$(symfile_h) $(gdb_string_h) $(gregset_h)
+somread.o: somread.c $(defs_h) $(bfd_h) $(symtab_h) $(symfile_h) \
+	$(objfiles_h) $(buildsym_h) $(stabsread_h) $(gdb_stabs_h) \
+	$(complaints_h) $(gdb_string_h) $(demangle_h) $(som_h) $(libhppa_h)
+somsolib.o: somsolib.c $(defs_h) $(frame_h) $(bfd_h) $(som_h) $(libhppa_h) \
+	$(gdbcore_h) $(symtab_h) $(breakpoint_h) $(symfile_h) $(objfiles_h) \
+	$(inferior_h) $(gdb_stabs_h) $(gdb_stat_h) $(gdbcmd_h) $(language_h) \
+	$(regcache_h) $(gdb_assert_h) $(exec_h) $(hppa_tdep_h)
+source.o: source.c $(defs_h) $(symtab_h) $(expression_h) $(language_h) \
+	$(command_h) $(source_h) $(gdbcmd_h) $(frame_h) $(value_h) \
+	$(gdb_string_h) $(gdb_stat_h) $(gdbcore_h) $(gdb_regex_h) \
+	$(symfile_h) $(objfiles_h) $(annotate_h) $(gdbtypes_h) $(linespec_h) \
+	$(filenames_h) $(completer_h) $(ui_out_h) $(readline_h)
+sparc64fbsd-nat.o: sparc64fbsd-nat.c $(defs_h) $(sparc64_tdep_h) \
+	$(sparc_nat_h)
+sparc64fbsd-tdep.o: sparc64fbsd-tdep.c $(defs_h) $(frame_h) \
+	$(frame_unwind_h) $(gdbcore_h) $(osabi_h) $(regcache_h) $(regset_h) \
+	$(target_h) $(trad_frame_h) $(gdb_assert_h) $(gdb_string_h) \
+	$(sparc64_tdep_h)
+sparc64-linux-nat.o: sparc64-linux-nat.c $(defs_h) $(sparc64_tdep_h) \
+	$(sparc_nat_h)
+sparc64-linux-tdep.o: sparc64-linux-tdep.c $(defs_h) $(gdbarch_h) $(osabi_h) \
+	$(solib_svr4_h) $(sparc64_tdep_h)
+sparc64-nat.o: sparc64-nat.c $(defs_h) $(gdbarch_h) $(sparc64_tdep_h) \
+	$(sparc_nat_h)
+sparc64nbsd-nat.o: sparc64nbsd-nat.c $(defs_h) $(sparc64_tdep_h) \
+	$(sparc_nat_h)
+sparc64nbsd-tdep.o: sparc64nbsd-tdep.c $(defs_h) $(frame_h) \
+	$(frame_unwind_h) $(gdbcore_h) $(osabi_h) $(regcache_h) $(regset_h) \
+	$(symtab_h) $(solib_svr4_h) $(trad_frame_h) $(gdb_assert_h) \
+	$(gdb_string_h) $(sparc64_tdep_h) $(nbsd_tdep_h)
+sparc64obsd-tdep.o: sparc64obsd-tdep.c $(defs_h) $(frame_h) \
+	$(frame_unwind_h) $(osabi_h) $(regset_h) $(symtab_h) $(solib_svr4_h) \
+	$(trad_frame_h) $(gdb_assert_h) $(sparc64_tdep_h) $(nbsd_tdep_h)
+sparc64-sol2-tdep.o: sparc64-sol2-tdep.c $(defs_h) $(frame_h) \
+	$(frame_unwind_h) $(gdbarch_h) $(symtab_h) $(objfiles_h) $(osabi_h) \
+	$(trad_frame_h) $(gdb_assert_h) $(sparc64_tdep_h) $(solib_svr4_h)
+sparc64-tdep.o: sparc64-tdep.c $(defs_h) $(arch_utils_h) $(floatformat_h) \
+	$(frame_h) $(frame_base_h) $(frame_unwind_h) $(gdbcore_h) \
+	$(gdbtypes_h) $(inferior_h) $(symtab_h) $(objfiles_h) $(osabi_h) \
+	$(regcache_h) $(target_h) $(value_h) $(gdb_assert_h) $(gdb_string_h) \
+	$(sparc64_tdep_h)
+sparc-linux-tdep.o: sparc-linux-tdep.c $(defs_h) $(floatformat_h) $(frame_h) \
+	$(frame_unwind_h) $(gdbarch_h) $(gdbcore_h) $(osabi_h) $(regcache_h) \
+	$(solib_svr4_h) $(symtab_h) $(trad_frame_h) $(gdb_assert_h) \
+	$(gdb_string_h) $(sparc_tdep_h)
+sparc-nat.o: sparc-nat.c $(defs_h) $(inferior_h) $(regcache_h) $(target_h) \
+	$(gdb_assert_h) $(gdb_string_h) $(gdb_wait_h) $(sparc_tdep_h) \
+	$(sparc_nat_h)
+sparcnbsd-nat.o: sparcnbsd-nat.c $(defs_h) $(gdbcore_h) $(regcache_h) \
+	$(sparc_tdep_h) $(sparc_nat_h) $(bsd_kvm_h)
+sparcnbsd-tdep.o: sparcnbsd-tdep.c $(defs_h) $(floatformat_h) $(frame_h) \
+	$(frame_unwind_h) $(gdbcore_h) $(osabi_h) $(regcache_h) $(regset_h) \
+	$(solib_svr4_h) $(symtab_h) $(trad_frame_h) $(gdb_assert_h) \
+	$(gdb_string_h) $(sparc_tdep_h) $(nbsd_tdep_h)
+sparcobsd-tdep.o: sparcobsd-tdep.c $(defs_h) $(floatformat_h) $(frame_h) \
+	$(frame_unwind_h) $(osabi_h) $(solib_svr4_h) $(symtab_h) \
+	$(trad_frame_h) $(gdb_assert_h) $(sparc_tdep_h) $(nbsd_tdep_h)
+sparc-sol2-nat.o: sparc-sol2-nat.c $(defs_h) $(regcache_h) $(gregset_h) \
+	$(sparc_tdep_h) $(sparc64_tdep_h)
+sparc-sol2-tdep.o: sparc-sol2-tdep.c $(defs_h) $(frame_h) $(frame_unwind_h) \
+	$(gdbcore_h) $(symtab_h) $(objfiles_h) $(osabi_h) $(regcache_h) \
+	$(target_h) $(trad_frame_h) $(gdb_assert_h) $(gdb_string_h) \
+	$(sparc_tdep_h) $(solib_svr4_h)
+sparc-stub.o: sparc-stub.c
+sparc-tdep.o: sparc-tdep.c $(defs_h) $(arch_utils_h) $(dis_asm_h) \
+	$(floatformat_h) $(frame_h) $(frame_base_h) $(frame_unwind_h) \
+	$(gdbcore_h) $(gdbtypes_h) $(inferior_h) $(symtab_h) $(objfiles_h) \
+	$(osabi_h) $(regcache_h) $(target_h) $(value_h) $(gdb_assert_h) \
+	$(gdb_string_h) $(sparc_tdep_h)
+stabsread.o: stabsread.c $(defs_h) $(gdb_string_h) $(bfd_h) $(gdb_obstack_h) \
+	$(symtab_h) $(gdbtypes_h) $(expression_h) $(symfile_h) $(objfiles_h) \
+	$(aout_stab_gnu_h) $(libaout_h) $(aout_aout64_h) $(gdb_stabs_h) \
+	$(buildsym_h) $(complaints_h) $(demangle_h) $(language_h) \
+	$(doublest_h) $(cp_abi_h) $(cp_support_h) $(stabsread_h)
+stack.o: stack.c $(defs_h) $(gdb_string_h) $(value_h) $(symtab_h) \
+	$(gdbtypes_h) $(expression_h) $(language_h) $(frame_h) $(gdbcmd_h) \
+	$(gdbcore_h) $(target_h) $(source_h) $(breakpoint_h) $(demangle_h) \
+	$(inferior_h) $(annotate_h) $(ui_out_h) $(block_h) $(stack_h) \
+	$(gdb_assert_h) $(dictionary_h) $(reggroups_h) $(regcache_h)
+standalone.o: standalone.c $(gdb_stat_h) $(defs_h) $(symtab_h) $(frame_h) \
+	$(inferior_h) $(gdb_wait_h)
+std-regs.o: std-regs.c $(defs_h) $(user_regs_h) $(frame_h) $(gdbtypes_h) \
+	$(value_h) $(gdb_string_h)
+stop-gdb.o: stop-gdb.c $(defs_h)
+symfile.o: symfile.c $(defs_h) $(bfdlink_h) $(symtab_h) $(gdbtypes_h) \
+	$(gdbcore_h) $(frame_h) $(target_h) $(value_h) $(symfile_h) \
+	$(objfiles_h) $(source_h) $(gdbcmd_h) $(breakpoint_h) $(language_h) \
+	$(complaints_h) $(demangle_h) $(inferior_h) $(filenames_h) \
+	$(gdb_stabs_h) $(gdb_obstack_h) $(completer_h) $(bcache_h) \
+	$(hashtab_h) $(readline_h) $(gdb_assert_h) $(block_h) \
+	$(gdb_string_h) $(gdb_stat_h)
+symfile-mem.o: symfile-mem.c $(defs_h) $(symtab_h) $(gdbcore_h) \
+	$(objfiles_h) $(gdbcmd_h) $(target_h) $(value_h) $(symfile_h)
+symmisc.o: symmisc.c $(defs_h) $(symtab_h) $(gdbtypes_h) $(bfd_h) \
+	$(symfile_h) $(objfiles_h) $(breakpoint_h) $(command_h) \
+	$(gdb_obstack_h) $(language_h) $(bcache_h) $(block_h) $(gdb_regex_h) \
+	$(dictionary_h) $(gdb_string_h) $(readline_h)
+symtab.o: symtab.c $(defs_h) $(symtab_h) $(gdbtypes_h) $(gdbcore_h) \
+	$(frame_h) $(target_h) $(value_h) $(symfile_h) $(objfiles_h) \
+	$(gdbcmd_h) $(call_cmds_h) $(gdb_regex_h) $(expression_h) \
+	$(language_h) $(demangle_h) $(inferior_h) $(linespec_h) $(source_h) \
+	$(filenames_h) $(objc_lang_h) $(hashtab_h) $(gdb_obstack_h) \
+	$(block_h) $(dictionary_h) $(gdb_string_h) $(gdb_stat_h) $(cp_abi_h)
+target.o: target.c $(defs_h) $(gdb_string_h) $(target_h) $(gdbcmd_h) \
+	$(symtab_h) $(inferior_h) $(bfd_h) $(symfile_h) $(objfiles_h) \
+	$(gdb_wait_h) $(dcache_h) $(regcache_h) $(gdb_assert_h) $(gdbcore_h)
+thread.o: thread.c $(defs_h) $(symtab_h) $(frame_h) $(inferior_h) \
+	$(environ_h) $(value_h) $(target_h) $(gdbthread_h) $(command_h) \
+	$(gdbcmd_h) $(regcache_h) $(gdb_h) $(gdb_string_h) $(ui_out_h)
+thread-db.o: thread-db.c $(defs_h) $(gdb_assert_h) $(gdb_proc_service_h) \
+	$(gdb_thread_db_h) $(bfd_h) $(gdbthread_h) $(inferior_h) \
+	$(symfile_h) $(objfiles_h) $(target_h) $(regcache_h) $(solib_svr4_h)
+top.o: top.c $(defs_h) $(gdbcmd_h) $(call_cmds_h) $(cli_cmds_h) \
+	$(cli_script_h) $(cli_setshow_h) $(cli_decode_h) $(symtab_h) \
+	$(inferior_h) $(target_h) $(breakpoint_h) $(gdbtypes_h) \
+	$(expression_h) $(value_h) $(language_h) $(terminal_h) $(annotate_h) \
+	$(completer_h) $(top_h) $(version_h) $(serial_h) $(doublest_h) \
+	$(gdb_assert_h) $(readline_h) $(readline_history_h) $(event_top_h) \
+	$(gdb_string_h) $(gdb_stat_h) $(ui_out_h) $(cli_out_h)
+tracepoint.o: tracepoint.c $(defs_h) $(symtab_h) $(frame_h) $(gdbtypes_h) \
+	$(expression_h) $(gdbcmd_h) $(value_h) $(target_h) $(language_h) \
+	$(gdb_string_h) $(inferior_h) $(tracepoint_h) $(remote_h) \
+	$(linespec_h) $(regcache_h) $(completer_h) $(gdb_events_h) \
+	$(block_h) $(dictionary_h) $(ax_h) $(ax_gdb_h) $(readline_h) \
+	$(readline_history_h)
+trad-frame.o: trad-frame.c $(defs_h) $(frame_h) $(trad_frame_h) \
+	$(regcache_h)
+tramp-frame.o: tramp-frame.c $(defs_h) $(tramp_frame_h) $(frame_unwind_h) \
+	$(gdbcore_h) $(symtab_h) $(objfiles_h) $(target_h) $(trad_frame_h) \
+	$(frame_base_h)
+typeprint.o: typeprint.c $(defs_h) $(gdb_obstack_h) $(bfd_h) $(symtab_h) \
+	$(gdbtypes_h) $(expression_h) $(value_h) $(gdbcore_h) $(command_h) \
+	$(gdbcmd_h) $(target_h) $(language_h) $(cp_abi_h) $(typeprint_h) \
+	$(gdb_string_h)
+ui-file.o: ui-file.c $(defs_h) $(ui_file_h) $(gdb_string_h)
+ui-out.o: ui-out.c $(defs_h) $(gdb_string_h) $(expression_h) $(language_h) \
+	$(ui_out_h) $(gdb_assert_h)
+user-regs.o: user-regs.c $(defs_h) $(user_regs_h) $(gdbtypes_h) \
+	$(gdb_string_h) $(gdb_assert_h) $(frame_h)
+utils.o: utils.c $(defs_h) $(gdb_assert_h) $(gdb_string_h) $(event_top_h) \
+	$(tui_h) $(gdbcmd_h) $(serial_h) $(bfd_h) $(target_h) $(demangle_h) \
+	$(expression_h) $(language_h) $(charset_h) $(annotate_h) \
+	$(filenames_h) $(inferior_h) $(readline_h)
+uw-thread.o: uw-thread.c $(defs_h) $(gdbthread_h) $(target_h) $(inferior_h) \
+	$(regcache_h) $(gregset_h)
+v850ice.o: v850ice.c $(defs_h) $(gdb_string_h) $(frame_h) $(symtab_h) \
+	$(inferior_h) $(breakpoint_h) $(symfile_h) $(target_h) $(objfiles_h) \
+	$(gdbcore_h) $(value_h) $(command_h) $(regcache_h)
+v850-tdep.o: v850-tdep.c $(defs_h) $(frame_h) $(inferior_h) $(target_h) \
+	$(value_h) $(bfd_h) $(gdb_string_h) $(gdbcore_h) $(objfiles_h) \
+	$(arch_utils_h) $(regcache_h) $(symtab_h) $(dis_asm_h)
+valarith.o: valarith.c $(defs_h) $(value_h) $(symtab_h) $(gdbtypes_h) \
+	$(expression_h) $(target_h) $(language_h) $(gdb_string_h) \
+	$(doublest_h) $(infcall_h)
+valops.o: valops.c $(defs_h) $(symtab_h) $(gdbtypes_h) $(value_h) $(frame_h) \
+	$(inferior_h) $(gdbcore_h) $(target_h) $(demangle_h) $(language_h) \
+	$(gdbcmd_h) $(regcache_h) $(cp_abi_h) $(block_h) $(infcall_h) \
+	$(dictionary_h) $(cp_support_h) $(gdb_string_h) $(gdb_assert_h) \
+	$(cp_support_h) $(observer_h)
+valprint.o: valprint.c $(defs_h) $(gdb_string_h) $(symtab_h) $(gdbtypes_h) \
+	$(value_h) $(gdbcore_h) $(gdbcmd_h) $(target_h) $(language_h) \
+	$(annotate_h) $(valprint_h) $(floatformat_h) $(doublest_h)
+values.o: values.c $(defs_h) $(gdb_string_h) $(symtab_h) $(gdbtypes_h) \
+	$(value_h) $(gdbcore_h) $(command_h) $(gdbcmd_h) $(target_h) \
+	$(language_h) $(scm_lang_h) $(demangle_h) $(doublest_h) \
+	$(gdb_assert_h) $(regcache_h) $(block_h)
+varobj.o: varobj.c $(defs_h) $(value_h) $(expression_h) $(frame_h) \
+	$(language_h) $(wrapper_h) $(gdbcmd_h) $(gdb_string_h) $(varobj_h)
+vax-tdep.o: vax-tdep.c $(defs_h) $(arch_utils_h) $(dis_asm_h) $(frame_h) \
+	$(frame_base_h) $(frame_unwind_h) $(gdbcore_h) $(osabi_h) \
+	$(regcache_h) $(regset_h) $(value_h) $(trad_frame_h) \
+	$(gdb_string_h) $(vax_tdep_h)
+vaxbsd-nat.o: vaxbsd-nat.c $(defs_h) $(inferior_h) $(regcache_h) $(vax_tdep_h)
+vaxnbsd-tdep.o: vaxnbsd-tdep.c $(defs_h) $(arch_utils_h) $(osabi_h) \
+	$(vax_tdep_h) $(solib_svr4_h) $(gdb_string_h)
+win32-nat.o: win32-nat.c $(defs_h) $(frame_h) $(inferior_h) $(target_h) \
+	$(gdbcore_h) $(command_h) $(completer_h) $(regcache_h) $(top_h) \
+	$(buildsym_h) $(symfile_h) $(objfiles_h) $(gdb_string_h) \
+	$(gdbthread_h) $(gdbcmd_h) $(exec_h) $(i386_tdep_h) $(i387_tdep_h)
+wince.o: wince.c $(defs_h) $(frame_h) $(inferior_h) $(target_h) $(gdbcore_h) \
+	$(command_h) $(buildsym_h) $(symfile_h) $(objfiles_h) \
+	$(gdb_string_h) $(gdbthread_h) $(gdbcmd_h) $(wince_stub_h) \
+	$(regcache_h) $(mips_tdep_h)
+wince-stub.o: wince-stub.c $(wince_stub_h)
+wrapper.o: wrapper.c $(defs_h) $(value_h) $(wrapper_h)
+xcoffread.o: xcoffread.c $(defs_h) $(bfd_h) $(gdb_string_h) $(gdb_stat_h) \
+	$(coff_internal_h) $(libcoff_h) $(coff_xcoff_h) $(libxcoff_h) \
+	$(coff_rs6000_h) $(symtab_h) $(gdbtypes_h) $(symfile_h) \
+	$(objfiles_h) $(buildsym_h) $(stabsread_h) $(expression_h) \
+	$(complaints_h) $(gdb_stabs_h) $(aout_stab_gnu_h)
+xcoffsolib.o: xcoffsolib.c $(defs_h) $(bfd_h) $(xcoffsolib_h) $(inferior_h) \
+	$(gdbcmd_h) $(symfile_h) $(frame_h) $(gdb_regex_h)
+xstormy16-tdep.o: xstormy16-tdep.c $(defs_h) $(value_h) $(inferior_h) \
+	$(arch_utils_h) $(regcache_h) $(gdbcore_h) $(objfiles_h) \
+	$(dis_asm_h)
+
+#
+# gdb/cli/ dependencies
+#
+# Need to explicitly specify the compile rule as make will do nothing
+# or try to compile the object file into the sub-directory.
+
+cli-cmds.o: $(srcdir)/cli/cli-cmds.c $(defs_h) $(readline_h) \
+	$(readline_tilde_h) $(completer_h) $(target_h) $(gdb_wait_h) \
+	$(gdb_regex_h) $(gdb_string_h) $(gdb_vfork_h) $(linespec_h) \
+	$(expression_h) $(frame_h) $(value_h) $(language_h) $(filenames_h) \
+	$(objfiles_h) $(source_h) $(disasm_h) $(ui_out_h) $(top_h) \
+	$(cli_decode_h) $(cli_script_h) $(cli_setshow_h) $(cli_cmds_h) \
+	$(tui_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/cli/cli-cmds.c
+cli-decode.o: $(srcdir)/cli/cli-decode.c $(defs_h) $(symtab_h) \
+	$(gdb_regex_h) $(gdb_string_h) $(ui_out_h) $(cli_cmds_h) \
+	$(cli_decode_h) $(tui_h) $(gdb_assert_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/cli/cli-decode.c
+cli-dump.o: $(srcdir)/cli/cli-dump.c $(defs_h) $(gdb_string_h) \
+	$(cli_decode_h) $(cli_cmds_h) $(value_h) $(completer_h) \
+	$(cli_dump_h) $(gdb_assert_h) $(target_h) $(readline_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/cli/cli-dump.c
+cli-interp.o: $(srcdir)/cli/cli-interp.c $(defs_h) $(interps_h) $(wrapper_h) \
+	$(event_top_h) $(ui_out_h) $(cli_out_h) $(top_h) $(gdb_string_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/cli/cli-interp.c
+cli-logging.o: $(srcdir)/cli/cli-logging.c $(defs_h) $(gdbcmd_h) $(ui_out_h) \
+	$(gdb_string_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/cli/cli-logging.c
+cli-script.o: $(srcdir)/cli/cli-script.c $(defs_h) $(value_h) $(language_h) \
+	$(ui_out_h) $(gdb_string_h) $(top_h) $(cli_cmds_h) $(cli_decode_h) \
+	$(cli_script_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/cli/cli-script.c
+cli-setshow.o: $(srcdir)/cli/cli-setshow.c $(defs_h) $(readline_tilde_h) \
+	$(value_h) $(gdb_string_h) $(ui_out_h) $(cli_decode_h) $(cli_cmds_h) \
+	$(cli_setshow_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/cli/cli-setshow.c
+cli-utils.o: $(srcdir)/cli/cli-utils.c $(defs_h) $(cli_utils_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/cli/cli-utils.c
+
+#
+# GDBTK sub-directory
+#
+# Need to explicitly specify the compile rule as make will do nothing
+# or try to compile the object file into the mi directory.
+
+all-gdbtk: insight$(EXEEXT)
+
+install-gdbtk:
+	transformed_name=`t='$(program_transform_name)'; \
+		  echo insight | sed -e $$t` ; \
+	if test "x$$transformed_name" = x; then \
+	  transformed_name=insight ; \
+	else \
+	  true ; \
+	fi ; \
+	$(SHELL) $(srcdir)/../mkinstalldirs $(DESTDIR)$(bindir); \
+	$(INSTALL_PROGRAM) insight$(EXEEXT) \
+		$(DESTDIR)$(bindir)/$$transformed_name$(EXEEXT) ; \
+	$(SHELL) $(srcdir)/../mkinstalldirs \
+		$(DESTDIR)$(GDBTK_LIBRARY) ; \
+	$(SHELL) $(srcdir)/../mkinstalldirs \
+		$(DESTDIR)$(libdir)/insight$(GDBTK_VERSION) ; \
+	$(INSTALL_DATA) $(srcdir)/gdbtk/plugins/plugins.tcl \
+		$(DESTDIR)$(libdir)/insight$(GDBTK_VERSION)/plugins.tcl ; \
+	$(SHELL) $(srcdir)/../mkinstalldirs \
+		$(DESTDIR)$(GDBTK_LIBRARY)/images \
+		$(DESTDIR)$(GDBTK_LIBRARY)/images2 ; \
+	$(SHELL) $(srcdir)/../mkinstalldirs \
+		$(DESTDIR)$(GDBTK_LIBRARY)/help \
+		$(DESTDIR)$(GDBTK_LIBRARY)/help/images \
+		$(DESTDIR)$(GDBTK_LIBRARY)/help/trace ; \
+	cd $(srcdir)/gdbtk/library ; \
+	for i in *.tcl *.itcl *.ith *.itb images/*.gif images2/*.gif images/icons.txt images2/icons.txt tclIndex help/*.html  help/trace/*.html help/trace/index.toc help/images/*.gif help/images/*.png; \
+	  do \
+		$(INSTALL_DATA) $$i $(DESTDIR)$(GDBTK_LIBRARY)/$$i ; \
+	  done ;
+
+uninstall-gdbtk:
+	transformed_name=`t='$(program_transform_name)'; \
+		  echo insight | sed -e $$t` ; \
+	if test "x$$transformed_name" = x; then \
+		transformed_name=insight ; \
+	else \
+		true ; \
+	fi ; \
+	rm -f $(DESTDIR)$(bindir)/$$transformed_name$(EXEEXT) ; \
+	rm -rf $(DESTDIR)$(GDBTK_LIBRARY)
+
+clean-gdbtk:
+	rm -f insight$(EXEEXT)
+
+# Removing the old gdb first works better if it is running, at least on SunOS.
+insight$(EXEEXT): gdbtk-main.o libgdb.a $(ADD_DEPS) \
+		$(CDEPS) $(TDEPLIBS)
+	rm -f insight$(EXEEXT)
+	$(CC_LD) $(INTERNAL_LDFLAGS) $(WIN32LDAPP) \
+		-o insight$(EXEEXT) gdbtk-main.o libgdb.a \
+		$(TDEPLIBS) $(TUI_LIBRARY) $(CLIBS) $(LOADLIBES)
+
+gdbres.o: $(srcdir)/gdbtk/gdb.rc $(srcdir)/gdbtk/gdbtool.ico
+	$(WINDRES) --include $(srcdir)/gdbtk $(srcdir)/gdbtk/gdb.rc gdbres.o
+
+gdbtk.o: $(srcdir)/gdbtk/generic/gdbtk.c \
+	$(srcdir)/gdbtk/generic/gdbtk.h $(defs_h) \
+	$(symtab_h) $(inferior_h) $(command_h) \
+	$(bfd_h) $(symfile_h) $(objfiles_h) $(target_h) $(gdb_string_h) \
+	$(tracepoint_h) $(top_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(IDE_CFLAGS) $(ITCL_CFLAGS) \
+        $(ITK_CFLAGS)  \
+	$(TCL_CFLAGS) $(TK_CFLAGS) $(X11_CFLAGS) $(GDBTK_CFLAGS)\
+		$(srcdir)/gdbtk/generic/gdbtk.c \
+		-DGDBTK_LIBRARY=\"$(GDBTK_LIBRARY)\" -DSRC_DIR=\"$(GDBTK_SRC_DIR)\"
+
+gdbtk-bp.o: $(srcdir)/gdbtk/generic/gdbtk-bp.c \
+		$(srcdir)/gdbtk/generic/gdbtk.h \
+		$(srcdir)/gdbtk/generic/gdbtk-cmds.h \
+		$(defs_h) $(breakpoint_h) $(tracepoint_h) \
+		$(symfile_h) $(symtab_h) $(gdb_string_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(IDE_CFLAGS) $(ITCL_CFLAGS) \
+	 $(TCL_CFLAGS) $(TK_CFLAGS) $(X11_CFLAGS)   \
+	$(GDBTK_CFLAGS) $(srcdir)/gdbtk/generic/gdbtk-bp.c \
+	-DGDBTK_LIBRARY=\"$(GDBTK_LIBRARY)\"
+
+gdbtk-cmds.o: $(srcdir)/gdbtk/generic/gdbtk-cmds.c \
+	$(srcdir)/gdbtk/generic/gdbtk.h $(srcdir)/gdbtk/generic/gdbtk-cmds.h \
+	$(defs_h) $(inferior_h)	$(source_h) $(symfile_h) $(objfiles_h) \
+	$(gdbcore_h) $(demangle_h) $(linespec_h) $(tui_file_h) $(top_h) \
+	$(annotate_h) $(block_h) $(dictionary_h) $(gdb_string_h) \
+	$(dis_asm_h) $(gdbcmd_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(IDE_CFLAGS) $(ITCL_CFLAGS)	\
+	 $(TCL_CFLAGS) $(TK_CFLAGS) $(X11_CFLAGS)		\
+	$(GDBTK_CFLAGS) $(srcdir)/gdbtk/generic/gdbtk-cmds.c		\
+	-DGDBTK_LIBRARY=\"$(GDBTK_LIBRARY)\"
+
+gdbtk-hooks.o: $(srcdir)/gdbtk/generic/gdbtk-hooks.c \
+	$(srcdir)/gdbtk/generic/gdbtk.h $(defs_h) \
+	$(symtab_h) $(inferior_h) $(command_h) \
+	$(bfd_h) $(symfile_h) $(objfiles_h) $(target_h) $(gdb_string_h) \
+	$(tracepoint_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(IDE_CFLAGS) $(ITCL_CFLAGS)  \
+	$(TCL_CFLAGS) $(TK_CFLAGS) $(X11_CFLAGS) $(GDBTK_CFLAGS)\
+		$(srcdir)/gdbtk/generic/gdbtk-hooks.c -DGDBTK_LIBRARY=\"$(GDBTK_LIBRARY)\"
+
+gdbtk-interp.o: $(srcdir)/gdbtk/generic/gdbtk-interp.c \
+	$(defs_h) $(interps_h) $(ui_out_h) $(ui_file_h) \
+	$(cli_out_h) $(gdb_string_h) $(cli_cmds_h) $(cli_decode_h) \
+	$(srcdir)/gdbtk/generic/gdbtk.h
+	$(CC) -c $(INTERNAL_CFLAGS) $(IDE_CFLAGS) $(ITCL_CFLAGS) \
+	$(TCL_CFLAGS) $(TK_CFLAGS) $(X11_CFLAGS) $(GDBTK_CFLAGS) \
+		$(srcdir)/gdbtk/generic/gdbtk-interp.c
+
+gdbtk-main.o: $(srcdir)/gdbtk/generic/gdbtk-main.c $(defs_h) $(main_h) \
+	$(gdb_string_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(IDE_CFLAGS) $(ITCL_CFLAGS)  \
+	$(TCL_CFLAGS) $(TK_CFLAGS) $(X11_CFLAGS) $(GDBTK_CFLAGS)\
+		$(srcdir)/gdbtk/generic/gdbtk-main.c -DGDBTK_LIBRARY=\"$(GDBTK_LIBRARY)\"
+
+gdbtk-register.o: $(srcdir)/gdbtk/generic/gdbtk-register.c \
+		$(srcdir)/gdbtk/generic/gdbtk.h \
+		$(srcdir)/gdbtk/generic/gdbtk-cmds.h \
+		$(defs_h) $(frame_h) $(value_h) $(gdb_string_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(IDE_CFLAGS) $(ITCL_CFLAGS) \
+	 $(TCL_CFLAGS) $(TK_CFLAGS) $(X11_CFLAGS)   \
+	$(GDBTK_CFLAGS) $(srcdir)/gdbtk/generic/gdbtk-register.c \
+	-DGDBTK_LIBRARY=\"$(GDBTK_LIBRARY)\"
+
+gdbtk-stack.o: $(srcdir)/gdbtk/generic/gdbtk-stack.c \
+	$(srcdir)/gdbtk/generic/gdbtk.h $(srcdir)/gdbtk/generic/gdbtk-cmds.h \
+	$(srcdir)/gdbtk/generic/gdbtk-wrapper.h \
+	$(defs_h) $(target_h) $(breakpoint_h) $(linespec_h) \
+	$(block_h) $(dictionary_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(IDE_CFLAGS) $(ITCL_CFLAGS) \
+	 $(TCL_CFLAGS) $(TK_CFLAGS) $(X11_CFLAGS)   \
+	$(GDBTK_CFLAGS) $(srcdir)/gdbtk/generic/gdbtk-stack.c \
+	-DGDBTK_LIBRARY=\"$(GDBTK_LIBRARY)\"
+
+gdbtk-varobj.o: $(srcdir)/gdbtk/generic/gdbtk-varobj.c \
+		$(srcdir)/gdbtk/generic/gdbtk.h \
+		$(defs_h) $(value_h) $(varobj_h) $(gdb_string_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(IDE_CFLAGS) $(ITCL_CFLAGS)  \
+	$(TCL_CFLAGS) $(TK_CFLAGS) $(X11_CFLAGS) $(GDBTK_CFLAGS)\
+		$(srcdir)/gdbtk/generic/gdbtk-varobj.c
+
+gdbtk-wrapper.o: $(srcdir)/gdbtk/generic/gdbtk-wrapper.c \
+	$(srcdir)/gdbtk/generic/gdbtk-wrapper.h \
+	$(defs_h) $(frame_h) $(value_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(IDE_CFLAGS) $(GDBTK_CFLAGS)\
+		$(srcdir)/gdbtk/generic/gdbtk-wrapper.c
+
+#
+# gdb/mi/ dependencies
+#
+# Need to explicitly specify the compile rule as make will do nothing
+# or try to compile the object file into the sub-directory.
+
+mi-cmd-break.o: $(srcdir)/mi/mi-cmd-break.c $(defs_h) $(mi_cmds_h) \
+	$(ui_out_h) $(mi_out_h) $(breakpoint_h) $(gdb_string_h) \
+	$(mi_getopt_h) $(gdb_events_h) $(gdb_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/mi/mi-cmd-break.c
+mi-cmd-disas.o: $(srcdir)/mi/mi-cmd-disas.c $(defs_h) $(target_h) $(value_h) \
+	$(mi_cmds_h) $(mi_getopt_h) $(gdb_string_h) $(ui_out_h) $(disasm_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/mi/mi-cmd-disas.c
+mi-cmd-env.o: $(srcdir)/mi/mi-cmd-env.c $(defs_h) $(inferior_h) $(value_h) \
+	$(mi_out_h) $(mi_cmds_h) $(mi_getopt_h) $(symtab_h) $(target_h) \
+	$(environ_h) $(command_h) $(ui_out_h) $(top_h) $(gdb_string_h) \
+	$(gdb_stat_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/mi/mi-cmd-env.c
+mi-cmd-file.o: $(srcdir)/mi/mi-cmd-file.c $(defs_h) $(mi_cmds_h) \
+	$(mi_getopt_h) $(ui_out_h) $(symtab_h) $(source_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/mi/mi-cmd-file.c
+mi-cmds.o: $(srcdir)/mi/mi-cmds.c $(defs_h) $(top_h) $(mi_cmds_h) \
+	$(gdb_string_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/mi/mi-cmds.c
+mi-cmd-stack.o: $(srcdir)/mi/mi-cmd-stack.c $(defs_h) $(target_h) $(frame_h) \
+	$(value_h) $(mi_cmds_h) $(ui_out_h) $(symtab_h) $(block_h) \
+	$(stack_h) $(dictionary_h) $(gdb_string_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/mi/mi-cmd-stack.c
+mi-cmd-var.o: $(srcdir)/mi/mi-cmd-var.c $(defs_h) $(mi_cmds_h) $(ui_out_h) \
+	$(mi_out_h) $(varobj_h) $(value_h) $(gdb_string_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/mi/mi-cmd-var.c
+mi-console.o: $(srcdir)/mi/mi-console.c $(defs_h) $(mi_console_h) \
+	$(gdb_string_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/mi/mi-console.c
+mi-getopt.o: $(srcdir)/mi/mi-getopt.c $(defs_h) $(mi_getopt_h) \
+	$(gdb_string_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/mi/mi-getopt.c
+mi-interp.o: $(srcdir)/mi/mi-interp.c $(defs_h) $(gdb_string_h) $(interps_h) \
+	$(event_top_h) $(event_loop_h) $(inferior_h) $(ui_out_h) $(top_h) \
+	$(mi_main_h) $(mi_cmds_h) $(mi_out_h) $(mi_console_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/mi/mi-interp.c
+mi-main.o: $(srcdir)/mi/mi-main.c $(defs_h) $(target_h) $(inferior_h) \
+	$(gdb_string_h) $(top_h) $(gdbthread_h) $(mi_cmds_h) $(mi_parse_h) \
+	$(mi_getopt_h) $(mi_console_h) $(ui_out_h) $(mi_out_h) $(interps_h) \
+	$(event_loop_h) $(event_top_h) $(gdbcore_h) $(value_h) $(regcache_h) \
+	$(gdb_h) $(frame_h) $(mi_main_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/mi/mi-main.c
+mi-out.o: $(srcdir)/mi/mi-out.c $(defs_h) $(ui_out_h) $(mi_out_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/mi/mi-out.c
+mi-parse.o: $(srcdir)/mi/mi-parse.c $(defs_h) $(mi_cmds_h) $(mi_parse_h) \
+	$(gdb_string_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/mi/mi-parse.c
+mi-symbol-cmds.o: $(srcdir)/mi/mi-symbol-cmds.c $(defs_h) $(mi_cmds_h) \
+	$(symtab_h) $(ui_out_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/mi/mi-symbol-cmds.c
+
+#
+# rdi-share sub-directory
+#
+# Need to explicitly specify the compile rule as make will do nothing
+# or try to compile the object file into the mi directory.
+
+rdi-share/libangsd.a:	force
+	@dir=rdi-share; \
+	if [ -f ./$${dir}/Makefile ] ; then \
+	  r=`pwd`; export r; \
+	  srcroot=`cd $(srcdir); pwd`; export srcroot; \
+	  (cd $${dir}; $(MAKE) $(FLAGS_TO_PASS) all); \
+	else \
+	  true; \
+	fi
+
+#
+# gdb/signals/ dependencies
+#
+# Need to explicitly specify the compile rule as make will do nothing
+# or try to compile the object file into the sub-directory.
+
+signals.o: $(srcdir)/signals/signals.c $(server_h) $(defs_h) $(target_h) \
+	$(gdb_string_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/signals/signals.c
+
+#
+# gdb/tui/ dependencies
+#
+# Need to explicitly specify the compile rule as make will do nothing
+# or try to compile the object file into the sub-directory.
+
+tui.o: $(srcdir)/tui/tui.c $(defs_h) $(gdbcmd_h) $(tui_h) $(tui_hooks_h) \
+	$(tui_data_h) $(tui_layout_h) $(tui_io_h) $(tui_regs_h) \
+	$(tui_stack_h) $(tui_win_h) $(tui_winsource_h) $(tui_windata_h) \
+	$(target_h) $(frame_h) $(breakpoint_h) $(inferior_h) $(symtab_h) \
+	$(source_h) $(gdb_curses_h) $(readline_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/tui/tui.c
+tui-command.o: $(srcdir)/tui/tui-command.c $(defs_h) $(tui_h) $(tui_data_h) \
+	$(tui_win_h) $(tui_io_h) $(gdb_curses_h) $(gdb_string_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/tui/tui-command.c
+tui-data.o: $(srcdir)/tui/tui-data.c $(defs_h) $(symtab_h) $(tui_h) \
+	$(tui_data_h) $(tui_wingeneral_h) $(gdb_string_h) $(gdb_curses_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/tui/tui-data.c
+tui-disasm.o: $(srcdir)/tui/tui-disasm.c $(defs_h) $(symtab_h) \
+	$(breakpoint_h) $(frame_h) $(value_h) $(source_h) $(disasm_h) \
+	$(gdb_string_h) $(tui_h) $(tui_data_h) $(tui_win_h) $(tui_layout_h) \
+	$(tui_winsource_h) $(tui_stack_h) $(tui_file_h) $(gdb_curses_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/tui/tui-disasm.c
+tui-file.o: $(srcdir)/tui/tui-file.c $(defs_h) $(ui_file_h) $(tui_file_h) \
+	$(tui_io_h) $(tui_h) $(gdb_string_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/tui/tui-file.c
+tui-hooks.o: $(srcdir)/tui/tui-hooks.c $(defs_h) $(symtab_h) $(inferior_h) \
+	$(command_h) $(bfd_h) $(symfile_h) $(objfiles_h) $(target_h) \
+	$(gdbcore_h) $(event_loop_h) $(event_top_h) $(frame_h) \
+	$(breakpoint_h) $(gdb_events_h) $(ui_out_h) $(top_h) $(readline_h) \
+	$(tui_h) $(tui_hooks_h) $(tui_data_h) $(tui_layout_h) $(tui_io_h) \
+	$(tui_regs_h) $(tui_win_h) $(tui_stack_h) $(tui_windata_h) \
+	$(tui_winsource_h) $(gdb_curses_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/tui/tui-hooks.c
+tui-interp.o: $(srcdir)/tui/tui-interp.c $(defs_h) $(interps_h) $(top_h) \
+	$(event_top_h) $(event_loop_h) $(ui_out_h) $(cli_out_h) \
+	$(tui_data_h) $(readline_h) $(tui_win_h) $(tui_h) $(tui_io_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/tui/tui-interp.c
+tui-io.o: $(srcdir)/tui/tui-io.c $(defs_h) $(terminal_h) $(target_h) \
+	$(event_loop_h) $(event_top_h) $(command_h) $(top_h) $(readline_h) \
+	$(tui_h) $(tui_data_h) $(tui_io_h) $(tui_command_h) $(tui_win_h) \
+	$(tui_wingeneral_h) $(tui_file_h) $(ui_out_h) $(cli_out_h) \
+	$(gdb_curses_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/tui/tui-io.c
+tui-layout.o: $(srcdir)/tui/tui-layout.c $(defs_h) $(command_h) $(symtab_h) \
+	$(frame_h) $(source_h) $(tui_h) $(tui_data_h) $(tui_windata_h) \
+	$(tui_wingeneral_h) $(tui_stack_h) $(tui_regs_h) $(tui_win_h) \
+	$(tui_winsource_h) $(tui_disasm_h) $(gdb_string_h) $(gdb_curses_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/tui/tui-layout.c
+tui-main.o: $(srcdir)/tui/tui-main.c $(defs_h) $(main_h) $(gdb_string_h) \
+	$(interps_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/tui/tui-main.c
+tui-out.o: $(srcdir)/tui/tui-out.c $(defs_h) $(ui_out_h) $(tui_h) \
+	$(gdb_string_h) $(gdb_assert_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/tui/tui-out.c
+tui-regs.o: $(srcdir)/tui/tui-regs.c $(defs_h) $(tui_h) $(tui_data_h) \
+	$(symtab_h) $(gdbtypes_h) $(gdbcmd_h) $(frame_h) $(regcache_h) \
+	$(inferior_h) $(target_h) $(gdb_string_h) $(tui_layout_h) \
+	$(tui_win_h) $(tui_windata_h) $(tui_wingeneral_h) $(tui_file_h) \
+	$(reggroups_h) $(gdb_curses_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/tui/tui-regs.c
+tui-source.o: $(srcdir)/tui/tui-source.c $(defs_h) $(symtab_h) $(frame_h) \
+	$(breakpoint_h) $(source_h) $(symtab_h) $(tui_h) $(tui_data_h) \
+	$(tui_stack_h) $(tui_winsource_h) $(tui_source_h) $(gdb_string_h) \
+	$(gdb_curses_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/tui/tui-source.c
+tui-stack.o: $(srcdir)/tui/tui-stack.c $(defs_h) $(symtab_h) $(breakpoint_h) \
+	$(frame_h) $(command_h) $(inferior_h) $(target_h) $(top_h) \
+	$(gdb_string_h) $(tui_h) $(tui_data_h) $(tui_stack_h) \
+	$(tui_wingeneral_h) $(tui_source_h) $(tui_winsource_h) $(tui_file_h) \
+	$(gdb_curses_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/tui/tui-stack.c
+tui-win.o: $(srcdir)/tui/tui-win.c $(defs_h) $(command_h) $(symtab_h) \
+	$(breakpoint_h) $(frame_h) $(cli_cmds_h) $(top_h) $(source_h) \
+	$(tui_h) $(tui_data_h) $(tui_wingeneral_h) $(tui_stack_h) \
+	$(tui_regs_h) $(tui_disasm_h) $(tui_source_h) $(tui_winsource_h) \
+	$(tui_windata_h) $(gdb_curses_h) $(gdb_string_h) $(readline_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/tui/tui-win.c
+tui-windata.o: $(srcdir)/tui/tui-windata.c $(defs_h) $(tui_h) $(tui_data_h) \
+	$(tui_wingeneral_h) $(tui_regs_h) $(gdb_string_h) $(gdb_curses_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/tui/tui-windata.c
+tui-wingeneral.o: $(srcdir)/tui/tui-wingeneral.c $(defs_h) $(tui_h) \
+	$(tui_data_h) $(tui_wingeneral_h) $(tui_win_h) $(gdb_curses_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/tui/tui-wingeneral.c
+tui-winsource.o: $(srcdir)/tui/tui-winsource.c $(defs_h) $(symtab_h) \
+	$(frame_h) $(breakpoint_h) $(value_h) $(source_h) $(tui_h) \
+	$(tui_data_h) $(tui_stack_h) $(tui_win_h) $(tui_wingeneral_h) \
+	$(tui_winsource_h) $(tui_source_h) $(tui_disasm_h) $(gdb_string_h) \
+	$(gdb_curses_h)
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/tui/tui-winsource.c
+
+#
+# vx-share sub-directory
+#
+
+xdr_ld.o: vx-share/xdr_ld.c $(defs_h) vx-share/vxTypes.h \
+	vx-share/vxWorks.h vx-share/xdr_ld.h
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/vx-share/xdr_ld.c
+
+xdr_ptrace.o: vx-share/xdr_ptrace.c $(defs_h) vx-share/vxTypes.h \
+	vx-share/vxWorks.h vx-share/xdr_ptrace.h
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/vx-share/xdr_ptrace.c
+
+xdr_rdb.o: vx-share/xdr_rdb.c $(defs_h) vx-share/vxTypes.h \
+	vx-share/vxWorks.h vx-share/xdr_rdb.h
+	$(CC) -c $(INTERNAL_CFLAGS) $(srcdir)/vx-share/xdr_rdb.c
+
+### end of the gdb Makefile.in.
diff --git a/gdb/ppc-tdep.h b/gdb/ppc-tdep.h
new file mode 100644
index 00000000000..1a5bc6fbf05
--- /dev/null
+++ b/gdb/ppc-tdep.h
@@ -0,0 +1,376 @@
+/* Target-dependent code for GDB, the GNU debugger.
+
+   Copyright 2000, 2001, 2002, 2003, 2004 Free Software Foundation,
+   Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA.  */
+
+#ifndef PPC_TDEP_H
+#define PPC_TDEP_H
+
+struct gdbarch;
+struct frame_info;
+struct value;
+struct regcache;
+struct type;
+
+/* From ppc-linux-tdep.c... */
+enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch,
+							struct type *valtype,
+							struct regcache *regcache,
+							void *readbuf,
+							const void *writebuf);
+enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch,
+							       struct type *valtype,
+							       struct regcache *regcache,
+							       void *readbuf,
+							       const void *writebuf);
+CORE_ADDR ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
+					struct value *function,
+					struct regcache *regcache,
+					CORE_ADDR bp_addr, int nargs,
+					struct value **args, CORE_ADDR sp,
+					int struct_return,
+					CORE_ADDR struct_addr);
+CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
+					  struct value *function,
+					  struct regcache *regcache,
+					  CORE_ADDR bp_addr, int nargs,
+					  struct value **args, CORE_ADDR sp,
+					  int struct_return,
+					  CORE_ADDR struct_addr);
+CORE_ADDR ppc64_sysv_abi_adjust_breakpoint_address (struct gdbarch *gdbarch,
+						    CORE_ADDR bpaddr);
+int ppc_linux_memory_remove_breakpoint (CORE_ADDR addr, char *contents_cache);
+struct link_map_offsets *ppc_linux_svr4_fetch_link_map_offsets (void);
+void ppc_linux_supply_gregset (struct regcache *regcache,
+			       int regnum, const void *gregs, size_t size,
+			       int wordsize);
+void ppc_linux_supply_fpregset (const struct regset *regset,
+				struct regcache *regcache,
+				int regnum, const void *gregs, size_t size);
+
+enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch,
+							  struct type *valtype,
+							  struct regcache *regcache,
+							  void *readbuf,
+							  const void *writebuf);
+
+/* From rs6000-tdep.c... */
+int altivec_register_p (int regno);
+int spe_register_p (int regno);
+
+/* Return non-zero if the architecture described by GDBARCH has
+   floating-point registers (f0 --- f31 and fpscr).  */
+int ppc_floating_point_unit_p (struct gdbarch *gdbarch);
+
+/* Register set description.  */
+
+struct ppc_reg_offsets
+{
+  /* General-purpose registers.  */
+  int r0_offset;
+  int pc_offset;
+  int ps_offset;
+  int cr_offset;
+  int lr_offset;
+  int ctr_offset;
+  int xer_offset;
+  int mq_offset;
+
+  /* Floating-point registers.  */
+  int f0_offset;
+  int fpscr_offset;
+
+  /* AltiVec registers.  */
+  int vr0_offset;
+  int vscr_offset;
+  int vrsave_offset;
+};
+
+/* Supply register REGNUM in the general-purpose register set REGSET
+   from the buffer specified by GREGS and LEN to register cache
+   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */
+
+extern void ppc_supply_gregset (const struct regset *regset,
+				struct regcache *regcache,
+				int regnum, const void *gregs, size_t len);
+
+/* Supply register REGNUM in the floating-point register set REGSET
+   from the buffer specified by FPREGS and LEN to register cache
+   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */
+
+extern void ppc_supply_fpregset (const struct regset *regset,
+				 struct regcache *regcache,
+				 int regnum, const void *fpregs, size_t len);
+
+/* Collect register REGNUM in the general-purpose register set
+   REGSET. from register cache REGCACHE into the buffer specified by
+   GREGS and LEN.  If REGNUM is -1, do this for all registers in
+   REGSET.  */
+
+extern void ppc_collect_gregset (const struct regset *regset,
+				 const struct regcache *regcache,
+				 int regnum, void *gregs, size_t len);
+
+/* Collect register REGNUM in the floating-point register set
+   REGSET. from register cache REGCACHE into the buffer specified by
+   FPREGS and LEN.  If REGNUM is -1, do this for all registers in
+   REGSET.  */
+
+extern void ppc_collect_fpregset (const struct regset *regset,
+				  const struct regcache *regcache,
+				  int regnum, void *fpregs, size_t len);
+
+/* Private data that this module attaches to struct gdbarch. */
+
+struct gdbarch_tdep
+  {
+    int wordsize;              /* size in bytes of fixed-point word */
+    const struct reg *regs;    /* from current variant */
+    int ppc_gp0_regnum;		/* GPR register 0 */
+    int ppc_toc_regnum;		/* TOC register */
+    int ppc_ps_regnum;	        /* Processor (or machine) status (%msr) */
+    int ppc_cr_regnum;		/* Condition register */
+    int ppc_lr_regnum;		/* Link register */
+    int ppc_ctr_regnum;		/* Count register */
+    int ppc_xer_regnum;		/* Integer exception register */
+
+    /* On PPC and RS6000 variants that have no floating-point
+       registers, the next two members will be -1.  */
+    int ppc_fp0_regnum;         /* floating-point register 0 */
+    int ppc_fpscr_regnum;	/* Floating point status and condition
+    				   register */
+
+    int ppc_sr0_regnum;         /* segment register 0, or -1 on
+                                   variants that have no segment
+                                   registers.  */
+
+    int ppc_mq_regnum;		/* Multiply/Divide extension register */
+    int ppc_vr0_regnum;		/* First AltiVec register */
+    int ppc_vrsave_regnum;	/* Last AltiVec register */
+    int ppc_ev0_upper_regnum;   /* First GPR upper half register */
+    int ppc_ev0_regnum;         /* First ev register */
+    int ppc_ev31_regnum;        /* Last ev register */
+    int ppc_acc_regnum;         /* SPE 'acc' register */
+    int ppc_spefscr_regnum;     /* SPE 'spefscr' register */
+    int lr_frame_offset;	/* Offset to ABI specific location where
+                                   link register is saved.  */
+
+    /* An array of integers, such that sim_regno[I] is the simulator
+       register number for GDB register number I, or -1 if the
+       simulator does not implement that register.  */
+    int *sim_regno;
+};
+
+
+/* Constants for register set sizes.  */
+enum
+  {
+    ppc_num_gprs = 32,          /* 32 general-purpose registers */
+    ppc_num_fprs = 32,          /* 32 floating-point registers */
+    ppc_num_srs = 16,           /* 16 segment registers */
+    ppc_num_vrs = 32            /* 32 Altivec vector registers */
+  };
+
+
+/* Constants for SPR register numbers.  These are *not* GDB register
+   numbers: they are the numbers used in the PowerPC ISA itself to
+   refer to these registers.
+
+   This table includes all the SPRs from all the variants I could find
+   documentation for.
+
+   There may be registers from different PowerPC variants assigned the
+   same number, but that's fine: GDB and the SIM always use the
+   numbers in the context of a particular variant, so it's not
+   ambiguous.
+
+   We need to deviate from the naming pattern when variants have
+   special-purpose registers of the same name, but with different
+   numbers.  Fortunately, this is rare: look below to see how we
+   handle the 'tcr' registers on the 403/403GX and 602.  */
+
+enum
+  {
+    ppc_spr_mq        =    0,
+    ppc_spr_xer       =    1,
+    ppc_spr_rtcu      =    4,
+    ppc_spr_rtcl      =    5,
+    ppc_spr_lr        =    8,
+    ppc_spr_ctr       =    9,
+    ppc_spr_cnt       =    9,
+    ppc_spr_dsisr     =   18,
+    ppc_spr_dar       =   19,
+    ppc_spr_dec       =   22,
+    ppc_spr_sdr1      =   25,
+    ppc_spr_srr0      =   26,
+    ppc_spr_srr1      =   27,
+    ppc_spr_eie       =   80,
+    ppc_spr_eid       =   81,
+    ppc_spr_nri       =   82,
+    ppc_spr_sp        =  102,
+    ppc_spr_cmpa      =  144,
+    ppc_spr_cmpb      =  145,
+    ppc_spr_cmpc      =  146,
+    ppc_spr_cmpd      =  147,
+    ppc_spr_icr       =  148,
+    ppc_spr_der       =  149,
+    ppc_spr_counta    =  150,
+    ppc_spr_countb    =  151,
+    ppc_spr_cmpe      =  152,
+    ppc_spr_cmpf      =  153,
+    ppc_spr_cmpg      =  154,
+    ppc_spr_cmph      =  155,
+    ppc_spr_lctrl1    =  156,
+    ppc_spr_lctrl2    =  157,
+    ppc_spr_ictrl     =  158,
+    ppc_spr_bar       =  159,
+    ppc_spr_vrsave    =  256,
+    ppc_spr_sprg0     =  272,
+    ppc_spr_sprg1     =  273,
+    ppc_spr_sprg2     =  274,
+    ppc_spr_sprg3     =  275,
+    ppc_spr_asr       =  280,
+    ppc_spr_ear       =  282,
+    ppc_spr_tbl       =  284,
+    ppc_spr_tbu       =  285,
+    ppc_spr_pvr       =  287,
+    ppc_spr_spefscr   =  512,
+    ppc_spr_ibat0u    =  528,
+    ppc_spr_ibat0l    =  529,
+    ppc_spr_ibat1u    =  530,
+    ppc_spr_ibat1l    =  531,
+    ppc_spr_ibat2u    =  532,
+    ppc_spr_ibat2l    =  533,
+    ppc_spr_ibat3u    =  534,
+    ppc_spr_ibat3l    =  535,
+    ppc_spr_dbat0u    =  536,
+    ppc_spr_dbat0l    =  537,
+    ppc_spr_dbat1u    =  538,
+    ppc_spr_dbat1l    =  539,
+    ppc_spr_dbat2u    =  540,
+    ppc_spr_dbat2l    =  541,
+    ppc_spr_dbat3u    =  542,
+    ppc_spr_dbat3l    =  543,
+    ppc_spr_ic_cst    =  560,
+    ppc_spr_ic_adr    =  561,
+    ppc_spr_ic_dat    =  562,
+    ppc_spr_dc_cst    =  568,
+    ppc_spr_dc_adr    =  569,
+    ppc_spr_dc_dat    =  570,
+    ppc_spr_dpdr      =  630,
+    ppc_spr_dpir      =  631,
+    ppc_spr_immr      =  638,
+    ppc_spr_mi_ctr    =  784,
+    ppc_spr_mi_ap     =  786,
+    ppc_spr_mi_epn    =  787,
+    ppc_spr_mi_twc    =  789,
+    ppc_spr_mi_rpn    =  790,
+    ppc_spr_mi_cam    =  816,
+    ppc_spr_mi_ram0   =  817,
+    ppc_spr_mi_ram1   =  818,
+    ppc_spr_md_ctr    =  792,
+    ppc_spr_m_casid   =  793,
+    ppc_spr_md_ap     =  794,
+    ppc_spr_md_epn    =  795,
+    ppc_spr_m_twb     =  796,
+    ppc_spr_md_twc    =  797,
+    ppc_spr_md_rpn    =  798,
+    ppc_spr_m_tw      =  799,
+    ppc_spr_mi_dbcam  =  816,
+    ppc_spr_mi_dbram0 =  817,
+    ppc_spr_mi_dbram1 =  818,
+    ppc_spr_md_dbcam  =  824,
+    ppc_spr_md_cam    =  824,
+    ppc_spr_md_dbram0 =  825,
+    ppc_spr_md_ram0   =  825,
+    ppc_spr_md_dbram1 =  826,
+    ppc_spr_md_ram1   =  826,
+    ppc_spr_ummcr0    =  936,
+    ppc_spr_upmc1     =  937,
+    ppc_spr_upmc2     =  938,
+    ppc_spr_usia      =  939,
+    ppc_spr_ummcr1    =  940,
+    ppc_spr_upmc3     =  941,
+    ppc_spr_upmc4     =  942,
+    ppc_spr_zpr       =  944,
+    ppc_spr_pid       =  945,
+    ppc_spr_mmcr0     =  952,
+    ppc_spr_pmc1      =  953,
+    ppc_spr_sgr       =  953,
+    ppc_spr_pmc2      =  954,
+    ppc_spr_dcwr      =  954,
+    ppc_spr_sia       =  955,
+    ppc_spr_mmcr1     =  956,
+    ppc_spr_pmc3      =  957,
+    ppc_spr_pmc4      =  958,
+    ppc_spr_sda       =  959,
+    ppc_spr_tbhu      =  972,
+    ppc_spr_tblu      =  973,
+    ppc_spr_dmiss     =  976,
+    ppc_spr_dcmp      =  977,
+    ppc_spr_hash1     =  978,
+    ppc_spr_hash2     =  979,
+    ppc_spr_icdbdr    =  979,
+    ppc_spr_imiss     =  980,
+    ppc_spr_esr       =  980,
+    ppc_spr_icmp      =  981,
+    ppc_spr_dear      =  981,
+    ppc_spr_rpa       =  982,
+    ppc_spr_evpr      =  982,
+    ppc_spr_cdbcr     =  983,
+    ppc_spr_tsr       =  984,
+    ppc_spr_602_tcr   =  984,
+    ppc_spr_403_tcr   =  986,
+    ppc_spr_ibr       =  986,
+    ppc_spr_pit       =  987,
+    ppc_spr_esasrr    =  988,
+    ppc_spr_tbhi      =  988,
+    ppc_spr_tblo      =  989,
+    ppc_spr_srr2      =  990,
+    ppc_spr_sebr      =  990,
+    ppc_spr_srr3      =  991,
+    ppc_spr_ser       =  991,
+    ppc_spr_hid0      = 1008,
+    ppc_spr_dbsr      = 1008,
+    ppc_spr_hid1      = 1009,
+    ppc_spr_iabr      = 1010,
+    ppc_spr_dbcr      = 1010,
+    ppc_spr_iac1      = 1012,
+    ppc_spr_dabr      = 1013,
+    ppc_spr_iac2      = 1013,
+    ppc_spr_dac1      = 1014,
+    ppc_spr_dac2      = 1015,
+    ppc_spr_l2cr      = 1017,
+    ppc_spr_dccr      = 1018,
+    ppc_spr_ictc      = 1019,
+    ppc_spr_iccr      = 1019,
+    ppc_spr_thrm1     = 1020,
+    ppc_spr_pbl1      = 1020,
+    ppc_spr_thrm2     = 1021,
+    ppc_spr_pbu1      = 1021,
+    ppc_spr_thrm3     = 1022,
+    ppc_spr_pbl2      = 1022,
+    ppc_spr_fpecr     = 1022,
+    ppc_spr_lt        = 1022,
+    ppc_spr_pir       = 1023,
+    ppc_spr_pbu2      = 1023
+  };
+
+#endif
diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
new file mode 100644
index 00000000000..61e2ef1794f
--- /dev/null
+++ b/gdb/rs6000-tdep.c
@@ -0,0 +1,3355 @@
+/* Target-dependent code for GDB, the GNU debugger.
+
+   Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996,
+   1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
+   Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA.  */
+
+#include "defs.h"
+#include "frame.h"
+#include "inferior.h"
+#include "symtab.h"
+#include "target.h"
+#include "gdbcore.h"
+#include "gdbcmd.h"
+#include "objfiles.h"
+#include "arch-utils.h"
+#include "regcache.h"
+#include "regset.h"
+#include "doublest.h"
+#include "value.h"
+#include "parser-defs.h"
+#include "osabi.h"
+#include "infcall.h"
+#include "sim-regno.h"
+#include "gdb/sim-ppc.h"
+#include "reggroups.h"
+
+#include "libbfd.h"		/* for bfd_default_set_arch_mach */
+#include "coff/internal.h"	/* for libcoff.h */
+#include "libcoff.h"		/* for xcoff_data */
+#include "coff/xcoff.h"
+#include "libxcoff.h"
+
+#include "elf-bfd.h"
+
+#include "solib-svr4.h"
+#include "ppc-tdep.h"
+
+#include "gdb_assert.h"
+#include "dis-asm.h"
+
+#include "trad-frame.h"
+#include "frame-unwind.h"
+#include "frame-base.h"
+
+/* If the kernel has to deliver a signal, it pushes a sigcontext
+   structure on the stack and then calls the signal handler, passing
+   the address of the sigcontext in an argument register. Usually
+   the signal handler doesn't save this register, so we have to
+   access the sigcontext structure via an offset from the signal handler
+   frame.
+   The following constants were determined by experimentation on AIX 3.2.  */
+#define SIG_FRAME_PC_OFFSET 96
+#define SIG_FRAME_LR_OFFSET 108
+#define SIG_FRAME_FP_OFFSET 284
+
+/* To be used by skip_prologue. */
+
+struct rs6000_framedata
+  {
+    int offset;			/* total size of frame --- the distance
+				   by which we decrement sp to allocate
+				   the frame */
+    int saved_gpr;		/* smallest # of saved gpr */
+    int saved_fpr;		/* smallest # of saved fpr */
+    int saved_vr;               /* smallest # of saved vr */
+    int saved_ev;               /* smallest # of saved ev */
+    int alloca_reg;		/* alloca register number (frame ptr) */
+    char frameless;		/* true if frameless functions. */
+    char nosavedpc;		/* true if pc not saved. */
+    int gpr_offset;		/* offset of saved gprs from prev sp */
+    int fpr_offset;		/* offset of saved fprs from prev sp */
+    int vr_offset;              /* offset of saved vrs from prev sp */
+    int ev_offset;              /* offset of saved evs from prev sp */
+    int lr_offset;		/* offset of saved lr */
+    int cr_offset;		/* offset of saved cr */
+    int vrsave_offset;          /* offset of saved vrsave register */
+  };
+
+/* Description of a single register. */
+
+struct reg
+  {
+    char *name;			/* name of register */
+    unsigned char sz32;		/* size on 32-bit arch, 0 if nonextant */
+    unsigned char sz64;		/* size on 64-bit arch, 0 if nonextant */
+    unsigned char fpr;		/* whether register is floating-point */
+    unsigned char pseudo;       /* whether register is pseudo */
+    int spr_num;                /* PowerPC SPR number, or -1 if not an SPR.
+                                   This is an ISA SPR number, not a GDB
+                                   register number.  */
+  };
+
+/* Breakpoint shadows for the single step instructions will be kept here. */
+
+static struct sstep_breaks
+  {
+    /* Address, or 0 if this is not in use.  */
+    CORE_ADDR address;
+    /* Shadow contents.  */
+    char data[4];
+  }
+stepBreaks[2];
+
+/* Hook for determining the TOC address when calling functions in the
+   inferior under AIX. The initialization code in rs6000-nat.c sets
+   this hook to point to find_toc_address.  */
+
+CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL;
+
+/* Hook to set the current architecture when starting a child process. 
+   rs6000-nat.c sets this. */
+
+void (*rs6000_set_host_arch_hook) (int) = NULL;
+
+/* Static function prototypes */
+
+static CORE_ADDR branch_dest (int opcode, int instr, CORE_ADDR pc,
+			      CORE_ADDR safety);
+static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR,
+                                struct rs6000_framedata *);
+
+/* Is REGNO an AltiVec register?  Return 1 if so, 0 otherwise.  */
+int
+altivec_register_p (int regno)
+{
+  struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+  if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
+    return 0;
+  else
+    return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
+}
+
+
+/* Return true if REGNO is an SPE register, false otherwise.  */
+int
+spe_register_p (int regno)
+{
+  struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+  
+  /* Is it a reference to EV0 -- EV31, and do we have those?  */
+  if (tdep->ppc_ev0_regnum >= 0
+      && tdep->ppc_ev31_regnum >= 0
+      && tdep->ppc_ev0_regnum <= regno && regno <= tdep->ppc_ev31_regnum)
+    return 1;
+
+  /* Is it a reference to one of the raw upper GPR halves?  */
+  if (tdep->ppc_ev0_upper_regnum >= 0
+      && tdep->ppc_ev0_upper_regnum <= regno
+      && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
+    return 1;
+
+  /* Is it a reference to the 64-bit accumulator, and do we have that?  */
+  if (tdep->ppc_acc_regnum >= 0
+      && tdep->ppc_acc_regnum == regno)
+    return 1;
+
+  /* Is it a reference to the SPE floating-point status and control register,
+     and do we have that?  */
+  if (tdep->ppc_spefscr_regnum >= 0
+      && tdep->ppc_spefscr_regnum == regno)
+    return 1;
+
+  return 0;
+}
+
+
+/* Return non-zero if the architecture described by GDBARCH has
+   floating-point registers (f0 --- f31 and fpscr).  */
+int
+ppc_floating_point_unit_p (struct gdbarch *gdbarch)
+{
+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+  return (tdep->ppc_fp0_regnum >= 0
+          && tdep->ppc_fpscr_regnum >= 0);
+}
+
+
+/* Check that TABLE[GDB_REGNO] is not already initialized, and then
+   set it to SIM_REGNO.
+
+   This is a helper function for init_sim_regno_table, constructing
+   the table mapping GDB register numbers to sim register numbers; we
+   initialize every element in that table to -1 before we start
+   filling it in.  */
+static void
+set_sim_regno (int *table, int gdb_regno, int sim_regno)
+{
+  /* Make sure we don't try to assign any given GDB register a sim
+     register number more than once.  */
+  gdb_assert (table[gdb_regno] == -1);
+  table[gdb_regno] = sim_regno;
+}
+
+
+/* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
+   numbers to simulator register numbers, based on the values placed
+   in the ARCH->tdep->ppc_foo_regnum members.  */
+static void
+init_sim_regno_table (struct gdbarch *arch)
+{
+  struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
+  int total_regs = gdbarch_num_regs (arch) + gdbarch_num_pseudo_regs (arch);
+  const struct reg *regs = tdep->regs;
+  int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
+  int i;
+
+  /* Presume that all registers not explicitly mentioned below are
+     unavailable from the sim.  */
+  for (i = 0; i < total_regs; i++)
+    sim_regno[i] = -1;
+
+  /* General-purpose registers.  */
+  for (i = 0; i < ppc_num_gprs; i++)
+    set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
+  
+  /* Floating-point registers.  */
+  if (tdep->ppc_fp0_regnum >= 0)
+    for (i = 0; i < ppc_num_fprs; i++)
+      set_sim_regno (sim_regno,
+                     tdep->ppc_fp0_regnum + i,
+                     sim_ppc_f0_regnum + i);
+  if (tdep->ppc_fpscr_regnum >= 0)
+    set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
+
+  set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
+  set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
+  set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
+
+  /* Segment registers.  */
+  if (tdep->ppc_sr0_regnum >= 0)
+    for (i = 0; i < ppc_num_srs; i++)
+      set_sim_regno (sim_regno,
+                     tdep->ppc_sr0_regnum + i,
+                     sim_ppc_sr0_regnum + i);
+
+  /* Altivec registers.  */
+  if (tdep->ppc_vr0_regnum >= 0)
+    {
+      for (i = 0; i < ppc_num_vrs; i++)
+        set_sim_regno (sim_regno,
+                       tdep->ppc_vr0_regnum + i,
+                       sim_ppc_vr0_regnum + i);
+
+      /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
+         we can treat this more like the other cases.  */
+      set_sim_regno (sim_regno,
+                     tdep->ppc_vr0_regnum + ppc_num_vrs,
+                     sim_ppc_vscr_regnum);
+    }
+  /* vsave is a special-purpose register, so the code below handles it.  */
+
+  /* SPE APU (E500) registers.  */
+  if (tdep->ppc_ev0_regnum >= 0)
+    for (i = 0; i < ppc_num_gprs; i++)
+      set_sim_regno (sim_regno,
+                     tdep->ppc_ev0_regnum + i,
+                     sim_ppc_ev0_regnum + i);
+  if (tdep->ppc_ev0_upper_regnum >= 0)
+    for (i = 0; i < ppc_num_gprs; i++)
+      set_sim_regno (sim_regno,
+                     tdep->ppc_ev0_upper_regnum + i,
+                     sim_ppc_rh0_regnum + i);
+  if (tdep->ppc_acc_regnum >= 0)
+    set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
+  /* spefscr is a special-purpose register, so the code below handles it.  */
+
+  /* Now handle all special-purpose registers.  Verify that they
+     haven't mistakenly been assigned numbers by any of the above
+     code).  */
+  for (i = 0; i < total_regs; i++)
+    if (regs[i].spr_num >= 0)
+      set_sim_regno (sim_regno, i, regs[i].spr_num + sim_ppc_spr0_regnum);
+
+  /* Drop the initialized array into place.  */
+  tdep->sim_regno = sim_regno;
+}
+
+
+/* Given a GDB register number REG, return the corresponding SIM
+   register number.  */
+static int
+rs6000_register_sim_regno (int reg)
+{
+  struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+  int sim_regno;
+
+  gdb_assert (0 <= reg && reg <= NUM_REGS + NUM_PSEUDO_REGS);
+  sim_regno = tdep->sim_regno[reg];
+
+  if (sim_regno >= 0)
+    return sim_regno;
+  else
+    return LEGACY_SIM_REGNO_IGNORE;
+}
+
+
+
+/* Register set support functions.  */
+
+static void
+ppc_supply_reg (struct regcache *regcache, int regnum, 
+		const char *regs, size_t offset)
+{
+  if (regnum != -1 && offset != -1)
+    regcache_raw_supply (regcache, regnum, regs + offset);
+}
+
+static void
+ppc_collect_reg (const struct regcache *regcache, int regnum,
+		 char *regs, size_t offset)
+{
+  if (regnum != -1 && offset != -1)
+    regcache_raw_collect (regcache, regnum, regs + offset);
+}
+    
+/* Supply register REGNUM in the general-purpose register set REGSET
+   from the buffer specified by GREGS and LEN to register cache
+   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */
+
+void
+ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
+		    int regnum, const void *gregs, size_t len)
+{
+  struct gdbarch *gdbarch = get_regcache_arch (regcache);
+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+  const struct ppc_reg_offsets *offsets = regset->descr;
+  size_t offset;
+  int i;
+
+  for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
+       i < tdep->ppc_gp0_regnum + ppc_num_gprs;
+       i++, offset += 4)
+    {
+      if (regnum == -1 || regnum == i)
+	ppc_supply_reg (regcache, i, gregs, offset);
+    }
+
+  if (regnum == -1 || regnum == PC_REGNUM)
+    ppc_supply_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
+  if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
+    ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
+		    gregs, offsets->ps_offset);
+  if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
+    ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
+		    gregs, offsets->cr_offset);
+  if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
+    ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
+		    gregs, offsets->lr_offset);
+  if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
+    ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
+		    gregs, offsets->ctr_offset);
+  if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
+    ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
+		    gregs, offsets->cr_offset);
+  if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
+    ppc_supply_reg (regcache, tdep->ppc_mq_regnum, gregs, offsets->mq_offset);
+}
+
+/* Supply register REGNUM in the floating-point register set REGSET
+   from the buffer specified by FPREGS and LEN to register cache
+   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */
+
+void
+ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
+		     int regnum, const void *fpregs, size_t len)
+{
+  struct gdbarch *gdbarch = get_regcache_arch (regcache);
+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+  const struct ppc_reg_offsets *offsets = regset->descr;
+  size_t offset;
+  int i;
+
+  gdb_assert (ppc_floating_point_unit_p (gdbarch));
+
+  offset = offsets->f0_offset;
+  for (i = tdep->ppc_fp0_regnum;
+       i < tdep->ppc_fp0_regnum + ppc_num_fprs;
+       i++, offset += 4)
+    {
+      if (regnum == -1 || regnum == i)
+	ppc_supply_reg (regcache, i, fpregs, offset);
+    }
+
+  if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
+    ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
+		    fpregs, offsets->fpscr_offset);
+}
+
+/* Collect register REGNUM in the general-purpose register set
+   REGSET. from register cache REGCACHE into the buffer specified by
+   GREGS and LEN.  If REGNUM is -1, do this for all registers in
+   REGSET.  */
+
+void
+ppc_collect_gregset (const struct regset *regset,
+		     const struct regcache *regcache,
+		     int regnum, void *gregs, size_t len)
+{
+  struct gdbarch *gdbarch = get_regcache_arch (regcache);
+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+  const struct ppc_reg_offsets *offsets = regset->descr;
+  size_t offset;
+  int i;
+
+  offset = offsets->r0_offset;
+  for (i = tdep->ppc_gp0_regnum;
+       i < tdep->ppc_gp0_regnum + ppc_num_gprs;
+       i++, offset += 4)
+    {
+      if (regnum == -1 || regnum == i)
+	ppc_collect_reg (regcache, i, gregs, offset);
+    }
+
+  if (regnum == -1 || regnum == PC_REGNUM)
+    ppc_collect_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
+  if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
+    ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
+		     gregs, offsets->ps_offset);
+  if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
+    ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
+		     gregs, offsets->cr_offset);
+  if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
+    ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
+		     gregs, offsets->lr_offset);
+  if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
+    ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
+		     gregs, offsets->ctr_offset);
+  if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
+    ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
+		     gregs, offsets->xer_offset);
+  if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
+    ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
+		     gregs, offsets->mq_offset);
+}
+
+/* Collect register REGNUM in the floating-point register set
+   REGSET. from register cache REGCACHE into the buffer specified by
+   FPREGS and LEN.  If REGNUM is -1, do this for all registers in
+   REGSET.  */
+
+void
+ppc_collect_fpregset (const struct regset *regset,
+		      const struct regcache *regcache,
+		      int regnum, void *fpregs, size_t len)
+{
+  struct gdbarch *gdbarch = get_regcache_arch (regcache);
+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+  const struct ppc_reg_offsets *offsets = regset->descr;
+  size_t offset;
+  int i;
+
+  gdb_assert (ppc_floating_point_unit_p (gdbarch));
+
+  offset = offsets->f0_offset;
+  for (i = tdep->ppc_fp0_regnum;
+       i <= tdep->ppc_fp0_regnum + ppc_num_fprs;
+       i++, offset += 4)
+    {
+      if (regnum == -1 || regnum == i)
+	ppc_collect_reg (regcache, regnum, fpregs, offset);
+    }
+
+  if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
+    ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
+		     fpregs, offsets->fpscr_offset);
+}
+
+
+/* Read a LEN-byte address from debugged memory address MEMADDR. */
+
+static CORE_ADDR
+read_memory_addr (CORE_ADDR memaddr, int len)
+{
+  return read_memory_unsigned_integer (memaddr, len);
+}
+
+static CORE_ADDR
+rs6000_skip_prologue (CORE_ADDR pc)
+{
+  struct rs6000_framedata frame;
+  pc = skip_prologue (pc, 0, &frame);
+  return pc;
+}
+
+
+/* Fill in fi->saved_regs */
+
+struct frame_extra_info
+{
+  /* Functions calling alloca() change the value of the stack
+     pointer. We need to use initial stack pointer (which is saved in
+     r31 by gcc) in such cases. If a compiler emits traceback table,
+     then we should use the alloca register specified in traceback
+     table. FIXME. */
+  CORE_ADDR initial_sp;		/* initial stack pointer. */
+};
+
+/* Get the ith function argument for the current function.  */
+static CORE_ADDR
+rs6000_fetch_pointer_argument (struct frame_info *frame, int argi, 
+			       struct type *type)
+{
+  CORE_ADDR addr;
+  get_frame_register (frame, 3 + argi, &addr);
+  return addr;
+}
+
+/* Calculate the destination of a branch/jump.  Return -1 if not a branch.  */
+
+static CORE_ADDR
+branch_dest (int opcode, int instr, CORE_ADDR pc, CORE_ADDR safety)
+{
+  CORE_ADDR dest;
+  int immediate;
+  int absolute;
+  int ext_op;
+
+  absolute = (int) ((instr >> 1) & 1);
+
+  switch (opcode)
+    {
+    case 18:
+      immediate = ((instr & ~3) << 6) >> 6;	/* br unconditional */
+      if (absolute)
+	dest = immediate;
+      else
+	dest = pc + immediate;
+      break;
+
+    case 16:
+      immediate = ((instr & ~3) << 16) >> 16;	/* br conditional */
+      if (absolute)
+	dest = immediate;
+      else
+	dest = pc + immediate;
+      break;
+
+    case 19:
+      ext_op = (instr >> 1) & 0x3ff;
+
+      if (ext_op == 16)		/* br conditional register */
+	{
+          dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
+
+	  /* If we are about to return from a signal handler, dest is
+	     something like 0x3c90.  The current frame is a signal handler
+	     caller frame, upon completion of the sigreturn system call
+	     execution will return to the saved PC in the frame.  */
+	  if (dest < TEXT_SEGMENT_BASE)
+	    {
+	      struct frame_info *fi;
+
+	      fi = get_current_frame ();
+	      if (fi != NULL)
+		dest = read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET,
+					 gdbarch_tdep (current_gdbarch)->wordsize);
+	    }
+	}
+
+      else if (ext_op == 528)	/* br cond to count reg */
+	{
+          dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3;
+
+	  /* If we are about to execute a system call, dest is something
+	     like 0x22fc or 0x3b00.  Upon completion the system call
+	     will return to the address in the link register.  */
+	  if (dest < TEXT_SEGMENT_BASE)
+            dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
+	}
+      else
+	return -1;
+      break;
+
+    default:
+      return -1;
+    }
+  return (dest < TEXT_SEGMENT_BASE) ? safety : dest;
+}
+
+
+/* Sequence of bytes for breakpoint instruction.  */
+
+const static unsigned char *
+rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size)
+{
+  static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
+  static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
+  *bp_size = 4;
+  if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+    return big_breakpoint;
+  else
+    return little_breakpoint;
+}
+
+
+/* AIX does not support PT_STEP. Simulate it. */
+
+void
+rs6000_software_single_step (enum target_signal signal,
+			     int insert_breakpoints_p)
+{
+  CORE_ADDR dummy;
+  int breakp_sz;
+  const char *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz);
+  int ii, insn;
+  CORE_ADDR loc;
+  CORE_ADDR breaks[2];
+  int opcode;
+
+  if (insert_breakpoints_p)
+    {
+
+      loc = read_pc ();
+
+      insn = read_memory_integer (loc, 4);
+
+      breaks[0] = loc + breakp_sz;
+      opcode = insn >> 26;
+      breaks[1] = branch_dest (opcode, insn, loc, breaks[0]);
+
+      /* Don't put two breakpoints on the same address. */
+      if (breaks[1] == breaks[0])
+	breaks[1] = -1;
+
+      stepBreaks[1].address = 0;
+
+      for (ii = 0; ii < 2; ++ii)
+	{
+
+	  /* ignore invalid breakpoint. */
+	  if (breaks[ii] == -1)
+	    continue;
+	  target_insert_breakpoint (breaks[ii], stepBreaks[ii].data);
+	  stepBreaks[ii].address = breaks[ii];
+	}
+
+    }
+  else
+    {
+
+      /* remove step breakpoints. */
+      for (ii = 0; ii < 2; ++ii)
+	if (stepBreaks[ii].address != 0)
+	  target_remove_breakpoint (stepBreaks[ii].address,
+				    stepBreaks[ii].data);
+    }
+  errno = 0;			/* FIXME, don't ignore errors! */
+  /* What errors?  {read,write}_memory call error().  */
+}
+
+
+/* return pc value after skipping a function prologue and also return
+   information about a function frame.
+
+   in struct rs6000_framedata fdata:
+   - frameless is TRUE, if function does not have a frame.
+   - nosavedpc is TRUE, if function does not save %pc value in its frame.
+   - offset is the initial size of this stack frame --- the amount by
+   which we decrement the sp to allocate the frame.
+   - saved_gpr is the number of the first saved gpr.
+   - saved_fpr is the number of the first saved fpr.
+   - saved_vr is the number of the first saved vr.
+   - saved_ev is the number of the first saved ev.
+   - alloca_reg is the number of the register used for alloca() handling.
+   Otherwise -1.
+   - gpr_offset is the offset of the first saved gpr from the previous frame.
+   - fpr_offset is the offset of the first saved fpr from the previous frame.
+   - vr_offset is the offset of the first saved vr from the previous frame.
+   - ev_offset is the offset of the first saved ev from the previous frame.
+   - lr_offset is the offset of the saved lr
+   - cr_offset is the offset of the saved cr
+   - vrsave_offset is the offset of the saved vrsave register
+ */
+
+#define SIGNED_SHORT(x) 						\
+  ((sizeof (short) == 2)						\
+   ? ((int)(short)(x))							\
+   : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
+
+#define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
+
+/* Limit the number of skipped non-prologue instructions, as the examining
+   of the prologue is expensive.  */
+static int max_skip_non_prologue_insns = 10;
+
+/* Given PC representing the starting address of a function, and
+   LIM_PC which is the (sloppy) limit to which to scan when looking
+   for a prologue, attempt to further refine this limit by using
+   the line data in the symbol table.  If successful, a better guess
+   on where the prologue ends is returned, otherwise the previous
+   value of lim_pc is returned.  */
+
+/* FIXME: cagney/2004-02-14: This function and logic have largely been
+   superseded by skip_prologue_using_sal.  */
+
+static CORE_ADDR
+refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc)
+{
+  struct symtab_and_line prologue_sal;
+
+  prologue_sal = find_pc_line (pc, 0);
+  if (prologue_sal.line != 0)
+    {
+      int i;
+      CORE_ADDR addr = prologue_sal.end;
+
+      /* Handle the case in which compiler's optimizer/scheduler
+         has moved instructions into the prologue.  We scan ahead
+	 in the function looking for address ranges whose corresponding
+	 line number is less than or equal to the first one that we
+	 found for the function.  (It can be less than when the
+	 scheduler puts a body instruction before the first prologue
+	 instruction.)  */
+      for (i = 2 * max_skip_non_prologue_insns; 
+           i > 0 && (lim_pc == 0 || addr < lim_pc);
+	   i--)
+        {
+	  struct symtab_and_line sal;
+
+	  sal = find_pc_line (addr, 0);
+	  if (sal.line == 0)
+	    break;
+	  if (sal.line <= prologue_sal.line 
+	      && sal.symtab == prologue_sal.symtab)
+	    {
+	      prologue_sal = sal;
+	    }
+	  addr = sal.end;
+	}
+
+      if (lim_pc == 0 || prologue_sal.end < lim_pc)
+	lim_pc = prologue_sal.end;
+    }
+  return lim_pc;
+}
+
+/* Return nonzero if the given instruction OP can be part of the prologue
+   of a function and saves a parameter on the stack.  FRAMEP should be
+   set if one of the previous instructions in the function has set the
+   Frame Pointer.  */
+
+static int
+store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
+{
+  /* Move parameters from argument registers to temporary register.  */
+  if ((op & 0xfc0007fe) == 0x7c000378)         /* mr(.)  Rx,Ry */
+    {
+      /* Rx must be scratch register r0.  */
+      const int rx_regno = (op >> 16) & 31;
+      /* Ry: Only r3 - r10 are used for parameter passing.  */
+      const int ry_regno = GET_SRC_REG (op);
+
+      if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
+        {
+          *r0_contains_arg = 1;
+          return 1;
+        }
+      else
+        return 0;
+    }
+
+  /* Save a General Purpose Register on stack.  */
+
+  if ((op & 0xfc1f0003) == 0xf8010000 ||       /* std  Rx,NUM(r1) */
+      (op & 0xfc1f0000) == 0xd8010000)         /* stfd Rx,NUM(r1) */
+    {
+      /* Rx: Only r3 - r10 are used for parameter passing.  */
+      const int rx_regno = GET_SRC_REG (op);
+
+      return (rx_regno >= 3 && rx_regno <= 10);
+    }
+           
+  /* Save a General Purpose Register on stack via the Frame Pointer.  */
+
+  if (framep &&
+      ((op & 0xfc1f0000) == 0x901f0000 ||     /* st rx,NUM(r31) */
+       (op & 0xfc1f0000) == 0x981f0000 ||     /* stb Rx,NUM(r31) */
+       (op & 0xfc1f0000) == 0xd81f0000))      /* stfd Rx,NUM(r31) */
+    {
+      /* Rx: Usually, only r3 - r10 are used for parameter passing.
+         However, the compiler sometimes uses r0 to hold an argument.  */
+      const int rx_regno = GET_SRC_REG (op);
+
+      return ((rx_regno >= 3 && rx_regno <= 10)
+              || (rx_regno == 0 && *r0_contains_arg));
+    }
+
+  if ((op & 0xfc1f0000) == 0xfc010000)         /* frsp, fp?,NUM(r1) */
+    {
+      /* Only f2 - f8 are used for parameter passing.  */
+      const int src_regno = GET_SRC_REG (op);
+
+      return (src_regno >= 2 && src_regno <= 8);
+    }
+
+  if (framep && ((op & 0xfc1f0000) == 0xfc1f0000))  /* frsp, fp?,NUM(r31) */
+    {
+      /* Only f2 - f8 are used for parameter passing.  */
+      const int src_regno = GET_SRC_REG (op);
+
+      return (src_regno >= 2 && src_regno <= 8);
+    }
+
+  /* Not an insn that saves a parameter on stack.  */
+  return 0;
+}
+
+static CORE_ADDR
+skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata)
+{
+  CORE_ADDR orig_pc = pc;
+  CORE_ADDR last_prologue_pc = pc;
+  CORE_ADDR li_found_pc = 0;
+  char buf[4];
+  unsigned long op;
+  long offset = 0;
+  long vr_saved_offset = 0;
+  int lr_reg = -1;
+  int cr_reg = -1;
+  int vr_reg = -1;
+  int ev_reg = -1;
+  long ev_offset = 0;
+  int vrsave_reg = -1;
+  int reg;
+  int framep = 0;
+  int minimal_toc_loaded = 0;
+  int prev_insn_was_prologue_insn = 1;
+  int num_skip_non_prologue_insns = 0;
+  int r0_contains_arg = 0;
+  const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch);
+  struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+  
+  /* Attempt to find the end of the prologue when no limit is specified.
+     Note that refine_prologue_limit() has been written so that it may
+     be used to "refine" the limits of non-zero PC values too, but this
+     is only safe if we 1) trust the line information provided by the
+     compiler and 2) iterate enough to actually find the end of the
+     prologue.  
+     
+     It may become a good idea at some point (for both performance and
+     accuracy) to unconditionally call refine_prologue_limit().  But,
+     until we can make a clear determination that this is beneficial,
+     we'll play it safe and only use it to obtain a limit when none
+     has been specified.  */
+  if (lim_pc == 0)
+    lim_pc = refine_prologue_limit (pc, lim_pc);
+
+  memset (fdata, 0, sizeof (struct rs6000_framedata));
+  fdata->saved_gpr = -1;
+  fdata->saved_fpr = -1;
+  fdata->saved_vr = -1;
+  fdata->saved_ev = -1;
+  fdata->alloca_reg = -1;
+  fdata->frameless = 1;
+  fdata->nosavedpc = 1;
+
+  for (;; pc += 4)
+    {
+      /* Sometimes it isn't clear if an instruction is a prologue
+         instruction or not.  When we encounter one of these ambiguous
+	 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
+	 Otherwise, we'll assume that it really is a prologue instruction. */
+      if (prev_insn_was_prologue_insn)
+	last_prologue_pc = pc;
+
+      /* Stop scanning if we've hit the limit.  */
+      if (lim_pc != 0 && pc >= lim_pc)
+	break;
+
+      prev_insn_was_prologue_insn = 1;
+
+      /* Fetch the instruction and convert it to an integer.  */
+      if (target_read_memory (pc, buf, 4))
+	break;
+      op = extract_signed_integer (buf, 4);
+
+      if ((op & 0xfc1fffff) == 0x7c0802a6)
+	{			/* mflr Rx */
+	  /* Since shared library / PIC code, which needs to get its
+	     address at runtime, can appear to save more than one link
+	     register vis:
+
+	     *INDENT-OFF*
+	     stwu r1,-304(r1)
+	     mflr r3
+	     bl 0xff570d0 (blrl)
+	     stw r30,296(r1)
+	     mflr r30
+	     stw r31,300(r1)
+	     stw r3,308(r1);
+	     ...
+	     *INDENT-ON*
+
+	     remember just the first one, but skip over additional
+	     ones.  */
+	  if (lr_reg < 0)
+	    lr_reg = (op & 0x03e00000);
+          if (lr_reg == 0)
+            r0_contains_arg = 0;
+	  continue;
+	}
+      else if ((op & 0xfc1fffff) == 0x7c000026)
+	{			/* mfcr Rx */
+	  cr_reg = (op & 0x03e00000);
+          if (cr_reg == 0)
+            r0_contains_arg = 0;
+	  continue;
+
+	}
+      else if ((op & 0xfc1f0000) == 0xd8010000)
+	{			/* stfd Rx,NUM(r1) */
+	  reg = GET_SRC_REG (op);
+	  if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
+	    {
+	      fdata->saved_fpr = reg;
+	      fdata->fpr_offset = SIGNED_SHORT (op) + offset;
+	    }
+	  continue;
+
+	}
+      else if (((op & 0xfc1f0000) == 0xbc010000) ||	/* stm Rx, NUM(r1) */
+	       (((op & 0xfc1f0000) == 0x90010000 ||	/* st rx,NUM(r1) */
+		 (op & 0xfc1f0003) == 0xf8010000) &&	/* std rx,NUM(r1) */
+		(op & 0x03e00000) >= 0x01a00000))	/* rx >= r13 */
+	{
+
+	  reg = GET_SRC_REG (op);
+	  if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
+	    {
+	      fdata->saved_gpr = reg;
+	      if ((op & 0xfc1f0003) == 0xf8010000)
+		op &= ~3UL;
+	      fdata->gpr_offset = SIGNED_SHORT (op) + offset;
+	    }
+	  continue;
+
+	}
+      else if ((op & 0xffff0000) == 0x60000000)
+        {
+	  /* nop */
+	  /* Allow nops in the prologue, but do not consider them to
+	     be part of the prologue unless followed by other prologue
+	     instructions. */
+	  prev_insn_was_prologue_insn = 0;
+	  continue;
+
+	}
+      else if ((op & 0xffff0000) == 0x3c000000)
+	{			/* addis 0,0,NUM, used
+				   for >= 32k frames */
+	  fdata->offset = (op & 0x0000ffff) << 16;
+	  fdata->frameless = 0;
+          r0_contains_arg = 0;
+	  continue;
+
+	}
+      else if ((op & 0xffff0000) == 0x60000000)
+	{			/* ori 0,0,NUM, 2nd ha
+				   lf of >= 32k frames */
+	  fdata->offset |= (op & 0x0000ffff);
+	  fdata->frameless = 0;
+          r0_contains_arg = 0;
+	  continue;
+
+	}
+      else if (lr_reg != -1 &&
+	       /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
+	       (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
+		/* stw Rx, NUM(r1) */
+		((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
+		/* stwu Rx, NUM(r1) */
+		((op & 0xffff0000) == (lr_reg | 0x94010000))))
+	{	/* where Rx == lr */
+	  fdata->lr_offset = offset;
+	  fdata->nosavedpc = 0;
+	  lr_reg = 0;
+	  if ((op & 0xfc000003) == 0xf8000000 ||	/* std */
+	      (op & 0xfc000000) == 0x90000000)		/* stw */
+	    {
+	      /* Does not update r1, so add displacement to lr_offset.  */
+	      fdata->lr_offset += SIGNED_SHORT (op);
+	    }
+	  continue;
+
+	}
+      else if (cr_reg != -1 &&
+	       /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
+	       (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
+		/* stw Rx, NUM(r1) */
+		((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
+		/* stwu Rx, NUM(r1) */
+		((op & 0xffff0000) == (cr_reg | 0x94010000))))
+	{	/* where Rx == cr */
+	  fdata->cr_offset = offset;
+	  cr_reg = 0;
+	  if ((op & 0xfc000003) == 0xf8000000 ||
+	      (op & 0xfc000000) == 0x90000000)
+	    {
+	      /* Does not update r1, so add displacement to cr_offset.  */
+	      fdata->cr_offset += SIGNED_SHORT (op);
+	    }
+	  continue;
+
+	}
+      else if (op == 0x48000005)
+	{			/* bl .+4 used in 
+				   -mrelocatable */
+	  continue;
+
+	}
+      else if (op == 0x48000004)
+	{			/* b .+4 (xlc) */
+	  break;
+
+	}
+      else if ((op & 0xffff0000) == 0x3fc00000 ||  /* addis 30,0,foo@ha, used
+						      in V.4 -mminimal-toc */
+	       (op & 0xffff0000) == 0x3bde0000)
+	{			/* addi 30,30,foo@l */
+	  continue;
+
+	}
+      else if ((op & 0xfc000001) == 0x48000001)
+	{			/* bl foo, 
+				   to save fprs??? */
+
+	  fdata->frameless = 0;
+	  /* Don't skip over the subroutine call if it is not within
+	     the first three instructions of the prologue.  */
+	  if ((pc - orig_pc) > 8)
+	    break;
+
+	  op = read_memory_integer (pc + 4, 4);
+
+	  /* At this point, make sure this is not a trampoline
+	     function (a function that simply calls another functions,
+	     and nothing else).  If the next is not a nop, this branch
+	     was part of the function prologue. */
+
+	  if (op == 0x4def7b82 || op == 0)	/* crorc 15, 15, 15 */
+	    break;		/* don't skip over 
+				   this branch */
+	  continue;
+
+	}
+      /* update stack pointer */
+      else if ((op & 0xfc1f0000) == 0x94010000)
+	{		/* stu rX,NUM(r1) ||  stwu rX,NUM(r1) */
+	  fdata->frameless = 0;
+	  fdata->offset = SIGNED_SHORT (op);
+	  offset = fdata->offset;
+	  continue;
+	}
+      else if ((op & 0xfc1f016a) == 0x7c01016e)
+	{			/* stwux rX,r1,rY */
+	  /* no way to figure out what r1 is going to be */
+	  fdata->frameless = 0;
+	  offset = fdata->offset;
+	  continue;
+	}
+      else if ((op & 0xfc1f0003) == 0xf8010001)
+	{			/* stdu rX,NUM(r1) */
+	  fdata->frameless = 0;
+	  fdata->offset = SIGNED_SHORT (op & ~3UL);
+	  offset = fdata->offset;
+	  continue;
+	}
+      else if ((op & 0xfc1f016a) == 0x7c01016a)
+	{			/* stdux rX,r1,rY */
+	  /* no way to figure out what r1 is going to be */
+	  fdata->frameless = 0;
+	  offset = fdata->offset;
+	  continue;
+	}
+      /* Load up minimal toc pointer */
+      else if (((op >> 22) == 0x20f	||	/* l r31,... or l r30,... */
+	       (op >> 22) == 0x3af)		/* ld r31,... or ld r30,... */
+	       && !minimal_toc_loaded)
+	{
+	  minimal_toc_loaded = 1;
+	  continue;
+
+	  /* move parameters from argument registers to local variable
+             registers */
+ 	}
+      else if ((op & 0xfc0007fe) == 0x7c000378 &&	/* mr(.)  Rx,Ry */
+               (((op >> 21) & 31) >= 3) &&              /* R3 >= Ry >= R10 */
+               (((op >> 21) & 31) <= 10) &&
+               ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
+	{
+	  continue;
+
+	  /* store parameters in stack */
+	}
+      /* Move parameters from argument registers to temporary register.  */
+      else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
+        {
+	  continue;
+
+	  /* Set up frame pointer */
+	}
+      else if (op == 0x603f0000	/* oril r31, r1, 0x0 */
+	       || op == 0x7c3f0b78)
+	{			/* mr r31, r1 */
+	  fdata->frameless = 0;
+	  framep = 1;
+	  fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
+	  continue;
+
+	  /* Another way to set up the frame pointer.  */
+	}
+      else if ((op & 0xfc1fffff) == 0x38010000)
+	{			/* addi rX, r1, 0x0 */
+	  fdata->frameless = 0;
+	  framep = 1;
+	  fdata->alloca_reg = (tdep->ppc_gp0_regnum
+			       + ((op & ~0x38010000) >> 21));
+	  continue;
+	}
+      /* AltiVec related instructions.  */
+      /* Store the vrsave register (spr 256) in another register for
+	 later manipulation, or load a register into the vrsave
+	 register.  2 instructions are used: mfvrsave and
+	 mtvrsave.  They are shorthand notation for mfspr Rn, SPR256
+	 and mtspr SPR256, Rn.  */
+      /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
+	 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110  */
+      else if ((op & 0xfc1fffff) == 0x7c0042a6)    /* mfvrsave Rn */
+	{
+          vrsave_reg = GET_SRC_REG (op);
+	  continue;
+	}
+      else if ((op & 0xfc1fffff) == 0x7c0043a6)     /* mtvrsave Rn */
+        {
+          continue;
+        }
+      /* Store the register where vrsave was saved to onto the stack:
+         rS is the register where vrsave was stored in a previous
+	 instruction.  */
+      /* 100100 sssss 00001 dddddddd dddddddd */
+      else if ((op & 0xfc1f0000) == 0x90010000)     /* stw rS, d(r1) */
+        {
+          if (vrsave_reg == GET_SRC_REG (op))
+	    {
+	      fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
+	      vrsave_reg = -1;
+	    }
+          continue;
+        }
+      /* Compute the new value of vrsave, by modifying the register
+         where vrsave was saved to.  */
+      else if (((op & 0xfc000000) == 0x64000000)    /* oris Ra, Rs, UIMM */
+	       || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
+	{
+	  continue;
+	}
+      /* li r0, SIMM (short for addi r0, 0, SIMM).  This is the first
+	 in a pair of insns to save the vector registers on the
+	 stack.  */
+      /* 001110 00000 00000 iiii iiii iiii iiii  */
+      /* 001110 01110 00000 iiii iiii iiii iiii  */
+      else if ((op & 0xffff0000) == 0x38000000         /* li r0, SIMM */
+               || (op & 0xffff0000) == 0x39c00000)     /* li r14, SIMM */
+	{
+          if ((op & 0xffff0000) == 0x38000000)
+            r0_contains_arg = 0;
+	  li_found_pc = pc;
+	  vr_saved_offset = SIGNED_SHORT (op);
+
+          /* This insn by itself is not part of the prologue, unless
+             if part of the pair of insns mentioned above. So do not
+             record this insn as part of the prologue yet.  */
+          prev_insn_was_prologue_insn = 0;
+	}
+      /* Store vector register S at (r31+r0) aligned to 16 bytes.  */      
+      /* 011111 sssss 11111 00000 00111001110 */
+      else if ((op & 0xfc1fffff) == 0x7c1f01ce)   /* stvx Vs, R31, R0 */
+        {
+	  if (pc == (li_found_pc + 4))
+	    {
+	      vr_reg = GET_SRC_REG (op);
+	      /* If this is the first vector reg to be saved, or if
+		 it has a lower number than others previously seen,
+		 reupdate the frame info.  */
+	      if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
+		{
+		  fdata->saved_vr = vr_reg;
+		  fdata->vr_offset = vr_saved_offset + offset;
+		}
+	      vr_saved_offset = -1;
+	      vr_reg = -1;
+	      li_found_pc = 0;
+	    }
+	}
+      /* End AltiVec related instructions.  */
+
+      /* Start BookE related instructions.  */
+      /* Store gen register S at (r31+uimm).
+         Any register less than r13 is volatile, so we don't care.  */
+      /* 000100 sssss 11111 iiiii 01100100001 */
+      else if (arch_info->mach == bfd_mach_ppc_e500
+	       && (op & 0xfc1f07ff) == 0x101f0321)    /* evstdd Rs,uimm(R31) */
+	{
+          if ((op & 0x03e00000) >= 0x01a00000)	/* Rs >= r13 */
+	    {
+              unsigned int imm;
+	      ev_reg = GET_SRC_REG (op);
+              imm = (op >> 11) & 0x1f;
+	      ev_offset = imm * 8;
+	      /* If this is the first vector reg to be saved, or if
+		 it has a lower number than others previously seen,
+		 reupdate the frame info.  */
+	      if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
+		{
+		  fdata->saved_ev = ev_reg;
+		  fdata->ev_offset = ev_offset + offset;
+		}
+	    }
+          continue;
+        }
+      /* Store gen register rS at (r1+rB).  */
+      /* 000100 sssss 00001 bbbbb 01100100000 */
+      else if (arch_info->mach == bfd_mach_ppc_e500
+	       && (op & 0xffe007ff) == 0x13e00320)     /* evstddx RS,R1,Rb */
+	{
+          if (pc == (li_found_pc + 4))
+            {
+              ev_reg = GET_SRC_REG (op);
+	      /* If this is the first vector reg to be saved, or if
+                 it has a lower number than others previously seen,
+                 reupdate the frame info.  */
+              /* We know the contents of rB from the previous instruction.  */
+	      if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
+		{
+                  fdata->saved_ev = ev_reg;
+                  fdata->ev_offset = vr_saved_offset + offset;
+		}
+	      vr_saved_offset = -1;
+	      ev_reg = -1;
+	      li_found_pc = 0;
+            }
+          continue;
+        }
+      /* Store gen register r31 at (rA+uimm).  */
+      /* 000100 11111 aaaaa iiiii 01100100001 */
+      else if (arch_info->mach == bfd_mach_ppc_e500
+	       && (op & 0xffe007ff) == 0x13e00321)   /* evstdd R31,Ra,UIMM */
+        {
+          /* Wwe know that the source register is 31 already, but
+             it can't hurt to compute it.  */
+	  ev_reg = GET_SRC_REG (op);
+          ev_offset = ((op >> 11) & 0x1f) * 8;
+	  /* If this is the first vector reg to be saved, or if
+	     it has a lower number than others previously seen,
+	     reupdate the frame info.  */
+	  if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
+	    {
+	      fdata->saved_ev = ev_reg;
+	      fdata->ev_offset = ev_offset + offset;
+	    }
+
+	  continue;
+      	}
+      /* Store gen register S at (r31+r0).
+         Store param on stack when offset from SP bigger than 4 bytes.  */
+      /* 000100 sssss 11111 00000 01100100000 */
+      else if (arch_info->mach == bfd_mach_ppc_e500
+	       && (op & 0xfc1fffff) == 0x101f0320)     /* evstddx Rs,R31,R0 */
+	{
+          if (pc == (li_found_pc + 4))
+            {
+              if ((op & 0x03e00000) >= 0x01a00000)
+		{
+		  ev_reg = GET_SRC_REG (op);
+		  /* If this is the first vector reg to be saved, or if
+		     it has a lower number than others previously seen,
+		     reupdate the frame info.  */
+                  /* We know the contents of r0 from the previous
+                     instruction.  */
+		  if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
+		    {
+		      fdata->saved_ev = ev_reg;
+		      fdata->ev_offset = vr_saved_offset + offset;
+		    }
+		  ev_reg = -1;
+		}
+	      vr_saved_offset = -1;
+	      li_found_pc = 0;
+	      continue;
+            }
+	}
+      /* End BookE related instructions.  */
+
+      else
+	{
+	  /* Not a recognized prologue instruction.
+	     Handle optimizer code motions into the prologue by continuing
+	     the search if we have no valid frame yet or if the return
+	     address is not yet saved in the frame.  */
+	  if (fdata->frameless == 0
+	      && (lr_reg == -1 || fdata->nosavedpc == 0))
+	    break;
+
+	  if (op == 0x4e800020		/* blr */
+	      || op == 0x4e800420)	/* bctr */
+	    /* Do not scan past epilogue in frameless functions or
+	       trampolines.  */
+	    break;
+	  if ((op & 0xf4000000) == 0x40000000) /* bxx */
+	    /* Never skip branches.  */
+	    break;
+
+	  if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
+	    /* Do not scan too many insns, scanning insns is expensive with
+	       remote targets.  */
+	    break;
+
+	  /* Continue scanning.  */
+	  prev_insn_was_prologue_insn = 0;
+	  continue;
+	}
+    }
+
+#if 0
+/* I have problems with skipping over __main() that I need to address
+ * sometime. Previously, I used to use misc_function_vector which
+ * didn't work as well as I wanted to be.  -MGO */
+
+  /* If the first thing after skipping a prolog is a branch to a function,
+     this might be a call to an initializer in main(), introduced by gcc2.
+     We'd like to skip over it as well.  Fortunately, xlc does some extra
+     work before calling a function right after a prologue, thus we can
+     single out such gcc2 behaviour.  */
+
+
+  if ((op & 0xfc000001) == 0x48000001)
+    {				/* bl foo, an initializer function? */
+      op = read_memory_integer (pc + 4, 4);
+
+      if (op == 0x4def7b82)
+	{			/* cror 0xf, 0xf, 0xf (nop) */
+
+	  /* Check and see if we are in main.  If so, skip over this
+	     initializer function as well.  */
+
+	  tmp = find_pc_misc_function (pc);
+	  if (tmp >= 0
+	      && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
+	    return pc + 8;
+	}
+    }
+#endif /* 0 */
+
+  fdata->offset = -fdata->offset;
+  return last_prologue_pc;
+}
+
+
+/*************************************************************************
+  Support for creating pushing a dummy frame into the stack, and popping
+  frames, etc. 
+*************************************************************************/
+
+
+/* All the ABI's require 16 byte alignment.  */
+static CORE_ADDR
+rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
+{
+  return (addr & -16);
+}
+
+/* Pass the arguments in either registers, or in the stack. In RS/6000,
+   the first eight words of the argument list (that might be less than
+   eight parameters if some parameters occupy more than one word) are
+   passed in r3..r10 registers.  float and double parameters are
+   passed in fpr's, in addition to that.  Rest of the parameters if any
+   are passed in user stack.  There might be cases in which half of the
+   parameter is copied into registers, the other half is pushed into
+   stack.
+
+   Stack must be aligned on 64-bit boundaries when synthesizing
+   function calls.
+
+   If the function is returning a structure, then the return address is passed
+   in r3, then the first 7 words of the parameters can be passed in registers,
+   starting from r4.  */
+
+static CORE_ADDR
+rs6000_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
+			struct regcache *regcache, CORE_ADDR bp_addr,
+			int nargs, struct value **args, CORE_ADDR sp,
+			int struct_return, CORE_ADDR struct_addr)
+{
+  struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+  int ii;
+  int len = 0;
+  int argno;			/* current argument number */
+  int argbytes;			/* current argument byte */
+  char tmp_buffer[50];
+  int f_argno = 0;		/* current floating point argno */
+  int wordsize = gdbarch_tdep (current_gdbarch)->wordsize;
+  CORE_ADDR func_addr = find_function_addr (function, NULL);
+
+  struct value *arg = 0;
+  struct type *type;
+
+  CORE_ADDR saved_sp;
+
+  /* The calling convention this function implements assumes the
+     processor has floating-point registers.  We shouldn't be using it
+     on PPC variants that lack them.  */
+  gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
+
+  /* The first eight words of ther arguments are passed in registers.
+     Copy them appropriately.  */
+  ii = 0;
+
+  /* If the function is returning a `struct', then the first word
+     (which will be passed in r3) is used for struct return address.
+     In that case we should advance one word and start from r4
+     register to copy parameters.  */
+  if (struct_return)
+    {
+      regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
+				   struct_addr);
+      ii++;
+    }
+
+/* 
+   effectively indirect call... gcc does...
+
+   return_val example( float, int);
+
+   eabi: 
+   float in fp0, int in r3
+   offset of stack on overflow 8/16
+   for varargs, must go by type.
+   power open:
+   float in r3&r4, int in r5
+   offset of stack on overflow different 
+   both: 
+   return in r3 or f0.  If no float, must study how gcc emulates floats;
+   pay attention to arg promotion.  
+   User may have to cast\args to handle promotion correctly 
+   since gdb won't know if prototype supplied or not.
+ */
+
+  for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii)
+    {
+      int reg_size = register_size (current_gdbarch, ii + 3);
+
+      arg = args[argno];
+      type = check_typedef (VALUE_TYPE (arg));
+      len = TYPE_LENGTH (type);
+
+      if (TYPE_CODE (type) == TYPE_CODE_FLT)
+	{
+
+	  /* Floating point arguments are passed in fpr's, as well as gpr's.
+	     There are 13 fpr's reserved for passing parameters. At this point
+	     there is no way we would run out of them.  */
+
+	  if (len > 8)
+	    printf_unfiltered ("Fatal Error: a floating point parameter "
+                               "#%d with a size > 8 is found!\n", argno);
+
+	  memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE
+                                        (tdep->ppc_fp0_regnum + 1 + f_argno)],
+		  VALUE_CONTENTS (arg),
+		  len);
+	  ++f_argno;
+	}
+
+      if (len > reg_size)
+	{
+
+	  /* Argument takes more than one register.  */
+	  while (argbytes < len)
+	    {
+	      memset (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 0,
+		      reg_size);
+	      memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)],
+		      ((char *) VALUE_CONTENTS (arg)) + argbytes,
+		      (len - argbytes) > reg_size
+		        ? reg_size : len - argbytes);
+	      ++ii, argbytes += reg_size;
+
+	      if (ii >= 8)
+		goto ran_out_of_registers_for_arguments;
+	    }
+	  argbytes = 0;
+	  --ii;
+	}
+      else
+	{
+	  /* Argument can fit in one register.  No problem.  */
+	  int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0;
+	  memset (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 0, reg_size);
+	  memcpy ((char *)&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)] + adj, 
+	          VALUE_CONTENTS (arg), len);
+	}
+      ++argno;
+    }
+
+ran_out_of_registers_for_arguments:
+
+  saved_sp = read_sp ();
+
+  /* Location for 8 parameters are always reserved.  */
+  sp -= wordsize * 8;
+
+  /* Another six words for back chain, TOC register, link register, etc.  */
+  sp -= wordsize * 6;
+
+  /* Stack pointer must be quadword aligned.  */
+  sp &= -16;
+
+  /* If there are more arguments, allocate space for them in 
+     the stack, then push them starting from the ninth one.  */
+
+  if ((argno < nargs) || argbytes)
+    {
+      int space = 0, jj;
+
+      if (argbytes)
+	{
+	  space += ((len - argbytes + 3) & -4);
+	  jj = argno + 1;
+	}
+      else
+	jj = argno;
+
+      for (; jj < nargs; ++jj)
+	{
+	  struct value *val = args[jj];
+	  space += ((TYPE_LENGTH (VALUE_TYPE (val))) + 3) & -4;
+	}
+
+      /* Add location required for the rest of the parameters.  */
+      space = (space + 15) & -16;
+      sp -= space;
+
+      /* This is another instance we need to be concerned about
+         securing our stack space. If we write anything underneath %sp
+         (r1), we might conflict with the kernel who thinks he is free
+         to use this area.  So, update %sp first before doing anything
+         else.  */
+
+      regcache_raw_write_signed (regcache, SP_REGNUM, sp);
+
+      /* If the last argument copied into the registers didn't fit there 
+         completely, push the rest of it into stack.  */
+
+      if (argbytes)
+	{
+	  write_memory (sp + 24 + (ii * 4),
+			((char *) VALUE_CONTENTS (arg)) + argbytes,
+			len - argbytes);
+	  ++argno;
+	  ii += ((len - argbytes + 3) & -4) / 4;
+	}
+
+      /* Push the rest of the arguments into stack.  */
+      for (; argno < nargs; ++argno)
+	{
+
+	  arg = args[argno];
+	  type = check_typedef (VALUE_TYPE (arg));
+	  len = TYPE_LENGTH (type);
+
+
+	  /* Float types should be passed in fpr's, as well as in the
+             stack.  */
+	  if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13)
+	    {
+
+	      if (len > 8)
+		printf_unfiltered ("Fatal Error: a floating point parameter"
+                                   " #%d with a size > 8 is found!\n", argno);
+
+	      memcpy (&(deprecated_registers
+                        [DEPRECATED_REGISTER_BYTE
+                         (tdep->ppc_fp0_regnum + 1 + f_argno)]),
+		      VALUE_CONTENTS (arg),
+		      len);
+	      ++f_argno;
+	    }
+
+	  write_memory (sp + 24 + (ii * 4),
+                        (char *) VALUE_CONTENTS (arg),
+                        len);
+	  ii += ((len + 3) & -4) / 4;
+	}
+    }
+
+  /* Set the stack pointer.  According to the ABI, the SP is meant to
+     be set _before_ the corresponding stack space is used.  On AIX,
+     this even applies when the target has been completely stopped!
+     Not doing this can lead to conflicts with the kernel which thinks
+     that it still has control over this not-yet-allocated stack
+     region.  */
+  regcache_raw_write_signed (regcache, SP_REGNUM, sp);
+
+  /* Set back chain properly.  */
+  store_unsigned_integer (tmp_buffer, 4, saved_sp);
+  write_memory (sp, tmp_buffer, 4);
+
+  /* Point the inferior function call's return address at the dummy's
+     breakpoint.  */
+  regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
+
+  /* Set the TOC register, get the value from the objfile reader
+     which, in turn, gets it from the VMAP table.  */
+  if (rs6000_find_toc_address_hook != NULL)
+    {
+      CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr);
+      regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue);
+    }
+
+  target_store_registers (-1);
+  return sp;
+}
+
+/* PowerOpen always puts structures in memory.  Vectors, which were
+   added later, do get returned in a register though.  */
+
+static int     
+rs6000_use_struct_convention (int gcc_p, struct type *value_type)
+{  
+  if ((TYPE_LENGTH (value_type) == 16 || TYPE_LENGTH (value_type) == 8)
+      && TYPE_VECTOR (value_type))
+    return 0;                            
+  return 1;
+}
+
+static void
+rs6000_extract_return_value (struct type *valtype, char *regbuf, char *valbuf)
+{
+  int offset = 0;
+  struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+  /* The calling convention this function implements assumes the
+     processor has floating-point registers.  We shouldn't be using it
+     on PPC variants that lack them.  */
+  gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
+
+  if (TYPE_CODE (valtype) == TYPE_CODE_FLT)
+    {
+
+      /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes.
+         We need to truncate the return value into float size (4 byte) if
+         necessary.  */
+
+      convert_typed_floating (&regbuf[DEPRECATED_REGISTER_BYTE
+                                      (tdep->ppc_fp0_regnum + 1)],
+                              builtin_type_double,
+                              valbuf,
+                              valtype);
+    }
+  else if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY
+           && TYPE_LENGTH (valtype) == 16
+           && TYPE_VECTOR (valtype))
+    {
+      memcpy (valbuf, regbuf + DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2),
+	      TYPE_LENGTH (valtype));
+    }
+  else
+    {
+      /* return value is copied starting from r3. */
+      if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
+	  && TYPE_LENGTH (valtype) < register_size (current_gdbarch, 3))
+	offset = register_size (current_gdbarch, 3) - TYPE_LENGTH (valtype);
+
+      memcpy (valbuf,
+	      regbuf + DEPRECATED_REGISTER_BYTE (3) + offset,
+	      TYPE_LENGTH (valtype));
+    }
+}
+
+/* Return whether handle_inferior_event() should proceed through code
+   starting at PC in function NAME when stepping.
+
+   The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
+   handle memory references that are too distant to fit in instructions
+   generated by the compiler.  For example, if 'foo' in the following
+   instruction:
+
+     lwz r9,foo(r2)
+
+   is greater than 32767, the linker might replace the lwz with a branch to
+   somewhere in @FIX1 that does the load in 2 instructions and then branches
+   back to where execution should continue.
+
+   GDB should silently step over @FIX code, just like AIX dbx does.
+   Unfortunately, the linker uses the "b" instruction for the branches,
+   meaning that the link register doesn't get set.  Therefore, GDB's usual
+   step_over_function() mechanism won't work.
+
+   Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and SKIP_TRAMPOLINE_CODE hooks
+   in handle_inferior_event() to skip past @FIX code.  */
+
+int
+rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name)
+{
+  return name && !strncmp (name, "@FIX", 4);
+}
+
+/* Skip code that the user doesn't want to see when stepping:
+
+   1. Indirect function calls use a piece of trampoline code to do context
+   switching, i.e. to set the new TOC table.  Skip such code if we are on
+   its first instruction (as when we have single-stepped to here).
+
+   2. Skip shared library trampoline code (which is different from
+   indirect function call trampolines).
+
+   3. Skip bigtoc fixup code.
+
+   Result is desired PC to step until, or NULL if we are not in
+   code that should be skipped.  */
+
+CORE_ADDR
+rs6000_skip_trampoline_code (CORE_ADDR pc)
+{
+  unsigned int ii, op;
+  int rel;
+  CORE_ADDR solib_target_pc;
+  struct minimal_symbol *msymbol;
+
+  static unsigned trampoline_code[] =
+  {
+    0x800b0000,			/*     l   r0,0x0(r11)  */
+    0x90410014,			/*    st   r2,0x14(r1)  */
+    0x7c0903a6,			/* mtctr   r0           */
+    0x804b0004,			/*     l   r2,0x4(r11)  */
+    0x816b0008,			/*     l  r11,0x8(r11)  */
+    0x4e800420,			/*  bctr                */
+    0x4e800020,			/*    br                */
+    0
+  };
+
+  /* Check for bigtoc fixup code.  */
+  msymbol = lookup_minimal_symbol_by_pc (pc);
+  if (msymbol && rs6000_in_solib_return_trampoline (pc, DEPRECATED_SYMBOL_NAME (msymbol)))
+    {
+      /* Double-check that the third instruction from PC is relative "b".  */
+      op = read_memory_integer (pc + 8, 4);
+      if ((op & 0xfc000003) == 0x48000000)
+	{
+	  /* Extract bits 6-29 as a signed 24-bit relative word address and
+	     add it to the containing PC.  */
+	  rel = ((int)(op << 6) >> 6);
+	  return pc + 8 + rel;
+	}
+    }
+
+  /* If pc is in a shared library trampoline, return its target.  */
+  solib_target_pc = find_solib_trampoline_target (pc);
+  if (solib_target_pc)
+    return solib_target_pc;
+
+  for (ii = 0; trampoline_code[ii]; ++ii)
+    {
+      op = read_memory_integer (pc + (ii * 4), 4);
+      if (op != trampoline_code[ii])
+	return 0;
+    }
+  ii = read_register (11);	/* r11 holds destination addr   */
+  pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */
+  return pc;
+}
+
+/* Return the size of register REG when words are WORDSIZE bytes long.  If REG
+   isn't available with that word size, return 0.  */
+
+static int
+regsize (const struct reg *reg, int wordsize)
+{
+  return wordsize == 8 ? reg->sz64 : reg->sz32;
+}
+
+/* Return the name of register number N, or null if no such register exists
+   in the current architecture.  */
+
+static const char *
+rs6000_register_name (int n)
+{
+  struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+  const struct reg *reg = tdep->regs + n;
+
+  if (!regsize (reg, tdep->wordsize))
+    return NULL;
+  return reg->name;
+}
+
+/* Return the GDB type object for the "standard" data type
+   of data in register N.  */
+
+static struct type *
+rs6000_register_type (struct gdbarch *gdbarch, int n)
+{
+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+  const struct reg *reg = tdep->regs + n;
+
+  if (reg->fpr)
+    return builtin_type_double;
+  else
+    {
+      int size = regsize (reg, tdep->wordsize);
+      switch (size)
+	{
+	case 0:
+	  return builtin_type_int0;
+	case 4:
+	  return builtin_type_uint32;
+	case 8:
+	  if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum)
+	    return builtin_type_vec64;
+	  else
+	    return builtin_type_uint64;
+	  break;
+	case 16:
+	  return builtin_type_vec128;
+	  break;
+	default:
+	  internal_error (__FILE__, __LINE__, "Register %d size %d unknown",
+			  n, size);
+	}
+    }
+}
+
+/* The register format for RS/6000 floating point registers is always
+   double, we need a conversion if the memory format is float.  */
+
+static int
+rs6000_convert_register_p (int regnum, struct type *type)
+{
+  const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
+  
+  return (reg->fpr
+          && TYPE_CODE (type) == TYPE_CODE_FLT
+          && TYPE_LENGTH (type) != TYPE_LENGTH (builtin_type_double));
+}
+
+static void
+rs6000_register_to_value (struct frame_info *frame,
+                          int regnum,
+                          struct type *type,
+                          void *to)
+{
+  const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
+  char from[MAX_REGISTER_SIZE];
+  
+  gdb_assert (reg->fpr);
+  gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
+
+  get_frame_register (frame, regnum, from);
+  convert_typed_floating (from, builtin_type_double, to, type);
+}
+
+static void
+rs6000_value_to_register (struct frame_info *frame,
+                          int regnum,
+                          struct type *type,
+                          const void *from)
+{
+  const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
+  char to[MAX_REGISTER_SIZE];
+
+  gdb_assert (reg->fpr);
+  gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
+
+  convert_typed_floating (from, type, to, builtin_type_double);
+  put_frame_register (frame, regnum, to);
+}
+
+/* Move SPE vector register values between a 64-bit buffer and the two
+   32-bit raw register halves in a regcache.  This function handles
+   both splitting a 64-bit value into two 32-bit halves, and joining
+   two halves into a whole 64-bit value, depending on the function
+   passed as the MOVE argument.
+
+   EV_REG must be the number of an SPE evN vector register --- a
+   pseudoregister.  REGCACHE must be a regcache, and BUFFER must be a
+   64-bit buffer.
+
+   Call MOVE once for each 32-bit half of that register, passing
+   REGCACHE, the number of the raw register corresponding to that
+   half, and the address of the appropriate half of BUFFER.
+
+   For example, passing 'regcache_raw_read' as the MOVE function will
+   fill BUFFER with the full 64-bit contents of EV_REG.  Or, passing
+   'regcache_raw_supply' will supply the contents of BUFFER to the
+   appropriate pair of raw registers in REGCACHE.
+
+   You may need to cast away some 'const' qualifiers when passing
+   MOVE, since this function can't tell at compile-time which of
+   REGCACHE or BUFFER is acting as the source of the data.  If C had
+   co-variant type qualifiers, ...  */
+static void
+e500_move_ev_register (void (*move) (struct regcache *regcache,
+                                     int regnum, void *buf),
+                       struct regcache *regcache, int ev_reg,
+                       void *buffer)
+{
+  struct gdbarch *arch = get_regcache_arch (regcache);
+  struct gdbarch_tdep *tdep = gdbarch_tdep (arch); 
+  int reg_index;
+  char *byte_buffer = buffer;
+
+  gdb_assert (tdep->ppc_ev0_regnum <= ev_reg
+              && ev_reg < tdep->ppc_ev0_regnum + ppc_num_gprs);
+
+  reg_index = ev_reg - tdep->ppc_ev0_regnum;
+
+  if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+    {
+      move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer);
+      move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4);
+    }
+  else
+    {
+      move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
+      move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4);
+    }
+}
+
+static void
+e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
+			   int reg_nr, void *buffer)
+{
+  struct gdbarch *regcache_arch = get_regcache_arch (regcache);
+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 
+
+  gdb_assert (regcache_arch == gdbarch);
+ 
+  if (tdep->ppc_ev0_regnum <= reg_nr
+      && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs)
+    e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer);
+  else
+    internal_error (__FILE__, __LINE__,
+                    "e500_pseudo_register_read: "
+                    "called on unexpected register '%s' (%d)",
+                    gdbarch_register_name (gdbarch, reg_nr), reg_nr);
+}
+
+static void
+e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
+			    int reg_nr, const void *buffer)
+{
+  struct gdbarch *regcache_arch = get_regcache_arch (regcache);
+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 
+
+  gdb_assert (regcache_arch == gdbarch);
+ 
+  if (tdep->ppc_ev0_regnum <= reg_nr
+      && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs)
+    e500_move_ev_register ((void (*) (struct regcache *, int, void *))
+                           regcache_raw_write,
+                           regcache, reg_nr, (void *) buffer);
+  else
+    internal_error (__FILE__, __LINE__,
+                    "e500_pseudo_register_read: "
+                    "called on unexpected register '%s' (%d)",
+                    gdbarch_register_name (gdbarch, reg_nr), reg_nr);
+}
+
+/* The E500 needs a custom reggroup function: it has anonymous raw
+   registers, and default_register_reggroup_p assumes that anonymous
+   registers are not members of any reggroup.  */
+static int
+e500_register_reggroup_p (struct gdbarch *gdbarch,
+                          int regnum,
+                          struct reggroup *group)
+{
+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+  /* The save and restore register groups need to include the
+     upper-half registers, even though they're anonymous.  */
+  if ((group == save_reggroup
+       || group == restore_reggroup)
+      && (tdep->ppc_ev0_upper_regnum <= regnum
+          && regnum < tdep->ppc_ev0_upper_regnum + ppc_num_gprs))
+    return 1;
+
+  /* In all other regards, the default reggroup definition is fine.  */
+  return default_register_reggroup_p (gdbarch, regnum, group);
+}
+
+/* Convert a DBX STABS register number to a GDB register number.  */
+static int
+rs6000_stab_reg_to_regnum (int num)
+{
+  struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+  if (0 <= num && num <= 31)
+    return tdep->ppc_gp0_regnum + num;
+  else if (32 <= num && num <= 63)
+    /* FIXME: jimb/2004-05-05: What should we do when the debug info
+       specifies registers the architecture doesn't have?  Our
+       callers don't check the value we return.  */
+    return tdep->ppc_fp0_regnum + (num - 32);
+  else if (77 <= num && num <= 108)
+    return tdep->ppc_vr0_regnum + (num - 77);
+  else if (1200 <= num && num < 1200 + 32)
+    return tdep->ppc_ev0_regnum + (num - 1200);
+  else
+    switch (num)
+      {
+      case 64: 
+        return tdep->ppc_mq_regnum;
+      case 65:
+        return tdep->ppc_lr_regnum;
+      case 66: 
+        return tdep->ppc_ctr_regnum;
+      case 76: 
+        return tdep->ppc_xer_regnum;
+      case 109:
+        return tdep->ppc_vrsave_regnum;
+      case 110:
+        return tdep->ppc_vrsave_regnum - 1; /* vscr */
+      case 111:
+        return tdep->ppc_acc_regnum;
+      case 112:
+        return tdep->ppc_spefscr_regnum;
+      default: 
+        return num;
+      }
+}
+
+
+/* Convert a Dwarf 2 register number to a GDB register number.  */
+static int
+rs6000_dwarf2_reg_to_regnum (int num)
+{
+  struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+  if (0 <= num && num <= 31)
+    return tdep->ppc_gp0_regnum + num;
+  else if (32 <= num && num <= 63)
+    /* FIXME: jimb/2004-05-05: What should we do when the debug info
+       specifies registers the architecture doesn't have?  Our
+       callers don't check the value we return.  */
+    return tdep->ppc_fp0_regnum + (num - 32);
+  else if (1124 <= num && num < 1124 + 32)
+    return tdep->ppc_vr0_regnum + (num - 1124);
+  else if (1200 <= num && num < 1200 + 32)
+    return tdep->ppc_ev0_regnum + (num - 1200);
+  else
+    switch (num)
+      {
+      case 67:
+        return tdep->ppc_vrsave_regnum - 1; /* vscr */
+      case 99:
+        return tdep->ppc_acc_regnum;
+      case 100:
+        return tdep->ppc_mq_regnum;
+      case 101:
+        return tdep->ppc_xer_regnum;
+      case 108:
+        return tdep->ppc_lr_regnum;
+      case 109:
+        return tdep->ppc_ctr_regnum;
+      case 356:
+        return tdep->ppc_vrsave_regnum;
+      case 612:
+        return tdep->ppc_spefscr_regnum;
+      default:
+        return num;
+      }
+}
+
+
+static void
+rs6000_store_return_value (struct type *type,
+                           struct regcache *regcache,
+                           const void *valbuf)
+{
+  struct gdbarch *gdbarch = get_regcache_arch (regcache);
+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+  int regnum = -1;
+
+  /* The calling convention this function implements assumes the
+     processor has floating-point registers.  We shouldn't be using it
+     on PPC variants that lack them.  */
+  gdb_assert (ppc_floating_point_unit_p (gdbarch));
+
+  if (TYPE_CODE (type) == TYPE_CODE_FLT)
+    /* Floating point values are returned starting from FPR1 and up.
+       Say a double_double_double type could be returned in
+       FPR1/FPR2/FPR3 triple.  */
+    regnum = tdep->ppc_fp0_regnum + 1;
+  else if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
+    {
+      if (TYPE_LENGTH (type) == 16
+          && TYPE_VECTOR (type))
+        regnum = tdep->ppc_vr0_regnum + 2;
+      else
+        internal_error (__FILE__, __LINE__,
+                        "rs6000_store_return_value: "
+                        "unexpected array return type");
+    }
+  else
+    /* Everything else is returned in GPR3 and up.  */
+    regnum = tdep->ppc_gp0_regnum + 3;
+
+  {
+    size_t bytes_written = 0;
+
+    while (bytes_written < TYPE_LENGTH (type))
+      {
+        /* How much of this value can we write to this register?  */
+        size_t bytes_to_write = min (TYPE_LENGTH (type) - bytes_written,
+                                     register_size (gdbarch, regnum));
+        regcache_cooked_write_part (regcache, regnum,
+                                    0, bytes_to_write,
+                                    (char *) valbuf + bytes_written);
+        regnum++;
+        bytes_written += bytes_to_write;
+      }
+  }
+}
+
+
+/* Extract from an array REGBUF containing the (raw) register state
+   the address in which a function should return its structure value,
+   as a CORE_ADDR (or an expression that can be used as one).  */
+
+static CORE_ADDR
+rs6000_extract_struct_value_address (struct regcache *regcache)
+{
+  /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior
+     function call GDB knows the address of the struct return value
+     and hence, should not need to call this function.  Unfortunately,
+     the current call_function_by_hand() code only saves the most
+     recent struct address leading to occasional calls.  The code
+     should instead maintain a stack of such addresses (in the dummy
+     frame object).  */
+  /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've
+     really got no idea where the return value is being stored.  While
+     r3, on function entry, contained the address it will have since
+     been reused (scratch) and hence wouldn't be valid */
+  return 0;
+}
+
+/* Hook called when a new child process is started.  */
+
+void
+rs6000_create_inferior (int pid)
+{
+  if (rs6000_set_host_arch_hook)
+    rs6000_set_host_arch_hook (pid);
+}
+
+/* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG).
+
+   Usually a function pointer's representation is simply the address
+   of the function. On the RS/6000 however, a function pointer is
+   represented by a pointer to a TOC entry. This TOC entry contains
+   three words, the first word is the address of the function, the
+   second word is the TOC pointer (r2), and the third word is the
+   static chain value.  Throughout GDB it is currently assumed that a
+   function pointer contains the address of the function, which is not
+   easy to fix.  In addition, the conversion of a function address to
+   a function pointer would require allocation of a TOC entry in the
+   inferior's memory space, with all its drawbacks.  To be able to
+   call C++ virtual methods in the inferior (which are called via
+   function pointers), find_function_addr uses this function to get the
+   function address from a function pointer.  */
+
+/* Return real function address if ADDR (a function pointer) is in the data
+   space and is therefore a special function pointer.  */
+
+static CORE_ADDR
+rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch,
+				   CORE_ADDR addr,
+				   struct target_ops *targ)
+{
+  struct obj_section *s;
+
+  s = find_pc_section (addr);
+  if (s && s->the_bfd_section->flags & SEC_CODE)
+    return addr;
+
+  /* ADDR is in the data space, so it's a special function pointer. */
+  return read_memory_addr (addr, gdbarch_tdep (current_gdbarch)->wordsize);
+}
+
+
+/* Handling the various POWER/PowerPC variants.  */
+
+
+/* The arrays here called registers_MUMBLE hold information about available
+   registers.
+
+   For each family of PPC variants, I've tried to isolate out the
+   common registers and put them up front, so that as long as you get
+   the general family right, GDB will correctly identify the registers
+   common to that family.  The common register sets are:
+
+   For the 60x family: hid0 hid1 iabr dabr pir
+
+   For the 505 and 860 family: eie eid nri
+
+   For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi
+   tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1
+   pbu1 pbl2 pbu2
+
+   Most of these register groups aren't anything formal.  I arrived at
+   them by looking at the registers that occurred in more than one
+   processor.
+   
+   Note: kevinb/2002-04-30: Support for the fpscr register was added
+   during April, 2002.  Slot 70 is being used for PowerPC and slot 71
+   for Power.  For PowerPC, slot 70 was unused and was already in the
+   PPC_UISA_SPRS which is ideally where fpscr should go.  For Power,
+   slot 70 was being used for "mq", so the next available slot (71)
+   was chosen.  It would have been nice to be able to make the
+   register numbers the same across processor cores, but this wasn't
+   possible without either 1) renumbering some registers for some
+   processors or 2) assigning fpscr to a really high slot that's
+   larger than any current register number.  Doing (1) is bad because
+   existing stubs would break.  Doing (2) is undesirable because it
+   would introduce a really large gap between fpscr and the rest of
+   the registers for most processors.  */
+
+/* Convenience macros for populating register arrays.  */
+
+/* Within another macro, convert S to a string.  */
+
+#define STR(s)	#s
+
+/* Return a struct reg defining register NAME that's 32 bits on 32-bit systems
+   and 64 bits on 64-bit systems.  */
+#define R(name)		{ STR(name), 4, 8, 0, 0, -1 }
+
+/* Return a struct reg defining register NAME that's 32 bits on all
+   systems.  */
+#define R4(name)	{ STR(name), 4, 4, 0, 0, -1 }
+
+/* Return a struct reg defining register NAME that's 64 bits on all
+   systems.  */
+#define R8(name)	{ STR(name), 8, 8, 0, 0, -1 }
+
+/* Return a struct reg defining register NAME that's 128 bits on all
+   systems.  */
+#define R16(name)       { STR(name), 16, 16, 0, 0, -1 }
+
+/* Return a struct reg defining floating-point register NAME.  */
+#define F(name)		{ STR(name), 8, 8, 1, 0, -1 }
+
+/* Return a struct reg defining a pseudo register NAME that is 64 bits
+   long on all systems.  */
+#define P8(name)	{ STR(name), 8, 8, 0, 1, -1 }
+
+/* Return a struct reg defining register NAME that's 32 bits on 32-bit
+   systems and that doesn't exist on 64-bit systems.  */
+#define R32(name)	{ STR(name), 4, 0, 0, 0, -1 }
+
+/* Return a struct reg defining register NAME that's 64 bits on 64-bit
+   systems and that doesn't exist on 32-bit systems.  */
+#define R64(name)	{ STR(name), 0, 8, 0, 0, -1 }
+
+/* Return a struct reg placeholder for a register that doesn't exist.  */
+#define R0		{ 0, 0, 0, 0, 0, -1 }
+
+/* Return a struct reg defining an anonymous raw register that's 32
+   bits on all systems.  */
+#define A4              { 0, 4, 4, 0, 0, -1 }
+
+/* Return a struct reg defining an SPR named NAME that is 32 bits on
+   32-bit systems and 64 bits on 64-bit systems.  */
+#define S(name)         { STR(name), 4, 8, 0, 0, ppc_spr_ ## name }
+  
+/* Return a struct reg defining an SPR named NAME that is 32 bits on
+   all systems.  */
+#define S4(name)        { STR(name), 4, 4, 0, 0, ppc_spr_ ## name }
+  
+/* Return a struct reg defining an SPR named NAME that is 32 bits on
+   all systems, and whose SPR number is NUMBER.  */
+#define SN4(name, number) { STR(name), 4, 4, 0, 0, (number) }
+  
+/* Return a struct reg defining an SPR named NAME that's 64 bits on
+   64-bit systems and that doesn't exist on 32-bit systems.  */
+#define S64(name)       { STR(name), 0, 8, 0, 0, ppc_spr_ ## name }
+  
+/* UISA registers common across all architectures, including POWER.  */
+
+#define COMMON_UISA_REGS \
+  /*  0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7),  \
+  /*  8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
+  /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
+  /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
+  /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7),  \
+  /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \
+  /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \
+  /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \
+  /* 64 */ R(pc), R(ps)
+
+/* UISA-level SPRs for PowerPC.  */
+#define PPC_UISA_SPRS \
+  /* 66 */ R4(cr),  S(lr), S(ctr), S4(xer), R4(fpscr)
+
+/* UISA-level SPRs for PowerPC without floating point support.  */
+#define PPC_UISA_NOFP_SPRS \
+  /* 66 */ R4(cr),  S(lr), S(ctr), S4(xer), R0
+
+/* Segment registers, for PowerPC.  */
+#define PPC_SEGMENT_REGS \
+  /* 71 */ R32(sr0),  R32(sr1),  R32(sr2),  R32(sr3),  \
+  /* 75 */ R32(sr4),  R32(sr5),  R32(sr6),  R32(sr7),  \
+  /* 79 */ R32(sr8),  R32(sr9),  R32(sr10), R32(sr11), \
+  /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15)
+
+/* OEA SPRs for PowerPC.  */
+#define PPC_OEA_SPRS \
+  /*  87 */ S4(pvr), \
+  /*  88 */ S(ibat0u), S(ibat0l), S(ibat1u), S(ibat1l), \
+  /*  92 */ S(ibat2u), S(ibat2l), S(ibat3u), S(ibat3l), \
+  /*  96 */ S(dbat0u), S(dbat0l), S(dbat1u), S(dbat1l), \
+  /* 100 */ S(dbat2u), S(dbat2l), S(dbat3u), S(dbat3l), \
+  /* 104 */ S(sdr1),   S64(asr),  S(dar),    S4(dsisr), \
+  /* 108 */ S(sprg0),  S(sprg1),  S(sprg2),  S(sprg3),  \
+  /* 112 */ S(srr0),   S(srr1),   S(tbl),    S(tbu),    \
+  /* 116 */ S4(dec),   S(dabr),   S4(ear)
+
+/* AltiVec registers.  */
+#define PPC_ALTIVEC_REGS \
+  /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7),  \
+  /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \
+  /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \
+  /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \
+  /*151*/R4(vscr), R4(vrsave)
+
+
+/* On machines supporting the SPE APU, the general-purpose registers
+   are 64 bits long.  There are SIMD vector instructions to treat them
+   as pairs of floats, but the rest of the instruction set treats them
+   as 32-bit registers, and only operates on their lower halves.
+
+   In the GDB regcache, we treat their high and low halves as separate
+   registers.  The low halves we present as the general-purpose
+   registers, and then we have pseudo-registers that stitch together
+   the upper and lower halves and present them as pseudo-registers.  */
+
+/* SPE GPR lower halves --- raw registers.  */
+#define PPC_SPE_GP_REGS \
+  /*  0 */ R4(r0), R4(r1), R4(r2), R4(r3), R4(r4), R4(r5), R4(r6), R4(r7),  \
+  /*  8 */ R4(r8), R4(r9), R4(r10),R4(r11),R4(r12),R4(r13),R4(r14),R4(r15), \
+  /* 16 */ R4(r16),R4(r17),R4(r18),R4(r19),R4(r20),R4(r21),R4(r22),R4(r23), \
+  /* 24 */ R4(r24),R4(r25),R4(r26),R4(r27),R4(r28),R4(r29),R4(r30),R4(r31)
+
+/* SPE GPR upper halves --- anonymous raw registers.  */
+#define PPC_SPE_UPPER_GP_REGS                   \
+  /*  0 */ A4, A4, A4, A4, A4, A4, A4, A4,      \
+  /*  8 */ A4, A4, A4, A4, A4, A4, A4, A4,      \
+  /* 16 */ A4, A4, A4, A4, A4, A4, A4, A4,      \
+  /* 24 */ A4, A4, A4, A4, A4, A4, A4, A4
+
+/* SPE GPR vector registers --- pseudo registers based on underlying
+   gprs and the anonymous upper half raw registers.  */
+#define PPC_EV_PSEUDO_REGS \
+/* 0*/P8(ev0), P8(ev1), P8(ev2), P8(ev3), P8(ev4), P8(ev5), P8(ev6), P8(ev7), \
+/* 8*/P8(ev8), P8(ev9), P8(ev10),P8(ev11),P8(ev12),P8(ev13),P8(ev14),P8(ev15),\
+/*16*/P8(ev16),P8(ev17),P8(ev18),P8(ev19),P8(ev20),P8(ev21),P8(ev22),P8(ev23),\
+/*24*/P8(ev24),P8(ev25),P8(ev26),P8(ev27),P8(ev28),P8(ev29),P8(ev30),P8(ev31)
+
+/* IBM POWER (pre-PowerPC) architecture, user-level view.  We only cover
+   user-level SPR's.  */
+static const struct reg registers_power[] =
+{
+  COMMON_UISA_REGS,
+  /* 66 */ R4(cnd), S(lr), S(cnt), S4(xer), S4(mq),
+  /* 71 */ R4(fpscr)
+};
+
+/* PowerPC UISA - a PPC processor as viewed by user-level code.  A UISA-only
+   view of the PowerPC.  */
+static const struct reg registers_powerpc[] =
+{
+  COMMON_UISA_REGS,
+  PPC_UISA_SPRS,
+  PPC_ALTIVEC_REGS
+};
+
+/* IBM PowerPC 403.
+
+   Some notes about the "tcr" special-purpose register:
+   - On the 403 and 403GC, SPR 986 is named "tcr", and it controls the
+     403's programmable interval timer, fixed interval timer, and
+     watchdog timer.
+   - On the 602, SPR 984 is named "tcr", and it controls the 602's
+     watchdog timer, and nothing else.
+
+   Some of the fields are similar between the two, but they're not
+   compatible with each other.  Since the two variants have different
+   registers, with different numbers, but the same name, we can't
+   splice the register name to get the SPR number.  */
+static const struct reg registers_403[] =
+{
+  COMMON_UISA_REGS,
+  PPC_UISA_SPRS,
+  PPC_SEGMENT_REGS,
+  PPC_OEA_SPRS,
+  /* 119 */ S(icdbdr), S(esr),  S(dear), S(evpr),
+  /* 123 */ S(cdbcr),  S(tsr),  SN4(tcr, ppc_spr_403_tcr), S(pit),
+  /* 127 */ S(tbhi),   S(tblo), S(srr2), S(srr3),
+  /* 131 */ S(dbsr),   S(dbcr), S(iac1), S(iac2),
+  /* 135 */ S(dac1),   S(dac2), S(dccr), S(iccr),
+  /* 139 */ S(pbl1),   S(pbu1), S(pbl2), S(pbu2)
+};
+
+/* IBM PowerPC 403GC.
+   See the comments about 'tcr' for the 403, above.  */
+static const struct reg registers_403GC[] =
+{
+  COMMON_UISA_REGS,
+  PPC_UISA_SPRS,
+  PPC_SEGMENT_REGS,
+  PPC_OEA_SPRS,
+  /* 119 */ S(icdbdr), S(esr),  S(dear), S(evpr),
+  /* 123 */ S(cdbcr),  S(tsr),  SN4(tcr, ppc_spr_403_tcr), S(pit),
+  /* 127 */ S(tbhi),   S(tblo), S(srr2), S(srr3),
+  /* 131 */ S(dbsr),   S(dbcr), S(iac1), S(iac2),
+  /* 135 */ S(dac1),   S(dac2), S(dccr), S(iccr),
+  /* 139 */ S(pbl1),   S(pbu1), S(pbl2), S(pbu2),
+  /* 143 */ S(zpr),    S(pid),  S(sgr),  S(dcwr),
+  /* 147 */ S(tbhu),   S(tblu)
+};
+
+/* Motorola PowerPC 505.  */
+static const struct reg registers_505[] =
+{
+  COMMON_UISA_REGS,
+  PPC_UISA_SPRS,
+  PPC_SEGMENT_REGS,
+  PPC_OEA_SPRS,
+  /* 119 */ S(eie), S(eid), S(nri)
+};
+
+/* Motorola PowerPC 860 or 850.  */
+static const struct reg registers_860[] =
+{
+  COMMON_UISA_REGS,
+  PPC_UISA_SPRS,
+  PPC_SEGMENT_REGS,
+  PPC_OEA_SPRS,
+  /* 119 */ S(eie), S(eid), S(nri), S(cmpa),
+  /* 123 */ S(cmpb), S(cmpc), S(cmpd), S(icr),
+  /* 127 */ S(der), S(counta), S(countb), S(cmpe),
+  /* 131 */ S(cmpf), S(cmpg), S(cmph), S(lctrl1),
+  /* 135 */ S(lctrl2), S(ictrl), S(bar), S(ic_cst),
+  /* 139 */ S(ic_adr), S(ic_dat), S(dc_cst), S(dc_adr),
+  /* 143 */ S(dc_dat), S(dpdr), S(dpir), S(immr),
+  /* 147 */ S(mi_ctr), S(mi_ap), S(mi_epn), S(mi_twc),
+  /* 151 */ S(mi_rpn), S(md_ctr), S(m_casid), S(md_ap),
+  /* 155 */ S(md_epn), S(m_twb), S(md_twc), S(md_rpn),
+  /* 159 */ S(m_tw), S(mi_dbcam), S(mi_dbram0), S(mi_dbram1),
+  /* 163 */ S(md_dbcam), S(md_dbram0), S(md_dbram1)
+};
+
+/* Motorola PowerPC 601.  Note that the 601 has different register numbers
+   for reading and writing RTCU and RTCL.  However, how one reads and writes a
+   register is the stub's problem.  */
+static const struct reg registers_601[] =
+{
+  COMMON_UISA_REGS,
+  PPC_UISA_SPRS,
+  PPC_SEGMENT_REGS,
+  PPC_OEA_SPRS,
+  /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
+  /* 123 */ S(pir), S(mq), S(rtcu), S(rtcl)
+};
+
+/* Motorola PowerPC 602.
+   See the notes under the 403 about 'tcr'.  */
+static const struct reg registers_602[] =
+{
+  COMMON_UISA_REGS,
+  PPC_UISA_SPRS,
+  PPC_SEGMENT_REGS,
+  PPC_OEA_SPRS,
+  /* 119 */ S(hid0), S(hid1), S(iabr), R0,
+  /* 123 */ R0, SN4(tcr, ppc_spr_602_tcr), S(ibr), S(esasrr),
+  /* 127 */ S(sebr), S(ser), S(sp), S(lt)
+};
+
+/* Motorola/IBM PowerPC 603 or 603e.  */
+static const struct reg registers_603[] =
+{
+  COMMON_UISA_REGS,
+  PPC_UISA_SPRS,
+  PPC_SEGMENT_REGS,
+  PPC_OEA_SPRS,
+  /* 119 */ S(hid0), S(hid1), S(iabr), R0,
+  /* 123 */ R0, S(dmiss), S(dcmp), S(hash1),
+  /* 127 */ S(hash2), S(imiss), S(icmp), S(rpa)
+};
+
+/* Motorola PowerPC 604 or 604e.  */
+static const struct reg registers_604[] =
+{
+  COMMON_UISA_REGS,
+  PPC_UISA_SPRS,
+  PPC_SEGMENT_REGS,
+  PPC_OEA_SPRS,
+  /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
+  /* 123 */ S(pir), S(mmcr0), S(pmc1), S(pmc2),
+  /* 127 */ S(sia), S(sda)
+};
+
+/* Motorola/IBM PowerPC 750 or 740.  */
+static const struct reg registers_750[] =
+{
+  COMMON_UISA_REGS,
+  PPC_UISA_SPRS,
+  PPC_SEGMENT_REGS,
+  PPC_OEA_SPRS,
+  /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
+  /* 123 */ R0, S(ummcr0), S(upmc1), S(upmc2),
+  /* 127 */ S(usia), S(ummcr1), S(upmc3), S(upmc4),
+  /* 131 */ S(mmcr0), S(pmc1), S(pmc2), S(sia),
+  /* 135 */ S(mmcr1), S(pmc3), S(pmc4), S(l2cr),
+  /* 139 */ S(ictc), S(thrm1), S(thrm2), S(thrm3)
+};
+
+
+/* Motorola PowerPC 7400.  */
+static const struct reg registers_7400[] =
+{
+  /* gpr0-gpr31, fpr0-fpr31 */
+  COMMON_UISA_REGS,
+  /* cr, lr, ctr, xer, fpscr */
+  PPC_UISA_SPRS,
+  /* sr0-sr15 */
+  PPC_SEGMENT_REGS,
+  PPC_OEA_SPRS,
+  /* vr0-vr31, vrsave, vscr */
+  PPC_ALTIVEC_REGS
+  /* FIXME? Add more registers? */
+};
+
+/* Motorola e500.  */
+static const struct reg registers_e500[] =
+{
+  /*   0 ..  31 */ PPC_SPE_GP_REGS,
+  /*  32 ..  63 */ PPC_SPE_UPPER_GP_REGS,
+  /*  64 ..  65 */ R(pc), R(ps),
+  /*  66 ..  70 */ PPC_UISA_NOFP_SPRS,
+  /*  71 ..  72 */ R8(acc), S4(spefscr),
+  /* NOTE: Add new registers here the end of the raw register
+     list and just before the first pseudo register.  */
+  /*  73 .. 104 */ PPC_EV_PSEUDO_REGS
+};
+
+/* Information about a particular processor variant.  */
+
+struct variant
+  {
+    /* Name of this variant.  */
+    char *name;
+
+    /* English description of the variant.  */
+    char *description;
+
+    /* bfd_arch_info.arch corresponding to variant.  */
+    enum bfd_architecture arch;
+
+    /* bfd_arch_info.mach corresponding to variant.  */
+    unsigned long mach;
+
+    /* Number of real registers.  */
+    int nregs;
+
+    /* Number of pseudo registers.  */
+    int npregs;
+
+    /* Number of total registers (the sum of nregs and npregs).  */
+    int num_tot_regs;
+
+    /* Table of register names; registers[R] is the name of the register
+       number R.  */
+    const struct reg *regs;
+  };
+
+#define tot_num_registers(list) (sizeof (list) / sizeof((list)[0]))
+
+static int
+num_registers (const struct reg *reg_list, int num_tot_regs)
+{
+  int i;
+  int nregs = 0;
+
+  for (i = 0; i < num_tot_regs; i++)
+    if (!reg_list[i].pseudo)
+      nregs++;
+       
+  return nregs;
+}
+
+static int
+num_pseudo_registers (const struct reg *reg_list, int num_tot_regs)
+{
+  int i;
+  int npregs = 0;
+
+  for (i = 0; i < num_tot_regs; i++)
+    if (reg_list[i].pseudo)
+      npregs ++; 
+
+  return npregs;
+}
+
+/* Information in this table comes from the following web sites:
+   IBM:       http://www.chips.ibm.com:80/products/embedded/
+   Motorola:  http://www.mot.com/SPS/PowerPC/
+
+   I'm sure I've got some of the variant descriptions not quite right.
+   Please report any inaccuracies you find to GDB's maintainer.
+
+   If you add entries to this table, please be sure to allow the new
+   value as an argument to the --with-cpu flag, in configure.in.  */
+
+static struct variant variants[] =
+{
+
+  {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
+   bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc),
+   registers_powerpc},
+  {"power", "POWER user-level", bfd_arch_rs6000,
+   bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power),
+   registers_power},
+  {"403", "IBM PowerPC 403", bfd_arch_powerpc,
+   bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403),
+   registers_403},
+  {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
+   bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601),
+   registers_601},
+  {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
+   bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602),
+   registers_602},
+  {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
+   bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603),
+   registers_603},
+  {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
+   604, -1, -1, tot_num_registers (registers_604),
+   registers_604},
+  {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
+   bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC),
+   registers_403GC},
+  {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
+   bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505),
+   registers_505},
+  {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
+   bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860),
+   registers_860},
+  {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
+   bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750),
+   registers_750},
+  {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
+   bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400),
+   registers_7400},
+  {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
+   bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500),
+   registers_e500},
+
+  /* 64-bit */
+  {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
+   bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc),
+   registers_powerpc},
+  {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
+   bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc),
+   registers_powerpc},
+  {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
+   bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc),
+   registers_powerpc},
+  {"a35", "PowerPC A35", bfd_arch_powerpc,
+   bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc),
+   registers_powerpc},
+  {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
+   bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc),
+   registers_powerpc},
+  {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
+   bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc),
+   registers_powerpc},
+
+  /* FIXME: I haven't checked the register sets of the following.  */
+  {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
+   bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power),
+   registers_power},
+  {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
+   bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power),
+   registers_power},
+  {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
+   bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power),
+   registers_power},
+
+  {0, 0, 0, 0, 0, 0, 0, 0}
+};
+
+/* Initialize the number of registers and pseudo registers in each variant.  */
+
+static void
+init_variants (void)
+{
+  struct variant *v;
+
+  for (v = variants; v->name; v++)
+    {
+      if (v->nregs == -1)
+        v->nregs = num_registers (v->regs, v->num_tot_regs);
+      if (v->npregs == -1)
+        v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs);
+    }  
+}
+
+/* Return the variant corresponding to architecture ARCH and machine number
+   MACH.  If no such variant exists, return null.  */
+
+static const struct variant *
+find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
+{
+  const struct variant *v;
+
+  for (v = variants; v->name; v++)
+    if (arch == v->arch && mach == v->mach)
+      return v;
+
+  return NULL;
+}
+
+static int
+gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
+{
+  if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+    return print_insn_big_powerpc (memaddr, info);
+  else
+    return print_insn_little_powerpc (memaddr, info);
+}
+
+static CORE_ADDR
+rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
+{
+  return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
+}
+
+static struct frame_id
+rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
+{
+  return frame_id_build (frame_unwind_register_unsigned (next_frame,
+							 SP_REGNUM),
+			 frame_pc_unwind (next_frame));
+}
+
+struct rs6000_frame_cache
+{
+  CORE_ADDR base;
+  CORE_ADDR initial_sp;
+  struct trad_frame_saved_reg *saved_regs;
+};
+
+static struct rs6000_frame_cache *
+rs6000_frame_cache (struct frame_info *next_frame, void **this_cache)
+{
+  struct rs6000_frame_cache *cache;
+  struct gdbarch *gdbarch = get_frame_arch (next_frame);
+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+  struct rs6000_framedata fdata;
+  int wordsize = tdep->wordsize;
+
+  if ((*this_cache) != NULL)
+    return (*this_cache);
+  cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
+  (*this_cache) = cache;
+  cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
+
+  skip_prologue (frame_func_unwind (next_frame), frame_pc_unwind (next_frame),
+		 &fdata);
+
+  /* If there were any saved registers, figure out parent's stack
+     pointer.  */
+  /* The following is true only if the frame doesn't have a call to
+     alloca(), FIXME.  */
+
+  if (fdata.saved_fpr == 0
+      && fdata.saved_gpr == 0
+      && fdata.saved_vr == 0
+      && fdata.saved_ev == 0
+      && fdata.lr_offset == 0
+      && fdata.cr_offset == 0
+      && fdata.vr_offset == 0
+      && fdata.ev_offset == 0)
+    cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
+  else
+    {
+      /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
+	 address of the current frame.  Things might be easier if the
+	 ->frame pointed to the outer-most address of the frame.  In
+	 the mean time, the address of the prev frame is used as the
+	 base address of this frame.  */
+      cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
+      if (!fdata.frameless)
+	/* Frameless really means stackless.  */
+	cache->base = read_memory_addr (cache->base, wordsize);
+    }
+  trad_frame_set_value (cache->saved_regs, SP_REGNUM, cache->base);
+
+  /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
+     All fpr's from saved_fpr to fp31 are saved.  */
+
+  if (fdata.saved_fpr >= 0)
+    {
+      int i;
+      CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
+
+      /* If skip_prologue says floating-point registers were saved,
+         but the current architecture has no floating-point registers,
+         then that's strange.  But we have no indices to even record
+         the addresses under, so we just ignore it.  */
+      if (ppc_floating_point_unit_p (gdbarch))
+        for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
+          {
+            cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
+            fpr_addr += 8;
+          }
+    }
+
+  /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
+     All gpr's from saved_gpr to gpr31 are saved.  */
+
+  if (fdata.saved_gpr >= 0)
+    {
+      int i;
+      CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
+      for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
+	{
+	  cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
+	  gpr_addr += wordsize;
+	}
+    }
+
+  /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
+     All vr's from saved_vr to vr31 are saved.  */
+  if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
+    {
+      if (fdata.saved_vr >= 0)
+	{
+	  int i;
+	  CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
+	  for (i = fdata.saved_vr; i < 32; i++)
+	    {
+	      cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
+	      vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
+	    }
+	}
+    }
+
+  /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
+     All vr's from saved_ev to ev31 are saved. ????? */
+  if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1)
+    {
+      if (fdata.saved_ev >= 0)
+	{
+	  int i;
+	  CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
+	  for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
+	    {
+	      cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
+              cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
+	      ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
+            }
+	}
+    }
+
+  /* If != 0, fdata.cr_offset is the offset from the frame that
+     holds the CR.  */
+  if (fdata.cr_offset != 0)
+    cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset;
+
+  /* If != 0, fdata.lr_offset is the offset from the frame that
+     holds the LR.  */
+  if (fdata.lr_offset != 0)
+    cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset;
+  /* The PC is found in the link register.  */
+  cache->saved_regs[PC_REGNUM] = cache->saved_regs[tdep->ppc_lr_regnum];
+
+  /* If != 0, fdata.vrsave_offset is the offset from the frame that
+     holds the VRSAVE.  */
+  if (fdata.vrsave_offset != 0)
+    cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset;
+
+  if (fdata.alloca_reg < 0)
+    /* If no alloca register used, then fi->frame is the value of the
+       %sp for this frame, and it is good enough.  */
+    cache->initial_sp = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
+  else
+    cache->initial_sp = frame_unwind_register_unsigned (next_frame,
+							fdata.alloca_reg);
+
+  return cache;
+}
+
+static void
+rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache,
+		      struct frame_id *this_id)
+{
+  struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
+							this_cache);
+  (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame));
+}
+
+static void
+rs6000_frame_prev_register (struct frame_info *next_frame,
+				 void **this_cache,
+				 int regnum, int *optimizedp,
+				 enum lval_type *lvalp, CORE_ADDR *addrp,
+				 int *realnump, void *valuep)
+{
+  struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
+							this_cache);
+  trad_frame_prev_register (next_frame, info->saved_regs, regnum,
+			    optimizedp, lvalp, addrp, realnump, valuep);
+}
+
+static const struct frame_unwind rs6000_frame_unwind =
+{
+  NORMAL_FRAME,
+  rs6000_frame_this_id,
+  rs6000_frame_prev_register
+};
+
+static const struct frame_unwind *
+rs6000_frame_sniffer (struct frame_info *next_frame)
+{
+  return &rs6000_frame_unwind;
+}
+
+
+
+static CORE_ADDR
+rs6000_frame_base_address (struct frame_info *next_frame,
+				void **this_cache)
+{
+  struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
+							this_cache);
+  return info->initial_sp;
+}
+
+static const struct frame_base rs6000_frame_base = {
+  &rs6000_frame_unwind,
+  rs6000_frame_base_address,
+  rs6000_frame_base_address,
+  rs6000_frame_base_address
+};
+
+static const struct frame_base *
+rs6000_frame_base_sniffer (struct frame_info *next_frame)
+{
+  return &rs6000_frame_base;
+}
+
+/* Initialize the current architecture based on INFO.  If possible, re-use an
+   architecture from ARCHES, which is a list of architectures already created
+   during this debugging session.
+
+   Called e.g. at program startup, when reading a core file, and when reading
+   a binary file.  */
+
+static struct gdbarch *
+rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+{
+  struct gdbarch *gdbarch;
+  struct gdbarch_tdep *tdep;
+  int wordsize, from_xcoff_exec, from_elf_exec, i, off;
+  struct reg *regs;
+  const struct variant *v;
+  enum bfd_architecture arch;
+  unsigned long mach;
+  bfd abfd;
+  int sysv_abi;
+  asection *sect;
+
+  from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
+    bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
+
+  from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
+    bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
+
+  sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
+
+  /* Check word size.  If INFO is from a binary file, infer it from
+     that, else choose a likely default.  */
+  if (from_xcoff_exec)
+    {
+      if (bfd_xcoff_is_xcoff64 (info.abfd))
+	wordsize = 8;
+      else
+	wordsize = 4;
+    }
+  else if (from_elf_exec)
+    {
+      if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
+	wordsize = 8;
+      else
+	wordsize = 4;
+    }
+  else
+    {
+      if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
+	wordsize = info.bfd_arch_info->bits_per_word /
+	  info.bfd_arch_info->bits_per_byte;
+      else
+	wordsize = 4;
+    }
+
+  /* Find a candidate among extant architectures.  */
+  for (arches = gdbarch_list_lookup_by_info (arches, &info);
+       arches != NULL;
+       arches = gdbarch_list_lookup_by_info (arches->next, &info))
+    {
+      /* Word size in the various PowerPC bfd_arch_info structs isn't
+         meaningful, because 64-bit CPUs can run in 32-bit mode.  So, perform
+         separate word size check.  */
+      tdep = gdbarch_tdep (arches->gdbarch);
+      if (tdep && tdep->wordsize == wordsize)
+	return arches->gdbarch;
+    }
+
+  /* None found, create a new architecture from INFO, whose bfd_arch_info
+     validity depends on the source:
+       - executable		useless
+       - rs6000_host_arch()	good
+       - core file		good
+       - "set arch"		trust blindly
+       - GDB startup		useless but harmless */
+
+  if (!from_xcoff_exec)
+    {
+      arch = info.bfd_arch_info->arch;
+      mach = info.bfd_arch_info->mach;
+    }
+  else
+    {
+      arch = bfd_arch_powerpc;
+      bfd_default_set_arch_mach (&abfd, arch, 0);
+      info.bfd_arch_info = bfd_get_arch_info (&abfd);
+      mach = info.bfd_arch_info->mach;
+    }
+  tdep = xmalloc (sizeof (struct gdbarch_tdep));
+  tdep->wordsize = wordsize;
+
+  /* For e500 executables, the apuinfo section is of help here.  Such
+     section contains the identifier and revision number of each
+     Application-specific Processing Unit that is present on the
+     chip.  The content of the section is determined by the assembler
+     which looks at each instruction and determines which unit (and
+     which version of it) can execute it. In our case we just look for
+     the existance of the section.  */
+
+  if (info.abfd)
+    {
+      sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo");
+      if (sect)
+	{
+	  arch = info.bfd_arch_info->arch;
+	  mach = bfd_mach_ppc_e500;
+	  bfd_default_set_arch_mach (&abfd, arch, mach);
+	  info.bfd_arch_info = bfd_get_arch_info (&abfd);
+	}
+    }
+
+  gdbarch = gdbarch_alloc (&info, tdep);
+
+  /* Initialize the number of real and pseudo registers in each variant.  */
+  init_variants ();
+
+  /* Choose variant.  */
+  v = find_variant_by_arch (arch, mach);
+  if (!v)
+    return NULL;
+
+  tdep->regs = v->regs;
+
+  tdep->ppc_gp0_regnum = 0;
+  tdep->ppc_toc_regnum = 2;
+  tdep->ppc_ps_regnum = 65;
+  tdep->ppc_cr_regnum = 66;
+  tdep->ppc_lr_regnum = 67;
+  tdep->ppc_ctr_regnum = 68;
+  tdep->ppc_xer_regnum = 69;
+  if (v->mach == bfd_mach_ppc_601)
+    tdep->ppc_mq_regnum = 124;
+  else if (arch == bfd_arch_rs6000)
+    tdep->ppc_mq_regnum = 70;
+  else
+    tdep->ppc_mq_regnum = -1;
+  tdep->ppc_fp0_regnum = 32;
+  tdep->ppc_fpscr_regnum = (arch == bfd_arch_rs6000) ? 71 : 70;
+  tdep->ppc_sr0_regnum = 71;
+  tdep->ppc_vr0_regnum = -1;
+  tdep->ppc_vrsave_regnum = -1;
+  tdep->ppc_ev0_upper_regnum = -1;
+  tdep->ppc_ev0_regnum = -1;
+  tdep->ppc_ev31_regnum = -1;
+  tdep->ppc_acc_regnum = -1;
+  tdep->ppc_spefscr_regnum = -1;
+
+  set_gdbarch_pc_regnum (gdbarch, 64);
+  set_gdbarch_sp_regnum (gdbarch, 1);
+  set_gdbarch_deprecated_fp_regnum (gdbarch, 1);
+  set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
+  if (sysv_abi && wordsize == 8)
+    set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
+  else if (sysv_abi && wordsize == 4)
+    set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
+  else
+    {
+      set_gdbarch_deprecated_extract_return_value (gdbarch, rs6000_extract_return_value);
+      set_gdbarch_store_return_value (gdbarch, rs6000_store_return_value);
+    }
+
+  /* Set lr_frame_offset.  */
+  if (wordsize == 8)
+    tdep->lr_frame_offset = 16;
+  else if (sysv_abi)
+    tdep->lr_frame_offset = 4;
+  else
+    tdep->lr_frame_offset = 8;
+
+  if (v->arch == bfd_arch_rs6000)
+    tdep->ppc_sr0_regnum = -1;
+  else if (v->arch == bfd_arch_powerpc)
+    switch (v->mach)
+      {
+      case bfd_mach_ppc: 
+        tdep->ppc_sr0_regnum = -1;
+	tdep->ppc_vr0_regnum = 71;
+	tdep->ppc_vrsave_regnum = 104;
+	break;
+      case bfd_mach_ppc_7400:
+	tdep->ppc_vr0_regnum = 119;
+	tdep->ppc_vrsave_regnum = 152;
+	break;
+      case bfd_mach_ppc_e500:
+        tdep->ppc_toc_regnum = -1;
+        tdep->ppc_ev0_upper_regnum = 32;
+	tdep->ppc_ev0_regnum = 73;
+	tdep->ppc_ev31_regnum = 104;
+        tdep->ppc_acc_regnum = 71;
+        tdep->ppc_spefscr_regnum = 72;
+        tdep->ppc_fp0_regnum = -1;
+        tdep->ppc_fpscr_regnum = -1;
+        tdep->ppc_sr0_regnum = -1;
+        set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read);
+        set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write);
+        set_gdbarch_register_reggroup_p (gdbarch, e500_register_reggroup_p);
+	break;
+
+      case bfd_mach_ppc64:
+      case bfd_mach_ppc_620:
+      case bfd_mach_ppc_630:
+      case bfd_mach_ppc_a35:
+      case bfd_mach_ppc_rs64ii:
+      case bfd_mach_ppc_rs64iii:
+        /* These processor's register sets don't have segment registers.  */
+        tdep->ppc_sr0_regnum = -1;
+        break;
+      }   
+  else
+    internal_error (__FILE__, __LINE__,
+                    "rs6000_gdbarch_init: "
+                    "received unexpected BFD 'arch' value");
+
+  /* Sanity check on registers.  */
+  gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0);
+
+  /* Select instruction printer.  */
+  if (arch == bfd_arch_rs6000)
+    set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
+  else
+    set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
+
+  set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
+
+  set_gdbarch_num_regs (gdbarch, v->nregs);
+  set_gdbarch_num_pseudo_regs (gdbarch, v->npregs);
+  set_gdbarch_register_name (gdbarch, rs6000_register_name);
+  set_gdbarch_register_type (gdbarch, rs6000_register_type);
+
+  set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
+  set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
+  set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
+  set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
+  set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
+  set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
+  set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
+  if (sysv_abi)
+    set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
+  else
+    set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
+  set_gdbarch_char_signed (gdbarch, 0);
+
+  set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
+  if (sysv_abi && wordsize == 8)
+    /* PPC64 SYSV.  */
+    set_gdbarch_frame_red_zone_size (gdbarch, 288);
+  else if (!sysv_abi && wordsize == 4)
+    /* PowerOpen / AIX 32 bit.  The saved area or red zone consists of
+       19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes.
+       Problem is, 220 isn't frame (16 byte) aligned.  Round it up to
+       224.  */
+    set_gdbarch_frame_red_zone_size (gdbarch, 224);
+
+  set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
+  set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
+  set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
+
+  set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
+  set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
+  /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments()
+     is correct for the SysV ABI when the wordsize is 8, but I'm also
+     fairly certain that ppc_sysv_abi_push_arguments() will give even
+     worse results since it only works for 32-bit code.  So, for the moment,
+     we're better off calling rs6000_push_arguments() since it works for
+     64-bit code.  At some point in the future, this matter needs to be
+     revisited.  */
+  if (sysv_abi && wordsize == 4)
+    set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
+  else if (sysv_abi && wordsize == 8)
+    set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
+  else
+    set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call);
+
+  set_gdbarch_deprecated_extract_struct_value_address (gdbarch, rs6000_extract_struct_value_address);
+
+  set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
+  set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
+  set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
+
+  /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN"
+     for the descriptor and ".FN" for the entry-point -- a user
+     specifying "break FN" will unexpectedly end up with a breakpoint
+     on the descriptor and not the function.  This architecture method
+     transforms any breakpoints on descriptors into breakpoints on the
+     corresponding entry point.  */
+  if (sysv_abi && wordsize == 8)
+    set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address);
+
+  /* Not sure on this. FIXMEmgo */
+  set_gdbarch_frame_args_skip (gdbarch, 8);
+
+  if (!sysv_abi)
+    set_gdbarch_deprecated_use_struct_convention (gdbarch, rs6000_use_struct_convention);
+
+  if (!sysv_abi)
+    {
+      /* Handle RS/6000 function pointers (which are really function
+         descriptors).  */
+      set_gdbarch_convert_from_func_ptr_addr (gdbarch,
+	rs6000_convert_from_func_ptr_addr);
+    }
+
+  /* Helpers for function argument information.  */
+  set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
+
+  /* Hook in ABI-specific overrides, if they have been registered.  */
+  gdbarch_init_osabi (info, gdbarch);
+
+  switch (info.osabi)
+    {
+    case GDB_OSABI_NETBSD_AOUT:
+    case GDB_OSABI_NETBSD_ELF:
+    case GDB_OSABI_UNKNOWN:
+    case GDB_OSABI_LINUX:
+      set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
+      frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
+      set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
+      frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
+      break;
+    default:
+      set_gdbarch_believe_pcc_promotion (gdbarch, 1);
+
+      set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
+      frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
+      set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
+      frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
+    }
+
+  if (from_xcoff_exec)
+    {
+      /* NOTE: jimix/2003-06-09: This test should really check for
+	 GDB_OSABI_AIX when that is defined and becomes
+	 available. (Actually, once things are properly split apart,
+	 the test goes away.) */
+       /* RS6000/AIX does not support PT_STEP.  Has to be simulated.  */
+       set_gdbarch_software_single_step (gdbarch, rs6000_software_single_step);
+    }
+
+  init_sim_regno_table (gdbarch);
+
+  return gdbarch;
+}
+
+static void
+rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
+{
+  struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+  if (tdep == NULL)
+    return;
+
+  /* FIXME: Dump gdbarch_tdep.  */
+}
+
+static struct cmd_list_element *info_powerpc_cmdlist = NULL;
+
+static void
+rs6000_info_powerpc_command (char *args, int from_tty)
+{
+  help_list (info_powerpc_cmdlist, "info powerpc ", class_info, gdb_stdout);
+}
+
+/* Initialization code.  */
+
+extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */
+
+void
+_initialize_rs6000_tdep (void)
+{
+  gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
+  gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);
+
+  /* Add root prefix command for "info powerpc" commands */
+  add_prefix_cmd ("powerpc", class_info, rs6000_info_powerpc_command,
+		  "Various POWERPC info specific commands.",
+		  &info_powerpc_cmdlist, "info powerpc ", 0, &infolist);
+}
diff --git a/include/gdb/ChangeLog b/include/gdb/ChangeLog
new file mode 100644
index 00000000000..41fc44be43c
--- /dev/null
+++ b/include/gdb/ChangeLog
@@ -0,0 +1,125 @@
+2004-08-04  Andrew Cagney  <cagney@gnu.org>
+
+	* sim-ppc.h: Add extern "C" wrapper.
+	(enum sim_ppc_regnum): Add full list of SPRs.
+
+2004-08-04  Jim Blandy  <jimb@redhat.com>
+
+	* sim-ppc.h: New file.
+
+2004-06-25  J"orn Rennecke <joern.rennecke@superh.com>
+
+	* callback.h (host_callback_struct): Replace members fdopen and
+	alwaysopen with fd_buddy.
+	[sim/common: * callback.c: Changed all users.  ]
+
+2003-10-31  Kevin Buettner  <kevin@redhat.com>
+
+	* sim-frv.h: New file.
+
+2003-10-15  J"orn Rennecke <joern.rennecke@superh.com>
+
+	* callback.h (struct host_callback_struct): New members ftruncate
+	and truncate.
+
+2003-06-10  Corinna Vinschen  <vinschen@redhat.com>
+
+	* gdb/fileio.h: New file.
+
+2003-05-07  Andrew Cagney  <cagney@redhat.com>
+
+	* sim-d10v.h (sim_d10v_translate_addr): Add regcache parameter.
+	(sim_d10v_translate_imap_addr): Add regcache parameter.
+	(sim_d10v_translate_dmap_addr): Ditto.
+
+2003-03-27  Nick Clifton  <nickc@redhat.com>
+
+	* sim-arm.h (sim_arm_regs): Add iWMMXt registers.
+
+2003-03-20  Nick Clifton  <nickc@redhat.com>
+
+	* sim-arm.h (sim_arm_regs): Add Maverick co-processor
+	registers.
+
+2003-02-27  Andrew Cagney  <cagney@redhat.com>
+
+	* remote-sim.h (sim_open, sim_load, sim_create_inferior): Rename
+	_bfd to bfd.
+
+2003-02-20  Andrew Cagney  <ac131313@redhat.com>
+
+	* remote-sim.h (SIM_RC): Delete unused SIM_RC_UNKNOWN_BREAKPOINT,
+	SIM_RC_INSUFFICIENT_RESOURCES and SIM_RC_DUPLICATE_BREAKPOINT.
+	(sim_set_breakpoint, sim_clear_breakpoint): Delete declarations.
+	(sim_clear_all_breakpoints, sim_enable_breakpoint): Ditto.
+	(sim_enable_all_breakpoints, sim_disable_breakpoint): Ditto.
+	(sim_disable_all_breakpoints): Ditto.
+
+2002-12-26  Kazu Hirata  <kazu@cs.umass.edu>
+
+	* sim-h8300.h: Remove ^M.
+
+2002-07-29  Andrey Volkov  <avolkov@transas.com>
+
+	* sim-h8300.h: Rename all enums from H8300_ to SIM_H8300_
+	 prefix.
+
+2002-07-23  Andrey Volkov  <avolkov@transas.com>
+
+	* sim-h8300.h: New file.
+
+2002-07-17  Andrew Cagney  <cagney@redhat.com>
+
+	* remote-sim.h: Update copyright.
+	(sim_set_callbacks, sim_size, sim_trace)
+	(sim_set_trace, sim_set_profile_size, sim_kill): Delete.  Moved to
+	"sim/common/run-sim.h".
+
+Wed Jul 17 19:36:38 2002  J"orn Rennecke <joern.rennecke@superh.com>
+
+	* sim-sh.h: Add enum constants for sh[1-4], sh3e, sh3?-dsp,
+	renumbering the sh-dsp registers to use distinct numbers.
+
+2002-06-15  Andrew Cagney  <ac131313@redhat.com>
+
+	* sim-arm.h (enum sim_arm_regs): Rename sim_arm_regnum.
+
+2002-06-12  Andrew Cagney  <ac131313@redhat.com>
+
+	* sim-arm.h: New file.
+
+2002-06-08  Andrew Cagney  <cagney@redhat.com>
+
+	* callback.h: Copy to here from directory above.
+	* remote-sim.h: Copy to here from directory above.
+
+2002-06-01  Andrew Cagney  <ac131313@redhat.com>
+
+	* sim-d10v.h (sim_d10v_regs): Expand to include all registers.
+	Update copyright.
+
+2002-05-23  Andrew Cagney  <ac131313@redhat.com>
+
+	* sim-d10v.h: New file.  Moved from include/sim-d10v.h.
+
+2002-05-10  Elena Zannoni  <ezannoni@redhat.com>
+
+        * sim-sh.h: New file, for sh gdb<->sim interface.
+
+2002-05-09  Daniel Jacobowitz  <drow@mvista.com>
+
+	* signals.h: Update comments.
+	(enum target_signal): Remove conditional compilation around
+	Mach-specific signals.  Move them to after TARGET_SIGNAL_DEFAULT.
+
+2002-03-10  Daniel Jacobowitz  <drow@mvista.com>
+
+	* signals.h: New file, from gdb/defs.h.
+
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/include/gdb/sim-ppc.h b/include/gdb/sim-ppc.h
new file mode 100644
index 00000000000..e31a6711292
--- /dev/null
+++ b/include/gdb/sim-ppc.h
@@ -0,0 +1,771 @@
+/* sim-ppc.h --- interface between PowerPC simulator and GDB.
+
+   Copyright 2004 Free Software Foundation, Inc.
+
+   Contributed by Red Hat.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or
+   modify it under the terms of the GNU General Public License as
+   published by the Free Software Foundation; either version 2 of the
+   License, or (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
+   02111-1307, USA.  */
+
+#if !defined (SIM_PPC_H)
+#define SIM_PPC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* The register access functions, sim_fetch_register and
+   sim_store_register, use the following numbering for PowerPC
+   registers.  */
+
+enum sim_ppc_regnum
+  {
+    /* General-purpose registers, r0 -- r31.  */
+    sim_ppc_r0_regnum,
+    sim_ppc_r1_regnum,
+    sim_ppc_r2_regnum,
+    sim_ppc_r3_regnum,
+    sim_ppc_r4_regnum,
+    sim_ppc_r5_regnum,
+    sim_ppc_r6_regnum,
+    sim_ppc_r7_regnum,
+    sim_ppc_r8_regnum,
+    sim_ppc_r9_regnum,
+    sim_ppc_r10_regnum,
+    sim_ppc_r11_regnum,
+    sim_ppc_r12_regnum,
+    sim_ppc_r13_regnum,
+    sim_ppc_r14_regnum,
+    sim_ppc_r15_regnum,
+    sim_ppc_r16_regnum,
+    sim_ppc_r17_regnum,
+    sim_ppc_r18_regnum,
+    sim_ppc_r19_regnum,
+    sim_ppc_r20_regnum,
+    sim_ppc_r21_regnum,
+    sim_ppc_r22_regnum,
+    sim_ppc_r23_regnum,
+    sim_ppc_r24_regnum,
+    sim_ppc_r25_regnum,
+    sim_ppc_r26_regnum,
+    sim_ppc_r27_regnum,
+    sim_ppc_r28_regnum,
+    sim_ppc_r29_regnum,
+    sim_ppc_r30_regnum,
+    sim_ppc_r31_regnum,
+
+    /* Floating-point registers, f0 -- f31.  */
+    sim_ppc_f0_regnum,
+    sim_ppc_f1_regnum,
+    sim_ppc_f2_regnum,
+    sim_ppc_f3_regnum,
+    sim_ppc_f4_regnum,
+    sim_ppc_f5_regnum,
+    sim_ppc_f6_regnum,
+    sim_ppc_f7_regnum,
+    sim_ppc_f8_regnum,
+    sim_ppc_f9_regnum,
+    sim_ppc_f10_regnum,
+    sim_ppc_f11_regnum,
+    sim_ppc_f12_regnum,
+    sim_ppc_f13_regnum,
+    sim_ppc_f14_regnum,
+    sim_ppc_f15_regnum,
+    sim_ppc_f16_regnum,
+    sim_ppc_f17_regnum,
+    sim_ppc_f18_regnum,
+    sim_ppc_f19_regnum,
+    sim_ppc_f20_regnum,
+    sim_ppc_f21_regnum,
+    sim_ppc_f22_regnum,
+    sim_ppc_f23_regnum,
+    sim_ppc_f24_regnum,
+    sim_ppc_f25_regnum,
+    sim_ppc_f26_regnum,
+    sim_ppc_f27_regnum,
+    sim_ppc_f28_regnum,
+    sim_ppc_f29_regnum,
+    sim_ppc_f30_regnum,
+    sim_ppc_f31_regnum,
+
+    /* Altivec vector registers, vr0 -- vr31.  */
+    sim_ppc_vr0_regnum,
+    sim_ppc_vr1_regnum,
+    sim_ppc_vr2_regnum,
+    sim_ppc_vr3_regnum,
+    sim_ppc_vr4_regnum,
+    sim_ppc_vr5_regnum,
+    sim_ppc_vr6_regnum,
+    sim_ppc_vr7_regnum,
+    sim_ppc_vr8_regnum,
+    sim_ppc_vr9_regnum,
+    sim_ppc_vr10_regnum,
+    sim_ppc_vr11_regnum,
+    sim_ppc_vr12_regnum,
+    sim_ppc_vr13_regnum,
+    sim_ppc_vr14_regnum,
+    sim_ppc_vr15_regnum,
+    sim_ppc_vr16_regnum,
+    sim_ppc_vr17_regnum,
+    sim_ppc_vr18_regnum,
+    sim_ppc_vr19_regnum,
+    sim_ppc_vr20_regnum,
+    sim_ppc_vr21_regnum,
+    sim_ppc_vr22_regnum,
+    sim_ppc_vr23_regnum,
+    sim_ppc_vr24_regnum,
+    sim_ppc_vr25_regnum,
+    sim_ppc_vr26_regnum,
+    sim_ppc_vr27_regnum,
+    sim_ppc_vr28_regnum,
+    sim_ppc_vr29_regnum,
+    sim_ppc_vr30_regnum,
+    sim_ppc_vr31_regnum,
+
+    /* SPE APU GPR upper halves.  These are the upper 32 bits of the
+       gprs; there is one upper-half register for each gpr, so it is
+       appropriate to use sim_ppc_num_gprs for iterating through
+       these.  */
+    sim_ppc_rh0_regnum,
+    sim_ppc_rh1_regnum,
+    sim_ppc_rh2_regnum,
+    sim_ppc_rh3_regnum,
+    sim_ppc_rh4_regnum,
+    sim_ppc_rh5_regnum,
+    sim_ppc_rh6_regnum,
+    sim_ppc_rh7_regnum,
+    sim_ppc_rh8_regnum,
+    sim_ppc_rh9_regnum,
+    sim_ppc_rh10_regnum,
+    sim_ppc_rh11_regnum,
+    sim_ppc_rh12_regnum,
+    sim_ppc_rh13_regnum,
+    sim_ppc_rh14_regnum,
+    sim_ppc_rh15_regnum,
+    sim_ppc_rh16_regnum,
+    sim_ppc_rh17_regnum,
+    sim_ppc_rh18_regnum,
+    sim_ppc_rh19_regnum,
+    sim_ppc_rh20_regnum,
+    sim_ppc_rh21_regnum,
+    sim_ppc_rh22_regnum,
+    sim_ppc_rh23_regnum,
+    sim_ppc_rh24_regnum,
+    sim_ppc_rh25_regnum,
+    sim_ppc_rh26_regnum,
+    sim_ppc_rh27_regnum,
+    sim_ppc_rh28_regnum,
+    sim_ppc_rh29_regnum,
+    sim_ppc_rh30_regnum,
+    sim_ppc_rh31_regnum,
+
+    /* SPE APU GPR full registers.  Each of these registers is the
+       64-bit concatenation of a 32-bit GPR (providing the lower bits)
+       and a 32-bit upper-half register (providing the higher bits).
+       As for the upper-half registers, it is appropriate to use
+       sim_ppc_num_gprs with these.  */
+    sim_ppc_ev0_regnum,
+    sim_ppc_ev1_regnum,
+    sim_ppc_ev2_regnum,
+    sim_ppc_ev3_regnum,
+    sim_ppc_ev4_regnum,
+    sim_ppc_ev5_regnum,
+    sim_ppc_ev6_regnum,
+    sim_ppc_ev7_regnum,
+    sim_ppc_ev8_regnum,
+    sim_ppc_ev9_regnum,
+    sim_ppc_ev10_regnum,
+    sim_ppc_ev11_regnum,
+    sim_ppc_ev12_regnum,
+    sim_ppc_ev13_regnum,
+    sim_ppc_ev14_regnum,
+    sim_ppc_ev15_regnum,
+    sim_ppc_ev16_regnum,
+    sim_ppc_ev17_regnum,
+    sim_ppc_ev18_regnum,
+    sim_ppc_ev19_regnum,
+    sim_ppc_ev20_regnum,
+    sim_ppc_ev21_regnum,
+    sim_ppc_ev22_regnum,
+    sim_ppc_ev23_regnum,
+    sim_ppc_ev24_regnum,
+    sim_ppc_ev25_regnum,
+    sim_ppc_ev26_regnum,
+    sim_ppc_ev27_regnum,
+    sim_ppc_ev28_regnum,
+    sim_ppc_ev29_regnum,
+    sim_ppc_ev30_regnum,
+    sim_ppc_ev31_regnum,
+
+    /* Segment registers, sr0 -- sr15.  */
+    sim_ppc_sr0_regnum,
+    sim_ppc_sr1_regnum,
+    sim_ppc_sr2_regnum,
+    sim_ppc_sr3_regnum,
+    sim_ppc_sr4_regnum,
+    sim_ppc_sr5_regnum,
+    sim_ppc_sr6_regnum,
+    sim_ppc_sr7_regnum,
+    sim_ppc_sr8_regnum,
+    sim_ppc_sr9_regnum,
+    sim_ppc_sr10_regnum,
+    sim_ppc_sr11_regnum,
+    sim_ppc_sr12_regnum,
+    sim_ppc_sr13_regnum,
+    sim_ppc_sr14_regnum,
+    sim_ppc_sr15_regnum,
+
+    /* Miscellaneous --- but non-SPR --- registers.  */
+    sim_ppc_pc_regnum,
+    sim_ppc_ps_regnum,
+    sim_ppc_cr_regnum,
+    sim_ppc_fpscr_regnum,
+    sim_ppc_acc_regnum,
+    sim_ppc_vscr_regnum,
+
+    /* Special-purpose registers.  */
+    sim_ppc_spr0_regnum, sim_ppc_spr1_regnum,
+    sim_ppc_spr2_regnum, sim_ppc_spr3_regnum,
+    sim_ppc_spr4_regnum, sim_ppc_spr5_regnum,
+    sim_ppc_spr6_regnum, sim_ppc_spr7_regnum,
+    sim_ppc_spr8_regnum, sim_ppc_spr9_regnum,
+    sim_ppc_spr10_regnum, sim_ppc_spr11_regnum,
+    sim_ppc_spr12_regnum, sim_ppc_spr13_regnum,
+    sim_ppc_spr14_regnum, sim_ppc_spr15_regnum,
+    sim_ppc_spr16_regnum, sim_ppc_spr17_regnum,
+    sim_ppc_spr18_regnum, sim_ppc_spr19_regnum,
+    sim_ppc_spr20_regnum, sim_ppc_spr21_regnum,
+    sim_ppc_spr22_regnum, sim_ppc_spr23_regnum,
+    sim_ppc_spr24_regnum, sim_ppc_spr25_regnum,
+    sim_ppc_spr26_regnum, sim_ppc_spr27_regnum,
+    sim_ppc_spr28_regnum, sim_ppc_spr29_regnum,
+    sim_ppc_spr30_regnum, sim_ppc_spr31_regnum,
+    sim_ppc_spr32_regnum, sim_ppc_spr33_regnum,
+    sim_ppc_spr34_regnum, sim_ppc_spr35_regnum,
+    sim_ppc_spr36_regnum, sim_ppc_spr37_regnum,
+    sim_ppc_spr38_regnum, sim_ppc_spr39_regnum,
+    sim_ppc_spr40_regnum, sim_ppc_spr41_regnum,
+    sim_ppc_spr42_regnum, sim_ppc_spr43_regnum,
+    sim_ppc_spr44_regnum, sim_ppc_spr45_regnum,
+    sim_ppc_spr46_regnum, sim_ppc_spr47_regnum,
+    sim_ppc_spr48_regnum, sim_ppc_spr49_regnum,
+    sim_ppc_spr50_regnum, sim_ppc_spr51_regnum,
+    sim_ppc_spr52_regnum, sim_ppc_spr53_regnum,
+    sim_ppc_spr54_regnum, sim_ppc_spr55_regnum,
+    sim_ppc_spr56_regnum, sim_ppc_spr57_regnum,
+    sim_ppc_spr58_regnum, sim_ppc_spr59_regnum,
+    sim_ppc_spr60_regnum, sim_ppc_spr61_regnum,
+    sim_ppc_spr62_regnum, sim_ppc_spr63_regnum,
+    sim_ppc_spr64_regnum, sim_ppc_spr65_regnum,
+    sim_ppc_spr66_regnum, sim_ppc_spr67_regnum,
+    sim_ppc_spr68_regnum, sim_ppc_spr69_regnum,
+    sim_ppc_spr70_regnum, sim_ppc_spr71_regnum,
+    sim_ppc_spr72_regnum, sim_ppc_spr73_regnum,
+    sim_ppc_spr74_regnum, sim_ppc_spr75_regnum,
+    sim_ppc_spr76_regnum, sim_ppc_spr77_regnum,
+    sim_ppc_spr78_regnum, sim_ppc_spr79_regnum,
+    sim_ppc_spr80_regnum, sim_ppc_spr81_regnum,
+    sim_ppc_spr82_regnum, sim_ppc_spr83_regnum,
+    sim_ppc_spr84_regnum, sim_ppc_spr85_regnum,
+    sim_ppc_spr86_regnum, sim_ppc_spr87_regnum,
+    sim_ppc_spr88_regnum, sim_ppc_spr89_regnum,
+    sim_ppc_spr90_regnum, sim_ppc_spr91_regnum,
+    sim_ppc_spr92_regnum, sim_ppc_spr93_regnum,
+    sim_ppc_spr94_regnum, sim_ppc_spr95_regnum,
+    sim_ppc_spr96_regnum, sim_ppc_spr97_regnum,
+    sim_ppc_spr98_regnum, sim_ppc_spr99_regnum,
+    sim_ppc_spr100_regnum, sim_ppc_spr101_regnum,
+    sim_ppc_spr102_regnum, sim_ppc_spr103_regnum,
+    sim_ppc_spr104_regnum, sim_ppc_spr105_regnum,
+    sim_ppc_spr106_regnum, sim_ppc_spr107_regnum,
+    sim_ppc_spr108_regnum, sim_ppc_spr109_regnum,
+    sim_ppc_spr110_regnum, sim_ppc_spr111_regnum,
+    sim_ppc_spr112_regnum, sim_ppc_spr113_regnum,
+    sim_ppc_spr114_regnum, sim_ppc_spr115_regnum,
+    sim_ppc_spr116_regnum, sim_ppc_spr117_regnum,
+    sim_ppc_spr118_regnum, sim_ppc_spr119_regnum,
+    sim_ppc_spr120_regnum, sim_ppc_spr121_regnum,
+    sim_ppc_spr122_regnum, sim_ppc_spr123_regnum,
+    sim_ppc_spr124_regnum, sim_ppc_spr125_regnum,
+    sim_ppc_spr126_regnum, sim_ppc_spr127_regnum,
+    sim_ppc_spr128_regnum, sim_ppc_spr129_regnum,
+    sim_ppc_spr130_regnum, sim_ppc_spr131_regnum,
+    sim_ppc_spr132_regnum, sim_ppc_spr133_regnum,
+    sim_ppc_spr134_regnum, sim_ppc_spr135_regnum,
+    sim_ppc_spr136_regnum, sim_ppc_spr137_regnum,
+    sim_ppc_spr138_regnum, sim_ppc_spr139_regnum,
+    sim_ppc_spr140_regnum, sim_ppc_spr141_regnum,
+    sim_ppc_spr142_regnum, sim_ppc_spr143_regnum,
+    sim_ppc_spr144_regnum, sim_ppc_spr145_regnum,
+    sim_ppc_spr146_regnum, sim_ppc_spr147_regnum,
+    sim_ppc_spr148_regnum, sim_ppc_spr149_regnum,
+    sim_ppc_spr150_regnum, sim_ppc_spr151_regnum,
+    sim_ppc_spr152_regnum, sim_ppc_spr153_regnum,
+    sim_ppc_spr154_regnum, sim_ppc_spr155_regnum,
+    sim_ppc_spr156_regnum, sim_ppc_spr157_regnum,
+    sim_ppc_spr158_regnum, sim_ppc_spr159_regnum,
+    sim_ppc_spr160_regnum, sim_ppc_spr161_regnum,
+    sim_ppc_spr162_regnum, sim_ppc_spr163_regnum,
+    sim_ppc_spr164_regnum, sim_ppc_spr165_regnum,
+    sim_ppc_spr166_regnum, sim_ppc_spr167_regnum,
+    sim_ppc_spr168_regnum, sim_ppc_spr169_regnum,
+    sim_ppc_spr170_regnum, sim_ppc_spr171_regnum,
+    sim_ppc_spr172_regnum, sim_ppc_spr173_regnum,
+    sim_ppc_spr174_regnum, sim_ppc_spr175_regnum,
+    sim_ppc_spr176_regnum, sim_ppc_spr177_regnum,
+    sim_ppc_spr178_regnum, sim_ppc_spr179_regnum,
+    sim_ppc_spr180_regnum, sim_ppc_spr181_regnum,
+    sim_ppc_spr182_regnum, sim_ppc_spr183_regnum,
+    sim_ppc_spr184_regnum, sim_ppc_spr185_regnum,
+    sim_ppc_spr186_regnum, sim_ppc_spr187_regnum,
+    sim_ppc_spr188_regnum, sim_ppc_spr189_regnum,
+    sim_ppc_spr190_regnum, sim_ppc_spr191_regnum,
+    sim_ppc_spr192_regnum, sim_ppc_spr193_regnum,
+    sim_ppc_spr194_regnum, sim_ppc_spr195_regnum,
+    sim_ppc_spr196_regnum, sim_ppc_spr197_regnum,
+    sim_ppc_spr198_regnum, sim_ppc_spr199_regnum,
+    sim_ppc_spr200_regnum, sim_ppc_spr201_regnum,
+    sim_ppc_spr202_regnum, sim_ppc_spr203_regnum,
+    sim_ppc_spr204_regnum, sim_ppc_spr205_regnum,
+    sim_ppc_spr206_regnum, sim_ppc_spr207_regnum,
+    sim_ppc_spr208_regnum, sim_ppc_spr209_regnum,
+    sim_ppc_spr210_regnum, sim_ppc_spr211_regnum,
+    sim_ppc_spr212_regnum, sim_ppc_spr213_regnum,
+    sim_ppc_spr214_regnum, sim_ppc_spr215_regnum,
+    sim_ppc_spr216_regnum, sim_ppc_spr217_regnum,
+    sim_ppc_spr218_regnum, sim_ppc_spr219_regnum,
+    sim_ppc_spr220_regnum, sim_ppc_spr221_regnum,
+    sim_ppc_spr222_regnum, sim_ppc_spr223_regnum,
+    sim_ppc_spr224_regnum, sim_ppc_spr225_regnum,
+    sim_ppc_spr226_regnum, sim_ppc_spr227_regnum,
+    sim_ppc_spr228_regnum, sim_ppc_spr229_regnum,
+    sim_ppc_spr230_regnum, sim_ppc_spr231_regnum,
+    sim_ppc_spr232_regnum, sim_ppc_spr233_regnum,
+    sim_ppc_spr234_regnum, sim_ppc_spr235_regnum,
+    sim_ppc_spr236_regnum, sim_ppc_spr237_regnum,
+    sim_ppc_spr238_regnum, sim_ppc_spr239_regnum,
+    sim_ppc_spr240_regnum, sim_ppc_spr241_regnum,
+    sim_ppc_spr242_regnum, sim_ppc_spr243_regnum,
+    sim_ppc_spr244_regnum, sim_ppc_spr245_regnum,
+    sim_ppc_spr246_regnum, sim_ppc_spr247_regnum,
+    sim_ppc_spr248_regnum, sim_ppc_spr249_regnum,
+    sim_ppc_spr250_regnum, sim_ppc_spr251_regnum,
+    sim_ppc_spr252_regnum, sim_ppc_spr253_regnum,
+    sim_ppc_spr254_regnum, sim_ppc_spr255_regnum,
+    sim_ppc_spr256_regnum, sim_ppc_spr257_regnum,
+    sim_ppc_spr258_regnum, sim_ppc_spr259_regnum,
+    sim_ppc_spr260_regnum, sim_ppc_spr261_regnum,
+    sim_ppc_spr262_regnum, sim_ppc_spr263_regnum,
+    sim_ppc_spr264_regnum, sim_ppc_spr265_regnum,
+    sim_ppc_spr266_regnum, sim_ppc_spr267_regnum,
+    sim_ppc_spr268_regnum, sim_ppc_spr269_regnum,
+    sim_ppc_spr270_regnum, sim_ppc_spr271_regnum,
+    sim_ppc_spr272_regnum, sim_ppc_spr273_regnum,
+    sim_ppc_spr274_regnum, sim_ppc_spr275_regnum,
+    sim_ppc_spr276_regnum, sim_ppc_spr277_regnum,
+    sim_ppc_spr278_regnum, sim_ppc_spr279_regnum,
+    sim_ppc_spr280_regnum, sim_ppc_spr281_regnum,
+    sim_ppc_spr282_regnum, sim_ppc_spr283_regnum,
+    sim_ppc_spr284_regnum, sim_ppc_spr285_regnum,
+    sim_ppc_spr286_regnum, sim_ppc_spr287_regnum,
+    sim_ppc_spr288_regnum, sim_ppc_spr289_regnum,
+    sim_ppc_spr290_regnum, sim_ppc_spr291_regnum,
+    sim_ppc_spr292_regnum, sim_ppc_spr293_regnum,
+    sim_ppc_spr294_regnum, sim_ppc_spr295_regnum,
+    sim_ppc_spr296_regnum, sim_ppc_spr297_regnum,
+    sim_ppc_spr298_regnum, sim_ppc_spr299_regnum,
+    sim_ppc_spr300_regnum, sim_ppc_spr301_regnum,
+    sim_ppc_spr302_regnum, sim_ppc_spr303_regnum,
+    sim_ppc_spr304_regnum, sim_ppc_spr305_regnum,
+    sim_ppc_spr306_regnum, sim_ppc_spr307_regnum,
+    sim_ppc_spr308_regnum, sim_ppc_spr309_regnum,
+    sim_ppc_spr310_regnum, sim_ppc_spr311_regnum,
+    sim_ppc_spr312_regnum, sim_ppc_spr313_regnum,
+    sim_ppc_spr314_regnum, sim_ppc_spr315_regnum,
+    sim_ppc_spr316_regnum, sim_ppc_spr317_regnum,
+    sim_ppc_spr318_regnum, sim_ppc_spr319_regnum,
+    sim_ppc_spr320_regnum, sim_ppc_spr321_regnum,
+    sim_ppc_spr322_regnum, sim_ppc_spr323_regnum,
+    sim_ppc_spr324_regnum, sim_ppc_spr325_regnum,
+    sim_ppc_spr326_regnum, sim_ppc_spr327_regnum,
+    sim_ppc_spr328_regnum, sim_ppc_spr329_regnum,
+    sim_ppc_spr330_regnum, sim_ppc_spr331_regnum,
+    sim_ppc_spr332_regnum, sim_ppc_spr333_regnum,
+    sim_ppc_spr334_regnum, sim_ppc_spr335_regnum,
+    sim_ppc_spr336_regnum, sim_ppc_spr337_regnum,
+    sim_ppc_spr338_regnum, sim_ppc_spr339_regnum,
+    sim_ppc_spr340_regnum, sim_ppc_spr341_regnum,
+    sim_ppc_spr342_regnum, sim_ppc_spr343_regnum,
+    sim_ppc_spr344_regnum, sim_ppc_spr345_regnum,
+    sim_ppc_spr346_regnum, sim_ppc_spr347_regnum,
+    sim_ppc_spr348_regnum, sim_ppc_spr349_regnum,
+    sim_ppc_spr350_regnum, sim_ppc_spr351_regnum,
+    sim_ppc_spr352_regnum, sim_ppc_spr353_regnum,
+    sim_ppc_spr354_regnum, sim_ppc_spr355_regnum,
+    sim_ppc_spr356_regnum, sim_ppc_spr357_regnum,
+    sim_ppc_spr358_regnum, sim_ppc_spr359_regnum,
+    sim_ppc_spr360_regnum, sim_ppc_spr361_regnum,
+    sim_ppc_spr362_regnum, sim_ppc_spr363_regnum,
+    sim_ppc_spr364_regnum, sim_ppc_spr365_regnum,
+    sim_ppc_spr366_regnum, sim_ppc_spr367_regnum,
+    sim_ppc_spr368_regnum, sim_ppc_spr369_regnum,
+    sim_ppc_spr370_regnum, sim_ppc_spr371_regnum,
+    sim_ppc_spr372_regnum, sim_ppc_spr373_regnum,
+    sim_ppc_spr374_regnum, sim_ppc_spr375_regnum,
+    sim_ppc_spr376_regnum, sim_ppc_spr377_regnum,
+    sim_ppc_spr378_regnum, sim_ppc_spr379_regnum,
+    sim_ppc_spr380_regnum, sim_ppc_spr381_regnum,
+    sim_ppc_spr382_regnum, sim_ppc_spr383_regnum,
+    sim_ppc_spr384_regnum, sim_ppc_spr385_regnum,
+    sim_ppc_spr386_regnum, sim_ppc_spr387_regnum,
+    sim_ppc_spr388_regnum, sim_ppc_spr389_regnum,
+    sim_ppc_spr390_regnum, sim_ppc_spr391_regnum,
+    sim_ppc_spr392_regnum, sim_ppc_spr393_regnum,
+    sim_ppc_spr394_regnum, sim_ppc_spr395_regnum,
+    sim_ppc_spr396_regnum, sim_ppc_spr397_regnum,
+    sim_ppc_spr398_regnum, sim_ppc_spr399_regnum,
+    sim_ppc_spr400_regnum, sim_ppc_spr401_regnum,
+    sim_ppc_spr402_regnum, sim_ppc_spr403_regnum,
+    sim_ppc_spr404_regnum, sim_ppc_spr405_regnum,
+    sim_ppc_spr406_regnum, sim_ppc_spr407_regnum,
+    sim_ppc_spr408_regnum, sim_ppc_spr409_regnum,
+    sim_ppc_spr410_regnum, sim_ppc_spr411_regnum,
+    sim_ppc_spr412_regnum, sim_ppc_spr413_regnum,
+    sim_ppc_spr414_regnum, sim_ppc_spr415_regnum,
+    sim_ppc_spr416_regnum, sim_ppc_spr417_regnum,
+    sim_ppc_spr418_regnum, sim_ppc_spr419_regnum,
+    sim_ppc_spr420_regnum, sim_ppc_spr421_regnum,
+    sim_ppc_spr422_regnum, sim_ppc_spr423_regnum,
+    sim_ppc_spr424_regnum, sim_ppc_spr425_regnum,
+    sim_ppc_spr426_regnum, sim_ppc_spr427_regnum,
+    sim_ppc_spr428_regnum, sim_ppc_spr429_regnum,
+    sim_ppc_spr430_regnum, sim_ppc_spr431_regnum,
+    sim_ppc_spr432_regnum, sim_ppc_spr433_regnum,
+    sim_ppc_spr434_regnum, sim_ppc_spr435_regnum,
+    sim_ppc_spr436_regnum, sim_ppc_spr437_regnum,
+    sim_ppc_spr438_regnum, sim_ppc_spr439_regnum,
+    sim_ppc_spr440_regnum, sim_ppc_spr441_regnum,
+    sim_ppc_spr442_regnum, sim_ppc_spr443_regnum,
+    sim_ppc_spr444_regnum, sim_ppc_spr445_regnum,
+    sim_ppc_spr446_regnum, sim_ppc_spr447_regnum,
+    sim_ppc_spr448_regnum, sim_ppc_spr449_regnum,
+    sim_ppc_spr450_regnum, sim_ppc_spr451_regnum,
+    sim_ppc_spr452_regnum, sim_ppc_spr453_regnum,
+    sim_ppc_spr454_regnum, sim_ppc_spr455_regnum,
+    sim_ppc_spr456_regnum, sim_ppc_spr457_regnum,
+    sim_ppc_spr458_regnum, sim_ppc_spr459_regnum,
+    sim_ppc_spr460_regnum, sim_ppc_spr461_regnum,
+    sim_ppc_spr462_regnum, sim_ppc_spr463_regnum,
+    sim_ppc_spr464_regnum, sim_ppc_spr465_regnum,
+    sim_ppc_spr466_regnum, sim_ppc_spr467_regnum,
+    sim_ppc_spr468_regnum, sim_ppc_spr469_regnum,
+    sim_ppc_spr470_regnum, sim_ppc_spr471_regnum,
+    sim_ppc_spr472_regnum, sim_ppc_spr473_regnum,
+    sim_ppc_spr474_regnum, sim_ppc_spr475_regnum,
+    sim_ppc_spr476_regnum, sim_ppc_spr477_regnum,
+    sim_ppc_spr478_regnum, sim_ppc_spr479_regnum,
+    sim_ppc_spr480_regnum, sim_ppc_spr481_regnum,
+    sim_ppc_spr482_regnum, sim_ppc_spr483_regnum,
+    sim_ppc_spr484_regnum, sim_ppc_spr485_regnum,
+    sim_ppc_spr486_regnum, sim_ppc_spr487_regnum,
+    sim_ppc_spr488_regnum, sim_ppc_spr489_regnum,
+    sim_ppc_spr490_regnum, sim_ppc_spr491_regnum,
+    sim_ppc_spr492_regnum, sim_ppc_spr493_regnum,
+    sim_ppc_spr494_regnum, sim_ppc_spr495_regnum,
+    sim_ppc_spr496_regnum, sim_ppc_spr497_regnum,
+    sim_ppc_spr498_regnum, sim_ppc_spr499_regnum,
+    sim_ppc_spr500_regnum, sim_ppc_spr501_regnum,
+    sim_ppc_spr502_regnum, sim_ppc_spr503_regnum,
+    sim_ppc_spr504_regnum, sim_ppc_spr505_regnum,
+    sim_ppc_spr506_regnum, sim_ppc_spr507_regnum,
+    sim_ppc_spr508_regnum, sim_ppc_spr509_regnum,
+    sim_ppc_spr510_regnum, sim_ppc_spr511_regnum,
+    sim_ppc_spr512_regnum, sim_ppc_spr513_regnum,
+    sim_ppc_spr514_regnum, sim_ppc_spr515_regnum,
+    sim_ppc_spr516_regnum, sim_ppc_spr517_regnum,
+    sim_ppc_spr518_regnum, sim_ppc_spr519_regnum,
+    sim_ppc_spr520_regnum, sim_ppc_spr521_regnum,
+    sim_ppc_spr522_regnum, sim_ppc_spr523_regnum,
+    sim_ppc_spr524_regnum, sim_ppc_spr525_regnum,
+    sim_ppc_spr526_regnum, sim_ppc_spr527_regnum,
+    sim_ppc_spr528_regnum, sim_ppc_spr529_regnum,
+    sim_ppc_spr530_regnum, sim_ppc_spr531_regnum,
+    sim_ppc_spr532_regnum, sim_ppc_spr533_regnum,
+    sim_ppc_spr534_regnum, sim_ppc_spr535_regnum,
+    sim_ppc_spr536_regnum, sim_ppc_spr537_regnum,
+    sim_ppc_spr538_regnum, sim_ppc_spr539_regnum,
+    sim_ppc_spr540_regnum, sim_ppc_spr541_regnum,
+    sim_ppc_spr542_regnum, sim_ppc_spr543_regnum,
+    sim_ppc_spr544_regnum, sim_ppc_spr545_regnum,
+    sim_ppc_spr546_regnum, sim_ppc_spr547_regnum,
+    sim_ppc_spr548_regnum, sim_ppc_spr549_regnum,
+    sim_ppc_spr550_regnum, sim_ppc_spr551_regnum,
+    sim_ppc_spr552_regnum, sim_ppc_spr553_regnum,
+    sim_ppc_spr554_regnum, sim_ppc_spr555_regnum,
+    sim_ppc_spr556_regnum, sim_ppc_spr557_regnum,
+    sim_ppc_spr558_regnum, sim_ppc_spr559_regnum,
+    sim_ppc_spr560_regnum, sim_ppc_spr561_regnum,
+    sim_ppc_spr562_regnum, sim_ppc_spr563_regnum,
+    sim_ppc_spr564_regnum, sim_ppc_spr565_regnum,
+    sim_ppc_spr566_regnum, sim_ppc_spr567_regnum,
+    sim_ppc_spr568_regnum, sim_ppc_spr569_regnum,
+    sim_ppc_spr570_regnum, sim_ppc_spr571_regnum,
+    sim_ppc_spr572_regnum, sim_ppc_spr573_regnum,
+    sim_ppc_spr574_regnum, sim_ppc_spr575_regnum,
+    sim_ppc_spr576_regnum, sim_ppc_spr577_regnum,
+    sim_ppc_spr578_regnum, sim_ppc_spr579_regnum,
+    sim_ppc_spr580_regnum, sim_ppc_spr581_regnum,
+    sim_ppc_spr582_regnum, sim_ppc_spr583_regnum,
+    sim_ppc_spr584_regnum, sim_ppc_spr585_regnum,
+    sim_ppc_spr586_regnum, sim_ppc_spr587_regnum,
+    sim_ppc_spr588_regnum, sim_ppc_spr589_regnum,
+    sim_ppc_spr590_regnum, sim_ppc_spr591_regnum,
+    sim_ppc_spr592_regnum, sim_ppc_spr593_regnum,
+    sim_ppc_spr594_regnum, sim_ppc_spr595_regnum,
+    sim_ppc_spr596_regnum, sim_ppc_spr597_regnum,
+    sim_ppc_spr598_regnum, sim_ppc_spr599_regnum,
+    sim_ppc_spr600_regnum, sim_ppc_spr601_regnum,
+    sim_ppc_spr602_regnum, sim_ppc_spr603_regnum,
+    sim_ppc_spr604_regnum, sim_ppc_spr605_regnum,
+    sim_ppc_spr606_regnum, sim_ppc_spr607_regnum,
+    sim_ppc_spr608_regnum, sim_ppc_spr609_regnum,
+    sim_ppc_spr610_regnum, sim_ppc_spr611_regnum,
+    sim_ppc_spr612_regnum, sim_ppc_spr613_regnum,
+    sim_ppc_spr614_regnum, sim_ppc_spr615_regnum,
+    sim_ppc_spr616_regnum, sim_ppc_spr617_regnum,
+    sim_ppc_spr618_regnum, sim_ppc_spr619_regnum,
+    sim_ppc_spr620_regnum, sim_ppc_spr621_regnum,
+    sim_ppc_spr622_regnum, sim_ppc_spr623_regnum,
+    sim_ppc_spr624_regnum, sim_ppc_spr625_regnum,
+    sim_ppc_spr626_regnum, sim_ppc_spr627_regnum,
+    sim_ppc_spr628_regnum, sim_ppc_spr629_regnum,
+    sim_ppc_spr630_regnum, sim_ppc_spr631_regnum,
+    sim_ppc_spr632_regnum, sim_ppc_spr633_regnum,
+    sim_ppc_spr634_regnum, sim_ppc_spr635_regnum,
+    sim_ppc_spr636_regnum, sim_ppc_spr637_regnum,
+    sim_ppc_spr638_regnum, sim_ppc_spr639_regnum,
+    sim_ppc_spr640_regnum, sim_ppc_spr641_regnum,
+    sim_ppc_spr642_regnum, sim_ppc_spr643_regnum,
+    sim_ppc_spr644_regnum, sim_ppc_spr645_regnum,
+    sim_ppc_spr646_regnum, sim_ppc_spr647_regnum,
+    sim_ppc_spr648_regnum, sim_ppc_spr649_regnum,
+    sim_ppc_spr650_regnum, sim_ppc_spr651_regnum,
+    sim_ppc_spr652_regnum, sim_ppc_spr653_regnum,
+    sim_ppc_spr654_regnum, sim_ppc_spr655_regnum,
+    sim_ppc_spr656_regnum, sim_ppc_spr657_regnum,
+    sim_ppc_spr658_regnum, sim_ppc_spr659_regnum,
+    sim_ppc_spr660_regnum, sim_ppc_spr661_regnum,
+    sim_ppc_spr662_regnum, sim_ppc_spr663_regnum,
+    sim_ppc_spr664_regnum, sim_ppc_spr665_regnum,
+    sim_ppc_spr666_regnum, sim_ppc_spr667_regnum,
+    sim_ppc_spr668_regnum, sim_ppc_spr669_regnum,
+    sim_ppc_spr670_regnum, sim_ppc_spr671_regnum,
+    sim_ppc_spr672_regnum, sim_ppc_spr673_regnum,
+    sim_ppc_spr674_regnum, sim_ppc_spr675_regnum,
+    sim_ppc_spr676_regnum, sim_ppc_spr677_regnum,
+    sim_ppc_spr678_regnum, sim_ppc_spr679_regnum,
+    sim_ppc_spr680_regnum, sim_ppc_spr681_regnum,
+    sim_ppc_spr682_regnum, sim_ppc_spr683_regnum,
+    sim_ppc_spr684_regnum, sim_ppc_spr685_regnum,
+    sim_ppc_spr686_regnum, sim_ppc_spr687_regnum,
+    sim_ppc_spr688_regnum, sim_ppc_spr689_regnum,
+    sim_ppc_spr690_regnum, sim_ppc_spr691_regnum,
+    sim_ppc_spr692_regnum, sim_ppc_spr693_regnum,
+    sim_ppc_spr694_regnum, sim_ppc_spr695_regnum,
+    sim_ppc_spr696_regnum, sim_ppc_spr697_regnum,
+    sim_ppc_spr698_regnum, sim_ppc_spr699_regnum,
+    sim_ppc_spr700_regnum, sim_ppc_spr701_regnum,
+    sim_ppc_spr702_regnum, sim_ppc_spr703_regnum,
+    sim_ppc_spr704_regnum, sim_ppc_spr705_regnum,
+    sim_ppc_spr706_regnum, sim_ppc_spr707_regnum,
+    sim_ppc_spr708_regnum, sim_ppc_spr709_regnum,
+    sim_ppc_spr710_regnum, sim_ppc_spr711_regnum,
+    sim_ppc_spr712_regnum, sim_ppc_spr713_regnum,
+    sim_ppc_spr714_regnum, sim_ppc_spr715_regnum,
+    sim_ppc_spr716_regnum, sim_ppc_spr717_regnum,
+    sim_ppc_spr718_regnum, sim_ppc_spr719_regnum,
+    sim_ppc_spr720_regnum, sim_ppc_spr721_regnum,
+    sim_ppc_spr722_regnum, sim_ppc_spr723_regnum,
+    sim_ppc_spr724_regnum, sim_ppc_spr725_regnum,
+    sim_ppc_spr726_regnum, sim_ppc_spr727_regnum,
+    sim_ppc_spr728_regnum, sim_ppc_spr729_regnum,
+    sim_ppc_spr730_regnum, sim_ppc_spr731_regnum,
+    sim_ppc_spr732_regnum, sim_ppc_spr733_regnum,
+    sim_ppc_spr734_regnum, sim_ppc_spr735_regnum,
+    sim_ppc_spr736_regnum, sim_ppc_spr737_regnum,
+    sim_ppc_spr738_regnum, sim_ppc_spr739_regnum,
+    sim_ppc_spr740_regnum, sim_ppc_spr741_regnum,
+    sim_ppc_spr742_regnum, sim_ppc_spr743_regnum,
+    sim_ppc_spr744_regnum, sim_ppc_spr745_regnum,
+    sim_ppc_spr746_regnum, sim_ppc_spr747_regnum,
+    sim_ppc_spr748_regnum, sim_ppc_spr749_regnum,
+    sim_ppc_spr750_regnum, sim_ppc_spr751_regnum,
+    sim_ppc_spr752_regnum, sim_ppc_spr753_regnum,
+    sim_ppc_spr754_regnum, sim_ppc_spr755_regnum,
+    sim_ppc_spr756_regnum, sim_ppc_spr757_regnum,
+    sim_ppc_spr758_regnum, sim_ppc_spr759_regnum,
+    sim_ppc_spr760_regnum, sim_ppc_spr761_regnum,
+    sim_ppc_spr762_regnum, sim_ppc_spr763_regnum,
+    sim_ppc_spr764_regnum, sim_ppc_spr765_regnum,
+    sim_ppc_spr766_regnum, sim_ppc_spr767_regnum,
+    sim_ppc_spr768_regnum, sim_ppc_spr769_regnum,
+    sim_ppc_spr770_regnum, sim_ppc_spr771_regnum,
+    sim_ppc_spr772_regnum, sim_ppc_spr773_regnum,
+    sim_ppc_spr774_regnum, sim_ppc_spr775_regnum,
+    sim_ppc_spr776_regnum, sim_ppc_spr777_regnum,
+    sim_ppc_spr778_regnum, sim_ppc_spr779_regnum,
+    sim_ppc_spr780_regnum, sim_ppc_spr781_regnum,
+    sim_ppc_spr782_regnum, sim_ppc_spr783_regnum,
+    sim_ppc_spr784_regnum, sim_ppc_spr785_regnum,
+    sim_ppc_spr786_regnum, sim_ppc_spr787_regnum,
+    sim_ppc_spr788_regnum, sim_ppc_spr789_regnum,
+    sim_ppc_spr790_regnum, sim_ppc_spr791_regnum,
+    sim_ppc_spr792_regnum, sim_ppc_spr793_regnum,
+    sim_ppc_spr794_regnum, sim_ppc_spr795_regnum,
+    sim_ppc_spr796_regnum, sim_ppc_spr797_regnum,
+    sim_ppc_spr798_regnum, sim_ppc_spr799_regnum,
+    sim_ppc_spr800_regnum, sim_ppc_spr801_regnum,
+    sim_ppc_spr802_regnum, sim_ppc_spr803_regnum,
+    sim_ppc_spr804_regnum, sim_ppc_spr805_regnum,
+    sim_ppc_spr806_regnum, sim_ppc_spr807_regnum,
+    sim_ppc_spr808_regnum, sim_ppc_spr809_regnum,
+    sim_ppc_spr810_regnum, sim_ppc_spr811_regnum,
+    sim_ppc_spr812_regnum, sim_ppc_spr813_regnum,
+    sim_ppc_spr814_regnum, sim_ppc_spr815_regnum,
+    sim_ppc_spr816_regnum, sim_ppc_spr817_regnum,
+    sim_ppc_spr818_regnum, sim_ppc_spr819_regnum,
+    sim_ppc_spr820_regnum, sim_ppc_spr821_regnum,
+    sim_ppc_spr822_regnum, sim_ppc_spr823_regnum,
+    sim_ppc_spr824_regnum, sim_ppc_spr825_regnum,
+    sim_ppc_spr826_regnum, sim_ppc_spr827_regnum,
+    sim_ppc_spr828_regnum, sim_ppc_spr829_regnum,
+    sim_ppc_spr830_regnum, sim_ppc_spr831_regnum,
+    sim_ppc_spr832_regnum, sim_ppc_spr833_regnum,
+    sim_ppc_spr834_regnum, sim_ppc_spr835_regnum,
+    sim_ppc_spr836_regnum, sim_ppc_spr837_regnum,
+    sim_ppc_spr838_regnum, sim_ppc_spr839_regnum,
+    sim_ppc_spr840_regnum, sim_ppc_spr841_regnum,
+    sim_ppc_spr842_regnum, sim_ppc_spr843_regnum,
+    sim_ppc_spr844_regnum, sim_ppc_spr845_regnum,
+    sim_ppc_spr846_regnum, sim_ppc_spr847_regnum,
+    sim_ppc_spr848_regnum, sim_ppc_spr849_regnum,
+    sim_ppc_spr850_regnum, sim_ppc_spr851_regnum,
+    sim_ppc_spr852_regnum, sim_ppc_spr853_regnum,
+    sim_ppc_spr854_regnum, sim_ppc_spr855_regnum,
+    sim_ppc_spr856_regnum, sim_ppc_spr857_regnum,
+    sim_ppc_spr858_regnum, sim_ppc_spr859_regnum,
+    sim_ppc_spr860_regnum, sim_ppc_spr861_regnum,
+    sim_ppc_spr862_regnum, sim_ppc_spr863_regnum,
+    sim_ppc_spr864_regnum, sim_ppc_spr865_regnum,
+    sim_ppc_spr866_regnum, sim_ppc_spr867_regnum,
+    sim_ppc_spr868_regnum, sim_ppc_spr869_regnum,
+    sim_ppc_spr870_regnum, sim_ppc_spr871_regnum,
+    sim_ppc_spr872_regnum, sim_ppc_spr873_regnum,
+    sim_ppc_spr874_regnum, sim_ppc_spr875_regnum,
+    sim_ppc_spr876_regnum, sim_ppc_spr877_regnum,
+    sim_ppc_spr878_regnum, sim_ppc_spr879_regnum,
+    sim_ppc_spr880_regnum, sim_ppc_spr881_regnum,
+    sim_ppc_spr882_regnum, sim_ppc_spr883_regnum,
+    sim_ppc_spr884_regnum, sim_ppc_spr885_regnum,
+    sim_ppc_spr886_regnum, sim_ppc_spr887_regnum,
+    sim_ppc_spr888_regnum, sim_ppc_spr889_regnum,
+    sim_ppc_spr890_regnum, sim_ppc_spr891_regnum,
+    sim_ppc_spr892_regnum, sim_ppc_spr893_regnum,
+    sim_ppc_spr894_regnum, sim_ppc_spr895_regnum,
+    sim_ppc_spr896_regnum, sim_ppc_spr897_regnum,
+    sim_ppc_spr898_regnum, sim_ppc_spr899_regnum,
+    sim_ppc_spr900_regnum, sim_ppc_spr901_regnum,
+    sim_ppc_spr902_regnum, sim_ppc_spr903_regnum,
+    sim_ppc_spr904_regnum, sim_ppc_spr905_regnum,
+    sim_ppc_spr906_regnum, sim_ppc_spr907_regnum,
+    sim_ppc_spr908_regnum, sim_ppc_spr909_regnum,
+    sim_ppc_spr910_regnum, sim_ppc_spr911_regnum,
+    sim_ppc_spr912_regnum, sim_ppc_spr913_regnum,
+    sim_ppc_spr914_regnum, sim_ppc_spr915_regnum,
+    sim_ppc_spr916_regnum, sim_ppc_spr917_regnum,
+    sim_ppc_spr918_regnum, sim_ppc_spr919_regnum,
+    sim_ppc_spr920_regnum, sim_ppc_spr921_regnum,
+    sim_ppc_spr922_regnum, sim_ppc_spr923_regnum,
+    sim_ppc_spr924_regnum, sim_ppc_spr925_regnum,
+    sim_ppc_spr926_regnum, sim_ppc_spr927_regnum,
+    sim_ppc_spr928_regnum, sim_ppc_spr929_regnum,
+    sim_ppc_spr930_regnum, sim_ppc_spr931_regnum,
+    sim_ppc_spr932_regnum, sim_ppc_spr933_regnum,
+    sim_ppc_spr934_regnum, sim_ppc_spr935_regnum,
+    sim_ppc_spr936_regnum, sim_ppc_spr937_regnum,
+    sim_ppc_spr938_regnum, sim_ppc_spr939_regnum,
+    sim_ppc_spr940_regnum, sim_ppc_spr941_regnum,
+    sim_ppc_spr942_regnum, sim_ppc_spr943_regnum,
+    sim_ppc_spr944_regnum, sim_ppc_spr945_regnum,
+    sim_ppc_spr946_regnum, sim_ppc_spr947_regnum,
+    sim_ppc_spr948_regnum, sim_ppc_spr949_regnum,
+    sim_ppc_spr950_regnum, sim_ppc_spr951_regnum,
+    sim_ppc_spr952_regnum, sim_ppc_spr953_regnum,
+    sim_ppc_spr954_regnum, sim_ppc_spr955_regnum,
+    sim_ppc_spr956_regnum, sim_ppc_spr957_regnum,
+    sim_ppc_spr958_regnum, sim_ppc_spr959_regnum,
+    sim_ppc_spr960_regnum, sim_ppc_spr961_regnum,
+    sim_ppc_spr962_regnum, sim_ppc_spr963_regnum,
+    sim_ppc_spr964_regnum, sim_ppc_spr965_regnum,
+    sim_ppc_spr966_regnum, sim_ppc_spr967_regnum,
+    sim_ppc_spr968_regnum, sim_ppc_spr969_regnum,
+    sim_ppc_spr970_regnum, sim_ppc_spr971_regnum,
+    sim_ppc_spr972_regnum, sim_ppc_spr973_regnum,
+    sim_ppc_spr974_regnum, sim_ppc_spr975_regnum,
+    sim_ppc_spr976_regnum, sim_ppc_spr977_regnum,
+    sim_ppc_spr978_regnum, sim_ppc_spr979_regnum,
+    sim_ppc_spr980_regnum, sim_ppc_spr981_regnum,
+    sim_ppc_spr982_regnum, sim_ppc_spr983_regnum,
+    sim_ppc_spr984_regnum, sim_ppc_spr985_regnum,
+    sim_ppc_spr986_regnum, sim_ppc_spr987_regnum,
+    sim_ppc_spr988_regnum, sim_ppc_spr989_regnum,
+    sim_ppc_spr990_regnum, sim_ppc_spr991_regnum,
+    sim_ppc_spr992_regnum, sim_ppc_spr993_regnum,
+    sim_ppc_spr994_regnum, sim_ppc_spr995_regnum,
+    sim_ppc_spr996_regnum, sim_ppc_spr997_regnum,
+    sim_ppc_spr998_regnum, sim_ppc_spr999_regnum,
+    sim_ppc_spr1000_regnum, sim_ppc_spr1001_regnum,
+    sim_ppc_spr1002_regnum, sim_ppc_spr1003_regnum,
+    sim_ppc_spr1004_regnum, sim_ppc_spr1005_regnum,
+    sim_ppc_spr1006_regnum, sim_ppc_spr1007_regnum,
+    sim_ppc_spr1008_regnum, sim_ppc_spr1009_regnum,
+    sim_ppc_spr1010_regnum, sim_ppc_spr1011_regnum,
+    sim_ppc_spr1012_regnum, sim_ppc_spr1013_regnum,
+    sim_ppc_spr1014_regnum, sim_ppc_spr1015_regnum,
+    sim_ppc_spr1016_regnum, sim_ppc_spr1017_regnum,
+    sim_ppc_spr1018_regnum, sim_ppc_spr1019_regnum,
+    sim_ppc_spr1020_regnum, sim_ppc_spr1021_regnum,
+    sim_ppc_spr1022_regnum, sim_ppc_spr1023_regnum
+  };
+
+
+/* Sizes of various register sets.  */
+enum
+  {
+    sim_ppc_num_gprs = 32,
+    sim_ppc_num_fprs = 32,
+    sim_ppc_num_vrs = 32,
+    sim_ppc_num_srs = 16,
+    sim_ppc_num_sprs = 1024,
+  };
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SIM_PPC_H */
diff --git a/sim/ppc/gdb-sim.c b/sim/ppc/gdb-sim.c
new file mode 100644
index 00000000000..648d8ef1285
--- /dev/null
+++ b/sim/ppc/gdb-sim.c
@@ -0,0 +1,1295 @@
+/*  This file is part of GDB.
+
+    Copyright 2004 Free Software Foundation, Inc.
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+ 
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ 
+    */
+
+
+#include "psim.h"
+#include "options.h"
+#include "registers.h"
+
+#include "ansidecl.h"
+#include "sim_callbacks.h"
+#include "gdb/callback.h"
+#include "gdb/remote-sim.h"
+#include "gdb/sim-ppc.h"
+
+/* Return the name of the register whose number is REGNUM, or zero if
+   REGNUM is an invalid register number.  */
+
+static const char *
+regnum2spr (int spr)
+{
+  if (spr_is_valid (spr))
+    return spr_name (spr);
+  else
+    return NULL;
+}
+
+static const char *
+regnum2name (int regnum)
+{
+  switch (regnum)
+    {
+    case sim_ppc_r0_regnum: return "r0";
+    case sim_ppc_r1_regnum: return "r1";
+    case sim_ppc_r2_regnum: return "r2";
+    case sim_ppc_r3_regnum: return "r3";
+    case sim_ppc_r4_regnum: return "r4";
+    case sim_ppc_r5_regnum: return "r5";
+    case sim_ppc_r6_regnum: return "r6";
+    case sim_ppc_r7_regnum: return "r7";
+    case sim_ppc_r8_regnum: return "r8";
+    case sim_ppc_r9_regnum: return "r9";
+    case sim_ppc_r10_regnum: return "r10";
+    case sim_ppc_r11_regnum: return "r11";
+    case sim_ppc_r12_regnum: return "r12";
+    case sim_ppc_r13_regnum: return "r13";
+    case sim_ppc_r14_regnum: return "r14";
+    case sim_ppc_r15_regnum: return "r15";
+    case sim_ppc_r16_regnum: return "r16";
+    case sim_ppc_r17_regnum: return "r17";
+    case sim_ppc_r18_regnum: return "r18";
+    case sim_ppc_r19_regnum: return "r19";
+    case sim_ppc_r20_regnum: return "r20";
+    case sim_ppc_r21_regnum: return "r21";
+    case sim_ppc_r22_regnum: return "r22";
+    case sim_ppc_r23_regnum: return "r23";
+    case sim_ppc_r24_regnum: return "r24";
+    case sim_ppc_r25_regnum: return "r25";
+    case sim_ppc_r26_regnum: return "r26";
+    case sim_ppc_r27_regnum: return "r27";
+    case sim_ppc_r28_regnum: return "r28";
+    case sim_ppc_r29_regnum: return "r29";
+    case sim_ppc_r30_regnum: return "r30";
+    case sim_ppc_r31_regnum: return "r31";
+
+    case sim_ppc_f0_regnum: return "f0";
+    case sim_ppc_f1_regnum: return "f1";
+    case sim_ppc_f2_regnum: return "f2";
+    case sim_ppc_f3_regnum: return "f3";
+    case sim_ppc_f4_regnum: return "f4";
+    case sim_ppc_f5_regnum: return "f5";
+    case sim_ppc_f6_regnum: return "f6";
+    case sim_ppc_f7_regnum: return "f7";
+    case sim_ppc_f8_regnum: return "f8";
+    case sim_ppc_f9_regnum: return "f9";
+    case sim_ppc_f10_regnum: return "f10";
+    case sim_ppc_f11_regnum: return "f11";
+    case sim_ppc_f12_regnum: return "f12";
+    case sim_ppc_f13_regnum: return "f13";
+    case sim_ppc_f14_regnum: return "f14";
+    case sim_ppc_f15_regnum: return "f15";
+    case sim_ppc_f16_regnum: return "f16";
+    case sim_ppc_f17_regnum: return "f17";
+    case sim_ppc_f18_regnum: return "f18";
+    case sim_ppc_f19_regnum: return "f19";
+    case sim_ppc_f20_regnum: return "f20";
+    case sim_ppc_f21_regnum: return "f21";
+    case sim_ppc_f22_regnum: return "f22";
+    case sim_ppc_f23_regnum: return "f23";
+    case sim_ppc_f24_regnum: return "f24";
+    case sim_ppc_f25_regnum: return "f25";
+    case sim_ppc_f26_regnum: return "f26";
+    case sim_ppc_f27_regnum: return "f27";
+    case sim_ppc_f28_regnum: return "f28";
+    case sim_ppc_f29_regnum: return "f29";
+    case sim_ppc_f30_regnum: return "f30";
+    case sim_ppc_f31_regnum: return "f31";
+
+    case sim_ppc_vr0_regnum: return "vr0";
+    case sim_ppc_vr1_regnum: return "vr1";
+    case sim_ppc_vr2_regnum: return "vr2";
+    case sim_ppc_vr3_regnum: return "vr3";
+    case sim_ppc_vr4_regnum: return "vr4";
+    case sim_ppc_vr5_regnum: return "vr5";
+    case sim_ppc_vr6_regnum: return "vr6";
+    case sim_ppc_vr7_regnum: return "vr7";
+    case sim_ppc_vr8_regnum: return "vr8";
+    case sim_ppc_vr9_regnum: return "vr9";
+    case sim_ppc_vr10_regnum: return "vr10";
+    case sim_ppc_vr11_regnum: return "vr11";
+    case sim_ppc_vr12_regnum: return "vr12";
+    case sim_ppc_vr13_regnum: return "vr13";
+    case sim_ppc_vr14_regnum: return "vr14";
+    case sim_ppc_vr15_regnum: return "vr15";
+    case sim_ppc_vr16_regnum: return "vr16";
+    case sim_ppc_vr17_regnum: return "vr17";
+    case sim_ppc_vr18_regnum: return "vr18";
+    case sim_ppc_vr19_regnum: return "vr19";
+    case sim_ppc_vr20_regnum: return "vr20";
+    case sim_ppc_vr21_regnum: return "vr21";
+    case sim_ppc_vr22_regnum: return "vr22";
+    case sim_ppc_vr23_regnum: return "vr23";
+    case sim_ppc_vr24_regnum: return "vr24";
+    case sim_ppc_vr25_regnum: return "vr25";
+    case sim_ppc_vr26_regnum: return "vr26";
+    case sim_ppc_vr27_regnum: return "vr27";
+    case sim_ppc_vr28_regnum: return "vr28";
+    case sim_ppc_vr29_regnum: return "vr29";
+    case sim_ppc_vr30_regnum: return "vr30";
+    case sim_ppc_vr31_regnum: return "vr31";
+    case sim_ppc_rh0_regnum: return "rh0";
+    case sim_ppc_rh1_regnum: return "rh1";
+    case sim_ppc_rh2_regnum: return "rh2";
+    case sim_ppc_rh3_regnum: return "rh3";
+    case sim_ppc_rh4_regnum: return "rh4";
+    case sim_ppc_rh5_regnum: return "rh5";
+    case sim_ppc_rh6_regnum: return "rh6";
+    case sim_ppc_rh7_regnum: return "rh7";
+    case sim_ppc_rh8_regnum: return "rh8";
+    case sim_ppc_rh9_regnum: return "rh9";
+    case sim_ppc_rh10_regnum: return "rh10";
+    case sim_ppc_rh11_regnum: return "rh11";
+    case sim_ppc_rh12_regnum: return "rh12";
+    case sim_ppc_rh13_regnum: return "rh13";
+    case sim_ppc_rh14_regnum: return "rh14";
+    case sim_ppc_rh15_regnum: return "rh15";
+    case sim_ppc_rh16_regnum: return "rh16";
+    case sim_ppc_rh17_regnum: return "rh17";
+    case sim_ppc_rh18_regnum: return "rh18";
+    case sim_ppc_rh19_regnum: return "rh19";
+    case sim_ppc_rh20_regnum: return "rh20";
+    case sim_ppc_rh21_regnum: return "rh21";
+    case sim_ppc_rh22_regnum: return "rh22";
+    case sim_ppc_rh23_regnum: return "rh23";
+    case sim_ppc_rh24_regnum: return "rh24";
+    case sim_ppc_rh25_regnum: return "rh25";
+    case sim_ppc_rh26_regnum: return "rh26";
+    case sim_ppc_rh27_regnum: return "rh27";
+    case sim_ppc_rh28_regnum: return "rh28";
+    case sim_ppc_rh29_regnum: return "rh29";
+    case sim_ppc_rh30_regnum: return "rh30";
+    case sim_ppc_rh31_regnum: return "rh31";
+
+    case sim_ppc_ev0_regnum: return "ev0";
+    case sim_ppc_ev1_regnum: return "ev1";
+    case sim_ppc_ev2_regnum: return "ev2";
+    case sim_ppc_ev3_regnum: return "ev3";
+    case sim_ppc_ev4_regnum: return "ev4";
+    case sim_ppc_ev5_regnum: return "ev5";
+    case sim_ppc_ev6_regnum: return "ev6";
+    case sim_ppc_ev7_regnum: return "ev7";
+    case sim_ppc_ev8_regnum: return "ev8";
+    case sim_ppc_ev9_regnum: return "ev9";
+    case sim_ppc_ev10_regnum: return "ev10";
+    case sim_ppc_ev11_regnum: return "ev11";
+    case sim_ppc_ev12_regnum: return "ev12";
+    case sim_ppc_ev13_regnum: return "ev13";
+    case sim_ppc_ev14_regnum: return "ev14";
+    case sim_ppc_ev15_regnum: return "ev15";
+    case sim_ppc_ev16_regnum: return "ev16";
+    case sim_ppc_ev17_regnum: return "ev17";
+    case sim_ppc_ev18_regnum: return "ev18";
+    case sim_ppc_ev19_regnum: return "ev19";
+    case sim_ppc_ev20_regnum: return "ev20";
+    case sim_ppc_ev21_regnum: return "ev21";
+    case sim_ppc_ev22_regnum: return "ev22";
+    case sim_ppc_ev23_regnum: return "ev23";
+    case sim_ppc_ev24_regnum: return "ev24";
+    case sim_ppc_ev25_regnum: return "ev25";
+    case sim_ppc_ev26_regnum: return "ev26";
+    case sim_ppc_ev27_regnum: return "ev27";
+    case sim_ppc_ev28_regnum: return "ev28";
+    case sim_ppc_ev29_regnum: return "ev29";
+    case sim_ppc_ev30_regnum: return "ev30";
+    case sim_ppc_ev31_regnum: return "ev31";
+
+    case sim_ppc_sr0_regnum: return "sr0";
+    case sim_ppc_sr1_regnum: return "sr1";
+    case sim_ppc_sr2_regnum: return "sr2";
+    case sim_ppc_sr3_regnum: return "sr3";
+    case sim_ppc_sr4_regnum: return "sr4";
+    case sim_ppc_sr5_regnum: return "sr5";
+    case sim_ppc_sr6_regnum: return "sr6";
+    case sim_ppc_sr7_regnum: return "sr7";
+    case sim_ppc_sr8_regnum: return "sr8";
+    case sim_ppc_sr9_regnum: return "sr9";
+    case sim_ppc_sr10_regnum: return "sr10";
+    case sim_ppc_sr11_regnum: return "sr11";
+    case sim_ppc_sr12_regnum: return "sr12";
+    case sim_ppc_sr13_regnum: return "sr13";
+    case sim_ppc_sr14_regnum: return "sr14";
+    case sim_ppc_sr15_regnum: return "sr15";
+
+    case sim_ppc_pc_regnum: return "pc";
+    case sim_ppc_ps_regnum: return "ps";
+    case sim_ppc_cr_regnum: return "cr";
+    case sim_ppc_fpscr_regnum: return "fpscr";
+    case sim_ppc_acc_regnum: return "acc";
+    case sim_ppc_vscr_regnum: return "vscr";
+
+    case sim_ppc_spr0_regnum: return regnum2spr (0);
+    case sim_ppc_spr1_regnum: return regnum2spr (1);
+    case sim_ppc_spr2_regnum: return regnum2spr (2);
+    case sim_ppc_spr3_regnum: return regnum2spr (3);
+    case sim_ppc_spr4_regnum: return regnum2spr (4);
+    case sim_ppc_spr5_regnum: return regnum2spr (5);
+    case sim_ppc_spr6_regnum: return regnum2spr (6);
+    case sim_ppc_spr7_regnum: return regnum2spr (7);
+    case sim_ppc_spr8_regnum: return regnum2spr (8);
+    case sim_ppc_spr9_regnum: return regnum2spr (9);
+    case sim_ppc_spr10_regnum: return regnum2spr (10);
+    case sim_ppc_spr11_regnum: return regnum2spr (11);
+    case sim_ppc_spr12_regnum: return regnum2spr (12);
+    case sim_ppc_spr13_regnum: return regnum2spr (13);
+    case sim_ppc_spr14_regnum: return regnum2spr (14);
+    case sim_ppc_spr15_regnum: return regnum2spr (15);
+    case sim_ppc_spr16_regnum: return regnum2spr (16);
+    case sim_ppc_spr17_regnum: return regnum2spr (17);
+    case sim_ppc_spr18_regnum: return regnum2spr (18);
+    case sim_ppc_spr19_regnum: return regnum2spr (19);
+    case sim_ppc_spr20_regnum: return regnum2spr (20);
+    case sim_ppc_spr21_regnum: return regnum2spr (21);
+    case sim_ppc_spr22_regnum: return regnum2spr (22);
+    case sim_ppc_spr23_regnum: return regnum2spr (23);
+    case sim_ppc_spr24_regnum: return regnum2spr (24);
+    case sim_ppc_spr25_regnum: return regnum2spr (25);
+    case sim_ppc_spr26_regnum: return regnum2spr (26);
+    case sim_ppc_spr27_regnum: return regnum2spr (27);
+    case sim_ppc_spr28_regnum: return regnum2spr (28);
+    case sim_ppc_spr29_regnum: return regnum2spr (29);
+    case sim_ppc_spr30_regnum: return regnum2spr (30);
+    case sim_ppc_spr31_regnum: return regnum2spr (31);
+    case sim_ppc_spr32_regnum: return regnum2spr (32);
+    case sim_ppc_spr33_regnum: return regnum2spr (33);
+    case sim_ppc_spr34_regnum: return regnum2spr (34);
+    case sim_ppc_spr35_regnum: return regnum2spr (35);
+    case sim_ppc_spr36_regnum: return regnum2spr (36);
+    case sim_ppc_spr37_regnum: return regnum2spr (37);
+    case sim_ppc_spr38_regnum: return regnum2spr (38);
+    case sim_ppc_spr39_regnum: return regnum2spr (39);
+    case sim_ppc_spr40_regnum: return regnum2spr (40);
+    case sim_ppc_spr41_regnum: return regnum2spr (41);
+    case sim_ppc_spr42_regnum: return regnum2spr (42);
+    case sim_ppc_spr43_regnum: return regnum2spr (43);
+    case sim_ppc_spr44_regnum: return regnum2spr (44);
+    case sim_ppc_spr45_regnum: return regnum2spr (45);
+    case sim_ppc_spr46_regnum: return regnum2spr (46);
+    case sim_ppc_spr47_regnum: return regnum2spr (47);
+    case sim_ppc_spr48_regnum: return regnum2spr (48);
+    case sim_ppc_spr49_regnum: return regnum2spr (49);
+    case sim_ppc_spr50_regnum: return regnum2spr (50);
+    case sim_ppc_spr51_regnum: return regnum2spr (51);
+    case sim_ppc_spr52_regnum: return regnum2spr (52);
+    case sim_ppc_spr53_regnum: return regnum2spr (53);
+    case sim_ppc_spr54_regnum: return regnum2spr (54);
+    case sim_ppc_spr55_regnum: return regnum2spr (55);
+    case sim_ppc_spr56_regnum: return regnum2spr (56);
+    case sim_ppc_spr57_regnum: return regnum2spr (57);
+    case sim_ppc_spr58_regnum: return regnum2spr (58);
+    case sim_ppc_spr59_regnum: return regnum2spr (59);
+    case sim_ppc_spr60_regnum: return regnum2spr (60);
+    case sim_ppc_spr61_regnum: return regnum2spr (61);
+    case sim_ppc_spr62_regnum: return regnum2spr (62);
+    case sim_ppc_spr63_regnum: return regnum2spr (63);
+    case sim_ppc_spr64_regnum: return regnum2spr (64);
+    case sim_ppc_spr65_regnum: return regnum2spr (65);
+    case sim_ppc_spr66_regnum: return regnum2spr (66);
+    case sim_ppc_spr67_regnum: return regnum2spr (67);
+    case sim_ppc_spr68_regnum: return regnum2spr (68);
+    case sim_ppc_spr69_regnum: return regnum2spr (69);
+    case sim_ppc_spr70_regnum: return regnum2spr (70);
+    case sim_ppc_spr71_regnum: return regnum2spr (71);
+    case sim_ppc_spr72_regnum: return regnum2spr (72);
+    case sim_ppc_spr73_regnum: return regnum2spr (73);
+    case sim_ppc_spr74_regnum: return regnum2spr (74);
+    case sim_ppc_spr75_regnum: return regnum2spr (75);
+    case sim_ppc_spr76_regnum: return regnum2spr (76);
+    case sim_ppc_spr77_regnum: return regnum2spr (77);
+    case sim_ppc_spr78_regnum: return regnum2spr (78);
+    case sim_ppc_spr79_regnum: return regnum2spr (79);
+    case sim_ppc_spr80_regnum: return regnum2spr (80);
+    case sim_ppc_spr81_regnum: return regnum2spr (81);
+    case sim_ppc_spr82_regnum: return regnum2spr (82);
+    case sim_ppc_spr83_regnum: return regnum2spr (83);
+    case sim_ppc_spr84_regnum: return regnum2spr (84);
+    case sim_ppc_spr85_regnum: return regnum2spr (85);
+    case sim_ppc_spr86_regnum: return regnum2spr (86);
+    case sim_ppc_spr87_regnum: return regnum2spr (87);
+    case sim_ppc_spr88_regnum: return regnum2spr (88);
+    case sim_ppc_spr89_regnum: return regnum2spr (89);
+    case sim_ppc_spr90_regnum: return regnum2spr (90);
+    case sim_ppc_spr91_regnum: return regnum2spr (91);
+    case sim_ppc_spr92_regnum: return regnum2spr (92);
+    case sim_ppc_spr93_regnum: return regnum2spr (93);
+    case sim_ppc_spr94_regnum: return regnum2spr (94);
+    case sim_ppc_spr95_regnum: return regnum2spr (95);
+    case sim_ppc_spr96_regnum: return regnum2spr (96);
+    case sim_ppc_spr97_regnum: return regnum2spr (97);
+    case sim_ppc_spr98_regnum: return regnum2spr (98);
+    case sim_ppc_spr99_regnum: return regnum2spr (99);
+    case sim_ppc_spr100_regnum: return regnum2spr (100);
+    case sim_ppc_spr101_regnum: return regnum2spr (101);
+    case sim_ppc_spr102_regnum: return regnum2spr (102);
+    case sim_ppc_spr103_regnum: return regnum2spr (103);
+    case sim_ppc_spr104_regnum: return regnum2spr (104);
+    case sim_ppc_spr105_regnum: return regnum2spr (105);
+    case sim_ppc_spr106_regnum: return regnum2spr (106);
+    case sim_ppc_spr107_regnum: return regnum2spr (107);
+    case sim_ppc_spr108_regnum: return regnum2spr (108);
+    case sim_ppc_spr109_regnum: return regnum2spr (109);
+    case sim_ppc_spr110_regnum: return regnum2spr (110);
+    case sim_ppc_spr111_regnum: return regnum2spr (111);
+    case sim_ppc_spr112_regnum: return regnum2spr (112);
+    case sim_ppc_spr113_regnum: return regnum2spr (113);
+    case sim_ppc_spr114_regnum: return regnum2spr (114);
+    case sim_ppc_spr115_regnum: return regnum2spr (115);
+    case sim_ppc_spr116_regnum: return regnum2spr (116);
+    case sim_ppc_spr117_regnum: return regnum2spr (117);
+    case sim_ppc_spr118_regnum: return regnum2spr (118);
+    case sim_ppc_spr119_regnum: return regnum2spr (119);
+    case sim_ppc_spr120_regnum: return regnum2spr (120);
+    case sim_ppc_spr121_regnum: return regnum2spr (121);
+    case sim_ppc_spr122_regnum: return regnum2spr (122);
+    case sim_ppc_spr123_regnum: return regnum2spr (123);
+    case sim_ppc_spr124_regnum: return regnum2spr (124);
+    case sim_ppc_spr125_regnum: return regnum2spr (125);
+    case sim_ppc_spr126_regnum: return regnum2spr (126);
+    case sim_ppc_spr127_regnum: return regnum2spr (127);
+    case sim_ppc_spr128_regnum: return regnum2spr (128);
+    case sim_ppc_spr129_regnum: return regnum2spr (129);
+    case sim_ppc_spr130_regnum: return regnum2spr (130);
+    case sim_ppc_spr131_regnum: return regnum2spr (131);
+    case sim_ppc_spr132_regnum: return regnum2spr (132);
+    case sim_ppc_spr133_regnum: return regnum2spr (133);
+    case sim_ppc_spr134_regnum: return regnum2spr (134);
+    case sim_ppc_spr135_regnum: return regnum2spr (135);
+    case sim_ppc_spr136_regnum: return regnum2spr (136);
+    case sim_ppc_spr137_regnum: return regnum2spr (137);
+    case sim_ppc_spr138_regnum: return regnum2spr (138);
+    case sim_ppc_spr139_regnum: return regnum2spr (139);
+    case sim_ppc_spr140_regnum: return regnum2spr (140);
+    case sim_ppc_spr141_regnum: return regnum2spr (141);
+    case sim_ppc_spr142_regnum: return regnum2spr (142);
+    case sim_ppc_spr143_regnum: return regnum2spr (143);
+    case sim_ppc_spr144_regnum: return regnum2spr (144);
+    case sim_ppc_spr145_regnum: return regnum2spr (145);
+    case sim_ppc_spr146_regnum: return regnum2spr (146);
+    case sim_ppc_spr147_regnum: return regnum2spr (147);
+    case sim_ppc_spr148_regnum: return regnum2spr (148);
+    case sim_ppc_spr149_regnum: return regnum2spr (149);
+    case sim_ppc_spr150_regnum: return regnum2spr (150);
+    case sim_ppc_spr151_regnum: return regnum2spr (151);
+    case sim_ppc_spr152_regnum: return regnum2spr (152);
+    case sim_ppc_spr153_regnum: return regnum2spr (153);
+    case sim_ppc_spr154_regnum: return regnum2spr (154);
+    case sim_ppc_spr155_regnum: return regnum2spr (155);
+    case sim_ppc_spr156_regnum: return regnum2spr (156);
+    case sim_ppc_spr157_regnum: return regnum2spr (157);
+    case sim_ppc_spr158_regnum: return regnum2spr (158);
+    case sim_ppc_spr159_regnum: return regnum2spr (159);
+    case sim_ppc_spr160_regnum: return regnum2spr (160);
+    case sim_ppc_spr161_regnum: return regnum2spr (161);
+    case sim_ppc_spr162_regnum: return regnum2spr (162);
+    case sim_ppc_spr163_regnum: return regnum2spr (163);
+    case sim_ppc_spr164_regnum: return regnum2spr (164);
+    case sim_ppc_spr165_regnum: return regnum2spr (165);
+    case sim_ppc_spr166_regnum: return regnum2spr (166);
+    case sim_ppc_spr167_regnum: return regnum2spr (167);
+    case sim_ppc_spr168_regnum: return regnum2spr (168);
+    case sim_ppc_spr169_regnum: return regnum2spr (169);
+    case sim_ppc_spr170_regnum: return regnum2spr (170);
+    case sim_ppc_spr171_regnum: return regnum2spr (171);
+    case sim_ppc_spr172_regnum: return regnum2spr (172);
+    case sim_ppc_spr173_regnum: return regnum2spr (173);
+    case sim_ppc_spr174_regnum: return regnum2spr (174);
+    case sim_ppc_spr175_regnum: return regnum2spr (175);
+    case sim_ppc_spr176_regnum: return regnum2spr (176);
+    case sim_ppc_spr177_regnum: return regnum2spr (177);
+    case sim_ppc_spr178_regnum: return regnum2spr (178);
+    case sim_ppc_spr179_regnum: return regnum2spr (179);
+    case sim_ppc_spr180_regnum: return regnum2spr (180);
+    case sim_ppc_spr181_regnum: return regnum2spr (181);
+    case sim_ppc_spr182_regnum: return regnum2spr (182);
+    case sim_ppc_spr183_regnum: return regnum2spr (183);
+    case sim_ppc_spr184_regnum: return regnum2spr (184);
+    case sim_ppc_spr185_regnum: return regnum2spr (185);
+    case sim_ppc_spr186_regnum: return regnum2spr (186);
+    case sim_ppc_spr187_regnum: return regnum2spr (187);
+    case sim_ppc_spr188_regnum: return regnum2spr (188);
+    case sim_ppc_spr189_regnum: return regnum2spr (189);
+    case sim_ppc_spr190_regnum: return regnum2spr (190);
+    case sim_ppc_spr191_regnum: return regnum2spr (191);
+    case sim_ppc_spr192_regnum: return regnum2spr (192);
+    case sim_ppc_spr193_regnum: return regnum2spr (193);
+    case sim_ppc_spr194_regnum: return regnum2spr (194);
+    case sim_ppc_spr195_regnum: return regnum2spr (195);
+    case sim_ppc_spr196_regnum: return regnum2spr (196);
+    case sim_ppc_spr197_regnum: return regnum2spr (197);
+    case sim_ppc_spr198_regnum: return regnum2spr (198);
+    case sim_ppc_spr199_regnum: return regnum2spr (199);
+    case sim_ppc_spr200_regnum: return regnum2spr (200);
+    case sim_ppc_spr201_regnum: return regnum2spr (201);
+    case sim_ppc_spr202_regnum: return regnum2spr (202);
+    case sim_ppc_spr203_regnum: return regnum2spr (203);
+    case sim_ppc_spr204_regnum: return regnum2spr (204);
+    case sim_ppc_spr205_regnum: return regnum2spr (205);
+    case sim_ppc_spr206_regnum: return regnum2spr (206);
+    case sim_ppc_spr207_regnum: return regnum2spr (207);
+    case sim_ppc_spr208_regnum: return regnum2spr (208);
+    case sim_ppc_spr209_regnum: return regnum2spr (209);
+    case sim_ppc_spr210_regnum: return regnum2spr (210);
+    case sim_ppc_spr211_regnum: return regnum2spr (211);
+    case sim_ppc_spr212_regnum: return regnum2spr (212);
+    case sim_ppc_spr213_regnum: return regnum2spr (213);
+    case sim_ppc_spr214_regnum: return regnum2spr (214);
+    case sim_ppc_spr215_regnum: return regnum2spr (215);
+    case sim_ppc_spr216_regnum: return regnum2spr (216);
+    case sim_ppc_spr217_regnum: return regnum2spr (217);
+    case sim_ppc_spr218_regnum: return regnum2spr (218);
+    case sim_ppc_spr219_regnum: return regnum2spr (219);
+    case sim_ppc_spr220_regnum: return regnum2spr (220);
+    case sim_ppc_spr221_regnum: return regnum2spr (221);
+    case sim_ppc_spr222_regnum: return regnum2spr (222);
+    case sim_ppc_spr223_regnum: return regnum2spr (223);
+    case sim_ppc_spr224_regnum: return regnum2spr (224);
+    case sim_ppc_spr225_regnum: return regnum2spr (225);
+    case sim_ppc_spr226_regnum: return regnum2spr (226);
+    case sim_ppc_spr227_regnum: return regnum2spr (227);
+    case sim_ppc_spr228_regnum: return regnum2spr (228);
+    case sim_ppc_spr229_regnum: return regnum2spr (229);
+    case sim_ppc_spr230_regnum: return regnum2spr (230);
+    case sim_ppc_spr231_regnum: return regnum2spr (231);
+    case sim_ppc_spr232_regnum: return regnum2spr (232);
+    case sim_ppc_spr233_regnum: return regnum2spr (233);
+    case sim_ppc_spr234_regnum: return regnum2spr (234);
+    case sim_ppc_spr235_regnum: return regnum2spr (235);
+    case sim_ppc_spr236_regnum: return regnum2spr (236);
+    case sim_ppc_spr237_regnum: return regnum2spr (237);
+    case sim_ppc_spr238_regnum: return regnum2spr (238);
+    case sim_ppc_spr239_regnum: return regnum2spr (239);
+    case sim_ppc_spr240_regnum: return regnum2spr (240);
+    case sim_ppc_spr241_regnum: return regnum2spr (241);
+    case sim_ppc_spr242_regnum: return regnum2spr (242);
+    case sim_ppc_spr243_regnum: return regnum2spr (243);
+    case sim_ppc_spr244_regnum: return regnum2spr (244);
+    case sim_ppc_spr245_regnum: return regnum2spr (245);
+    case sim_ppc_spr246_regnum: return regnum2spr (246);
+    case sim_ppc_spr247_regnum: return regnum2spr (247);
+    case sim_ppc_spr248_regnum: return regnum2spr (248);
+    case sim_ppc_spr249_regnum: return regnum2spr (249);
+    case sim_ppc_spr250_regnum: return regnum2spr (250);
+    case sim_ppc_spr251_regnum: return regnum2spr (251);
+    case sim_ppc_spr252_regnum: return regnum2spr (252);
+    case sim_ppc_spr253_regnum: return regnum2spr (253);
+    case sim_ppc_spr254_regnum: return regnum2spr (254);
+    case sim_ppc_spr255_regnum: return regnum2spr (255);
+    case sim_ppc_spr256_regnum: return regnum2spr (256);
+    case sim_ppc_spr257_regnum: return regnum2spr (257);
+    case sim_ppc_spr258_regnum: return regnum2spr (258);
+    case sim_ppc_spr259_regnum: return regnum2spr (259);
+    case sim_ppc_spr260_regnum: return regnum2spr (260);
+    case sim_ppc_spr261_regnum: return regnum2spr (261);
+    case sim_ppc_spr262_regnum: return regnum2spr (262);
+    case sim_ppc_spr263_regnum: return regnum2spr (263);
+    case sim_ppc_spr264_regnum: return regnum2spr (264);
+    case sim_ppc_spr265_regnum: return regnum2spr (265);
+    case sim_ppc_spr266_regnum: return regnum2spr (266);
+    case sim_ppc_spr267_regnum: return regnum2spr (267);
+    case sim_ppc_spr268_regnum: return regnum2spr (268);
+    case sim_ppc_spr269_regnum: return regnum2spr (269);
+    case sim_ppc_spr270_regnum: return regnum2spr (270);
+    case sim_ppc_spr271_regnum: return regnum2spr (271);
+    case sim_ppc_spr272_regnum: return regnum2spr (272);
+    case sim_ppc_spr273_regnum: return regnum2spr (273);
+    case sim_ppc_spr274_regnum: return regnum2spr (274);
+    case sim_ppc_spr275_regnum: return regnum2spr (275);
+    case sim_ppc_spr276_regnum: return regnum2spr (276);
+    case sim_ppc_spr277_regnum: return regnum2spr (277);
+    case sim_ppc_spr278_regnum: return regnum2spr (278);
+    case sim_ppc_spr279_regnum: return regnum2spr (279);
+    case sim_ppc_spr280_regnum: return regnum2spr (280);
+    case sim_ppc_spr281_regnum: return regnum2spr (281);
+    case sim_ppc_spr282_regnum: return regnum2spr (282);
+    case sim_ppc_spr283_regnum: return regnum2spr (283);
+    case sim_ppc_spr284_regnum: return regnum2spr (284);
+    case sim_ppc_spr285_regnum: return regnum2spr (285);
+    case sim_ppc_spr286_regnum: return regnum2spr (286);
+    case sim_ppc_spr287_regnum: return regnum2spr (287);
+    case sim_ppc_spr288_regnum: return regnum2spr (288);
+    case sim_ppc_spr289_regnum: return regnum2spr (289);
+    case sim_ppc_spr290_regnum: return regnum2spr (290);
+    case sim_ppc_spr291_regnum: return regnum2spr (291);
+    case sim_ppc_spr292_regnum: return regnum2spr (292);
+    case sim_ppc_spr293_regnum: return regnum2spr (293);
+    case sim_ppc_spr294_regnum: return regnum2spr (294);
+    case sim_ppc_spr295_regnum: return regnum2spr (295);
+    case sim_ppc_spr296_regnum: return regnum2spr (296);
+    case sim_ppc_spr297_regnum: return regnum2spr (297);
+    case sim_ppc_spr298_regnum: return regnum2spr (298);
+    case sim_ppc_spr299_regnum: return regnum2spr (299);
+    case sim_ppc_spr300_regnum: return regnum2spr (300);
+    case sim_ppc_spr301_regnum: return regnum2spr (301);
+    case sim_ppc_spr302_regnum: return regnum2spr (302);
+    case sim_ppc_spr303_regnum: return regnum2spr (303);
+    case sim_ppc_spr304_regnum: return regnum2spr (304);
+    case sim_ppc_spr305_regnum: return regnum2spr (305);
+    case sim_ppc_spr306_regnum: return regnum2spr (306);
+    case sim_ppc_spr307_regnum: return regnum2spr (307);
+    case sim_ppc_spr308_regnum: return regnum2spr (308);
+    case sim_ppc_spr309_regnum: return regnum2spr (309);
+    case sim_ppc_spr310_regnum: return regnum2spr (310);
+    case sim_ppc_spr311_regnum: return regnum2spr (311);
+    case sim_ppc_spr312_regnum: return regnum2spr (312);
+    case sim_ppc_spr313_regnum: return regnum2spr (313);
+    case sim_ppc_spr314_regnum: return regnum2spr (314);
+    case sim_ppc_spr315_regnum: return regnum2spr (315);
+    case sim_ppc_spr316_regnum: return regnum2spr (316);
+    case sim_ppc_spr317_regnum: return regnum2spr (317);
+    case sim_ppc_spr318_regnum: return regnum2spr (318);
+    case sim_ppc_spr319_regnum: return regnum2spr (319);
+    case sim_ppc_spr320_regnum: return regnum2spr (320);
+    case sim_ppc_spr321_regnum: return regnum2spr (321);
+    case sim_ppc_spr322_regnum: return regnum2spr (322);
+    case sim_ppc_spr323_regnum: return regnum2spr (323);
+    case sim_ppc_spr324_regnum: return regnum2spr (324);
+    case sim_ppc_spr325_regnum: return regnum2spr (325);
+    case sim_ppc_spr326_regnum: return regnum2spr (326);
+    case sim_ppc_spr327_regnum: return regnum2spr (327);
+    case sim_ppc_spr328_regnum: return regnum2spr (328);
+    case sim_ppc_spr329_regnum: return regnum2spr (329);
+    case sim_ppc_spr330_regnum: return regnum2spr (330);
+    case sim_ppc_spr331_regnum: return regnum2spr (331);
+    case sim_ppc_spr332_regnum: return regnum2spr (332);
+    case sim_ppc_spr333_regnum: return regnum2spr (333);
+    case sim_ppc_spr334_regnum: return regnum2spr (334);
+    case sim_ppc_spr335_regnum: return regnum2spr (335);
+    case sim_ppc_spr336_regnum: return regnum2spr (336);
+    case sim_ppc_spr337_regnum: return regnum2spr (337);
+    case sim_ppc_spr338_regnum: return regnum2spr (338);
+    case sim_ppc_spr339_regnum: return regnum2spr (339);
+    case sim_ppc_spr340_regnum: return regnum2spr (340);
+    case sim_ppc_spr341_regnum: return regnum2spr (341);
+    case sim_ppc_spr342_regnum: return regnum2spr (342);
+    case sim_ppc_spr343_regnum: return regnum2spr (343);
+    case sim_ppc_spr344_regnum: return regnum2spr (344);
+    case sim_ppc_spr345_regnum: return regnum2spr (345);
+    case sim_ppc_spr346_regnum: return regnum2spr (346);
+    case sim_ppc_spr347_regnum: return regnum2spr (347);
+    case sim_ppc_spr348_regnum: return regnum2spr (348);
+    case sim_ppc_spr349_regnum: return regnum2spr (349);
+    case sim_ppc_spr350_regnum: return regnum2spr (350);
+    case sim_ppc_spr351_regnum: return regnum2spr (351);
+    case sim_ppc_spr352_regnum: return regnum2spr (352);
+    case sim_ppc_spr353_regnum: return regnum2spr (353);
+    case sim_ppc_spr354_regnum: return regnum2spr (354);
+    case sim_ppc_spr355_regnum: return regnum2spr (355);
+    case sim_ppc_spr356_regnum: return regnum2spr (356);
+    case sim_ppc_spr357_regnum: return regnum2spr (357);
+    case sim_ppc_spr358_regnum: return regnum2spr (358);
+    case sim_ppc_spr359_regnum: return regnum2spr (359);
+    case sim_ppc_spr360_regnum: return regnum2spr (360);
+    case sim_ppc_spr361_regnum: return regnum2spr (361);
+    case sim_ppc_spr362_regnum: return regnum2spr (362);
+    case sim_ppc_spr363_regnum: return regnum2spr (363);
+    case sim_ppc_spr364_regnum: return regnum2spr (364);
+    case sim_ppc_spr365_regnum: return regnum2spr (365);
+    case sim_ppc_spr366_regnum: return regnum2spr (366);
+    case sim_ppc_spr367_regnum: return regnum2spr (367);
+    case sim_ppc_spr368_regnum: return regnum2spr (368);
+    case sim_ppc_spr369_regnum: return regnum2spr (369);
+    case sim_ppc_spr370_regnum: return regnum2spr (370);
+    case sim_ppc_spr371_regnum: return regnum2spr (371);
+    case sim_ppc_spr372_regnum: return regnum2spr (372);
+    case sim_ppc_spr373_regnum: return regnum2spr (373);
+    case sim_ppc_spr374_regnum: return regnum2spr (374);
+    case sim_ppc_spr375_regnum: return regnum2spr (375);
+    case sim_ppc_spr376_regnum: return regnum2spr (376);
+    case sim_ppc_spr377_regnum: return regnum2spr (377);
+    case sim_ppc_spr378_regnum: return regnum2spr (378);
+    case sim_ppc_spr379_regnum: return regnum2spr (379);
+    case sim_ppc_spr380_regnum: return regnum2spr (380);
+    case sim_ppc_spr381_regnum: return regnum2spr (381);
+    case sim_ppc_spr382_regnum: return regnum2spr (382);
+    case sim_ppc_spr383_regnum: return regnum2spr (383);
+    case sim_ppc_spr384_regnum: return regnum2spr (384);
+    case sim_ppc_spr385_regnum: return regnum2spr (385);
+    case sim_ppc_spr386_regnum: return regnum2spr (386);
+    case sim_ppc_spr387_regnum: return regnum2spr (387);
+    case sim_ppc_spr388_regnum: return regnum2spr (388);
+    case sim_ppc_spr389_regnum: return regnum2spr (389);
+    case sim_ppc_spr390_regnum: return regnum2spr (390);
+    case sim_ppc_spr391_regnum: return regnum2spr (391);
+    case sim_ppc_spr392_regnum: return regnum2spr (392);
+    case sim_ppc_spr393_regnum: return regnum2spr (393);
+    case sim_ppc_spr394_regnum: return regnum2spr (394);
+    case sim_ppc_spr395_regnum: return regnum2spr (395);
+    case sim_ppc_spr396_regnum: return regnum2spr (396);
+    case sim_ppc_spr397_regnum: return regnum2spr (397);
+    case sim_ppc_spr398_regnum: return regnum2spr (398);
+    case sim_ppc_spr399_regnum: return regnum2spr (399);
+    case sim_ppc_spr400_regnum: return regnum2spr (400);
+    case sim_ppc_spr401_regnum: return regnum2spr (401);
+    case sim_ppc_spr402_regnum: return regnum2spr (402);
+    case sim_ppc_spr403_regnum: return regnum2spr (403);
+    case sim_ppc_spr404_regnum: return regnum2spr (404);
+    case sim_ppc_spr405_regnum: return regnum2spr (405);
+    case sim_ppc_spr406_regnum: return regnum2spr (406);
+    case sim_ppc_spr407_regnum: return regnum2spr (407);
+    case sim_ppc_spr408_regnum: return regnum2spr (408);
+    case sim_ppc_spr409_regnum: return regnum2spr (409);
+    case sim_ppc_spr410_regnum: return regnum2spr (410);
+    case sim_ppc_spr411_regnum: return regnum2spr (411);
+    case sim_ppc_spr412_regnum: return regnum2spr (412);
+    case sim_ppc_spr413_regnum: return regnum2spr (413);
+    case sim_ppc_spr414_regnum: return regnum2spr (414);
+    case sim_ppc_spr415_regnum: return regnum2spr (415);
+    case sim_ppc_spr416_regnum: return regnum2spr (416);
+    case sim_ppc_spr417_regnum: return regnum2spr (417);
+    case sim_ppc_spr418_regnum: return regnum2spr (418);
+    case sim_ppc_spr419_regnum: return regnum2spr (419);
+    case sim_ppc_spr420_regnum: return regnum2spr (420);
+    case sim_ppc_spr421_regnum: return regnum2spr (421);
+    case sim_ppc_spr422_regnum: return regnum2spr (422);
+    case sim_ppc_spr423_regnum: return regnum2spr (423);
+    case sim_ppc_spr424_regnum: return regnum2spr (424);
+    case sim_ppc_spr425_regnum: return regnum2spr (425);
+    case sim_ppc_spr426_regnum: return regnum2spr (426);
+    case sim_ppc_spr427_regnum: return regnum2spr (427);
+    case sim_ppc_spr428_regnum: return regnum2spr (428);
+    case sim_ppc_spr429_regnum: return regnum2spr (429);
+    case sim_ppc_spr430_regnum: return regnum2spr (430);
+    case sim_ppc_spr431_regnum: return regnum2spr (431);
+    case sim_ppc_spr432_regnum: return regnum2spr (432);
+    case sim_ppc_spr433_regnum: return regnum2spr (433);
+    case sim_ppc_spr434_regnum: return regnum2spr (434);
+    case sim_ppc_spr435_regnum: return regnum2spr (435);
+    case sim_ppc_spr436_regnum: return regnum2spr (436);
+    case sim_ppc_spr437_regnum: return regnum2spr (437);
+    case sim_ppc_spr438_regnum: return regnum2spr (438);
+    case sim_ppc_spr439_regnum: return regnum2spr (439);
+    case sim_ppc_spr440_regnum: return regnum2spr (440);
+    case sim_ppc_spr441_regnum: return regnum2spr (441);
+    case sim_ppc_spr442_regnum: return regnum2spr (442);
+    case sim_ppc_spr443_regnum: return regnum2spr (443);
+    case sim_ppc_spr444_regnum: return regnum2spr (444);
+    case sim_ppc_spr445_regnum: return regnum2spr (445);
+    case sim_ppc_spr446_regnum: return regnum2spr (446);
+    case sim_ppc_spr447_regnum: return regnum2spr (447);
+    case sim_ppc_spr448_regnum: return regnum2spr (448);
+    case sim_ppc_spr449_regnum: return regnum2spr (449);
+    case sim_ppc_spr450_regnum: return regnum2spr (450);
+    case sim_ppc_spr451_regnum: return regnum2spr (451);
+    case sim_ppc_spr452_regnum: return regnum2spr (452);
+    case sim_ppc_spr453_regnum: return regnum2spr (453);
+    case sim_ppc_spr454_regnum: return regnum2spr (454);
+    case sim_ppc_spr455_regnum: return regnum2spr (455);
+    case sim_ppc_spr456_regnum: return regnum2spr (456);
+    case sim_ppc_spr457_regnum: return regnum2spr (457);
+    case sim_ppc_spr458_regnum: return regnum2spr (458);
+    case sim_ppc_spr459_regnum: return regnum2spr (459);
+    case sim_ppc_spr460_regnum: return regnum2spr (460);
+    case sim_ppc_spr461_regnum: return regnum2spr (461);
+    case sim_ppc_spr462_regnum: return regnum2spr (462);
+    case sim_ppc_spr463_regnum: return regnum2spr (463);
+    case sim_ppc_spr464_regnum: return regnum2spr (464);
+    case sim_ppc_spr465_regnum: return regnum2spr (465);
+    case sim_ppc_spr466_regnum: return regnum2spr (466);
+    case sim_ppc_spr467_regnum: return regnum2spr (467);
+    case sim_ppc_spr468_regnum: return regnum2spr (468);
+    case sim_ppc_spr469_regnum: return regnum2spr (469);
+    case sim_ppc_spr470_regnum: return regnum2spr (470);
+    case sim_ppc_spr471_regnum: return regnum2spr (471);
+    case sim_ppc_spr472_regnum: return regnum2spr (472);
+    case sim_ppc_spr473_regnum: return regnum2spr (473);
+    case sim_ppc_spr474_regnum: return regnum2spr (474);
+    case sim_ppc_spr475_regnum: return regnum2spr (475);
+    case sim_ppc_spr476_regnum: return regnum2spr (476);
+    case sim_ppc_spr477_regnum: return regnum2spr (477);
+    case sim_ppc_spr478_regnum: return regnum2spr (478);
+    case sim_ppc_spr479_regnum: return regnum2spr (479);
+    case sim_ppc_spr480_regnum: return regnum2spr (480);
+    case sim_ppc_spr481_regnum: return regnum2spr (481);
+    case sim_ppc_spr482_regnum: return regnum2spr (482);
+    case sim_ppc_spr483_regnum: return regnum2spr (483);
+    case sim_ppc_spr484_regnum: return regnum2spr (484);
+    case sim_ppc_spr485_regnum: return regnum2spr (485);
+    case sim_ppc_spr486_regnum: return regnum2spr (486);
+    case sim_ppc_spr487_regnum: return regnum2spr (487);
+    case sim_ppc_spr488_regnum: return regnum2spr (488);
+    case sim_ppc_spr489_regnum: return regnum2spr (489);
+    case sim_ppc_spr490_regnum: return regnum2spr (490);
+    case sim_ppc_spr491_regnum: return regnum2spr (491);
+    case sim_ppc_spr492_regnum: return regnum2spr (492);
+    case sim_ppc_spr493_regnum: return regnum2spr (493);
+    case sim_ppc_spr494_regnum: return regnum2spr (494);
+    case sim_ppc_spr495_regnum: return regnum2spr (495);
+    case sim_ppc_spr496_regnum: return regnum2spr (496);
+    case sim_ppc_spr497_regnum: return regnum2spr (497);
+    case sim_ppc_spr498_regnum: return regnum2spr (498);
+    case sim_ppc_spr499_regnum: return regnum2spr (499);
+    case sim_ppc_spr500_regnum: return regnum2spr (500);
+    case sim_ppc_spr501_regnum: return regnum2spr (501);
+    case sim_ppc_spr502_regnum: return regnum2spr (502);
+    case sim_ppc_spr503_regnum: return regnum2spr (503);
+    case sim_ppc_spr504_regnum: return regnum2spr (504);
+    case sim_ppc_spr505_regnum: return regnum2spr (505);
+    case sim_ppc_spr506_regnum: return regnum2spr (506);
+    case sim_ppc_spr507_regnum: return regnum2spr (507);
+    case sim_ppc_spr508_regnum: return regnum2spr (508);
+    case sim_ppc_spr509_regnum: return regnum2spr (509);
+    case sim_ppc_spr510_regnum: return regnum2spr (510);
+    case sim_ppc_spr511_regnum: return regnum2spr (511);
+    case sim_ppc_spr512_regnum: return regnum2spr (512);
+    case sim_ppc_spr513_regnum: return regnum2spr (513);
+    case sim_ppc_spr514_regnum: return regnum2spr (514);
+    case sim_ppc_spr515_regnum: return regnum2spr (515);
+    case sim_ppc_spr516_regnum: return regnum2spr (516);
+    case sim_ppc_spr517_regnum: return regnum2spr (517);
+    case sim_ppc_spr518_regnum: return regnum2spr (518);
+    case sim_ppc_spr519_regnum: return regnum2spr (519);
+    case sim_ppc_spr520_regnum: return regnum2spr (520);
+    case sim_ppc_spr521_regnum: return regnum2spr (521);
+    case sim_ppc_spr522_regnum: return regnum2spr (522);
+    case sim_ppc_spr523_regnum: return regnum2spr (523);
+    case sim_ppc_spr524_regnum: return regnum2spr (524);
+    case sim_ppc_spr525_regnum: return regnum2spr (525);
+    case sim_ppc_spr526_regnum: return regnum2spr (526);
+    case sim_ppc_spr527_regnum: return regnum2spr (527);
+    case sim_ppc_spr528_regnum: return regnum2spr (528);
+    case sim_ppc_spr529_regnum: return regnum2spr (529);
+    case sim_ppc_spr530_regnum: return regnum2spr (530);
+    case sim_ppc_spr531_regnum: return regnum2spr (531);
+    case sim_ppc_spr532_regnum: return regnum2spr (532);
+    case sim_ppc_spr533_regnum: return regnum2spr (533);
+    case sim_ppc_spr534_regnum: return regnum2spr (534);
+    case sim_ppc_spr535_regnum: return regnum2spr (535);
+    case sim_ppc_spr536_regnum: return regnum2spr (536);
+    case sim_ppc_spr537_regnum: return regnum2spr (537);
+    case sim_ppc_spr538_regnum: return regnum2spr (538);
+    case sim_ppc_spr539_regnum: return regnum2spr (539);
+    case sim_ppc_spr540_regnum: return regnum2spr (540);
+    case sim_ppc_spr541_regnum: return regnum2spr (541);
+    case sim_ppc_spr542_regnum: return regnum2spr (542);
+    case sim_ppc_spr543_regnum: return regnum2spr (543);
+    case sim_ppc_spr544_regnum: return regnum2spr (544);
+    case sim_ppc_spr545_regnum: return regnum2spr (545);
+    case sim_ppc_spr546_regnum: return regnum2spr (546);
+    case sim_ppc_spr547_regnum: return regnum2spr (547);
+    case sim_ppc_spr548_regnum: return regnum2spr (548);
+    case sim_ppc_spr549_regnum: return regnum2spr (549);
+    case sim_ppc_spr550_regnum: return regnum2spr (550);
+    case sim_ppc_spr551_regnum: return regnum2spr (551);
+    case sim_ppc_spr552_regnum: return regnum2spr (552);
+    case sim_ppc_spr553_regnum: return regnum2spr (553);
+    case sim_ppc_spr554_regnum: return regnum2spr (554);
+    case sim_ppc_spr555_regnum: return regnum2spr (555);
+    case sim_ppc_spr556_regnum: return regnum2spr (556);
+    case sim_ppc_spr557_regnum: return regnum2spr (557);
+    case sim_ppc_spr558_regnum: return regnum2spr (558);
+    case sim_ppc_spr559_regnum: return regnum2spr (559);
+    case sim_ppc_spr560_regnum: return regnum2spr (560);
+    case sim_ppc_spr561_regnum: return regnum2spr (561);
+    case sim_ppc_spr562_regnum: return regnum2spr (562);
+    case sim_ppc_spr563_regnum: return regnum2spr (563);
+    case sim_ppc_spr564_regnum: return regnum2spr (564);
+    case sim_ppc_spr565_regnum: return regnum2spr (565);
+    case sim_ppc_spr566_regnum: return regnum2spr (566);
+    case sim_ppc_spr567_regnum: return regnum2spr (567);
+    case sim_ppc_spr568_regnum: return regnum2spr (568);
+    case sim_ppc_spr569_regnum: return regnum2spr (569);
+    case sim_ppc_spr570_regnum: return regnum2spr (570);
+    case sim_ppc_spr571_regnum: return regnum2spr (571);
+    case sim_ppc_spr572_regnum: return regnum2spr (572);
+    case sim_ppc_spr573_regnum: return regnum2spr (573);
+    case sim_ppc_spr574_regnum: return regnum2spr (574);
+    case sim_ppc_spr575_regnum: return regnum2spr (575);
+    case sim_ppc_spr576_regnum: return regnum2spr (576);
+    case sim_ppc_spr577_regnum: return regnum2spr (577);
+    case sim_ppc_spr578_regnum: return regnum2spr (578);
+    case sim_ppc_spr579_regnum: return regnum2spr (579);
+    case sim_ppc_spr580_regnum: return regnum2spr (580);
+    case sim_ppc_spr581_regnum: return regnum2spr (581);
+    case sim_ppc_spr582_regnum: return regnum2spr (582);
+    case sim_ppc_spr583_regnum: return regnum2spr (583);
+    case sim_ppc_spr584_regnum: return regnum2spr (584);
+    case sim_ppc_spr585_regnum: return regnum2spr (585);
+    case sim_ppc_spr586_regnum: return regnum2spr (586);
+    case sim_ppc_spr587_regnum: return regnum2spr (587);
+    case sim_ppc_spr588_regnum: return regnum2spr (588);
+    case sim_ppc_spr589_regnum: return regnum2spr (589);
+    case sim_ppc_spr590_regnum: return regnum2spr (590);
+    case sim_ppc_spr591_regnum: return regnum2spr (591);
+    case sim_ppc_spr592_regnum: return regnum2spr (592);
+    case sim_ppc_spr593_regnum: return regnum2spr (593);
+    case sim_ppc_spr594_regnum: return regnum2spr (594);
+    case sim_ppc_spr595_regnum: return regnum2spr (595);
+    case sim_ppc_spr596_regnum: return regnum2spr (596);
+    case sim_ppc_spr597_regnum: return regnum2spr (597);
+    case sim_ppc_spr598_regnum: return regnum2spr (598);
+    case sim_ppc_spr599_regnum: return regnum2spr (599);
+    case sim_ppc_spr600_regnum: return regnum2spr (600);
+    case sim_ppc_spr601_regnum: return regnum2spr (601);
+    case sim_ppc_spr602_regnum: return regnum2spr (602);
+    case sim_ppc_spr603_regnum: return regnum2spr (603);
+    case sim_ppc_spr604_regnum: return regnum2spr (604);
+    case sim_ppc_spr605_regnum: return regnum2spr (605);
+    case sim_ppc_spr606_regnum: return regnum2spr (606);
+    case sim_ppc_spr607_regnum: return regnum2spr (607);
+    case sim_ppc_spr608_regnum: return regnum2spr (608);
+    case sim_ppc_spr609_regnum: return regnum2spr (609);
+    case sim_ppc_spr610_regnum: return regnum2spr (610);
+    case sim_ppc_spr611_regnum: return regnum2spr (611);
+    case sim_ppc_spr612_regnum: return regnum2spr (612);
+    case sim_ppc_spr613_regnum: return regnum2spr (613);
+    case sim_ppc_spr614_regnum: return regnum2spr (614);
+    case sim_ppc_spr615_regnum: return regnum2spr (615);
+    case sim_ppc_spr616_regnum: return regnum2spr (616);
+    case sim_ppc_spr617_regnum: return regnum2spr (617);
+    case sim_ppc_spr618_regnum: return regnum2spr (618);
+    case sim_ppc_spr619_regnum: return regnum2spr (619);
+    case sim_ppc_spr620_regnum: return regnum2spr (620);
+    case sim_ppc_spr621_regnum: return regnum2spr (621);
+    case sim_ppc_spr622_regnum: return regnum2spr (622);
+    case sim_ppc_spr623_regnum: return regnum2spr (623);
+    case sim_ppc_spr624_regnum: return regnum2spr (624);
+    case sim_ppc_spr625_regnum: return regnum2spr (625);
+    case sim_ppc_spr626_regnum: return regnum2spr (626);
+    case sim_ppc_spr627_regnum: return regnum2spr (627);
+    case sim_ppc_spr628_regnum: return regnum2spr (628);
+    case sim_ppc_spr629_regnum: return regnum2spr (629);
+    case sim_ppc_spr630_regnum: return regnum2spr (630);
+    case sim_ppc_spr631_regnum: return regnum2spr (631);
+    case sim_ppc_spr632_regnum: return regnum2spr (632);
+    case sim_ppc_spr633_regnum: return regnum2spr (633);
+    case sim_ppc_spr634_regnum: return regnum2spr (634);
+    case sim_ppc_spr635_regnum: return regnum2spr (635);
+    case sim_ppc_spr636_regnum: return regnum2spr (636);
+    case sim_ppc_spr637_regnum: return regnum2spr (637);
+    case sim_ppc_spr638_regnum: return regnum2spr (638);
+    case sim_ppc_spr639_regnum: return regnum2spr (639);
+    case sim_ppc_spr640_regnum: return regnum2spr (640);
+    case sim_ppc_spr641_regnum: return regnum2spr (641);
+    case sim_ppc_spr642_regnum: return regnum2spr (642);
+    case sim_ppc_spr643_regnum: return regnum2spr (643);
+    case sim_ppc_spr644_regnum: return regnum2spr (644);
+    case sim_ppc_spr645_regnum: return regnum2spr (645);
+    case sim_ppc_spr646_regnum: return regnum2spr (646);
+    case sim_ppc_spr647_regnum: return regnum2spr (647);
+    case sim_ppc_spr648_regnum: return regnum2spr (648);
+    case sim_ppc_spr649_regnum: return regnum2spr (649);
+    case sim_ppc_spr650_regnum: return regnum2spr (650);
+    case sim_ppc_spr651_regnum: return regnum2spr (651);
+    case sim_ppc_spr652_regnum: return regnum2spr (652);
+    case sim_ppc_spr653_regnum: return regnum2spr (653);
+    case sim_ppc_spr654_regnum: return regnum2spr (654);
+    case sim_ppc_spr655_regnum: return regnum2spr (655);
+    case sim_ppc_spr656_regnum: return regnum2spr (656);
+    case sim_ppc_spr657_regnum: return regnum2spr (657);
+    case sim_ppc_spr658_regnum: return regnum2spr (658);
+    case sim_ppc_spr659_regnum: return regnum2spr (659);
+    case sim_ppc_spr660_regnum: return regnum2spr (660);
+    case sim_ppc_spr661_regnum: return regnum2spr (661);
+    case sim_ppc_spr662_regnum: return regnum2spr (662);
+    case sim_ppc_spr663_regnum: return regnum2spr (663);
+    case sim_ppc_spr664_regnum: return regnum2spr (664);
+    case sim_ppc_spr665_regnum: return regnum2spr (665);
+    case sim_ppc_spr666_regnum: return regnum2spr (666);
+    case sim_ppc_spr667_regnum: return regnum2spr (667);
+    case sim_ppc_spr668_regnum: return regnum2spr (668);
+    case sim_ppc_spr669_regnum: return regnum2spr (669);
+    case sim_ppc_spr670_regnum: return regnum2spr (670);
+    case sim_ppc_spr671_regnum: return regnum2spr (671);
+    case sim_ppc_spr672_regnum: return regnum2spr (672);
+    case sim_ppc_spr673_regnum: return regnum2spr (673);
+    case sim_ppc_spr674_regnum: return regnum2spr (674);
+    case sim_ppc_spr675_regnum: return regnum2spr (675);
+    case sim_ppc_spr676_regnum: return regnum2spr (676);
+    case sim_ppc_spr677_regnum: return regnum2spr (677);
+    case sim_ppc_spr678_regnum: return regnum2spr (678);
+    case sim_ppc_spr679_regnum: return regnum2spr (679);
+    case sim_ppc_spr680_regnum: return regnum2spr (680);
+    case sim_ppc_spr681_regnum: return regnum2spr (681);
+    case sim_ppc_spr682_regnum: return regnum2spr (682);
+    case sim_ppc_spr683_regnum: return regnum2spr (683);
+    case sim_ppc_spr684_regnum: return regnum2spr (684);
+    case sim_ppc_spr685_regnum: return regnum2spr (685);
+    case sim_ppc_spr686_regnum: return regnum2spr (686);
+    case sim_ppc_spr687_regnum: return regnum2spr (687);
+    case sim_ppc_spr688_regnum: return regnum2spr (688);
+    case sim_ppc_spr689_regnum: return regnum2spr (689);
+    case sim_ppc_spr690_regnum: return regnum2spr (690);
+    case sim_ppc_spr691_regnum: return regnum2spr (691);
+    case sim_ppc_spr692_regnum: return regnum2spr (692);
+    case sim_ppc_spr693_regnum: return regnum2spr (693);
+    case sim_ppc_spr694_regnum: return regnum2spr (694);
+    case sim_ppc_spr695_regnum: return regnum2spr (695);
+    case sim_ppc_spr696_regnum: return regnum2spr (696);
+    case sim_ppc_spr697_regnum: return regnum2spr (697);
+    case sim_ppc_spr698_regnum: return regnum2spr (698);
+    case sim_ppc_spr699_regnum: return regnum2spr (699);
+    case sim_ppc_spr700_regnum: return regnum2spr (700);
+    case sim_ppc_spr701_regnum: return regnum2spr (701);
+    case sim_ppc_spr702_regnum: return regnum2spr (702);
+    case sim_ppc_spr703_regnum: return regnum2spr (703);
+    case sim_ppc_spr704_regnum: return regnum2spr (704);
+    case sim_ppc_spr705_regnum: return regnum2spr (705);
+    case sim_ppc_spr706_regnum: return regnum2spr (706);
+    case sim_ppc_spr707_regnum: return regnum2spr (707);
+    case sim_ppc_spr708_regnum: return regnum2spr (708);
+    case sim_ppc_spr709_regnum: return regnum2spr (709);
+    case sim_ppc_spr710_regnum: return regnum2spr (710);
+    case sim_ppc_spr711_regnum: return regnum2spr (711);
+    case sim_ppc_spr712_regnum: return regnum2spr (712);
+    case sim_ppc_spr713_regnum: return regnum2spr (713);
+    case sim_ppc_spr714_regnum: return regnum2spr (714);
+    case sim_ppc_spr715_regnum: return regnum2spr (715);
+    case sim_ppc_spr716_regnum: return regnum2spr (716);
+    case sim_ppc_spr717_regnum: return regnum2spr (717);
+    case sim_ppc_spr718_regnum: return regnum2spr (718);
+    case sim_ppc_spr719_regnum: return regnum2spr (719);
+    case sim_ppc_spr720_regnum: return regnum2spr (720);
+    case sim_ppc_spr721_regnum: return regnum2spr (721);
+    case sim_ppc_spr722_regnum: return regnum2spr (722);
+    case sim_ppc_spr723_regnum: return regnum2spr (723);
+    case sim_ppc_spr724_regnum: return regnum2spr (724);
+    case sim_ppc_spr725_regnum: return regnum2spr (725);
+    case sim_ppc_spr726_regnum: return regnum2spr (726);
+    case sim_ppc_spr727_regnum: return regnum2spr (727);
+    case sim_ppc_spr728_regnum: return regnum2spr (728);
+    case sim_ppc_spr729_regnum: return regnum2spr (729);
+    case sim_ppc_spr730_regnum: return regnum2spr (730);
+    case sim_ppc_spr731_regnum: return regnum2spr (731);
+    case sim_ppc_spr732_regnum: return regnum2spr (732);
+    case sim_ppc_spr733_regnum: return regnum2spr (733);
+    case sim_ppc_spr734_regnum: return regnum2spr (734);
+    case sim_ppc_spr735_regnum: return regnum2spr (735);
+    case sim_ppc_spr736_regnum: return regnum2spr (736);
+    case sim_ppc_spr737_regnum: return regnum2spr (737);
+    case sim_ppc_spr738_regnum: return regnum2spr (738);
+    case sim_ppc_spr739_regnum: return regnum2spr (739);
+    case sim_ppc_spr740_regnum: return regnum2spr (740);
+    case sim_ppc_spr741_regnum: return regnum2spr (741);
+    case sim_ppc_spr742_regnum: return regnum2spr (742);
+    case sim_ppc_spr743_regnum: return regnum2spr (743);
+    case sim_ppc_spr744_regnum: return regnum2spr (744);
+    case sim_ppc_spr745_regnum: return regnum2spr (745);
+    case sim_ppc_spr746_regnum: return regnum2spr (746);
+    case sim_ppc_spr747_regnum: return regnum2spr (747);
+    case sim_ppc_spr748_regnum: return regnum2spr (748);
+    case sim_ppc_spr749_regnum: return regnum2spr (749);
+    case sim_ppc_spr750_regnum: return regnum2spr (750);
+    case sim_ppc_spr751_regnum: return regnum2spr (751);
+    case sim_ppc_spr752_regnum: return regnum2spr (752);
+    case sim_ppc_spr753_regnum: return regnum2spr (753);
+    case sim_ppc_spr754_regnum: return regnum2spr (754);
+    case sim_ppc_spr755_regnum: return regnum2spr (755);
+    case sim_ppc_spr756_regnum: return regnum2spr (756);
+    case sim_ppc_spr757_regnum: return regnum2spr (757);
+    case sim_ppc_spr758_regnum: return regnum2spr (758);
+    case sim_ppc_spr759_regnum: return regnum2spr (759);
+    case sim_ppc_spr760_regnum: return regnum2spr (760);
+    case sim_ppc_spr761_regnum: return regnum2spr (761);
+    case sim_ppc_spr762_regnum: return regnum2spr (762);
+    case sim_ppc_spr763_regnum: return regnum2spr (763);
+    case sim_ppc_spr764_regnum: return regnum2spr (764);
+    case sim_ppc_spr765_regnum: return regnum2spr (765);
+    case sim_ppc_spr766_regnum: return regnum2spr (766);
+    case sim_ppc_spr767_regnum: return regnum2spr (767);
+    case sim_ppc_spr768_regnum: return regnum2spr (768);
+    case sim_ppc_spr769_regnum: return regnum2spr (769);
+    case sim_ppc_spr770_regnum: return regnum2spr (770);
+    case sim_ppc_spr771_regnum: return regnum2spr (771);
+    case sim_ppc_spr772_regnum: return regnum2spr (772);
+    case sim_ppc_spr773_regnum: return regnum2spr (773);
+    case sim_ppc_spr774_regnum: return regnum2spr (774);
+    case sim_ppc_spr775_regnum: return regnum2spr (775);
+    case sim_ppc_spr776_regnum: return regnum2spr (776);
+    case sim_ppc_spr777_regnum: return regnum2spr (777);
+    case sim_ppc_spr778_regnum: return regnum2spr (778);
+    case sim_ppc_spr779_regnum: return regnum2spr (779);
+    case sim_ppc_spr780_regnum: return regnum2spr (780);
+    case sim_ppc_spr781_regnum: return regnum2spr (781);
+    case sim_ppc_spr782_regnum: return regnum2spr (782);
+    case sim_ppc_spr783_regnum: return regnum2spr (783);
+    case sim_ppc_spr784_regnum: return regnum2spr (784);
+    case sim_ppc_spr785_regnum: return regnum2spr (785);
+    case sim_ppc_spr786_regnum: return regnum2spr (786);
+    case sim_ppc_spr787_regnum: return regnum2spr (787);
+    case sim_ppc_spr788_regnum: return regnum2spr (788);
+    case sim_ppc_spr789_regnum: return regnum2spr (789);
+    case sim_ppc_spr790_regnum: return regnum2spr (790);
+    case sim_ppc_spr791_regnum: return regnum2spr (791);
+    case sim_ppc_spr792_regnum: return regnum2spr (792);
+    case sim_ppc_spr793_regnum: return regnum2spr (793);
+    case sim_ppc_spr794_regnum: return regnum2spr (794);
+    case sim_ppc_spr795_regnum: return regnum2spr (795);
+    case sim_ppc_spr796_regnum: return regnum2spr (796);
+    case sim_ppc_spr797_regnum: return regnum2spr (797);
+    case sim_ppc_spr798_regnum: return regnum2spr (798);
+    case sim_ppc_spr799_regnum: return regnum2spr (799);
+    case sim_ppc_spr800_regnum: return regnum2spr (800);
+    case sim_ppc_spr801_regnum: return regnum2spr (801);
+    case sim_ppc_spr802_regnum: return regnum2spr (802);
+    case sim_ppc_spr803_regnum: return regnum2spr (803);
+    case sim_ppc_spr804_regnum: return regnum2spr (804);
+    case sim_ppc_spr805_regnum: return regnum2spr (805);
+    case sim_ppc_spr806_regnum: return regnum2spr (806);
+    case sim_ppc_spr807_regnum: return regnum2spr (807);
+    case sim_ppc_spr808_regnum: return regnum2spr (808);
+    case sim_ppc_spr809_regnum: return regnum2spr (809);
+    case sim_ppc_spr810_regnum: return regnum2spr (810);
+    case sim_ppc_spr811_regnum: return regnum2spr (811);
+    case sim_ppc_spr812_regnum: return regnum2spr (812);
+    case sim_ppc_spr813_regnum: return regnum2spr (813);
+    case sim_ppc_spr814_regnum: return regnum2spr (814);
+    case sim_ppc_spr815_regnum: return regnum2spr (815);
+    case sim_ppc_spr816_regnum: return regnum2spr (816);
+    case sim_ppc_spr817_regnum: return regnum2spr (817);
+    case sim_ppc_spr818_regnum: return regnum2spr (818);
+    case sim_ppc_spr819_regnum: return regnum2spr (819);
+    case sim_ppc_spr820_regnum: return regnum2spr (820);
+    case sim_ppc_spr821_regnum: return regnum2spr (821);
+    case sim_ppc_spr822_regnum: return regnum2spr (822);
+    case sim_ppc_spr823_regnum: return regnum2spr (823);
+    case sim_ppc_spr824_regnum: return regnum2spr (824);
+    case sim_ppc_spr825_regnum: return regnum2spr (825);
+    case sim_ppc_spr826_regnum: return regnum2spr (826);
+    case sim_ppc_spr827_regnum: return regnum2spr (827);
+    case sim_ppc_spr828_regnum: return regnum2spr (828);
+    case sim_ppc_spr829_regnum: return regnum2spr (829);
+    case sim_ppc_spr830_regnum: return regnum2spr (830);
+    case sim_ppc_spr831_regnum: return regnum2spr (831);
+    case sim_ppc_spr832_regnum: return regnum2spr (832);
+    case sim_ppc_spr833_regnum: return regnum2spr (833);
+    case sim_ppc_spr834_regnum: return regnum2spr (834);
+    case sim_ppc_spr835_regnum: return regnum2spr (835);
+    case sim_ppc_spr836_regnum: return regnum2spr (836);
+    case sim_ppc_spr837_regnum: return regnum2spr (837);
+    case sim_ppc_spr838_regnum: return regnum2spr (838);
+    case sim_ppc_spr839_regnum: return regnum2spr (839);
+    case sim_ppc_spr840_regnum: return regnum2spr (840);
+    case sim_ppc_spr841_regnum: return regnum2spr (841);
+    case sim_ppc_spr842_regnum: return regnum2spr (842);
+    case sim_ppc_spr843_regnum: return regnum2spr (843);
+    case sim_ppc_spr844_regnum: return regnum2spr (844);
+    case sim_ppc_spr845_regnum: return regnum2spr (845);
+    case sim_ppc_spr846_regnum: return regnum2spr (846);
+    case sim_ppc_spr847_regnum: return regnum2spr (847);
+    case sim_ppc_spr848_regnum: return regnum2spr (848);
+    case sim_ppc_spr849_regnum: return regnum2spr (849);
+    case sim_ppc_spr850_regnum: return regnum2spr (850);
+    case sim_ppc_spr851_regnum: return regnum2spr (851);
+    case sim_ppc_spr852_regnum: return regnum2spr (852);
+    case sim_ppc_spr853_regnum: return regnum2spr (853);
+    case sim_ppc_spr854_regnum: return regnum2spr (854);
+    case sim_ppc_spr855_regnum: return regnum2spr (855);
+    case sim_ppc_spr856_regnum: return regnum2spr (856);
+    case sim_ppc_spr857_regnum: return regnum2spr (857);
+    case sim_ppc_spr858_regnum: return regnum2spr (858);
+    case sim_ppc_spr859_regnum: return regnum2spr (859);
+    case sim_ppc_spr860_regnum: return regnum2spr (860);
+    case sim_ppc_spr861_regnum: return regnum2spr (861);
+    case sim_ppc_spr862_regnum: return regnum2spr (862);
+    case sim_ppc_spr863_regnum: return regnum2spr (863);
+    case sim_ppc_spr864_regnum: return regnum2spr (864);
+    case sim_ppc_spr865_regnum: return regnum2spr (865);
+    case sim_ppc_spr866_regnum: return regnum2spr (866);
+    case sim_ppc_spr867_regnum: return regnum2spr (867);
+    case sim_ppc_spr868_regnum: return regnum2spr (868);
+    case sim_ppc_spr869_regnum: return regnum2spr (869);
+    case sim_ppc_spr870_regnum: return regnum2spr (870);
+    case sim_ppc_spr871_regnum: return regnum2spr (871);
+    case sim_ppc_spr872_regnum: return regnum2spr (872);
+    case sim_ppc_spr873_regnum: return regnum2spr (873);
+    case sim_ppc_spr874_regnum: return regnum2spr (874);
+    case sim_ppc_spr875_regnum: return regnum2spr (875);
+    case sim_ppc_spr876_regnum: return regnum2spr (876);
+    case sim_ppc_spr877_regnum: return regnum2spr (877);
+    case sim_ppc_spr878_regnum: return regnum2spr (878);
+    case sim_ppc_spr879_regnum: return regnum2spr (879);
+    case sim_ppc_spr880_regnum: return regnum2spr (880);
+    case sim_ppc_spr881_regnum: return regnum2spr (881);
+    case sim_ppc_spr882_regnum: return regnum2spr (882);
+    case sim_ppc_spr883_regnum: return regnum2spr (883);
+    case sim_ppc_spr884_regnum: return regnum2spr (884);
+    case sim_ppc_spr885_regnum: return regnum2spr (885);
+    case sim_ppc_spr886_regnum: return regnum2spr (886);
+    case sim_ppc_spr887_regnum: return regnum2spr (887);
+    case sim_ppc_spr888_regnum: return regnum2spr (888);
+    case sim_ppc_spr889_regnum: return regnum2spr (889);
+    case sim_ppc_spr890_regnum: return regnum2spr (890);
+    case sim_ppc_spr891_regnum: return regnum2spr (891);
+    case sim_ppc_spr892_regnum: return regnum2spr (892);
+    case sim_ppc_spr893_regnum: return regnum2spr (893);
+    case sim_ppc_spr894_regnum: return regnum2spr (894);
+    case sim_ppc_spr895_regnum: return regnum2spr (895);
+    case sim_ppc_spr896_regnum: return regnum2spr (896);
+    case sim_ppc_spr897_regnum: return regnum2spr (897);
+    case sim_ppc_spr898_regnum: return regnum2spr (898);
+    case sim_ppc_spr899_regnum: return regnum2spr (899);
+    case sim_ppc_spr900_regnum: return regnum2spr (900);
+    case sim_ppc_spr901_regnum: return regnum2spr (901);
+    case sim_ppc_spr902_regnum: return regnum2spr (902);
+    case sim_ppc_spr903_regnum: return regnum2spr (903);
+    case sim_ppc_spr904_regnum: return regnum2spr (904);
+    case sim_ppc_spr905_regnum: return regnum2spr (905);
+    case sim_ppc_spr906_regnum: return regnum2spr (906);
+    case sim_ppc_spr907_regnum: return regnum2spr (907);
+    case sim_ppc_spr908_regnum: return regnum2spr (908);
+    case sim_ppc_spr909_regnum: return regnum2spr (909);
+    case sim_ppc_spr910_regnum: return regnum2spr (910);
+    case sim_ppc_spr911_regnum: return regnum2spr (911);
+    case sim_ppc_spr912_regnum: return regnum2spr (912);
+    case sim_ppc_spr913_regnum: return regnum2spr (913);
+    case sim_ppc_spr914_regnum: return regnum2spr (914);
+    case sim_ppc_spr915_regnum: return regnum2spr (915);
+    case sim_ppc_spr916_regnum: return regnum2spr (916);
+    case sim_ppc_spr917_regnum: return regnum2spr (917);
+    case sim_ppc_spr918_regnum: return regnum2spr (918);
+    case sim_ppc_spr919_regnum: return regnum2spr (919);
+    case sim_ppc_spr920_regnum: return regnum2spr (920);
+    case sim_ppc_spr921_regnum: return regnum2spr (921);
+    case sim_ppc_spr922_regnum: return regnum2spr (922);
+    case sim_ppc_spr923_regnum: return regnum2spr (923);
+    case sim_ppc_spr924_regnum: return regnum2spr (924);
+    case sim_ppc_spr925_regnum: return regnum2spr (925);
+    case sim_ppc_spr926_regnum: return regnum2spr (926);
+    case sim_ppc_spr927_regnum: return regnum2spr (927);
+    case sim_ppc_spr928_regnum: return regnum2spr (928);
+    case sim_ppc_spr929_regnum: return regnum2spr (929);
+    case sim_ppc_spr930_regnum: return regnum2spr (930);
+    case sim_ppc_spr931_regnum: return regnum2spr (931);
+    case sim_ppc_spr932_regnum: return regnum2spr (932);
+    case sim_ppc_spr933_regnum: return regnum2spr (933);
+    case sim_ppc_spr934_regnum: return regnum2spr (934);
+    case sim_ppc_spr935_regnum: return regnum2spr (935);
+    case sim_ppc_spr936_regnum: return regnum2spr (936);
+    case sim_ppc_spr937_regnum: return regnum2spr (937);
+    case sim_ppc_spr938_regnum: return regnum2spr (938);
+    case sim_ppc_spr939_regnum: return regnum2spr (939);
+    case sim_ppc_spr940_regnum: return regnum2spr (940);
+    case sim_ppc_spr941_regnum: return regnum2spr (941);
+    case sim_ppc_spr942_regnum: return regnum2spr (942);
+    case sim_ppc_spr943_regnum: return regnum2spr (943);
+    case sim_ppc_spr944_regnum: return regnum2spr (944);
+    case sim_ppc_spr945_regnum: return regnum2spr (945);
+    case sim_ppc_spr946_regnum: return regnum2spr (946);
+    case sim_ppc_spr947_regnum: return regnum2spr (947);
+    case sim_ppc_spr948_regnum: return regnum2spr (948);
+    case sim_ppc_spr949_regnum: return regnum2spr (949);
+    case sim_ppc_spr950_regnum: return regnum2spr (950);
+    case sim_ppc_spr951_regnum: return regnum2spr (951);
+    case sim_ppc_spr952_regnum: return regnum2spr (952);
+    case sim_ppc_spr953_regnum: return regnum2spr (953);
+    case sim_ppc_spr954_regnum: return regnum2spr (954);
+    case sim_ppc_spr955_regnum: return regnum2spr (955);
+    case sim_ppc_spr956_regnum: return regnum2spr (956);
+    case sim_ppc_spr957_regnum: return regnum2spr (957);
+    case sim_ppc_spr958_regnum: return regnum2spr (958);
+    case sim_ppc_spr959_regnum: return regnum2spr (959);
+    case sim_ppc_spr960_regnum: return regnum2spr (960);
+    case sim_ppc_spr961_regnum: return regnum2spr (961);
+    case sim_ppc_spr962_regnum: return regnum2spr (962);
+    case sim_ppc_spr963_regnum: return regnum2spr (963);
+    case sim_ppc_spr964_regnum: return regnum2spr (964);
+    case sim_ppc_spr965_regnum: return regnum2spr (965);
+    case sim_ppc_spr966_regnum: return regnum2spr (966);
+    case sim_ppc_spr967_regnum: return regnum2spr (967);
+    case sim_ppc_spr968_regnum: return regnum2spr (968);
+    case sim_ppc_spr969_regnum: return regnum2spr (969);
+    case sim_ppc_spr970_regnum: return regnum2spr (970);
+    case sim_ppc_spr971_regnum: return regnum2spr (971);
+    case sim_ppc_spr972_regnum: return regnum2spr (972);
+    case sim_ppc_spr973_regnum: return regnum2spr (973);
+    case sim_ppc_spr974_regnum: return regnum2spr (974);
+    case sim_ppc_spr975_regnum: return regnum2spr (975);
+    case sim_ppc_spr976_regnum: return regnum2spr (976);
+    case sim_ppc_spr977_regnum: return regnum2spr (977);
+    case sim_ppc_spr978_regnum: return regnum2spr (978);
+    case sim_ppc_spr979_regnum: return regnum2spr (979);
+    case sim_ppc_spr980_regnum: return regnum2spr (980);
+    case sim_ppc_spr981_regnum: return regnum2spr (981);
+    case sim_ppc_spr982_regnum: return regnum2spr (982);
+    case sim_ppc_spr983_regnum: return regnum2spr (983);
+    case sim_ppc_spr984_regnum: return regnum2spr (984);
+    case sim_ppc_spr985_regnum: return regnum2spr (985);
+    case sim_ppc_spr986_regnum: return regnum2spr (986);
+    case sim_ppc_spr987_regnum: return regnum2spr (987);
+    case sim_ppc_spr988_regnum: return regnum2spr (988);
+    case sim_ppc_spr989_regnum: return regnum2spr (989);
+    case sim_ppc_spr990_regnum: return regnum2spr (990);
+    case sim_ppc_spr991_regnum: return regnum2spr (991);
+    case sim_ppc_spr992_regnum: return regnum2spr (992);
+    case sim_ppc_spr993_regnum: return regnum2spr (993);
+    case sim_ppc_spr994_regnum: return regnum2spr (994);
+    case sim_ppc_spr995_regnum: return regnum2spr (995);
+    case sim_ppc_spr996_regnum: return regnum2spr (996);
+    case sim_ppc_spr997_regnum: return regnum2spr (997);
+    case sim_ppc_spr998_regnum: return regnum2spr (998);
+    case sim_ppc_spr999_regnum: return regnum2spr (999);
+    case sim_ppc_spr1000_regnum: return regnum2spr (1000);
+    case sim_ppc_spr1001_regnum: return regnum2spr (1001);
+    case sim_ppc_spr1002_regnum: return regnum2spr (1002);
+    case sim_ppc_spr1003_regnum: return regnum2spr (1003);
+    case sim_ppc_spr1004_regnum: return regnum2spr (1004);
+    case sim_ppc_spr1005_regnum: return regnum2spr (1005);
+    case sim_ppc_spr1006_regnum: return regnum2spr (1006);
+    case sim_ppc_spr1007_regnum: return regnum2spr (1007);
+    case sim_ppc_spr1008_regnum: return regnum2spr (1008);
+    case sim_ppc_spr1009_regnum: return regnum2spr (1009);
+    case sim_ppc_spr1010_regnum: return regnum2spr (1010);
+    case sim_ppc_spr1011_regnum: return regnum2spr (1011);
+    case sim_ppc_spr1012_regnum: return regnum2spr (1012);
+    case sim_ppc_spr1013_regnum: return regnum2spr (1013);
+    case sim_ppc_spr1014_regnum: return regnum2spr (1014);
+    case sim_ppc_spr1015_regnum: return regnum2spr (1015);
+    case sim_ppc_spr1016_regnum: return regnum2spr (1016);
+    case sim_ppc_spr1017_regnum: return regnum2spr (1017);
+    case sim_ppc_spr1018_regnum: return regnum2spr (1018);
+    case sim_ppc_spr1019_regnum: return regnum2spr (1019);
+    case sim_ppc_spr1020_regnum: return regnum2spr (1020);
+    case sim_ppc_spr1021_regnum: return regnum2spr (1021);
+    case sim_ppc_spr1022_regnum: return regnum2spr (1022);
+    case sim_ppc_spr1023_regnum: return regnum2spr (1023);
+    default:
+      /* Not a valid register number at all.  */
+      return NULL;
+    }
+}
+
+
+int
+sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
+{
+  const char *regname = regnum2name (regno);
+
+  if (simulator == NULL || regname == NULL)
+    return -1;
+
+  TRACE(trace_gdb, ("sim_fetch_register(regno=%d(%s), buf=0x%lx)\n",
+		    regno, regname, (long)buf));
+  return psim_read_register(simulator, MAX_NR_PROCESSORS,
+			    buf, regname, raw_transfer);
+}
+
+
+int
+sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
+{
+  const char *regname = regnum2name (regno);
+
+  if (simulator == NULL || regname == NULL)
+    return -1;
+
+  TRACE(trace_gdb, ("sim_store_register(regno=%d(%s), buf=0x%lx)\n",
+		    regno, regname, (long)buf));
+  return psim_write_register(simulator, MAX_NR_PROCESSORS,
+			     buf, regname, raw_transfer);
+}
diff --git a/sim/ppc/sim_callbacks.h b/sim/ppc/sim_callbacks.h
index 322af9de8a1..9fb815b4682 100644
--- a/sim/ppc/sim_callbacks.h
+++ b/sim/ppc/sim_callbacks.h
@@ -103,6 +103,10 @@ void sim_io_flush_stdoutput
 (void);
 
 
+/* Simulator instance.  */
+extern psim *simulator;
+
+
 /* Memory management with an allocator that clears memory before use. */
 
 void *zalloc
diff --git a/sim/ppc/sim_calls.c b/sim/ppc/sim_calls.c
index 040ce833202..ae74593dd69 100644
--- a/sim/ppc/sim_calls.c
+++ b/sim/ppc/sim_calls.c
@@ -40,7 +40,6 @@
 #endif
 #endif
 
-#include "defs.h"
 #include "bfd.h"
 #include "gdb/callback.h"
 #include "gdb/remote-sim.h"
@@ -55,33 +54,10 @@ static int poll_quit_count = POLL_QUIT_INTERVAL;
 
 /* Structures used by the simulator, for gdb just have static structures */
 
-static psim *simulator;
+psim *simulator;
 static device *root_device;
 static host_callback *callbacks;
 
-/* We use GDB's gdbarch_register_name function to map GDB register
-   numbers onto names, which we can then look up in the register
-   table.  Since the `set architecture' command can select a new
-   processor variant at run-time, the meanings of the register numbers
-   can change, so we need to make sure the sim uses the same
-   name/number mapping that GDB uses.
-
-   (We don't use the REGISTER_NAME macro, which is a wrapper for
-   gdbarch_register_name.  We #include GDB's "defs.h", which tries to
-   #include GDB's "config.h", but gets ours instead, and REGISTER_NAME
-   ends up not getting defined.  Simpler to just use
-   gdbarch_register_name directly.)
-
-   We used to just use the REGISTER_NAMES macro from GDB's
-   target-dependent header files, which expanded into an initializer
-   for an array of strings.  That was kind of nice, because it meant
-   that libsim.a had only a compile-time dependency on GDB; using
-   gdbarch_register_name directly means that there are now link-time
-   and run-time dependencies too.
-
-   Perhaps the host_callback structure could provide a function for
-   retrieving register names; that would be cleaner.  */
-
 SIM_DESC
 sim_open (SIM_OPEN_KIND kind,
 	  host_callback *callback,
@@ -176,54 +152,6 @@ sim_write (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length)
   return result;
 }
 
-
-int
-sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
-{
-  const char *regname;
-
-  if (simulator == NULL) {
-    return 0;
-  }
-
-  /* GDB will sometimes ask for the contents of a register named "";
-     we ignore such requests, and leave garbage in *BUF.  In GDB
-     terms, the empty string means "the register with this number is
-     not present in the currently selected architecture variant."
-     That's following the kludge we're using for the MIPS processors.
-     But there are loops that just walk through the entire list of
-     names and try to get everything.  */
-  regname = gdbarch_register_name (current_gdbarch, regno);
-  if (! regname || regname[0] == '\0')
-    return -1;
-
-  TRACE(trace_gdb, ("sim_fetch_register(regno=%d(%s), buf=0x%lx)\n",
-		    regno, regname, (long)buf));
-  return psim_read_register(simulator, MAX_NR_PROCESSORS,
-			    buf, regname, raw_transfer);
-}
-
-
-int
-sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
-{
-  const char *regname;
-
-  if (simulator == NULL)
-    return 0;
-
-  /* See comments in sim_fetch_register, above.  */
-  regname = gdbarch_register_name (current_gdbarch, regno);
-  if (! regname || regname[0] == '\0')
-    return -1;
-
-  TRACE(trace_gdb, ("sim_store_register(regno=%d(%s), buf=0x%lx)\n",
-		    regno, regname, (long)buf));
-  return psim_write_register(simulator, MAX_NR_PROCESSORS,
-			     buf, regname, raw_transfer);
-}
-
-
 void
 sim_info (SIM_DESC sd, int verbose)
 {