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authoryufeng <yufeng>2012-10-15 15:07:48 +0000
committeryufeng <yufeng>2012-10-15 15:07:48 +0000
commitec53cfb44193d6488a810f63eefa85d0ae1345f5 (patch)
tree9dc7e3980e20d77f34d71259ac19b3aa0100897f
parent5a45da1e3ac5869358554a783e2f43d5a4ef4919 (diff)
downloadgdb-ec53cfb44193d6488a810f63eefa85d0ae1345f5.tar.gz
Updated the system register table.
opcodes/ * aarch64-opc.c (aarch64_sys_regs): Add rmr_el1, rmr_el2 and rmr_el3; remove daifset and daifclr. gas/testsuite/ * gas/aarch64/sysreg-1.s: Add tests of rmr_el1, rmr_el2 and rmr_el3. * gas/aarch64/sysreg-1.d: Update. * gas/aarch64/illegal.s: Add tests of daifset and daifclr. * gas/aarch64/illegal.d: Update.
-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/aarch64-opc.c7
2 files changed, 8 insertions, 4 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index ad5a070346f..398ae6f16b1 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,10 @@
2012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
+ * aarch64-opc.c (aarch64_sys_regs): Add rmr_el1, rmr_el2 and
+ rmr_el3; remove daifset and daifclr.
+
+2012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
+
* aarch64-opc.c (operand_general_constraint_met_p): Change to check
the alignment of addr.offset.imm instead of that of shifter.amount for
operand type AARCH64_OPND_ADDR_UIMM12.
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 8c709383004..b5e0984f6c6 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -2771,6 +2771,9 @@ const struct aarch64_name_value_pair aarch64_sys_regs [] =
{ "rvbar_el1", CPENC(3,0,C12,C0,1) }, /* RO */
{ "rvbar_el2", CPENC(3,4,C12,C0,1) }, /* RO */
{ "rvbar_el3", CPENC(3,6,C12,C0,1) }, /* RO */
+ { "rmr_el1", CPENC(3,0,C12,C0,2) },
+ { "rmr_el2", CPENC(3,4,C12,C0,2) },
+ { "rmr_el3", CPENC(3,6,C12,C0,2) },
{ "isr_el1", CPENC(3,0,C12,C1,0) }, /* RO */
{ "contextidr_el1", CPENC(3,0,C13,C0,1) },
{ "tpidr_el0", CPENC(3,3,C13,C0,2) },
@@ -2962,10 +2965,6 @@ const struct aarch64_name_value_pair aarch64_sys_regs [] =
{ "pmevtyper29_el0", CPENC(3,3,C14,C15,5) },
{ "pmevtyper30_el0", CPENC(3,3,C14,C15,6) },
{ "pmccfiltr_el0", CPENC(3,3,C14,C15,7) },
-
- { "daifset", CPENC(0,3,C4,C0,6) },
- { "daifclr", CPENC(0,3,C4,C0,7) },
-
{ 0, CPENC(0,0,0,0,0) },
};