diff options
| author | Nick Clifton <nickc@redhat.com> | 2004-02-09 12:15:57 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2004-02-09 12:15:57 +0000 |
| commit | 8c8a4ea65f3e896f6f28656ad40a235323223bdd (patch) | |
| tree | f4e02fee5512559ed0be8b1ed329eec195afc82d | |
| parent | 00a45f85a9055e61a63aff6a81edf8cdd3e1e1a0 (diff) | |
| download | gdb-8c8a4ea65f3e896f6f28656ad40a235323223bdd.tar.gz | |
Add support for relaxing the 32bit ldc/stc instructions.
| -rw-r--r-- | bfd/ChangeLog | 5 | ||||
| -rw-r--r-- | bfd/coff-h8300.c | 4 | ||||
| -rw-r--r-- | bfd/elf32-h8300.c | 2 | ||||
| -rw-r--r-- | include/opcode/ChangeLog | 4 | ||||
| -rw-r--r-- | include/opcode/h8300.h | 9 |
5 files changed, 17 insertions, 7 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog index cbd41d03c1c..81c80d3f2b2 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,8 @@ +2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com> + + * coff-h8300.c: Added comments about relaxation for ldc.w and stc.w. + * elf32-h8300.c: Likewise. + 2004-02-09 Christian Vogel <vogelchr@vogel.cx> Nick Clifton <nickc@redhat.com> diff --git a/bfd/coff-h8300.c b/bfd/coff-h8300.c index bd798a64b65..e4d1399e31f 100644 --- a/bfd/coff-h8300.c +++ b/bfd/coff-h8300.c @@ -780,8 +780,8 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info, instructions: "band", "bclr", "biand", "bild", "bior", "bist", "bixor", - "bld", "bnot", "bor", "bset", "bst", "btst", "bxor", and - "mov.[bwl]" + "bld", "bnot", "bor", "bset", "bst", "btst", "bxor", "ldc.w", + "stc.w" and "mov.[bwl]" We may relax this into an 16-bit absolute address if it's in the right range. */ diff --git a/bfd/elf32-h8300.c b/bfd/elf32-h8300.c index 1a176214f01..547adfaa935 100644 --- a/bfd/elf32-h8300.c +++ b/bfd/elf32-h8300.c @@ -1198,7 +1198,7 @@ elf32_h8_relax_section (bfd *abfd, asection *sec, "band", "bclr", "biand", "bild", "bior", "bist", "bixor", "bld", "bnot", "bor", "bset", "bst", "btst", - "bxor", and "mov.[bwl]" + "bxor", "ldc.w", "stc.w" and "mov.[bwl]" We may relax this into an 16-bit absolute address if it's in the right range. */ diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 8f0d6d76359..438c6d8ad11 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,7 @@ +2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com> + + * h8300.h (32bit ldc/stc): Add relaxing support. + 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com> * h8300.h (BITOP): Pass MEMRELAX flag. diff --git a/include/opcode/h8300.h b/include/opcode/h8300.h index 76d42e58a72..29374df5b4f 100644 --- a/include/opcode/h8300.h +++ b/include/opcode/h8300.h @@ -1434,8 +1434,9 @@ struct h8_opcode h8_opcodes[] = {O (O_LDC, SW), AV_H8S, 2, "ldc", {{DISP32SRC, EXR | DST, E}}, {{PREFIXLDC, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xB, 0x2, IGNORE, SRC | DISP32LIST, E}}}, {O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS16SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, IGNORE, SRC | ABS16LIST, E}}}, {O (O_LDC, SW), AV_H8S, 2, "ldc", {{ABS16SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, IGNORE, SRC | ABS16LIST, E}}}, - {O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | ABS32LIST, E}}}, - {O (O_LDC, SW), AV_H8S, 2, "ldc", {{ABS32SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | ABS32LIST, E}}}, + {O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | MEMRELAX | ABS32LIST, E}}}, + {O (O_LDC, SW), AV_H8S, 2, "ldc", {{ABS32SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | MEMRELAX | ABS32LIST, E}}}, + {O (O_LDC, SL), AV_H8SX, 0, "ldc", {{RS32, B30 | VBR_SBR | DST, E}}, {{0x0, 0x3, B30 | VBR_SBR | DST, RS32, E}}}, @@ -1809,8 +1810,8 @@ struct h8_opcode h8_opcodes[] = {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, DISP32DST, E}}, {{PREFIXSTC, 0x7, 0x8, B30 | DSTDISPREG, 0, 0x6, 0xB, 0xA, IGNORE, DSTDISP32LIST, E}}}, {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, ABS16DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0x8, IGNORE, DST | ABS16LIST, E}}}, {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, ABS16DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0x8, IGNORE, DST | ABS16LIST, E}}}, - {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, ABS32DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | ABS32LIST, E}}}, - {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, ABS32DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | ABS32LIST, E}}}, + {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, ABS32DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | MEMRELAX | ABS32LIST, E}}}, + {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, ABS32DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | MEMRELAX | ABS32LIST, E}}}, {O (O_STC, SL), AV_H8SX, 0, "stc", {{B30 | VBR_SBR | SRC, RD32, E}}, {{0x0, 0x2, B30 | VBR_SBR | SRC, RD32, E}}}, |