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authorH.J. Lu <hjl@lucon.org>2005-11-02 16:58:31 +0000
committerH.J. Lu <hjl@lucon.org>2005-11-02 16:58:31 +0000
commit11f1cd8e04ab11df670a8ead8ff1bb5e8482f113 (patch)
tree6c4aef77fdb9ad2cc0172ca3ef0812591418b78e
parent90e2ef90c9871cf93e0fa1d0ea95aef955673575 (diff)
downloadgdb-11f1cd8e04ab11df670a8ead8ff1bb5e8482f113.tar.gz
2005-11-02 H.J. Lu <hongjiu.lu@intel.com>
* iq2000-desc.c: Regenerated. * iq2000-desc.h: Likewise. * iq2000-dis.c: Likewise. * iq2000-opc.c: Likewise.
Diffstat
-rw-r--r--opcodes/ChangeLog7
-rw-r--r--opcodes/iq2000-desc.c851
-rw-r--r--opcodes/iq2000-desc.h50
-rw-r--r--opcodes/iq2000-dis.c28
-rw-r--r--opcodes/iq2000-opc.c188
5 files changed, 594 insertions, 530 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 7d6757c80a6..0496dbe732e 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2005-11-02 H.J. Lu <hongjiu.lu@intel.com>
+
+ * iq2000-desc.c: Regenerated.
+ * iq2000-desc.h: Likewise.
+ * iq2000-dis.c: Likewise.
+ * iq2000-opc.c: Likewise.
+
2005-11-02 Paul Brook <paul@codesourcery.com>
* arm-dis.c (print_insn_thumb32): Word align blx target address.
diff --git a/opcodes/iq2000-desc.c b/opcodes/iq2000-desc.c
index 39bda648e4a..5f47e4c8e7b 100644
--- a/opcodes/iq2000-desc.c
+++ b/opcodes/iq2000-desc.c
@@ -136,70 +136,70 @@ static const CGEN_MACH iq2000_cgen_mach_table[] = {
static CGEN_KEYWORD_ENTRY iq2000_cgen_opval_gr_names_entries[] =
{
- { "r0", 0, {0, {0}}, 0, 0 },
- { "%0", 0, {0, {0}}, 0, 0 },
- { "r1", 1, {0, {0}}, 0, 0 },
- { "%1", 1, {0, {0}}, 0, 0 },
- { "r2", 2, {0, {0}}, 0, 0 },
- { "%2", 2, {0, {0}}, 0, 0 },
- { "r3", 3, {0, {0}}, 0, 0 },
- { "%3", 3, {0, {0}}, 0, 0 },
- { "r4", 4, {0, {0}}, 0, 0 },
- { "%4", 4, {0, {0}}, 0, 0 },
- { "r5", 5, {0, {0}}, 0, 0 },
- { "%5", 5, {0, {0}}, 0, 0 },
- { "r6", 6, {0, {0}}, 0, 0 },
- { "%6", 6, {0, {0}}, 0, 0 },
- { "r7", 7, {0, {0}}, 0, 0 },
- { "%7", 7, {0, {0}}, 0, 0 },
- { "r8", 8, {0, {0}}, 0, 0 },
- { "%8", 8, {0, {0}}, 0, 0 },
- { "r9", 9, {0, {0}}, 0, 0 },
- { "%9", 9, {0, {0}}, 0, 0 },
- { "r10", 10, {0, {0}}, 0, 0 },
- { "%10", 10, {0, {0}}, 0, 0 },
- { "r11", 11, {0, {0}}, 0, 0 },
- { "%11", 11, {0, {0}}, 0, 0 },
- { "r12", 12, {0, {0}}, 0, 0 },
- { "%12", 12, {0, {0}}, 0, 0 },
- { "r13", 13, {0, {0}}, 0, 0 },
- { "%13", 13, {0, {0}}, 0, 0 },
- { "r14", 14, {0, {0}}, 0, 0 },
- { "%14", 14, {0, {0}}, 0, 0 },
- { "r15", 15, {0, {0}}, 0, 0 },
- { "%15", 15, {0, {0}}, 0, 0 },
- { "r16", 16, {0, {0}}, 0, 0 },
- { "%16", 16, {0, {0}}, 0, 0 },
- { "r17", 17, {0, {0}}, 0, 0 },
- { "%17", 17, {0, {0}}, 0, 0 },
- { "r18", 18, {0, {0}}, 0, 0 },
- { "%18", 18, {0, {0}}, 0, 0 },
- { "r19", 19, {0, {0}}, 0, 0 },
- { "%19", 19, {0, {0}}, 0, 0 },
- { "r20", 20, {0, {0}}, 0, 0 },
- { "%20", 20, {0, {0}}, 0, 0 },
- { "r21", 21, {0, {0}}, 0, 0 },
- { "%21", 21, {0, {0}}, 0, 0 },
- { "r22", 22, {0, {0}}, 0, 0 },
- { "%22", 22, {0, {0}}, 0, 0 },
- { "r23", 23, {0, {0}}, 0, 0 },
- { "%23", 23, {0, {0}}, 0, 0 },
- { "r24", 24, {0, {0}}, 0, 0 },
- { "%24", 24, {0, {0}}, 0, 0 },
- { "r25", 25, {0, {0}}, 0, 0 },
- { "%25", 25, {0, {0}}, 0, 0 },
- { "r26", 26, {0, {0}}, 0, 0 },
- { "%26", 26, {0, {0}}, 0, 0 },
- { "r27", 27, {0, {0}}, 0, 0 },
- { "%27", 27, {0, {0}}, 0, 0 },
- { "r28", 28, {0, {0}}, 0, 0 },
- { "%28", 28, {0, {0}}, 0, 0 },
- { "r29", 29, {0, {0}}, 0, 0 },
- { "%29", 29, {0, {0}}, 0, 0 },
- { "r30", 30, {0, {0}}, 0, 0 },
- { "%30", 30, {0, {0}}, 0, 0 },
- { "r31", 31, {0, {0}}, 0, 0 },
- { "%31", 31, {0, {0}}, 0, 0 }
+ { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
+ { "%0", 0, {0, {{{0, 0}}}}, 0, 0 },
+ { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
+ { "%1", 1, {0, {{{0, 0}}}}, 0, 0 },
+ { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
+ { "%2", 2, {0, {{{0, 0}}}}, 0, 0 },
+ { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
+ { "%3", 3, {0, {{{0, 0}}}}, 0, 0 },
+ { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
+ { "%4", 4, {0, {{{0, 0}}}}, 0, 0 },
+ { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
+ { "%5", 5, {0, {{{0, 0}}}}, 0, 0 },
+ { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
+ { "%6", 6, {0, {{{0, 0}}}}, 0, 0 },
+ { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
+ { "%7", 7, {0, {{{0, 0}}}}, 0, 0 },
+ { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
+ { "%8", 8, {0, {{{0, 0}}}}, 0, 0 },
+ { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
+ { "%9", 9, {0, {{{0, 0}}}}, 0, 0 },
+ { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
+ { "%10", 10, {0, {{{0, 0}}}}, 0, 0 },
+ { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
+ { "%11", 11, {0, {{{0, 0}}}}, 0, 0 },
+ { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
+ { "%12", 12, {0, {{{0, 0}}}}, 0, 0 },
+ { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
+ { "%13", 13, {0, {{{0, 0}}}}, 0, 0 },
+ { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
+ { "%14", 14, {0, {{{0, 0}}}}, 0, 0 },
+ { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
+ { "%15", 15, {0, {{{0, 0}}}}, 0, 0 },
+ { "r16", 16, {0, {{{0, 0}}}}, 0, 0 },
+ { "%16", 16, {0, {{{0, 0}}}}, 0, 0 },
+ { "r17", 17, {0, {{{0, 0}}}}, 0, 0 },
+ { "%17", 17, {0, {{{0, 0}}}}, 0, 0 },
+ { "r18", 18, {0, {{{0, 0}}}}, 0, 0 },
+ { "%18", 18, {0, {{{0, 0}}}}, 0, 0 },
+ { "r19", 19, {0, {{{0, 0}}}}, 0, 0 },
+ { "%19", 19, {0, {{{0, 0}}}}, 0, 0 },
+ { "r20", 20, {0, {{{0, 0}}}}, 0, 0 },
+ { "%20", 20, {0, {{{0, 0}}}}, 0, 0 },
+ { "r21", 21, {0, {{{0, 0}}}}, 0, 0 },
+ { "%21", 21, {0, {{{0, 0}}}}, 0, 0 },
+ { "r22", 22, {0, {{{0, 0}}}}, 0, 0 },
+ { "%22", 22, {0, {{{0, 0}}}}, 0, 0 },
+ { "r23", 23, {0, {{{0, 0}}}}, 0, 0 },
+ { "%23", 23, {0, {{{0, 0}}}}, 0, 0 },
+ { "r24", 24, {0, {{{0, 0}}}}, 0, 0 },
+ { "%24", 24, {0, {{{0, 0}}}}, 0, 0 },
+ { "r25", 25, {0, {{{0, 0}}}}, 0, 0 },
+ { "%25", 25, {0, {{{0, 0}}}}, 0, 0 },
+ { "r26", 26, {0, {{{0, 0}}}}, 0, 0 },
+ { "%26", 26, {0, {{{0, 0}}}}, 0, 0 },
+ { "r27", 27, {0, {{{0, 0}}}}, 0, 0 },
+ { "%27", 27, {0, {{{0, 0}}}}, 0, 0 },
+ { "r28", 28, {0, {{{0, 0}}}}, 0, 0 },
+ { "%28", 28, {0, {{{0, 0}}}}, 0, 0 },
+ { "r29", 29, {0, {{{0, 0}}}}, 0, 0 },
+ { "%29", 29, {0, {{{0, 0}}}}, 0, 0 },
+ { "r30", 30, {0, {{{0, 0}}}}, 0, 0 },
+ { "%30", 30, {0, {{{0, 0}}}}, 0, 0 },
+ { "r31", 31, {0, {{{0, 0}}}}, 0, 0 },
+ { "%31", 31, {0, {{{0, 0}}}}, 0, 0 }
};
CGEN_KEYWORD iq2000_cgen_opval_gr_names =
@@ -220,14 +220,14 @@ CGEN_KEYWORD iq2000_cgen_opval_gr_names =
const CGEN_HW_ENTRY iq2000_cgen_hw_table[] =
{
- { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
- { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
- { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
- { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
- { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
- { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
- { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & iq2000_cgen_opval_gr_names, { 0, { (1<<MACH_BASE) } } },
- { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
+ { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & iq2000_cgen_opval_gr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
};
#undef A
@@ -243,44 +243,44 @@ const CGEN_HW_ENTRY iq2000_cgen_hw_table[] =
const CGEN_IFLD iq2000_cgen_ifld_table[] =
{
- { IQ2000_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_OPCODE, "f-opcode", 0, 32, 31, 6, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_RS, "f-rs", 0, 32, 25, 5, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_RT, "f-rt", 0, 32, 20, 5, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_RD, "f-rd", 0, 32, 15, 5, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_SHAMT, "f-shamt", 0, 32, 10, 5, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_CP_OP, "f-cp-op", 0, 32, 10, 3, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_CP_OP_10, "f-cp-op-10", 0, 32, 10, 5, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_CP_GRP, "f-cp-grp", 0, 32, 7, 2, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_FUNC, "f-func", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_IMM, "f-imm", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_RD_RS, "f-rd-rs", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
- { IQ2000_F_RD_RT, "f-rd-rt", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
- { IQ2000_F_RT_RS, "f-rt-rs", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
- { IQ2000_F_JTARG, "f-jtarg", 0, 32, 15, 16, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
- { IQ2000_F_JTARGQ10, "f-jtargq10", 0, 32, 20, 21, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
- { IQ2000_F_OFFSET, "f-offset", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
- { IQ2000_F_COUNT, "f-count", 0, 32, 15, 7, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_BYTECOUNT, "f-bytecount", 0, 32, 7, 8, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_INDEX, "f-index", 0, 32, 8, 9, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_MASK, "f-mask", 0, 32, 9, 4, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_MASKQ10, "f-maskq10", 0, 32, 10, 5, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_MASKL, "f-maskl", 0, 32, 4, 5, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_EXCODE, "f-excode", 0, 32, 25, 20, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_RSRVD, "f-rsrvd", 0, 32, 25, 10, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_10_11, "f-10-11", 0, 32, 10, 11, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_24_19, "f-24-19", 0, 32, 24, 19, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_5, "f-5", 0, 32, 5, 1, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_10, "f-10", 0, 32, 10, 1, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_25, "f-25", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_CAM_Z, "f-cam-z", 0, 32, 5, 3, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_CAM_Y, "f-cam-y", 0, 32, 2, 3, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_CM_3FUNC, "f-cm-3func", 0, 32, 5, 3, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_CM_4FUNC, "f-cm-4func", 0, 32, 5, 4, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_CM_3Z, "f-cm-3z", 0, 32, 1, 2, { 0, { (1<<MACH_BASE) } } },
- { IQ2000_F_CM_4Z, "f-cm-4z", 0, 32, 2, 3, { 0, { (1<<MACH_BASE) } } },
- { 0, 0, 0, 0, 0, 0, {0, {0}} }
+ { IQ2000_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_OPCODE, "f-opcode", 0, 32, 31, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_RS, "f-rs", 0, 32, 25, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_RT, "f-rt", 0, 32, 20, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_RD, "f-rd", 0, 32, 15, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_SHAMT, "f-shamt", 0, 32, 10, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_CP_OP, "f-cp-op", 0, 32, 10, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_CP_OP_10, "f-cp-op-10", 0, 32, 10, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_CP_GRP, "f-cp-grp", 0, 32, 7, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_FUNC, "f-func", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_IMM, "f-imm", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_RD_RS, "f-rd-rs", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_RD_RT, "f-rd-rt", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_RT_RS, "f-rt-rs", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_JTARG, "f-jtarg", 0, 32, 15, 16, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_JTARGQ10, "f-jtargq10", 0, 32, 20, 21, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_OFFSET, "f-offset", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_COUNT, "f-count", 0, 32, 15, 7, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_BYTECOUNT, "f-bytecount", 0, 32, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_INDEX, "f-index", 0, 32, 8, 9, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_MASK, "f-mask", 0, 32, 9, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_MASKQ10, "f-maskq10", 0, 32, 10, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_MASKL, "f-maskl", 0, 32, 4, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_EXCODE, "f-excode", 0, 32, 25, 20, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_RSRVD, "f-rsrvd", 0, 32, 25, 10, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_10_11, "f-10-11", 0, 32, 10, 11, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_24_19, "f-24-19", 0, 32, 24, 19, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_5, "f-5", 0, 32, 5, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_10, "f-10", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_25, "f-25", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_CAM_Z, "f-cam-z", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_CAM_Y, "f-cam-y", 0, 32, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_CM_3FUNC, "f-cm-3func", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_CM_4FUNC, "f-cm-4func", 0, 32, 5, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_CM_3Z, "f-cm-3z", 0, 32, 1, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { IQ2000_F_CM_4Z, "f-cm-4z", 0, 32, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
};
#undef A
@@ -333,135 +333,135 @@ const CGEN_OPERAND iq2000_cgen_operand_table[] =
/* pc: program counter */
{ "pc", IQ2000_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_NIL] } },
- { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* rs: register Rs */
{ "rs", IQ2000_OPERAND_RS, HW_H_GR, 25, 5,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rt: register Rt */
{ "rt", IQ2000_OPERAND_RT, HW_H_GR, 20, 5,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rd: register Rd */
{ "rd", IQ2000_OPERAND_RD, HW_H_GR, 15, 5,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RD] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rd-rs: register Rd from Rs */
{ "rd-rs", IQ2000_OPERAND_RD_RS, HW_H_GR, 15, 10,
{ 2, { (const PTR) &IQ2000_F_RD_RS_MULTI_IFIELD[0] } },
- { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* rd-rt: register Rd from Rt */
{ "rd-rt", IQ2000_OPERAND_RD_RT, HW_H_GR, 15, 10,
{ 2, { (const PTR) &IQ2000_F_RD_RT_MULTI_IFIELD[0] } },
- { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* rt-rs: register Rt from Rs */
{ "rt-rs", IQ2000_OPERAND_RT_RS, HW_H_GR, 20, 10,
{ 2, { (const PTR) &IQ2000_F_RT_RS_MULTI_IFIELD[0] } },
- { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* shamt: shift amount */
{ "shamt", IQ2000_OPERAND_SHAMT, HW_H_UINT, 10, 5,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_SHAMT] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* imm: immediate */
{ "imm", IQ2000_OPERAND_IMM, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* offset: pc-relative offset */
{ "offset", IQ2000_OPERAND_OFFSET, HW_H_IADDR, 15, 16,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_OFFSET] } },
- { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
+ { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* baseoff: base register offset */
{ "baseoff", IQ2000_OPERAND_BASEOFF, HW_H_IADDR, 15, 16,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* jmptarg: jump target */
{ "jmptarg", IQ2000_OPERAND_JMPTARG, HW_H_IADDR, 15, 16,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_JTARG] } },
- { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
+ { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* mask: mask */
{ "mask", IQ2000_OPERAND_MASK, HW_H_UINT, 9, 4,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASK] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* maskq10: iq10 mask */
{ "maskq10", IQ2000_OPERAND_MASKQ10, HW_H_UINT, 10, 5,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASKQ10] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* maskl: mask left */
{ "maskl", IQ2000_OPERAND_MASKL, HW_H_UINT, 4, 5,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASKL] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* count: count */
{ "count", IQ2000_OPERAND_COUNT, HW_H_UINT, 15, 7,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_COUNT] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* _index: index */
{ "_index", IQ2000_OPERAND__INDEX, HW_H_UINT, 8, 9,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_INDEX] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* execode: execcode */
{ "execode", IQ2000_OPERAND_EXECODE, HW_H_UINT, 25, 20,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_EXCODE] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* bytecount: byte count */
{ "bytecount", IQ2000_OPERAND_BYTECOUNT, HW_H_UINT, 7, 8,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_BYTECOUNT] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cam-y: cam global opn y */
{ "cam-y", IQ2000_OPERAND_CAM_Y, HW_H_UINT, 2, 3,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CAM_Y] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cam-z: cam global mask z */
{ "cam-z", IQ2000_OPERAND_CAM_Z, HW_H_UINT, 5, 3,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CAM_Z] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cm-3func: CM 3 bit fn field */
{ "cm-3func", IQ2000_OPERAND_CM_3FUNC, HW_H_UINT, 5, 3,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_3FUNC] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cm-4func: CM 4 bit fn field */
{ "cm-4func", IQ2000_OPERAND_CM_4FUNC, HW_H_UINT, 5, 4,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_4FUNC] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cm-3z: CM 3 bit Z field */
{ "cm-3z", IQ2000_OPERAND_CM_3Z, HW_H_UINT, 1, 2,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_3Z] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cm-4z: CM 4 bit Z field */
{ "cm-4z", IQ2000_OPERAND_CM_4Z, HW_H_UINT, 2, 3,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_4Z] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* base: base register */
{ "base", IQ2000_OPERAND_BASE, HW_H_GR, 25, 5,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* maskr: mask right */
{ "maskr", IQ2000_OPERAND_MASKR, HW_H_UINT, 25, 5,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* bitnum: bit number */
{ "bitnum", IQ2000_OPERAND_BITNUM, HW_H_UINT, 20, 5,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* hi16: high 16 bit immediate */
{ "hi16", IQ2000_OPERAND_HI16, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* lo16: 16 bit signed immediate, for low */
{ "lo16", IQ2000_OPERAND_LO16, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* mlo16: negated 16 bit signed immediate */
{ "mlo16", IQ2000_OPERAND_MLO16, HW_H_UINT, 15, 16,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* jmptargq10: iq10 21-bit jump offset */
{ "jmptargq10", IQ2000_OPERAND_JMPTARGQ10, HW_H_IADDR, 20, 21,
{ 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_JTARGQ10] } },
- { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
+ { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
{ 0, { (const PTR) 0 } },
- { 0, { 0 } } }
+ { 0, { { { (1<<MACH_BASE), 0 } } } } }
};
#undef A
@@ -481,1381 +481,1381 @@ static const CGEN_IBASE iq2000_cgen_insn_table[MAX_INSNS] =
/* Special null first entry.
A `num' value of zero is thus invalid.
Also, the special `invalid' insn resides here. */
- { 0, 0, 0, 0, {0, {0}} },
+ { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* add ${rd-rs},$rt */
{
-1, "add2", "add", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* add $rd,$rs,$rt */
{
IQ2000_INSN_ADD, "add", "add", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
},
/* addi ${rt-rs},$lo16 */
{
-1, "addi2", "addi", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* addi $rt,$rs,$lo16 */
{
IQ2000_INSN_ADDI, "addi", "addi", 32,
- { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
},
/* addiu ${rt-rs},$lo16 */
{
-1, "addiu2", "addiu", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* addiu $rt,$rs,$lo16 */
{
IQ2000_INSN_ADDIU, "addiu", "addiu", 32,
- { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
},
/* addu ${rd-rs},$rt */
{
-1, "addu2", "addu", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* addu $rd,$rs,$rt */
{
IQ2000_INSN_ADDU, "addu", "addu", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
},
/* ado16 ${rd-rs},$rt */
{
-1, "ado162", "ado16", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* ado16 $rd,$rs,$rt */
{
IQ2000_INSN_ADO16, "ado16", "ado16", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
},
/* and ${rd-rs},$rt */
{
-1, "and2", "and", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* and $rd,$rs,$rt */
{
IQ2000_INSN_AND, "and", "and", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
},
/* andi ${rt-rs},$lo16 */
{
-1, "andi2", "andi", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* andi $rt,$rs,$lo16 */
{
IQ2000_INSN_ANDI, "andi", "andi", 32,
- { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
},
/* andoi ${rt-rs},$lo16 */
{
-1, "andoi2", "andoi", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* andoi $rt,$rs,$lo16 */
{
IQ2000_INSN_ANDOI, "andoi", "andoi", 32,
- { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
},
/* nor ${rd-rs},$rt */
{
-1, "nor2", "nor", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* nor $rd,$rs,$rt */
{
IQ2000_INSN_NOR, "nor", "nor", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
},
/* or ${rd-rs},$rt */
{
-1, "or2", "or", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* or $rd,$rs,$rt */
{
IQ2000_INSN_OR, "or", "or", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
},
/* ori ${rt-rs},$lo16 */
{
-1, "ori2", "ori", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* ori $rt,$rs,$lo16 */
{
IQ2000_INSN_ORI, "ori", "ori", 32,
- { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
},
/* ram $rd,$rt,$shamt,$maskl,$maskr */
{
IQ2000_INSN_RAM, "ram", "ram", 32,
- { 0|A(USES_RT)|A(USES_RD), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
},
/* sll $rd,$rt,$shamt */
{
IQ2000_INSN_SLL, "sll", "sll", 32,
- { 0|A(USES_RT)|A(USES_RD), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
},
/* sllv ${rd-rt},$rs */
{
-1, "sllv2", "sllv", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* sllv $rd,$rt,$rs */
{
IQ2000_INSN_SLLV, "sllv", "sllv", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
},
/* slmv ${rd-rt},$rs,$shamt */
{
-1, "slmv2", "slmv", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* slmv $rd,$rt,$rs,$shamt */
{
IQ2000_INSN_SLMV, "slmv", "slmv", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
},
/* slt ${rd-rs},$rt */
{
-1, "slt2", "slt", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* slt $rd,$rs,$rt */
{
IQ2000_INSN_SLT, "slt", "slt", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
},
/* slti ${rt-rs},$imm */
{
-1, "slti2", "slti", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* slti $rt,$rs,$imm */
{
IQ2000_INSN_SLTI, "slti", "slti", 32,
- { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
},
/* sltiu ${rt-rs},$imm */
{
-1, "sltiu2", "sltiu", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* sltiu $rt,$rs,$imm */
{
IQ2000_INSN_SLTIU, "sltiu", "sltiu", 32,
- { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
},
/* sltu ${rd-rs},$rt */
{
-1, "sltu2", "sltu", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* sltu $rd,$rs,$rt */
{
IQ2000_INSN_SLTU, "sltu", "sltu", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
},
/* sra ${rd-rt},$shamt */
{
-1, "sra2", "sra", 32,
- { 0|A(USES_RT)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* sra $rd,$rt,$shamt */
{
IQ2000_INSN_SRA, "sra", "sra", 32,
- { 0|A(USES_RT)|A(USES_RD), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
},
/* srav ${rd-rt},$rs */
{
-1, "srav2", "srav", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* srav $rd,$rt,$rs */
{
IQ2000_INSN_SRAV, "srav", "srav", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
},
/* srl $rd,$rt,$shamt */
{
IQ2000_INSN_SRL, "srl", "srl", 32,
- { 0|A(USES_RT)|A(USES_RD), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
},
/* srlv ${rd-rt},$rs */
{
-1, "srlv2", "srlv", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* srlv $rd,$rt,$rs */
{
IQ2000_INSN_SRLV, "srlv", "srlv", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
},
/* srmv ${rd-rt},$rs,$shamt */
{
-1, "srmv2", "srmv", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* srmv $rd,$rt,$rs,$shamt */
{
IQ2000_INSN_SRMV, "srmv", "srmv", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
},
/* sub ${rd-rs},$rt */
{
-1, "sub2", "sub", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* sub $rd,$rs,$rt */
{
IQ2000_INSN_SUB, "sub", "sub", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
},
/* subu ${rd-rs},$rt */
{
-1, "subu2", "subu", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* subu $rd,$rs,$rt */
{
IQ2000_INSN_SUBU, "subu", "subu", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
},
/* xor ${rd-rs},$rt */
{
-1, "xor2", "xor", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* xor $rd,$rs,$rt */
{
IQ2000_INSN_XOR, "xor", "xor", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } }
},
/* xori ${rt-rs},$lo16 */
{
-1, "xori2", "xori", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* xori $rt,$rs,$lo16 */
{
IQ2000_INSN_XORI, "xori", "xori", 32,
- { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
},
/* bbi $rs($bitnum),$offset */
{
IQ2000_INSN_BBI, "bbi", "bbi", 32,
- { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+ { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
},
/* bbin $rs($bitnum),$offset */
{
IQ2000_INSN_BBIN, "bbin", "bbin", 32,
- { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+ { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
},
/* bbv $rs,$rt,$offset */
{
IQ2000_INSN_BBV, "bbv", "bbv", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
},
/* bbvn $rs,$rt,$offset */
{
IQ2000_INSN_BBVN, "bbvn", "bbvn", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
},
/* beq $rs,$rt,$offset */
{
IQ2000_INSN_BEQ, "beq", "beq", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
},
/* beql $rs,$rt,$offset */
{
IQ2000_INSN_BEQL, "beql", "beql", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
},
/* bgez $rs,$offset */
{
IQ2000_INSN_BGEZ, "bgez", "bgez", 32,
- { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+ { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
},
/* bgezal $rs,$offset */
{
IQ2000_INSN_BGEZAL, "bgezal", "bgezal", 32,
- { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+ { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
},
/* bgezall $rs,$offset */
{
IQ2000_INSN_BGEZALL, "bgezall", "bgezall", 32,
- { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+ { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
},
/* bgezl $rs,$offset */
{
IQ2000_INSN_BGEZL, "bgezl", "bgezl", 32,
- { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+ { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
},
/* bltz $rs,$offset */
{
IQ2000_INSN_BLTZ, "bltz", "bltz", 32,
- { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+ { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
},
/* bltzl $rs,$offset */
{
IQ2000_INSN_BLTZL, "bltzl", "bltzl", 32,
- { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+ { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
},
/* bltzal $rs,$offset */
{
IQ2000_INSN_BLTZAL, "bltzal", "bltzal", 32,
- { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+ { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
},
/* bltzall $rs,$offset */
{
IQ2000_INSN_BLTZALL, "bltzall", "bltzall", 32,
- { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+ { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
},
/* bmb0 $rs,$rt,$offset */
{
IQ2000_INSN_BMB0, "bmb0", "bmb0", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
},
/* bmb1 $rs,$rt,$offset */
{
IQ2000_INSN_BMB1, "bmb1", "bmb1", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
},
/* bmb2 $rs,$rt,$offset */
{
IQ2000_INSN_BMB2, "bmb2", "bmb2", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
},
/* bmb3 $rs,$rt,$offset */
{
IQ2000_INSN_BMB3, "bmb3", "bmb3", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
},
/* bne $rs,$rt,$offset */
{
IQ2000_INSN_BNE, "bne", "bne", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
},
/* bnel $rs,$rt,$offset */
{
IQ2000_INSN_BNEL, "bnel", "bnel", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
},
/* jalr $rd,$rs */
{
IQ2000_INSN_JALR, "jalr", "jalr", 32,
- { 0|A(USES_RS)|A(USES_RD)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+ { 0|A(USES_RS)|A(USES_RD)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
},
/* jr $rs */
{
IQ2000_INSN_JR, "jr", "jr", 32,
- { 0|A(USES_RS)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+ { 0|A(USES_RS)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
},
/* lb $rt,$lo16($base) */
{
IQ2000_INSN_LB, "lb", "lb", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } }
},
/* lbu $rt,$lo16($base) */
{
IQ2000_INSN_LBU, "lbu", "lbu", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } }
},
/* lh $rt,$lo16($base) */
{
IQ2000_INSN_LH, "lh", "lh", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } }
},
/* lhu $rt,$lo16($base) */
{
IQ2000_INSN_LHU, "lhu", "lhu", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } }
},
/* lui $rt,$hi16 */
{
IQ2000_INSN_LUI, "lui", "lui", 32,
- { 0|A(USES_RT), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT), { { { (1<<MACH_BASE), 0 } } } }
},
/* lw $rt,$lo16($base) */
{
IQ2000_INSN_LW, "lw", "lw", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } }
},
/* sb $rt,$lo16($base) */
{
IQ2000_INSN_SB, "sb", "sb", 32,
- { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
},
/* sh $rt,$lo16($base) */
{
IQ2000_INSN_SH, "sh", "sh", 32,
- { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
},
/* sw $rt,$lo16($base) */
{
IQ2000_INSN_SW, "sw", "sw", 32,
- { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_BASE) } }
+ { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } }
},
/* break */
{
IQ2000_INSN_BREAK, "break", "break", 32,
- { 0, { (1<<MACH_BASE) } }
+ { 0, { { { (1<<MACH_BASE), 0 } } } }
},
/* syscall */
{
IQ2000_INSN_SYSCALL, "syscall", "syscall", 32,
- { 0|A(YIELD_INSN), { (1<<MACH_BASE) } }
+ { 0|A(YIELD_INSN), { { { (1<<MACH_BASE), 0 } } } }
},
/* andoui $rt,$rs,$hi16 */
{
IQ2000_INSN_ANDOUI, "andoui", "andoui", 32,
- { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* andoui ${rt-rs},$hi16 */
{
-1, "andoui2", "andoui", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* orui ${rt-rs},$hi16 */
{
-1, "orui2", "orui", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* orui $rt,$rs,$hi16 */
{
IQ2000_INSN_ORUI, "orui", "orui", 32,
- { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* bgtz $rs,$offset */
{
IQ2000_INSN_BGTZ, "bgtz", "bgtz", 32,
- { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* bgtzl $rs,$offset */
{
IQ2000_INSN_BGTZL, "bgtzl", "bgtzl", 32,
- { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* blez $rs,$offset */
{
IQ2000_INSN_BLEZ, "blez", "blez", 32,
- { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* blezl $rs,$offset */
{
IQ2000_INSN_BLEZL, "blezl", "blezl", 32,
- { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* mrgb $rd,$rs,$rt,$mask */
{
IQ2000_INSN_MRGB, "mrgb", "mrgb", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* mrgb ${rd-rs},$rt,$mask */
{
-1, "mrgb2", "mrgb", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* bctxt $rs,$offset */
{
IQ2000_INSN_BCTXT, "bctxt", "bctxt", 32,
- { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* bc0f $offset */
{
IQ2000_INSN_BC0F, "bc0f", "bc0f", 32,
- { 0|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
+ { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* bc0fl $offset */
{
IQ2000_INSN_BC0FL, "bc0fl", "bc0fl", 32,
- { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
+ { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* bc3f $offset */
{
IQ2000_INSN_BC3F, "bc3f", "bc3f", 32,
- { 0|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
+ { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* bc3fl $offset */
{
IQ2000_INSN_BC3FL, "bc3fl", "bc3fl", 32,
- { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
+ { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* bc0t $offset */
{
IQ2000_INSN_BC0T, "bc0t", "bc0t", 32,
- { 0|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
+ { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* bc0tl $offset */
{
IQ2000_INSN_BC0TL, "bc0tl", "bc0tl", 32,
- { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
+ { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* bc3t $offset */
{
IQ2000_INSN_BC3T, "bc3t", "bc3t", 32,
- { 0|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
+ { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* bc3tl $offset */
{
IQ2000_INSN_BC3TL, "bc3tl", "bc3tl", 32,
- { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
+ { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* cfc0 $rt,$rd */
{
IQ2000_INSN_CFC0, "cfc0", "cfc0", 32,
- { 0|A(USES_RT)|A(LOAD_DELAY), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* cfc1 $rt,$rd */
{
IQ2000_INSN_CFC1, "cfc1", "cfc1", 32,
- { 0|A(USES_RT)|A(LOAD_DELAY), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* cfc2 $rt,$rd */
{
IQ2000_INSN_CFC2, "cfc2", "cfc2", 32,
- { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* cfc3 $rt,$rd */
{
IQ2000_INSN_CFC3, "cfc3", "cfc3", 32,
- { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* chkhdr $rd,$rt */
{
IQ2000_INSN_CHKHDR, "chkhdr", "chkhdr", 32,
- { 0|A(YIELD_INSN)|A(USES_RD)|A(LOAD_DELAY), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RD)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* ctc0 $rt,$rd */
{
IQ2000_INSN_CTC0, "ctc0", "ctc0", 32,
- { 0|A(USES_RT), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* ctc1 $rt,$rd */
{
IQ2000_INSN_CTC1, "ctc1", "ctc1", 32,
- { 0|A(USES_RT), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* ctc2 $rt,$rd */
{
IQ2000_INSN_CTC2, "ctc2", "ctc2", 32,
- { 0|A(USES_RT), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* ctc3 $rt,$rd */
{
IQ2000_INSN_CTC3, "ctc3", "ctc3", 32,
- { 0|A(USES_RT), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* jcr $rs */
{
IQ2000_INSN_JCR, "jcr", "jcr", 32,
- { 0|A(USES_RS)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_RS)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* luc32 $rt,$rd */
{
IQ2000_INSN_LUC32, "luc32", "luc32", 32,
- { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* luc32l $rt,$rd */
{
IQ2000_INSN_LUC32L, "luc32l", "luc32l", 32,
- { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* luc64 $rt,$rd */
{
IQ2000_INSN_LUC64, "luc64", "luc64", 32,
- { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* luc64l $rt,$rd */
{
IQ2000_INSN_LUC64L, "luc64l", "luc64l", 32,
- { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* luk $rt,$rd */
{
IQ2000_INSN_LUK, "luk", "luk", 32,
- { 0|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* lulck $rt */
{
IQ2000_INSN_LULCK, "lulck", "lulck", 32,
- { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* lum32 $rt,$rd */
{
IQ2000_INSN_LUM32, "lum32", "lum32", 32,
- { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* lum32l $rt,$rd */
{
IQ2000_INSN_LUM32L, "lum32l", "lum32l", 32,
- { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* lum64 $rt,$rd */
{
IQ2000_INSN_LUM64, "lum64", "lum64", 32,
- { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* lum64l $rt,$rd */
{
IQ2000_INSN_LUM64L, "lum64l", "lum64l", 32,
- { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* lur $rt,$rd */
{
IQ2000_INSN_LUR, "lur", "lur", 32,
- { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* lurl $rt,$rd */
{
IQ2000_INSN_LURL, "lurl", "lurl", 32,
- { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* luulck $rt */
{
IQ2000_INSN_LUULCK, "luulck", "luulck", 32,
- { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* mfc0 $rt,$rd */
{
IQ2000_INSN_MFC0, "mfc0", "mfc0", 32,
- { 0|A(USES_RT)|A(LOAD_DELAY), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* mfc1 $rt,$rd */
{
IQ2000_INSN_MFC1, "mfc1", "mfc1", 32,
- { 0|A(USES_RT)|A(LOAD_DELAY), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* mfc2 $rt,$rd */
{
IQ2000_INSN_MFC2, "mfc2", "mfc2", 32,
- { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* mfc3 $rt,$rd */
{
IQ2000_INSN_MFC3, "mfc3", "mfc3", 32,
- { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* mtc0 $rt,$rd */
{
IQ2000_INSN_MTC0, "mtc0", "mtc0", 32,
- { 0|A(USES_RT), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* mtc1 $rt,$rd */
{
IQ2000_INSN_MTC1, "mtc1", "mtc1", 32,
- { 0|A(USES_RT), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* mtc2 $rt,$rd */
{
IQ2000_INSN_MTC2, "mtc2", "mtc2", 32,
- { 0|A(USES_RT), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* mtc3 $rt,$rd */
{
IQ2000_INSN_MTC3, "mtc3", "mtc3", 32,
- { 0|A(USES_RT), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* pkrl $rd,$rt */
{
IQ2000_INSN_PKRL, "pkrl", "pkrl", 32,
- { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* pkrlr1 $rt,$_index,$count */
{
IQ2000_INSN_PKRLR1, "pkrlr1", "pkrlr1", 32,
- { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* pkrlr30 $rt,$_index,$count */
{
IQ2000_INSN_PKRLR30, "pkrlr30", "pkrlr30", 32,
- { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* rb $rd,$rt */
{
IQ2000_INSN_RB, "rb", "rb", 32,
- { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* rbr1 $rt,$_index,$count */
{
IQ2000_INSN_RBR1, "rbr1", "rbr1", 32,
- { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* rbr30 $rt,$_index,$count */
{
IQ2000_INSN_RBR30, "rbr30", "rbr30", 32,
- { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* rfe */
{
IQ2000_INSN_RFE, "rfe", "rfe", 32,
- { 0, { (1<<MACH_IQ2000) } }
+ { 0, { { { (1<<MACH_IQ2000), 0 } } } }
},
/* rx $rd,$rt */
{
IQ2000_INSN_RX, "rx", "rx", 32,
- { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* rxr1 $rt,$_index,$count */
{
IQ2000_INSN_RXR1, "rxr1", "rxr1", 32,
- { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* rxr30 $rt,$_index,$count */
{
IQ2000_INSN_RXR30, "rxr30", "rxr30", 32,
- { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* sleep */
{
IQ2000_INSN_SLEEP, "sleep", "sleep", 32,
- { 0|A(YIELD_INSN), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* srrd $rt */
{
IQ2000_INSN_SRRD, "srrd", "srrd", 32,
- { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* srrdl $rt */
{
IQ2000_INSN_SRRDL, "srrdl", "srrdl", 32,
- { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* srulck $rt */
{
IQ2000_INSN_SRULCK, "srulck", "srulck", 32,
- { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* srwr $rt,$rd */
{
IQ2000_INSN_SRWR, "srwr", "srwr", 32,
- { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* srwru $rt,$rd */
{
IQ2000_INSN_SRWRU, "srwru", "srwru", 32,
- { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* trapqfl */
{
IQ2000_INSN_TRAPQFL, "trapqfl", "trapqfl", 32,
- { 0|A(YIELD_INSN), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* trapqne */
{
IQ2000_INSN_TRAPQNE, "trapqne", "trapqne", 32,
- { 0|A(YIELD_INSN), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* traprel $rt */
{
IQ2000_INSN_TRAPREL, "traprel", "traprel", 32,
- { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* wb $rd,$rt */
{
IQ2000_INSN_WB, "wb", "wb", 32,
- { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* wbu $rd,$rt */
{
IQ2000_INSN_WBU, "wbu", "wbu", 32,
- { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* wbr1 $rt,$_index,$count */
{
IQ2000_INSN_WBR1, "wbr1", "wbr1", 32,
- { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* wbr1u $rt,$_index,$count */
{
IQ2000_INSN_WBR1U, "wbr1u", "wbr1u", 32,
- { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* wbr30 $rt,$_index,$count */
{
IQ2000_INSN_WBR30, "wbr30", "wbr30", 32,
- { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* wbr30u $rt,$_index,$count */
{
IQ2000_INSN_WBR30U, "wbr30u", "wbr30u", 32,
- { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* wx $rd,$rt */
{
IQ2000_INSN_WX, "wx", "wx", 32,
- { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* wxu $rd,$rt */
{
IQ2000_INSN_WXU, "wxu", "wxu", 32,
- { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* wxr1 $rt,$_index,$count */
{
IQ2000_INSN_WXR1, "wxr1", "wxr1", 32,
- { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* wxr1u $rt,$_index,$count */
{
IQ2000_INSN_WXR1U, "wxr1u", "wxr1u", 32,
- { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* wxr30 $rt,$_index,$count */
{
IQ2000_INSN_WXR30, "wxr30", "wxr30", 32,
- { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* wxr30u $rt,$_index,$count */
{
IQ2000_INSN_WXR30U, "wxr30u", "wxr30u", 32,
- { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
+ { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* ldw $rt,$lo16($base) */
{
IQ2000_INSN_LDW, "ldw", "ldw", 32,
- { 0|A(USES_RT)|A(LOAD_DELAY)|A(EVEN_REG_NUM), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_RT)|A(LOAD_DELAY)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* sdw $rt,$lo16($base) */
{
IQ2000_INSN_SDW, "sdw", "sdw", 32,
- { 0|A(USES_RT)|A(EVEN_REG_NUM), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* j $jmptarg */
{
IQ2000_INSN_J, "j", "j", 32,
- { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
+ { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* jal $jmptarg */
{
IQ2000_INSN_JAL, "jal", "jal", 32,
- { 0|A(USES_R31)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_R31)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* bmb $rs,$rt,$offset */
{
IQ2000_INSN_BMB, "bmb", "bmb", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* andoui $rt,$rs,$hi16 */
{
IQ2000_INSN_ANDOUI_Q10, "andoui-q10", "andoui", 32,
- { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* andoui ${rt-rs},$hi16 */
{
-1, "andoui2-q10", "andoui", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* orui $rt,$rs,$hi16 */
{
IQ2000_INSN_ORUI_Q10, "orui-q10", "orui", 32,
- { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* orui ${rt-rs},$hi16 */
{
-1, "orui2-q10", "orui", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* mrgb $rd,$rs,$rt,$maskq10 */
{
IQ2000_INSN_MRGBQ10, "mrgbq10", "mrgb", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
},
/* mrgb ${rd-rs},$rt,$maskq10 */
{
-1, "mrgbq102", "mrgb", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* j $jmptarg */
{
IQ2000_INSN_JQ10, "jq10", "j", 32,
- { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
+ { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* jal $rt,$jmptarg */
{
IQ2000_INSN_JALQ10, "jalq10", "jal", 32,
- { 0|A(USES_RT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* jal $jmptarg */
{
IQ2000_INSN_JALQ10_2, "jalq10-2", "jal", 32,
- { 0|A(USES_RT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* bbil $rs($bitnum),$offset */
{
IQ2000_INSN_BBIL, "bbil", "bbil", 32,
- { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* bbinl $rs($bitnum),$offset */
{
IQ2000_INSN_BBINL, "bbinl", "bbinl", 32,
- { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* bbvl $rs,$rt,$offset */
{
IQ2000_INSN_BBVL, "bbvl", "bbvl", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* bbvnl $rs,$rt,$offset */
{
IQ2000_INSN_BBVNL, "bbvnl", "bbvnl", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* bgtzal $rs,$offset */
{
IQ2000_INSN_BGTZAL, "bgtzal", "bgtzal", 32,
- { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* bgtzall $rs,$offset */
{
IQ2000_INSN_BGTZALL, "bgtzall", "bgtzall", 32,
- { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* blezal $rs,$offset */
{
IQ2000_INSN_BLEZAL, "blezal", "blezal", 32,
- { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* blezall $rs,$offset */
{
IQ2000_INSN_BLEZALL, "blezall", "blezall", 32,
- { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* bgtz $rs,$offset */
{
IQ2000_INSN_BGTZ_Q10, "bgtz-q10", "bgtz", 32,
- { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* bgtzl $rs,$offset */
{
IQ2000_INSN_BGTZL_Q10, "bgtzl-q10", "bgtzl", 32,
- { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* blez $rs,$offset */
{
IQ2000_INSN_BLEZ_Q10, "blez-q10", "blez", 32,
- { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* blezl $rs,$offset */
{
IQ2000_INSN_BLEZL_Q10, "blezl-q10", "blezl", 32,
- { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* bmb $rs,$rt,$offset */
{
IQ2000_INSN_BMB_Q10, "bmb-q10", "bmb", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* bmbl $rs,$rt,$offset */
{
IQ2000_INSN_BMBL, "bmbl", "bmbl", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* bri $rs,$offset */
{
IQ2000_INSN_BRI, "bri", "bri", 32,
- { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* brv $rs,$offset */
{
IQ2000_INSN_BRV, "brv", "brv", 32,
- { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* bctx $rs,$offset */
{
IQ2000_INSN_BCTX, "bctx", "bctx", 32,
- { 0|A(USES_RS)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RS)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* yield */
{
IQ2000_INSN_YIELD, "yield", "yield", 32,
- { 0, { (1<<MACH_IQ10) } }
+ { 0, { { { (1<<MACH_IQ10), 0 } } } }
},
/* crc32 $rd,$rs,$rt */
{
IQ2000_INSN_CRC32, "crc32", "crc32", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
},
/* crc32b $rd,$rs,$rt */
{
IQ2000_INSN_CRC32B, "crc32b", "crc32b", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cnt1s $rd,$rs */
{
IQ2000_INSN_CNT1S, "cnt1s", "cnt1s", 32,
- { 0|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
},
/* avail $rd */
{
IQ2000_INSN_AVAIL, "avail", "avail", 32,
- { 0|A(USES_RD), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
},
/* free $rd,$rs */
{
IQ2000_INSN_FREE, "free", "free", 32,
- { 0|A(USES_RD)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* tstod $rd,$rs */
{
IQ2000_INSN_TSTOD, "tstod", "tstod", 32,
- { 0|A(USES_RD)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cmphdr $rd */
{
IQ2000_INSN_CMPHDR, "cmphdr", "cmphdr", 32,
- { 0|A(USES_RD), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
},
/* mcid $rd,$rt */
{
IQ2000_INSN_MCID, "mcid", "mcid", 32,
- { 0|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
},
/* dba $rd */
{
IQ2000_INSN_DBA, "dba", "dba", 32,
- { 0|A(USES_RD), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
},
/* dbd $rd,$rs,$rt */
{
IQ2000_INSN_DBD, "dbd", "dbd", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* dpwt $rd,$rs */
{
IQ2000_INSN_DPWT, "dpwt", "dpwt", 32,
- { 0|A(USES_RD)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* chkhdr $rd,$rs */
{
IQ2000_INSN_CHKHDRQ10, "chkhdrq10", "chkhdr", 32,
- { 0|A(USES_RD)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* rba $rd,$rs,$rt */
{
IQ2000_INSN_RBA, "rba", "rba", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* rbal $rd,$rs,$rt */
{
IQ2000_INSN_RBAL, "rbal", "rbal", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* rbar $rd,$rs,$rt */
{
IQ2000_INSN_RBAR, "rbar", "rbar", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* wba $rd,$rs,$rt */
{
IQ2000_INSN_WBA, "wba", "wba", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* wbau $rd,$rs,$rt */
{
IQ2000_INSN_WBAU, "wbau", "wbau", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* wbac $rd,$rs,$rt */
{
IQ2000_INSN_WBAC, "wbac", "wbac", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* rbi $rd,$rs,$rt,$bytecount */
{
IQ2000_INSN_RBI, "rbi", "rbi", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
},
/* rbil $rd,$rs,$rt,$bytecount */
{
IQ2000_INSN_RBIL, "rbil", "rbil", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
},
/* rbir $rd,$rs,$rt,$bytecount */
{
IQ2000_INSN_RBIR, "rbir", "rbir", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
},
/* wbi $rd,$rs,$rt,$bytecount */
{
IQ2000_INSN_WBI, "wbi", "wbi", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
},
/* wbic $rd,$rs,$rt,$bytecount */
{
IQ2000_INSN_WBIC, "wbic", "wbic", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
},
/* wbiu $rd,$rs,$rt,$bytecount */
{
IQ2000_INSN_WBIU, "wbiu", "wbiu", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
},
/* pkrli $rd,$rs,$rt,$bytecount */
{
IQ2000_INSN_PKRLI, "pkrli", "pkrli", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
},
/* pkrlih $rd,$rs,$rt,$bytecount */
{
IQ2000_INSN_PKRLIH, "pkrlih", "pkrlih", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
},
/* pkrliu $rd,$rs,$rt,$bytecount */
{
IQ2000_INSN_PKRLIU, "pkrliu", "pkrliu", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
},
/* pkrlic $rd,$rs,$rt,$bytecount */
{
IQ2000_INSN_PKRLIC, "pkrlic", "pkrlic", 32,
- { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
},
/* pkrla $rd,$rs,$rt */
{
IQ2000_INSN_PKRLA, "pkrla", "pkrla", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* pkrlau $rd,$rs,$rt */
{
IQ2000_INSN_PKRLAU, "pkrlau", "pkrlau", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* pkrlah $rd,$rs,$rt */
{
IQ2000_INSN_PKRLAH, "pkrlah", "pkrlah", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* pkrlac $rd,$rs,$rt */
{
IQ2000_INSN_PKRLAC, "pkrlac", "pkrlac", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* lock $rd,$rt */
{
IQ2000_INSN_LOCK, "lock", "lock", 32,
- { 0|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } }
},
/* unlk $rd,$rt */
{
IQ2000_INSN_UNLK, "unlk", "unlk", 32,
- { 0|A(USES_RD)|A(USES_RT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* swrd $rd,$rt */
{
IQ2000_INSN_SWRD, "swrd", "swrd", 32,
- { 0|A(USES_RD)|A(USES_RT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* swrdl $rd,$rt */
{
IQ2000_INSN_SWRDL, "swrdl", "swrdl", 32,
- { 0|A(USES_RD)|A(USES_RT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* swwr $rd,$rs,$rt */
{
IQ2000_INSN_SWWR, "swwr", "swwr", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* swwru $rd,$rs,$rt */
{
IQ2000_INSN_SWWRU, "swwru", "swwru", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* dwrd $rd,$rt */
{
IQ2000_INSN_DWRD, "dwrd", "dwrd", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
},
/* dwrdl $rd,$rt */
{
IQ2000_INSN_DWRDL, "dwrdl", "dwrdl", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cam36 $rd,$rt,${cam-z},${cam-y} */
{
IQ2000_INSN_CAM36, "cam36", "cam36", 32,
- { 0|A(USES_RD)|A(USES_RT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cam72 $rd,$rt,${cam-y},${cam-z} */
{
IQ2000_INSN_CAM72, "cam72", "cam72", 32,
- { 0|A(USES_RD)|A(USES_RT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cam144 $rd,$rt,${cam-y},${cam-z} */
{
IQ2000_INSN_CAM144, "cam144", "cam144", 32,
- { 0|A(USES_RD)|A(USES_RT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cam288 $rd,$rt,${cam-y},${cam-z} */
{
IQ2000_INSN_CAM288, "cam288", "cam288", 32,
- { 0|A(USES_RD)|A(USES_RT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm32and $rd,$rs,$rt */
{
IQ2000_INSN_CM32AND, "cm32and", "cm32and", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm32andn $rd,$rs,$rt */
{
IQ2000_INSN_CM32ANDN, "cm32andn", "cm32andn", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm32or $rd,$rs,$rt */
{
IQ2000_INSN_CM32OR, "cm32or", "cm32or", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm32ra $rd,$rs,$rt */
{
IQ2000_INSN_CM32RA, "cm32ra", "cm32ra", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm32rd $rd,$rt */
{
IQ2000_INSN_CM32RD, "cm32rd", "cm32rd", 32,
- { 0|A(USES_RD)|A(USES_RT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm32ri $rd,$rt */
{
IQ2000_INSN_CM32RI, "cm32ri", "cm32ri", 32,
- { 0|A(USES_RD)|A(USES_RT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm32rs $rd,$rs,$rt */
{
IQ2000_INSN_CM32RS, "cm32rs", "cm32rs", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm32sa $rd,$rs,$rt */
{
IQ2000_INSN_CM32SA, "cm32sa", "cm32sa", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm32sd $rd,$rt */
{
IQ2000_INSN_CM32SD, "cm32sd", "cm32sd", 32,
- { 0|A(USES_RD)|A(USES_RT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm32si $rd,$rt */
{
IQ2000_INSN_CM32SI, "cm32si", "cm32si", 32,
- { 0|A(USES_RD)|A(USES_RT), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm32ss $rd,$rs,$rt */
{
IQ2000_INSN_CM32SS, "cm32ss", "cm32ss", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm32xor $rd,$rs,$rt */
{
IQ2000_INSN_CM32XOR, "cm32xor", "cm32xor", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm64clr $rd,$rt */
{
IQ2000_INSN_CM64CLR, "cm64clr", "cm64clr", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm64ra $rd,$rs,$rt */
{
IQ2000_INSN_CM64RA, "cm64ra", "cm64ra", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm64rd $rd,$rt */
{
IQ2000_INSN_CM64RD, "cm64rd", "cm64rd", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm64ri $rd,$rt */
{
IQ2000_INSN_CM64RI, "cm64ri", "cm64ri", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm64ria2 $rd,$rs,$rt */
{
IQ2000_INSN_CM64RIA2, "cm64ria2", "cm64ria2", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm64rs $rd,$rs,$rt */
{
IQ2000_INSN_CM64RS, "cm64rs", "cm64rs", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm64sa $rd,$rs,$rt */
{
IQ2000_INSN_CM64SA, "cm64sa", "cm64sa", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm64sd $rd,$rt */
{
IQ2000_INSN_CM64SD, "cm64sd", "cm64sd", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm64si $rd,$rt */
{
IQ2000_INSN_CM64SI, "cm64si", "cm64si", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm64sia2 $rd,$rs,$rt */
{
IQ2000_INSN_CM64SIA2, "cm64sia2", "cm64sia2", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm64ss $rd,$rs,$rt */
{
IQ2000_INSN_CM64SS, "cm64ss", "cm64ss", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm128ria2 $rd,$rs,$rt */
{
IQ2000_INSN_CM128RIA2, "cm128ria2", "cm128ria2", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm128ria3 $rd,$rs,$rt,${cm-3z} */
{
IQ2000_INSN_CM128RIA3, "cm128ria3", "cm128ria3", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm128ria4 $rd,$rs,$rt,${cm-4z} */
{
IQ2000_INSN_CM128RIA4, "cm128ria4", "cm128ria4", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm128sia2 $rd,$rs,$rt */
{
IQ2000_INSN_CM128SIA2, "cm128sia2", "cm128sia2", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm128sia3 $rd,$rs,$rt,${cm-3z} */
{
IQ2000_INSN_CM128SIA3, "cm128sia3", "cm128sia3", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm128sia4 $rd,$rs,$rt,${cm-4z} */
{
IQ2000_INSN_CM128SIA4, "cm128sia4", "cm128sia4", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm128vsa $rd,$rs,$rt */
{
IQ2000_INSN_CM128VSA, "cm128vsa", "cm128vsa", 32,
- { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cfc $rd,$rt */
{
IQ2000_INSN_CFC, "cfc", "cfc", 32,
- { 0|A(YIELD_INSN)|A(USES_RD)|A(LOAD_DELAY), { (1<<MACH_IQ10) } }
+ { 0|A(YIELD_INSN)|A(USES_RD)|A(LOAD_DELAY), { { { (1<<MACH_IQ10), 0 } } } }
},
/* ctc $rs,$rt */
{
IQ2000_INSN_CTC, "ctc", "ctc", 32,
- { 0|A(USES_RS), { (1<<MACH_IQ10) } }
+ { 0|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } }
},
};
@@ -1978,7 +1978,7 @@ static void
iq2000_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
{
int i;
- unsigned int isas = cd->isas;
+ CGEN_BITSET *isas = cd->isas;
unsigned int machs = cd->machs;
cd->int_insn_p = CGEN_INT_INSN_P;
@@ -1990,7 +1990,7 @@ iq2000_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
cd->max_insn_bitsize = 0;
for (i = 0; i < MAX_ISAS; ++i)
- if (((1 << i) & isas) != 0)
+ if (cgen_bitset_contains (isas, i))
{
const CGEN_ISA *isa = & iq2000_cgen_isa_table[i];
@@ -2075,7 +2075,7 @@ iq2000_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
{
CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
static int init_p;
- unsigned int isas = 0; /* 0 = "unspecified" */
+ CGEN_BITSET *isas = 0; /* 0 = "unspecified" */
unsigned int machs = 0; /* 0 = "unspecified" */
enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
va_list ap;
@@ -2094,7 +2094,7 @@ iq2000_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
switch (arg_type)
{
case CGEN_CPU_OPEN_ISAS :
- isas = va_arg (ap, unsigned int);
+ isas = va_arg (ap, CGEN_BITSET *);
break;
case CGEN_CPU_OPEN_MACHS :
machs = va_arg (ap, unsigned int);
@@ -2125,9 +2125,6 @@ iq2000_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
machs = (1 << MAX_MACHS) - 1;
/* Base mach is always selected. */
machs |= 1;
- /* ISA unspecified means "all". */
- if (isas == 0)
- isas = (1 << MAX_ISAS) - 1;
if (endian == CGEN_ENDIAN_UNKNOWN)
{
/* ??? If target has only one, could have a default. */
@@ -2135,7 +2132,7 @@ iq2000_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
abort ();
}
- cd->isas = isas;
+ cd->isas = cgen_bitset_copy (isas);
cd->machs = machs;
cd->endian = endian;
/* FIXME: for the sparc case we can determine insn-endianness statically.
diff --git a/opcodes/iq2000-desc.h b/opcodes/iq2000-desc.h
index cd644a8eb6c..9efdca9952c 100644
--- a/opcodes/iq2000-desc.h
+++ b/opcodes/iq2000-desc.h
@@ -25,6 +25,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#ifndef IQ2000_CPU_H
#define IQ2000_CPU_H
+#include "opcode/cgen-bitset.h"
+
#define CGEN_ARCH iq2000
/* Given symbol S, return iq2000_cgen_<S>. */
@@ -200,6 +202,15 @@ typedef enum cgen_ifld_attr {
/* Number of non-boolean elements in cgen_ifld_attr. */
#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
+/* cgen_ifld attribute accessor macros. */
+#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
+
/* Enum declaration for iq2000 ifield types. */
typedef enum ifield_type {
IQ2000_F_NIL, IQ2000_F_ANYOF, IQ2000_F_OPCODE, IQ2000_F_RS
@@ -227,6 +238,13 @@ typedef enum cgen_hw_attr {
/* Number of non-boolean elements in cgen_hw_attr. */
#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
+/* cgen_hw attribute accessor macros. */
+#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
+#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
+
/* Enum declaration for iq2000 hardware types. */
typedef enum cgen_hw_type {
HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
@@ -247,6 +265,17 @@ typedef enum cgen_operand_attr {
/* Number of non-boolean elements in cgen_operand_attr. */
#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
+/* cgen_operand attribute accessor macros. */
+#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
+
/* Enum declaration for iq2000 operand types. */
typedef enum cgen_operand_type {
IQ2000_OPERAND_PC, IQ2000_OPERAND_RS, IQ2000_OPERAND_RT, IQ2000_OPERAND_RD
@@ -281,6 +310,27 @@ typedef enum cgen_insn_attr {
/* Number of non-boolean elements in cgen_insn_attr. */
#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
+/* cgen_insn attribute accessor macros. */
+#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
+#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
+#define CGEN_ATTR_CGEN_INSN_YIELD_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_YIELD_INSN)) != 0)
+#define CGEN_ATTR_CGEN_INSN_LOAD_DELAY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_LOAD_DELAY)) != 0)
+#define CGEN_ATTR_CGEN_INSN_EVEN_REG_NUM_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_EVEN_REG_NUM)) != 0)
+#define CGEN_ATTR_CGEN_INSN_UNSUPPORTED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNSUPPORTED)) != 0)
+#define CGEN_ATTR_CGEN_INSN_USES_RD_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_RD)) != 0)
+#define CGEN_ATTR_CGEN_INSN_USES_RS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_RS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_USES_RT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_RT)) != 0)
+#define CGEN_ATTR_CGEN_INSN_USES_R31_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_R31)) != 0)
+
/* cgen.h uses things we just defined. */
#include "opcode/cgen.h"
diff --git a/opcodes/iq2000-dis.c b/opcodes/iq2000-dis.c
index 02f535e6d79..b8a7c2edff5 100644
--- a/opcodes/iq2000-dis.c
+++ b/opcodes/iq2000-dis.c
@@ -4,7 +4,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
- Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
+ Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
@@ -497,7 +497,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
typedef struct cpu_desc_list
{
struct cpu_desc_list *next;
- int isa;
+ CGEN_BITSET *isa;
int mach;
int endian;
CGEN_CPU_DESC cd;
@@ -509,11 +509,12 @@ print_insn_iq2000 (bfd_vma pc, disassemble_info *info)
static cpu_desc_list *cd_list = 0;
cpu_desc_list *cl = 0;
static CGEN_CPU_DESC cd = 0;
- static int prev_isa;
+ static CGEN_BITSET *prev_isa;
static int prev_mach;
static int prev_endian;
int length;
- int isa,mach;
+ CGEN_BITSET *isa;
+ int mach;
int endian = (info->endian == BFD_ENDIAN_BIG
? CGEN_ENDIAN_BIG
: CGEN_ENDIAN_LITTLE);
@@ -536,25 +537,34 @@ print_insn_iq2000 (bfd_vma pc, disassemble_info *info)
#endif
#ifdef CGEN_COMPUTE_ISA
- isa = CGEN_COMPUTE_ISA (info);
+ {
+ static CGEN_BITSET *permanent_isa;
+
+ if (!permanent_isa)
+ permanent_isa = cgen_bitset_create (MAX_ISAS);
+ isa = permanent_isa;
+ cgen_bitset_clear (isa);
+ cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
+ }
#else
isa = info->insn_sets;
#endif
/* If we've switched cpu's, try to find a handle we've used before */
if (cd
- && (isa != prev_isa
+ && (cgen_bitset_compare (isa, prev_isa) != 0
|| mach != prev_mach
|| endian != prev_endian))
{
cd = 0;
for (cl = cd_list; cl; cl = cl->next)
{
- if (cl->isa == isa &&
+ if (cgen_bitset_compare (cl->isa, isa) == 0 &&
cl->mach == mach &&
cl->endian == endian)
{
cd = cl->cd;
+ prev_isa = cd->isas;
break;
}
}
@@ -570,7 +580,7 @@ print_insn_iq2000 (bfd_vma pc, disassemble_info *info)
abort ();
mach_name = arch_type->printable_name;
- prev_isa = isa;
+ prev_isa = cgen_bitset_copy (isa);
prev_mach = mach;
prev_endian = endian;
cd = iq2000_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
@@ -583,7 +593,7 @@ print_insn_iq2000 (bfd_vma pc, disassemble_info *info)
/* Save this away for future reference. */
cl = xmalloc (sizeof (struct cpu_desc_list));
cl->cd = cd;
- cl->isa = isa;
+ cl->isa = prev_isa;
cl->mach = mach;
cl->endian = endian;
cl->next = cd_list;
diff --git a/opcodes/iq2000-opc.c b/opcodes/iq2000-opc.c
index 2ea3bf8c323..6f2f257e13d 100644
--- a/opcodes/iq2000-opc.c
+++ b/opcodes/iq2000-opc.c
@@ -2312,472 +2312,472 @@ static const CGEN_IBASE iq2000_cgen_macro_insn_table[] =
/* nop */
{
-1, "nop", "nop", 32,
- { 0|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* li $rs,$imm */
{
-1, "li", "li", 32,
- { 0|A(NO_DIS)|A(USES_RS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(NO_DIS)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* move $rd,$rt */
{
-1, "move", "move", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(USES_RD)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(USES_RD)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* lb $rt,$lo16 */
{
-1, "lb-base-0", "lb", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* lbu $rt,$lo16 */
{
-1, "lbu-base-0", "lbu", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* lh $rt,$lo16 */
{
-1, "lh-base-0", "lh", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* lw $rt,$lo16 */
{
-1, "lw-base-0", "lw", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* add $rt,$rs,$lo16 */
{
-1, "m-add", "add", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* addu $rt,$rs,$lo16 */
{
-1, "m-addu", "addu", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* and $rt,$rs,$lo16 */
{
-1, "m-and", "and", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* j $rs */
{
-1, "m-j", "j", 32,
- { 0|A(NO_DIS)|A(USES_RS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(NO_DIS)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* or $rt,$rs,$lo16 */
{
-1, "m-or", "or", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* sll $rd,$rt,$rs */
{
-1, "m-sll", "sll", 32,
- { 0|A(NO_DIS)|A(USES_RS)|A(USES_RT)|A(USES_RD)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(NO_DIS)|A(USES_RS)|A(USES_RT)|A(USES_RD)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* slt $rt,$rs,$imm */
{
-1, "m-slt", "slt", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* sltu $rt,$rs,$imm */
{
-1, "m-sltu", "sltu", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* sra $rd,$rt,$rs */
{
-1, "m-sra", "sra", 32,
- { 0|A(NO_DIS)|A(USES_RS)|A(USES_RT)|A(USES_RD)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(NO_DIS)|A(USES_RS)|A(USES_RT)|A(USES_RD)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* srl $rd,$rt,$rs */
{
-1, "m-srl", "srl", 32,
- { 0|A(NO_DIS)|A(USES_RS)|A(USES_RT)|A(USES_RD)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(NO_DIS)|A(USES_RS)|A(USES_RT)|A(USES_RD)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* not $rd,$rt */
{
-1, "not", "not", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(USES_RD)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(USES_RD)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* subi $rt,$rs,$mlo16 */
{
-1, "subi", "subi", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* sub $rt,$rs,$mlo16 */
{
-1, "m-sub", "sub", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* subu $rt,$rs,$mlo16 */
{
-1, "m-subu", "subu", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* sb $rt,$lo16 */
{
-1, "sb-base-0", "sb", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* sh $rt,$lo16 */
{
-1, "sh-base-0", "sh", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* sw $rt,$lo16 */
{
-1, "sw-base-0", "sw", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* xor $rt,$rs,$lo16 */
{
-1, "m-xor", "xor", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_BASE) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
},
/* ldw $rt,$lo16 */
{
-1, "ldw-base-0", "ldw", 32,
- { 0|A(NO_DIS)|A(USES_RS)|A(USES_RT)|A(LOAD_DELAY)|A(EVEN_REG_NUM)|A(ALIAS), { (1<<MACH_IQ2000) } }
+ { 0|A(NO_DIS)|A(USES_RS)|A(USES_RT)|A(LOAD_DELAY)|A(EVEN_REG_NUM)|A(ALIAS), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* sdw $rt,$lo16 */
{
-1, "sdw-base-0", "sdw", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(EVEN_REG_NUM)|A(ALIAS), { (1<<MACH_IQ2000) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(EVEN_REG_NUM)|A(ALIAS), { { { (1<<MACH_IQ2000), 0 } } } }
},
/* avail */
{
-1, "m-avail", "avail", 32,
- { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cam36 $rd,$rt,${cam-z} */
{
-1, "m-cam36", "cam36", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cam72 $rd,$rt,${cam-z} */
{
-1, "m-cam72", "cam72", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cam144 $rd,$rt,${cam-z} */
{
-1, "m-cam144", "cam144", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cam288 $rd,$rt,${cam-z} */
{
-1, "m-cam288", "cam288", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm32read $rd,$rt */
{
-1, "m-cm32read", "cm32read", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm64read $rd,$rt */
{
-1, "m-cm64read", "cm64read", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm32mlog $rs,$rt */
{
-1, "m-cm32mlog", "cm32mlog", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm32and $rs,$rt */
{
-1, "m-cm32and", "cm32and", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm32andn $rs,$rt */
{
-1, "m-cm32andn", "cm32andn", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm32or $rs,$rt */
{
-1, "m-cm32or", "cm32or", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm32ra $rs,$rt */
{
-1, "m-cm32ra", "cm32ra", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm32rd $rt */
{
-1, "m-cm32rd", "cm32rd", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm32ri $rt */
{
-1, "m-cm32ri", "cm32ri", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm32rs $rs,$rt */
{
-1, "m-cm32rs", "cm32rs", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm32sa $rs,$rt */
{
-1, "m-cm32sa", "cm32sa", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm32sd $rt */
{
-1, "m-cm32sd", "cm32sd", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm32si $rt */
{
-1, "m-cm32si", "cm32si", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm32ss $rs,$rt */
{
-1, "m-cm32ss", "cm32ss", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm32xor $rs,$rt */
{
-1, "m-cm32xor", "cm32xor", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm64clr $rt */
{
-1, "m-cm64clr", "cm64clr", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm64ra $rs,$rt */
{
-1, "m-cm64ra", "cm64ra", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm64rd $rt */
{
-1, "m-cm64rd", "cm64rd", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm64ri $rt */
{
-1, "m-cm64ri", "cm64ri", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm64ria2 $rs,$rt */
{
-1, "m-cm64ria2", "cm64ria2", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm64rs $rs,$rt */
{
-1, "m-cm64rs", "cm64rs", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm64sa $rs,$rt */
{
-1, "m-cm64sa", "cm64sa", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm64sd $rt */
{
-1, "m-cm64sd", "cm64sd", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm64si $rt */
{
-1, "m-cm64si", "cm64si", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm64sia2 $rs,$rt */
{
-1, "m-cm64sia2", "cm64sia2", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm64ss $rs,$rt */
{
-1, "m-cm64ss", "cm64ss", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm128ria2 $rs,$rt */
{
-1, "m-cm128ria2", "cm128ria2", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm128ria3 $rs,$rt,${cm-3z} */
{
-1, "m-cm128ria3", "cm128ria3", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm128ria4 $rs,$rt,${cm-4z} */
{
-1, "m-cm128ria4", "cm128ria4", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm128sia2 $rs,$rt */
{
-1, "m-cm128sia2", "cm128sia2", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm128sia3 $rs,$rt,${cm-3z} */
{
-1, "m-cm128sia3", "cm128sia3", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cm128sia4 $rs,$rt,${cm-4z} */
{
-1, "m-cm128sia4", "cm128sia4", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* cmphdr */
{
-1, "m-cmphdr", "cmphdr", 32,
- { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* dbd $rd,$rt */
{
-1, "m-dbd", "dbd", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(USES_RD)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(USES_RD)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* dbd $rt */
{
-1, "m2-dbd", "dbd", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* dpwt $rs */
{
-1, "m-dpwt", "dpwt", 32,
- { 0|A(NO_DIS)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* free $rs */
{
-1, "m-free", "free", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* lock $rt */
{
-1, "m-lock", "lock", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* pkrla $rs,$rt */
{
-1, "m-pkrla", "pkrla", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* pkrlac $rs,$rt */
{
-1, "m-pkrlac", "pkrlac", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* pkrlah $rs,$rt */
{
-1, "m-pkrlah", "pkrlah", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* pkrlau $rs,$rt */
{
-1, "m-pkrlau", "pkrlau", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* pkrli $rs,$rt,$bytecount */
{
-1, "m-pkrli", "pkrli", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* pkrlic $rs,$rt,$bytecount */
{
-1, "m-pkrlic", "pkrlic", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* pkrlih $rs,$rt,$bytecount */
{
-1, "m-pkrlih", "pkrlih", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* pkrliu $rs,$rt,$bytecount */
{
-1, "m-pkrliu", "pkrliu", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* rba $rs,$rt */
{
-1, "m-rba", "rba", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* rbal $rs,$rt */
{
-1, "m-rbal", "rbal", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* rbar $rs,$rt */
{
-1, "m-rbar", "rbar", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* rbi $rs,$rt,$bytecount */
{
-1, "m-rbi", "rbi", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* rbil $rs,$rt,$bytecount */
{
-1, "m-rbil", "rbil", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* rbir $rs,$rt,$bytecount */
{
-1, "m-rbir", "rbir", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* swwr $rs,$rt */
{
-1, "m-swwr", "swwr", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* swwru $rs,$rt */
{
-1, "m-swwru", "swwru", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* tstod $rs */
{
-1, "m-tstod", "tstod", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* unlk $rt */
{
-1, "m-unlk", "unlk", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* wba $rs,$rt */
{
-1, "m-wba", "wba", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* wbac $rs,$rt */
{
-1, "m-wbac", "wbac", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* wbau $rs,$rt */
{
-1, "m-wbau", "wbau", 32,
- { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* wbi $rs,$rt,$bytecount */
{
-1, "m-wbi", "wbi", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* wbic $rs,$rt,$bytecount */
{
-1, "m-wbic", "wbic", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
/* wbiu $rs,$rt,$bytecount */
{
-1, "m-wbiu", "wbiu", 32,
- { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(ALIAS), { (1<<MACH_IQ10) } }
+ { 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
},
};
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