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author | Stephane Carrez <stcarrez@nerim.fr> | 2003-03-01 16:00:09 +0000 |
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committer | Stephane Carrez <stcarrez@nerim.fr> | 2003-03-01 16:00:09 +0000 |
commit | 3fa05c0606e80cb13f9c7343cbef0179b382391e (patch) | |
tree | 42b865fec29e27b469d99f4de7bbb1f5f206b0f0 | |
parent | 0f62f80e2abe002c9856e24541f0fb6839ced9d2 (diff) | |
download | gdb-3fa05c0606e80cb13f9c7343cbef0179b382391e.tar.gz |
* interp.c (sim_fetch_register): Only store a single byte for
1 byte registers.
-rw-r--r-- | sim/m68hc11/ChangeLog | 5 | ||||
-rw-r--r-- | sim/m68hc11/interp.c | 11 |
2 files changed, 14 insertions, 2 deletions
diff --git a/sim/m68hc11/ChangeLog b/sim/m68hc11/ChangeLog index 325b8874a7c..21957ef7791 100644 --- a/sim/m68hc11/ChangeLog +++ b/sim/m68hc11/ChangeLog @@ -1,3 +1,8 @@ +2003-03-01 Stephane Carrez <stcarrez@nerim.fr> + + * interp.c (sim_fetch_register): Only store a single byte for + 1 byte registers. + 2003-02-27 Andrew Cagney <cagney@redhat.com> * interp.c (sim_prepare_for_program, sim_open) diff --git a/sim/m68hc11/interp.c b/sim/m68hc11/interp.c index 8a60606223a..3da382d88ad 100644 --- a/sim/m68hc11/interp.c +++ b/sim/m68hc11/interp.c @@ -554,8 +554,15 @@ sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length) val = 0; break; } - memory[0] = val >> 8; - memory[1] = val & 0x0FF; + if (size == 1) + { + memory[0] = val; + } + else + { + memory[0] = val >> 8; + memory[1] = val & 0x0FF; + } return size; } |