diff options
author | Daniel Jacobowitz <dan@debian.org> | 2005-03-28 15:30:09 +0000 |
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committer | Daniel Jacobowitz <dan@debian.org> | 2005-03-28 15:30:09 +0000 |
commit | ab79d506645b787042f9f2d4d48de7e0d11f21d1 (patch) | |
tree | 8de0edd178f54cc1d55bb7f74dc63334781d78bf | |
parent | 4702a83ea8c26bfbbd80eab3479856d05f52d5f9 (diff) | |
download | gdb-ab79d506645b787042f9f2d4d48de7e0d11f21d1.tar.gz |
Backport ARM patches from HEAD to binutils-csl-arm-2005q1-branch.
-rw-r--r-- | ChangeLog.csl | 58 | ||||
-rw-r--r-- | include/opcode/arm.h | 9 | ||||
-rw-r--r-- | opcodes/arm-dis.c | 54 | ||||
-rw-r--r-- | opcodes/po/es.gmo | bin | 16621 -> 16747 bytes | |||
-rw-r--r-- | opcodes/po/fr.gmo | bin | 16283 -> 16408 bytes |
5 files changed, 118 insertions, 3 deletions
diff --git a/ChangeLog.csl b/ChangeLog.csl new file mode 100644 index 00000000000..daecaa72846 --- /dev/null +++ b/ChangeLog.csl @@ -0,0 +1,58 @@ +2005-03-23 Jim Blandy <jimb@redhat.com> + + * config/tc-arm.c (arm_adjust_symtab): Fetch elf_sym's binding + attributes properly. + +2005-03-21 Nick Clifton <nickc@redhat.com> + + * gas/testsuite/gas/arm/iwmmxt.s: Update instructions that use the "never" value + in the conditional field to use "le" instead. This is so that the + disassembler will disassemble them. + * gas/testsuite/gas/arm/iwmmxt.d: Update expected disassemblies. + +2005-03-18 Julian Brown <julian@codesourcery.com> + + * ld/scripttempl/armbpapi.sc (.rel.dyn): Add .rel.init_array, + .rel.fini_array. + (.rela.dyn): Add .rela.init_array, .rela.fini_array. + (SECTIONS): Add .rel.other, .rela.other, .reli.other after PLT relocs. + +2005-03-16 Daniel Jacobowitz <dan@codesourcery.com> + + * gas/configure.tgt: Set emulation for arm-*-eabi*. + * gas/config/tc-arm.c (meabi_flags): Check EABI_DEFAULT. + * gas/config/te-armeabi.h: New file. + * gas/config/te-armlinuxeabi.h (EABI_DEFAULT): Define. + * gas/config/te-symbian.h: Include "te-armeabi.h". + +2005-03-15 Zack Weinberg <zack@codesourcery.com> + + * gas/config/tc-arm.c (do_mla): Rename to do_mlas, take second + is_mls parameter; do not diagnose Rm==Rd when is_mls. + (do_mla, do_mls, five_bit_unsigned_immediate, bfci_lsb_and_width) + (do_bfc, do_bfi, do_bfx, do_rbit, do_mov16, do_ldsttv4): New functions. + (insns): Add ARMv6T2 instructions: + bfc bfi mls movw movt rbit sbfx ubfx ldrht ldrsht ldrsbt strht. + (arm_archs): Add V6T2 variants. + +2005-03-12 Zack Weinberg <zack@codesourcery.com> + + * gas/config/tc-arm.c (tinsns): Add ARMv6K instructions sev, wfe, + wfi, yield. + + * opcodes/arm-dis.c (thumb_opcodes): Add ARMv6K instructions nop, sev, + wfe, wfi, yield. + + * gas/testsuite/gas/arm/thumbv6k.d, gas/arm/thumbv6k.s: New dump test. + * gas/testsuite/gas/arm/arm.exp: Run it. + +2005-03-12 Zack Weinberg <zack@codesourcery.com> + + * opcodes/arm-dis.c (arm_opcodes): Document %E and %V. + Add entries for v6T2 ARM instructions: + bfc bfi mls strht ldrht ldrsht ldrsbt movw movt rbit ubfx sbfx. + (print_insn_arm): Add support for %E and %V. + + * include/opcode/arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T. + Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, + and ARM_ARCH_V6ZKT2. diff --git a/include/opcode/arm.h b/include/opcode/arm.h index dd90e2ac669..db3666591e5 100644 --- a/include/opcode/arm.h +++ b/include/opcode/arm.h @@ -25,15 +25,16 @@ #define ARM_EXT_V3 0x00000008 /* MSR MRS. */ #define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */ #define ARM_EXT_V4 0x00000020 /* Allow half word loads. */ -#define ARM_EXT_V4T 0x00000040 /* Thumb v1. */ +#define ARM_EXT_V4T 0x00000040 /* Thumb. */ #define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */ -#define ARM_EXT_V5T 0x00000100 /* Thumb v2. */ +#define ARM_EXT_V5T 0x00000100 /* Improved interworking. */ #define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */ #define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */ #define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */ #define ARM_EXT_V6 0x00001000 /* ARM V6. */ #define ARM_EXT_V6K 0x00002000 /* ARM V6K. */ #define ARM_EXT_V6Z 0x00004000 /* ARM V6Z. */ +#define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */ /* Co-processor space extensions. */ #define ARM_CEXT_XSCALE 0x00800000 /* Allow MIA etc. */ @@ -65,6 +66,10 @@ #define ARM_ARCH_V6K (ARM_ARCH_V6 | ARM_EXT_V6K) #define ARM_ARCH_V6Z (ARM_ARCH_V6 | ARM_EXT_V6Z) #define ARM_ARCH_V6ZK (ARM_ARCH_V6 | ARM_EXT_V6K | ARM_EXT_V6Z) +#define ARM_ARCH_V6T2 (ARM_ARCH_V6 | ARM_EXT_V6T2) +#define ARM_ARCH_V6KT2 (ARM_ARCH_V6 | ARM_EXT_V6T2 | ARM_EXT_V6K) +#define ARM_ARCH_V6ZT2 (ARM_ARCH_V6 | ARM_EXT_V6T2 | ARM_EXT_V6Z) +#define ARM_ARCH_V6ZKT2 (ARM_ARCH_V6 | ARM_EXT_V6T2 | ARM_EXT_V6K | ARM_EXT_V6Z) /* Processors with specific extensions in the co-processor space. */ #define ARM_ARCH_XSCALE (ARM_ARCH_V5TE | ARM_CEXT_XSCALE) diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 5388bd1c3d2..a87bcc0b2f8 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -81,6 +81,8 @@ %m print register mask for ldm/stm instruction %C print the PSR sub type. %F print the COUNT field of a LFM/SFM instruction. + %E print the LSB and WIDTH fields of a BFI or BFC instruction. + %V print the 16-bit immediate field of a MOVT or MOVW instruction. IWMMXT specific format options: %<bitfield>g print as an iWMMXt 64-bit register %<bitfield>G print as an iWMMXt general purpose or control register @@ -118,6 +120,17 @@ static const struct arm_opcode arm_opcodes[] = {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, + /* ARM V6T2 instructions. */ + {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15r, %E"}, + {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15r, %0-3r, %E"}, + {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "str%cht\t%12-15r, %s"}, + {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%c%6's%5?hbt\t%12-15r, %s"}, + {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15r, %V"}, + {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15r, %V"}, + {ARM_EXT_V6T2, 0x03ff0f30, 0x0fff0ff0, "rbit%c\t%12-15r, %0-3r"}, + {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"}, + /* ARM V6Z instructions. */ {ARM_EXT_V6Z, 0x01600070, 0x0ff000f0, "smi%c\t%e"}, @@ -622,6 +635,13 @@ static const struct thumb_opcode thumb_opcodes[] = { /* Thumb instructions. */ + /* ARM V6K no-argument instructions. */ + {ARM_EXT_V6K, 0xbf00, 0xffff, "nop"}, + {ARM_EXT_V6K, 0xbf10, 0xffff, "yield"}, + {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe"}, + {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi"}, + {ARM_EXT_V6K, 0xbf40, 0xffff, "sev"}, + /* ARM V6. */ {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f"}, {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f"}, @@ -929,7 +949,13 @@ print_insn_arm (pc, info, given) && info->mach != bfd_mach_arm_iWMMXt) insn = insn + IWMMXT_INSN_COUNT; - if ((given & insn->mask) == insn->value) + if ((given & insn->mask) == insn->value + /* Special case: an instruction with all bits set in the condition field + (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask, + or by the catchall at the end of the table. */ + && ((given & 0xF0000000) != 0xF0000000 + || (insn->mask & 0xF0000000) == 0xF0000000 + || (insn->mask == 0 && insn->value == 0))) { char * c; @@ -1613,6 +1639,32 @@ print_insn_arm (pc, info, given) } break; + case 'E': + /* LSB and WIDTH fields of BFI or BFC. The machine- + language instruction encodes LSB and MSB. */ + { + long msb = (given & 0x001f0000) >> 16; + long lsb = (given & 0x00000f80) >> 7; + + long width = msb - lsb + 1; + if (width > 0) + func (stream, "#%lu, #%lu", lsb, width); + else + func (stream, "(invalid: %lu:%lu)", lsb, msb); + } + break; + + case 'V': + /* 16-bit unsigned immediate from a MOVT or MOVW + instruction, encoded in bits 0:11 and 15:19. */ + { + long hi = (given & 0x000f0000) >> 4; + long lo = (given & 0x00000fff); + long imm16 = hi | lo; + func (stream, "#%lu\t; 0x%lx", imm16, imm16); + } + break; + default: abort (); } diff --git a/opcodes/po/es.gmo b/opcodes/po/es.gmo Binary files differindex 8382c264ea7..b4084c506d7 100644 --- a/opcodes/po/es.gmo +++ b/opcodes/po/es.gmo diff --git a/opcodes/po/fr.gmo b/opcodes/po/fr.gmo Binary files differindex 20c70127178..47a17c62c28 100644 --- a/opcodes/po/fr.gmo +++ b/opcodes/po/fr.gmo |