diff options
| author | Markus Deuling <deuling@de.ibm.com> | 2007-11-19 05:06:24 +0000 |
|---|---|---|
| committer | Markus Deuling <deuling@de.ibm.com> | 2007-11-19 05:06:24 +0000 |
| commit | 491c0a0433791f6eb9317450f2be2a5be330c64c (patch) | |
| tree | 3be78bb03a4436b3cbca742d8a84a4d651733a1b /gdb/frv-tdep.c | |
| parent | 63e96df41108df00cce03eed8bd27c08a28b0a49 (diff) | |
| download | gdb-491c0a0433791f6eb9317450f2be2a5be330c64c.tar.gz | |
2007-11-19 Markus Deuling <deuling@de.ibm.com>
* gdbarch.sh (register_sim_regno): Add gdbarch as parameter.
* gdbarch.{c,h}: Regenerate.
* arch-utils.h (legacy_register_sim_regno): Add gdbarch as parameter.
* score-tdep.c (score_register_sim_regno): Likewise.
* sim-regno.h (one2one_register_sim_regno): Likewise.
* arch-utils.c (legacy_register_sim_regno): Add gdbarch as parameter.
Replace current_gdbarch by gdbarch.
* sh-tdep.c (sh_sh2a_register_sim_regno)
(sh_dsp_register_sim_regno): Likewise.
* rs6000-tdep.c (rs6000_register_sim_regno): Likewise.
* mips-tdep.c (mips_register_sim_regno): Likewise.
* m32c-tdep.c (m32c_register_sim_regno): Likewise.
* frv-tdep.c (frv_register_sim_regno): Likewise.
* arm-tdep.c (arm_register_sim_regno): Likewise.
* remote-sim.c (one2one_register_sim_regno): Likewise.
Diffstat (limited to 'gdb/frv-tdep.c')
| -rw-r--r-- | gdb/frv-tdep.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gdb/frv-tdep.c b/gdb/frv-tdep.c index 6f49f0a551d..a4dced12ae5 100644 --- a/gdb/frv-tdep.c +++ b/gdb/frv-tdep.c @@ -349,7 +349,7 @@ frv_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, } static int -frv_register_sim_regno (int reg) +frv_register_sim_regno (struct gdbarch *gdbarch, int reg) { static const int spr_map[] = { @@ -393,7 +393,7 @@ frv_register_sim_regno (int reg) H_SPR_FNER1, /* fner1_regnum */ }; - gdb_assert (reg >= 0 && reg < gdbarch_num_regs (current_gdbarch)); + gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch)); if (first_gpr_regnum <= reg && reg <= last_gpr_regnum) return reg - first_gpr_regnum + SIM_FRV_GR0_REGNUM; |