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authorAndrew Cagney <cagney@redhat.com>2004-01-17 16:27:30 +0000
committerAndrew Cagney <cagney@redhat.com>2004-01-17 16:27:30 +0000
commitc98474a8b613c550245dc1797e26fd8f3a447c18 (patch)
tree366ac70a38cab321add8b9fce480986adb848fe6 /gdb/mips-tdep.c
parentcd6b9fef449c3f908024de104932fb12e85088aa (diff)
downloadgdb-c98474a8b613c550245dc1797e26fd8f3a447c18.tar.gz
2004-01-17 Andrew Cagney <cagney@redhat.com>
* mips-tdep.c: Re-indent. Group functions by ABI.
Diffstat (limited to 'gdb/mips-tdep.c')
-rw-r--r--gdb/mips-tdep.c2000
1 files changed, 986 insertions, 1014 deletions
diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c
index fa78a1ac9c2..fe2aef739ff 100644
--- a/gdb/mips-tdep.c
+++ b/gdb/mips-tdep.c
@@ -81,10 +81,10 @@ static const char *mips_abi_strings[] = {
};
struct frame_extra_info
- {
- mips_extra_func_info_t proc_desc;
- int num_args;
- };
+{
+ mips_extra_func_info_t proc_desc;
+ int num_args;
+};
/* Various MIPS ISA options (related to stack analysis) can be
overridden dynamically. Establish an enum/array for managing
@@ -106,11 +106,11 @@ static const char *size_enums[] = {
FP_REGISTER_DOUBLE. */
enum mips_fpu_type
- {
- MIPS_FPU_DOUBLE, /* Full double precision floating point. */
- MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
- MIPS_FPU_NONE /* No floating point. */
- };
+{
+ MIPS_FPU_DOUBLE, /* Full double precision floating point. */
+ MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
+ MIPS_FPU_NONE /* No floating point. */
+};
#ifndef MIPS_DEFAULT_FPU_TYPE
#define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
@@ -122,30 +122,30 @@ static int mips_debug = 0;
/* MIPS specific per-architecture information */
struct gdbarch_tdep
- {
- /* from the elf header */
- int elf_flags;
-
- /* mips options */
- enum mips_abi mips_abi;
- enum mips_abi found_abi;
- enum mips_fpu_type mips_fpu_type;
- int mips_last_arg_regnum;
- int mips_last_fp_arg_regnum;
- int mips_default_saved_regsize;
- int mips_fp_register_double;
- int mips_default_stack_argsize;
- int default_mask_address_p;
- /* Is the target using 64-bit raw integer registers but only
- storing a left-aligned 32-bit value in each? */
- int mips64_transfers_32bit_regs_p;
- /* Indexes for various registers. IRIX and embedded have
- different values. This contains the "public" fields. Don't
- add any that do not need to be public. */
- const struct mips_regnum *regnum;
- /* Register names table for the current register set. */
- const char **mips_processor_reg_names;
- };
+{
+ /* from the elf header */
+ int elf_flags;
+
+ /* mips options */
+ enum mips_abi mips_abi;
+ enum mips_abi found_abi;
+ enum mips_fpu_type mips_fpu_type;
+ int mips_last_arg_regnum;
+ int mips_last_fp_arg_regnum;
+ int mips_default_saved_regsize;
+ int mips_fp_register_double;
+ int mips_default_stack_argsize;
+ int default_mask_address_p;
+ /* Is the target using 64-bit raw integer registers but only
+ storing a left-aligned 32-bit value in each? */
+ int mips64_transfers_32bit_regs_p;
+ /* Indexes for various registers. IRIX and embedded have
+ different values. This contains the "public" fields. Don't
+ add any that do not need to be public. */
+ const struct mips_regnum *regnum;
+ /* Register names table for the current register set. */
+ const char **mips_processor_reg_names;
+};
const struct mips_regnum *
mips_regnum (struct gdbarch *gdbarch)
@@ -196,7 +196,8 @@ read_signed_register (int regnum)
{
void *buf = alloca (register_size (current_gdbarch, regnum));
deprecated_read_register_gen (regnum, buf);
- return (extract_signed_integer (buf, register_size (current_gdbarch, regnum)));
+ return (extract_signed_integer
+ (buf, register_size (current_gdbarch, regnum)));
}
static LONGEST
@@ -244,7 +245,7 @@ mips_saved_regsize (struct gdbarch_tdep *tdep)
return tdep->mips_default_saved_regsize;
else if (mips_saved_regsize_string == size_64)
return 8;
- else /* if (mips_saved_regsize_string == size_32) */
+ else /* if (mips_saved_regsize_string == size_32) */
return 4;
}
@@ -259,14 +260,14 @@ mips_saved_regsize (struct gdbarch_tdep *tdep)
MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
static void
-mips_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
-{
- if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16)
- {
- MSYMBOL_INFO (msym) = (char *)
- (((long) MSYMBOL_INFO (msym)) | 0x80000000);
- SYMBOL_VALUE_ADDRESS (msym) |= 1;
- }
+mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym)
+{
+ if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16)
+ {
+ MSYMBOL_INFO (msym) = (char *)
+ (((long) MSYMBOL_INFO (msym)) | 0x80000000);
+ SYMBOL_VALUE_ADDRESS (msym) |= 1;
+ }
}
static int
@@ -282,8 +283,8 @@ msymbol_is_special (struct minimal_symbol *msym)
static void
mips_xfer_register (struct regcache *regcache, int reg_num, int length,
- enum bfd_endian endian, bfd_byte *in, const bfd_byte *out,
- int buf_offset)
+ enum bfd_endian endian, bfd_byte * in,
+ const bfd_byte * out, int buf_offset)
{
bfd_byte reg[MAX_REGISTER_SIZE];
int reg_offset = 0;
@@ -298,7 +299,7 @@ mips_xfer_register (struct regcache *regcache, int reg_num, int length,
case BFD_ENDIAN_LITTLE:
reg_offset = 0;
break;
- case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */
+ case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */
reg_offset = 0;
break;
default:
@@ -316,9 +317,11 @@ mips_xfer_register (struct regcache *regcache, int reg_num, int length,
fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]);
}
if (in != NULL)
- regcache_cooked_read_part (regcache, reg_num, reg_offset, length, in + buf_offset);
+ regcache_cooked_read_part (regcache, reg_num, reg_offset, length,
+ in + buf_offset);
if (out != NULL)
- regcache_cooked_write_part (regcache, reg_num, reg_offset, length, out + buf_offset);
+ regcache_cooked_write_part (regcache, reg_num, reg_offset, length,
+ out + buf_offset);
if (mips_debug && in != NULL)
{
int i;
@@ -339,7 +342,8 @@ mips2_fp_compat (void)
{
/* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
meaningful. */
- if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == 4)
+ if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) ==
+ 4)
return 0;
#if 0
@@ -373,7 +377,7 @@ mips_stack_argsize (struct gdbarch_tdep *tdep)
return tdep->mips_default_stack_argsize;
else if (mips_stack_argsize_string == size_64)
return 8;
- else /* if (mips_stack_argsize_string == size_32) */
+ else /* if (mips_stack_argsize_string == size_32) */
return 4;
}
@@ -407,54 +411,55 @@ static struct cmd_list_element *showmipscmdlist = NULL;
mips_register_name(). Processor specific registers 32 and above
are listed in the followign tables. */
-enum { NUM_MIPS_PROCESSOR_REGS = (90 - 32) };
+enum
+{ NUM_MIPS_PROCESSOR_REGS = (90 - 32) };
/* Generic MIPS. */
static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
- "sr", "lo", "hi", "bad", "cause","pc",
- "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
- "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
- "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
- "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
- "fsr", "fir", ""/*"fp"*/, "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
+ "sr", "lo", "hi", "bad", "cause", "pc",
+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
+ "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
+ "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+ "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
+ "fsr", "fir", "" /*"fp" */ , "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
};
/* Names of IDT R3041 registers. */
static const char *mips_r3041_reg_names[] = {
- "sr", "lo", "hi", "bad", "cause","pc",
- "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
- "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
- "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
- "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
- "fsr", "fir", "",/*"fp"*/ "",
- "", "", "bus", "ccfg", "", "", "", "",
- "", "", "port", "cmp", "", "", "epc", "prid",
+ "sr", "lo", "hi", "bad", "cause", "pc",
+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
+ "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
+ "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+ "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
+ "fsr", "fir", "", /*"fp" */ "",
+ "", "", "bus", "ccfg", "", "", "", "",
+ "", "", "port", "cmp", "", "", "epc", "prid",
};
/* Names of tx39 registers. */
static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
- "sr", "lo", "hi", "bad", "cause","pc",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "config", "cache", "debug", "depc", "epc", ""
+ "sr", "lo", "hi", "bad", "cause", "pc",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "config", "cache", "debug", "depc", "epc", ""
};
/* Names of IRIX registers. */
static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
- "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
- "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
- "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
- "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
- "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
+ "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
+ "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+ "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
+ "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
};
@@ -465,18 +470,18 @@ mips_register_name (int regno)
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
/* GPR names for all ABIs other than n32/n64. */
static char *mips_gpr_names[] = {
- "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
- "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
- "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
- "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
+ "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
+ "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
+ "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
+ "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
};
/* GPR names for n32 and n64 ABIs. */
static char *mips_n32_n64_gpr_names[] = {
- "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
- "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
- "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
- "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
+ "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
+ "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
+ "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
+ "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
};
enum mips_abi abi = mips_abi (current_gdbarch);
@@ -525,8 +530,7 @@ mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
/* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
(gdbarch), as not all architectures are multi-arch. */
raw_p = rawnum < NUM_REGS;
- if (REGISTER_NAME (regnum) == NULL
- || REGISTER_NAME (regnum)[0] == '\0')
+ if (REGISTER_NAME (regnum) == NULL || REGISTER_NAME (regnum)[0] == '\0')
return 0;
if (reggroup == float_reggroup)
return float_p && pseudo;
@@ -542,7 +546,7 @@ mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
/* Restore the same pseudo register. */
if (reggroup == restore_reggroup)
return raw_p && pseudo;
- return 0;
+ return 0;
}
/* Map the symbol table registers which live in the range [1 *
@@ -557,7 +561,8 @@ mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS);
if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
regcache_raw_read (regcache, rawnum, buf);
- else if (register_size (gdbarch, rawnum) > register_size (gdbarch, cookednum))
+ else if (register_size (gdbarch, rawnum) >
+ register_size (gdbarch, cookednum))
{
if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
|| TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
@@ -570,14 +575,16 @@ mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
}
static void
-mips_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
- int cookednum, const void *buf)
+mips_pseudo_register_write (struct gdbarch *gdbarch,
+ struct regcache *regcache, int cookednum,
+ const void *buf)
{
int rawnum = cookednum % NUM_REGS;
gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS);
if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
regcache_raw_write (regcache, rawnum, buf);
- else if (register_size (gdbarch, rawnum) > register_size (gdbarch, cookednum))
+ else if (register_size (gdbarch, rawnum) >
+ register_size (gdbarch, cookednum))
{
if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
|| TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
@@ -590,8 +597,7 @@ mips_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
}
/* Table to translate MIPS16 register field to actual register number. */
-static int mips16_to_32_reg[8] =
-{16, 17, 2, 3, 4, 5, 6, 7};
+static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
/* Heuristic_proc_start may hunt through the text section for a long
time across a 2400 baud serial line. Allows the user to limit this
@@ -617,10 +623,10 @@ static unsigned int heuristic_fence_post = 0;
#define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
struct linked_proc_info
- {
- struct mips_extra_func_info info;
- struct linked_proc_info *next;
- }
+{
+ struct mips_extra_func_info info;
+ struct linked_proc_info *next;
+}
*linked_proc_desc_table = NULL;
/* Number of bytes of storage in the actual machine representation for
@@ -654,8 +660,7 @@ mips_convert_register_p (int regnum, struct type *type)
&& register_size (current_gdbarch, regnum) == 4
&& (regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0
&& (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32
- && TYPE_CODE(type) == TYPE_CODE_FLT
- && TYPE_LENGTH(type) == 8);
+ && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8);
}
static void
@@ -703,7 +708,8 @@ mips_register_type (struct gdbarch *gdbarch, int regnum)
internal_error (__FILE__, __LINE__, "bad switch");
}
}
- else if (regnum >= (NUM_REGS + mips_regnum (current_gdbarch)->fp_control_status)
+ else if (regnum >=
+ (NUM_REGS + mips_regnum (current_gdbarch)->fp_control_status)
&& regnum <= NUM_REGS + LAST_EMBED_REGNUM)
/* The pseudo/cooked view of the embedded registers is always
32-bit. The raw view is handled below. */
@@ -746,8 +752,7 @@ mips_mask_address_p (struct gdbarch_tdep *tdep)
case AUTO_BOOLEAN_AUTO:
return tdep->default_mask_address_p;
default:
- internal_error (__FILE__, __LINE__,
- "mips_mask_address_p: bad switch");
+ internal_error (__FILE__, __LINE__, "mips_mask_address_p: bad switch");
return -1;
}
}
@@ -765,42 +770,16 @@ show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c)
printf_filtered ("The 32 bit mips address mask is disabled\n");
break;
case AUTO_BOOLEAN_AUTO:
- printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
- mips_mask_address_p (tdep) ? "enabled" : "disabled");
+ printf_filtered
+ ("The 32 bit address mask is set automatically. Currently %s\n",
+ mips_mask_address_p (tdep) ? "enabled" : "disabled");
break;
default:
- internal_error (__FILE__, __LINE__,
- "show_mask_address: bad switch");
+ internal_error (__FILE__, __LINE__, "show_mask_address: bad switch");
break;
}
}
-/* Should call_function allocate stack space for a struct return? */
-
-static int
-mips_eabi_use_struct_convention (int gcc_p, struct type *type)
-{
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
- return (TYPE_LENGTH (type) > 2 * mips_saved_regsize (tdep));
-}
-
-/* Should call_function pass struct by reference?
- For each architecture, structs are passed either by
- value or by reference, depending on their size. */
-
-static int
-mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type)
-{
- enum type_code typecode = TYPE_CODE (check_typedef (type));
- int len = TYPE_LENGTH (check_typedef (type));
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
-
- if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
- return (len > mips_saved_regsize (tdep));
-
- return 0;
-}
-
/* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
static int
@@ -835,8 +814,7 @@ mips_read_pc (ptid_t ptid)
find the prologue, then return 0. */
static CORE_ADDR
-after_prologue (CORE_ADDR pc,
- mips_extra_func_info_t proc_desc)
+after_prologue (CORE_ADDR pc, mips_extra_func_info_t proc_desc)
{
struct symtab_and_line sal;
CORE_ADDR func_addr, func_end;
@@ -883,7 +861,7 @@ mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask,
{
int reg;
- if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
+ if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
|| (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
|| (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
{
@@ -896,7 +874,7 @@ mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask,
*gen_mask |= (1 << reg);
}
else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
- || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
+ || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
|| (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
{
@@ -994,7 +972,7 @@ mips32_next_pc (CORE_ADDR pc)
if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */
{
if (itype_op (inst) >> 2 == 5)
- /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
+ /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
{
op = (itype_op (inst) & 0x03);
switch (op)
@@ -1012,11 +990,13 @@ mips32_next_pc (CORE_ADDR pc)
}
}
else if (itype_op (inst) == 17 && itype_rs (inst) == 8)
- /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
+ /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
{
int tf = itype_rt (inst) & 0x01;
int cnum = itype_rt (inst) >> 2;
- int fcrcs = read_signed_register (mips_regnum (current_gdbarch)->fp_control_status);
+ int fcrcs =
+ read_signed_register (mips_regnum (current_gdbarch)->
+ fp_control_status);
int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01);
if (((cond >> cnum) & 0x01) == tf)
@@ -1046,7 +1026,7 @@ mips32_next_pc (CORE_ADDR pc)
pc += 4;
}
- break; /* end SPECIAL */
+ break; /* end SPECIAL */
case 1: /* REGIMM */
{
op = itype_rt (inst); /* branch condition */
@@ -1076,7 +1056,7 @@ mips32_next_pc (CORE_ADDR pc)
pc += 4;
}
}
- break; /* end REGIMM */
+ break; /* end REGIMM */
case 2: /* J */
case 3: /* JAL */
{
@@ -1168,11 +1148,11 @@ enum mips16_inst_fmts
/* I am heaping all the fields of the formats into one structure and
then, only the fields which are involved in instruction extension */
struct upk_mips16
- {
- CORE_ADDR offset;
- unsigned int regx; /* Function in i8 type */
- unsigned int regy;
- };
+{
+ CORE_ADDR offset;
+ unsigned int regx; /* Function in i8 type */
+ unsigned int regy;
+};
/* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
@@ -1212,8 +1192,7 @@ static void
unpack_mips16 (CORE_ADDR pc,
unsigned int extension,
unsigned int inst,
- enum mips16_inst_fmts insn_format,
- struct upk_mips16 *upk)
+ enum mips16_inst_fmts insn_format, struct upk_mips16 *upk)
{
CORE_ADDR offset;
int regx;
@@ -1227,7 +1206,7 @@ unpack_mips16 (CORE_ADDR pc,
{
value = extended_offset (extension);
value = value << 11; /* rom for the original value */
- value |= inst & 0x7ff; /* eleven bits from instruction */
+ value |= inst & 0x7ff; /* eleven bits from instruction */
}
else
{
@@ -1286,8 +1265,7 @@ unpack_mips16 (CORE_ADDR pc,
break;
}
default:
- internal_error (__FILE__, __LINE__,
- "bad switch");
+ internal_error (__FILE__, __LINE__, "bad switch");
}
upk->offset = offset;
upk->regx = regx;
@@ -1303,13 +1281,12 @@ add_offset_16 (CORE_ADDR pc, int offset)
static CORE_ADDR
extended_mips16_next_pc (CORE_ADDR pc,
- unsigned int extension,
- unsigned int insn)
+ unsigned int extension, unsigned int insn)
{
int op = (insn >> 11);
switch (op)
{
- case 2: /* Branch */
+ case 2: /* Branch */
{
CORE_ADDR offset;
struct upk_mips16 upk;
@@ -1323,7 +1300,7 @@ extended_mips16_next_pc (CORE_ADDR pc,
pc += (offset << 1) + 2;
break;
}
- case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
+ case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
{
struct upk_mips16 upk;
unpack_mips16 (pc, extension, insn, jalxtype, &upk);
@@ -1334,7 +1311,7 @@ extended_mips16_next_pc (CORE_ADDR pc,
pc |= 0x01;
break;
}
- case 4: /* beqz */
+ case 4: /* beqz */
{
struct upk_mips16 upk;
int reg;
@@ -1346,7 +1323,7 @@ extended_mips16_next_pc (CORE_ADDR pc,
pc += 2;
break;
}
- case 5: /* bnez */
+ case 5: /* bnez */
{
struct upk_mips16 upk;
int reg;
@@ -1358,7 +1335,7 @@ extended_mips16_next_pc (CORE_ADDR pc,
pc += 2;
break;
}
- case 12: /* I8 Formats btez btnez */
+ case 12: /* I8 Formats btez btnez */
{
struct upk_mips16 upk;
int reg;
@@ -1373,7 +1350,7 @@ extended_mips16_next_pc (CORE_ADDR pc,
pc += 2;
break;
}
- case 29: /* RR Formats JR, JALR, JALR-RA */
+ case 29: /* RR Formats JR, JALR, JALR-RA */
{
struct upk_mips16 upk;
/* upk.fmt = rrtype; */
@@ -1390,13 +1367,13 @@ extended_mips16_next_pc (CORE_ADDR pc,
break;
case 1:
reg = 31;
- break; /* Function return instruction */
+ break; /* Function return instruction */
case 2:
reg = upk.regx;
break;
default:
reg = 31;
- break; /* BOGUS Guess */
+ break; /* BOGUS Guess */
}
pc = read_signed_register (reg);
}
@@ -1486,8 +1463,9 @@ mips_find_saved_regs (struct frame_info *fci)
{
for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
{
- CORE_ADDR reg_position = (get_frame_base (fci) + SIGFRAME_REGSAVE_OFF
- + ireg * mips_regsize (current_gdbarch));
+ CORE_ADDR reg_position =
+ (get_frame_base (fci) + SIGFRAME_REGSAVE_OFF +
+ ireg * mips_regsize (current_gdbarch));
set_reg_offset (saved_regs, ireg, reg_position);
}
for (ireg = 0; ireg < MIPS_NUMREGS; ireg++)
@@ -1495,10 +1473,13 @@ mips_find_saved_regs (struct frame_info *fci)
CORE_ADDR reg_position = (get_frame_base (fci)
+ SIGFRAME_FPREGSAVE_OFF
+ ireg * mips_regsize (current_gdbarch));
- set_reg_offset (saved_regs, mips_regnum (current_gdbarch)->fp0 + ireg, reg_position);
+ set_reg_offset (saved_regs,
+ mips_regnum (current_gdbarch)->fp0 + ireg,
+ reg_position);
}
- set_reg_offset (saved_regs, PC_REGNUM, get_frame_base (fci) + SIGFRAME_PC_OFF);
+ set_reg_offset (saved_regs, PC_REGNUM,
+ get_frame_base (fci) + SIGFRAME_PC_OFF);
/* SP_REGNUM, contains the value and not the address. */
set_reg_offset (saved_regs, SP_REGNUM, get_frame_base (fci));
return;
@@ -1515,25 +1496,21 @@ mips_find_saved_regs (struct frame_info *fci)
gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc);
float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc);
- if (/* In any frame other than the innermost or a frame interrupted
- by a signal, we assume that all registers have been saved.
- This assumes that all register saves in a function happen
- before the first function call. */
+ if ( /* In any frame other than the innermost or a frame interrupted
+ by a signal, we assume that all registers have been saved.
+ This assumes that all register saves in a function happen
+ before the first function call. */
(get_next_frame (fci) == NULL
|| (get_frame_type (get_next_frame (fci)) == SIGTRAMP_FRAME))
-
/* In a dummy frame we know exactly where things are saved. */
&& !PROC_DESC_IS_DUMMY (proc_desc)
-
/* Don't bother unless we are inside a function prologue.
- Outside the prologue, we know where everything is. */
-
+ Outside the prologue, we know where everything is. */
&& in_prologue (get_frame_pc (fci), PROC_LOW_ADDR (proc_desc))
-
/* Not sure exactly what kernel_trap means, but if it means the
- kernel saves the registers without a prologue doing it, we
- better not examine the prologue to see whether registers
- have been saved yet. */
+ kernel saves the registers without a prologue doing it, we
+ better not examine the prologue to see whether registers
+ have been saved yet. */
&& !kernel_trap)
{
/* We need to figure out whether the registers that the
@@ -1598,7 +1575,7 @@ mips_find_saved_regs (struct frame_info *fci)
reg_position -= mips_saved_regsize (tdep);
/* Check if the s0 and s1 registers were pushed on the
- stack. */
+ stack. */
for (reg = 16; reg < sreg_count + 16; reg++)
{
set_reg_offset (saved_regs, reg, reg_position);
@@ -1622,36 +1599,40 @@ mips_find_saved_regs (struct frame_info *fci)
&& TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
{
/* On a big endian 32 bit ABI, floating point registers
- are paired to form doubles such that the most
- significant part is in $f[N+1] and the least
- significant in $f[N] vis: $f[N+1] ||| $f[N]. The
- registers are also spilled as a pair and stored as a
- double.
+ are paired to form doubles such that the most
+ significant part is in $f[N+1] and the least
+ significant in $f[N] vis: $f[N+1] ||| $f[N]. The
+ registers are also spilled as a pair and stored as a
+ double.
When little-endian the least significant part is
stored first leading to the memory order $f[N] and
then $f[N+1].
- Unfortunately, when big-endian the most significant
- part of the double is stored first, and the least
- significant is stored second. This leads to the
- registers being ordered in memory as firt $f[N+1] and
- then $f[N].
-
- For the big-endian case make certain that the
- addresses point at the correct (swapped) locations
- $f[N] and $f[N+1] pair (keep in mind that
- reg_position is decremented each time through the
- loop). */
+ Unfortunately, when big-endian the most significant
+ part of the double is stored first, and the least
+ significant is stored second. This leads to the
+ registers being ordered in memory as firt $f[N+1] and
+ then $f[N].
+
+ For the big-endian case make certain that the
+ addresses point at the correct (swapped) locations
+ $f[N] and $f[N+1] pair (keep in mind that
+ reg_position is decremented each time through the
+ loop). */
if ((ireg & 1))
- set_reg_offset (saved_regs, mips_regnum (current_gdbarch)->fp0 + ireg,
+ set_reg_offset (saved_regs,
+ mips_regnum (current_gdbarch)->fp0 + ireg,
reg_position - mips_saved_regsize (tdep));
else
- set_reg_offset (saved_regs, mips_regnum (current_gdbarch)->fp0 + ireg,
+ set_reg_offset (saved_regs,
+ mips_regnum (current_gdbarch)->fp0 + ireg,
reg_position + mips_saved_regsize (tdep));
}
else
- set_reg_offset (saved_regs, mips_regnum (current_gdbarch)->fp0 + ireg, reg_position);
+ set_reg_offset (saved_regs,
+ mips_regnum (current_gdbarch)->fp0 + ireg,
+ reg_position);
reg_position -= mips_saved_regsize (tdep);
}
@@ -1690,8 +1671,7 @@ static CORE_ADDR
mips_addr_bits_remove (CORE_ADDR addr)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
- if (mips_mask_address_p (tdep)
- && (((ULONGEST) addr) >> 32 == 0xffffffffUL))
+ if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL))
/* This hack is a work-around for existing boards using PMON, the
simulator, and any other 64-bit targets that doesn't have true
64-bit addressing. On these targets, the upper 32 bits of
@@ -1747,8 +1727,7 @@ mips_init_frame_pc_first (int fromleaf, struct frame_info *prev)
pc = ((fromleaf)
? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev))
: get_next_frame (prev)
- ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev))
- : read_pc ());
+ ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev)) : read_pc ());
tmp = SKIP_TRAMPOLINE_CODE (pc);
return tmp ? tmp : pc;
}
@@ -1771,8 +1750,8 @@ mips_frame_saved_pc (struct frame_info *frame)
= get_frame_extra_info (frame)->proc_desc;
if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc))
saved_pc = read_memory_integer ((get_frame_base (frame)
- - mips_saved_regsize (tdep))
- , mips_saved_regsize (tdep));
+ - mips_saved_regsize (tdep)),
+ mips_saved_regsize (tdep));
else
{
/* We have to get the saved pc from the sigcontext if it is
@@ -1853,8 +1832,7 @@ heuristic_proc_start (CORE_ADDR pc)
if (start_pc == 0)
return 0;
- if (heuristic_fence_post == UINT_MAX
- || fence < VM_MIN_ADDRESS)
+ if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS)
fence = VM_MIN_ADDRESS;
instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN;
@@ -1871,8 +1849,9 @@ heuristic_proc_start (CORE_ADDR pc)
{
static int blurb_printed = 0;
- warning ("Warning: GDB can't find the start of the function at 0x%s.",
- paddr_nz (pc));
+ warning
+ ("Warning: GDB can't find the start of the function at 0x%s.",
+ paddr_nz (pc));
if (!blurb_printed)
{
@@ -1892,8 +1871,7 @@ stack pointer.\n\
However, if you think GDB should simply search farther back\n\
from 0x%s for code which looks like the beginning of a\n\
function, you can increase the range of the search using the `set\n\
-heuristic-fence-post' command.\n",
- paddr_nz (pc), paddr_nz (pc));
+heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc));
blurb_printed = 1;
}
}
@@ -1939,9 +1917,9 @@ heuristic-fence-post' command.\n",
static int
mips16_get_imm (unsigned short prev_inst, /* previous instruction */
unsigned short inst, /* current instruction */
- int nbits, /* number of bits in imm field */
- int scale, /* scale factor to be applied to imm */
- int is_signed) /* is the imm field signed? */
+ int nbits, /* number of bits in imm field */
+ int scale, /* scale factor to be applied to imm */
+ int is_signed) /* is the imm field signed? */
{
int offset;
@@ -1993,7 +1971,7 @@ mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
/* Fetch and decode the instruction. */
inst = (unsigned short) mips_fetch_instruction (cur_pc);
if ((inst & 0xff00) == 0x6300 /* addiu sp */
- || (inst & 0xff00) == 0xfb00) /* daddiu sp */
+ || (inst & 0xff00) == 0xfb00) /* daddiu sp */
{
offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
if (offset < 0) /* negative stack adjustment? */
@@ -2154,7 +2132,8 @@ restart:
but the register size used is only 32 bits. Make the address
for the saved register point to the lower 32 bits. */
PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
- set_reg_offset (temp_saved_regs, reg, sp + low_word + 8 - mips_regsize (current_gdbarch));
+ set_reg_offset (temp_saved_regs, reg,
+ sp + low_word + 8 - mips_regsize (current_gdbarch));
}
else if (high_word == 0x27be) /* addiu $30,$sp,size */
{
@@ -2287,7 +2266,7 @@ non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr)
priv = (struct mips_objfile_private *) sec->objfile->obj_private;
/* Search the ".pdr" section generated by GAS. This includes most of
- the information normally found in ECOFF PDRs. */
+ the information normally found in ECOFF PDRs. */
the_bfd = sec->objfile->obfd;
if (priv == NULL
@@ -2299,7 +2278,7 @@ non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr)
This means that we should not bother with this method on 64-bit
targets (until that is fixed). */
- priv = obstack_alloc (& sec->objfile->psymbol_obstack,
+ priv = obstack_alloc (&sec->objfile->psymbol_obstack,
sizeof (struct mips_objfile_private));
priv->size = 0;
sec->objfile->obj_private = priv;
@@ -2308,23 +2287,24 @@ non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr)
{
asection *bfdsec;
- priv = obstack_alloc (& sec->objfile->psymbol_obstack,
+ priv = obstack_alloc (&sec->objfile->psymbol_obstack,
sizeof (struct mips_objfile_private));
bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr");
if (bfdsec != NULL)
{
priv->size = bfd_section_size (sec->objfile->obfd, bfdsec);
- priv->contents = obstack_alloc (& sec->objfile->psymbol_obstack,
+ priv->contents = obstack_alloc (&sec->objfile->psymbol_obstack,
priv->size);
bfd_get_section_contents (sec->objfile->obfd, bfdsec,
priv->contents, 0, priv->size);
/* In general, the .pdr section is sorted. However, in the
- presence of multiple code sections (and other corner cases)
- it can become unsorted. Sort it so that we can use a faster
- binary search. */
- qsort (priv->contents, priv->size / 32, 32, compare_pdr_entries);
+ presence of multiple code sections (and other corner cases)
+ it can become unsorted. Sort it so that we can use a faster
+ binary search. */
+ qsort (priv->contents, priv->size / 32, 32,
+ compare_pdr_entries);
}
else
priv->size = 0;
@@ -2401,8 +2381,8 @@ non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr)
if (startaddr > BLOCK_START (b))
{
/* This is the "pathological" case referred to in a comment in
- print_frame_info. It might be better to move this check into
- symbol reading. */
+ print_frame_info. It might be better to move this check into
+ symbol reading. */
return NULL;
}
@@ -2448,8 +2428,7 @@ find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame)
if (proc_symbol)
{
val = find_pc_line (BLOCK_START
- (SYMBOL_BLOCK_VALUE (proc_symbol)),
- 0);
+ (SYMBOL_BLOCK_VALUE (proc_symbol)), 0);
val.pc = val.end ? val.end : pc;
}
if (!proc_symbol || pc < val.pc)
@@ -2479,19 +2458,16 @@ find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame)
if (startaddr == 0)
startaddr = heuristic_proc_start (pc);
- proc_desc =
- heuristic_proc_desc (startaddr, pc, next_frame, cur_frame);
+ proc_desc = heuristic_proc_desc (startaddr, pc, next_frame, cur_frame);
}
return proc_desc;
}
static CORE_ADDR
-get_frame_pointer (struct frame_info *frame,
- mips_extra_func_info_t proc_desc)
+get_frame_pointer (struct frame_info *frame, mips_extra_func_info_t proc_desc)
{
return (read_next_frame_reg (frame, NUM_REGS + PROC_FRAME_REG (proc_desc))
- + PROC_FRAME_OFFSET (proc_desc)
- - PROC_FRAME_ADJUST (proc_desc));
+ + PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc));
}
static mips_extra_func_info_t cached_proc_desc;
@@ -2529,7 +2505,7 @@ mips_frame_chain (struct frame_info *frame)
if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
&& PROC_FRAME_OFFSET (proc_desc) == 0
/* The previous frame from a sigtramp frame might be frameless
- and have frame size zero. */
+ and have frame size zero. */
&& !(get_frame_type (frame) == SIGTRAMP_FRAME)
/* For a generic dummy frame, let get_frame_pointer() unwind a
register value saved as part of the dummy frame call. */
@@ -2556,7 +2532,7 @@ mips_init_extra_frame_info (int fromleaf, struct frame_info *fci)
get_next_frame (fci)
? cached_proc_desc
: find_proc_desc (get_frame_pc (fci),
- NULL /* i.e, get_next_frame (fci) */,
+ NULL /* i.e, get_next_frame (fci) */ ,
1);
frame_extra_info_zalloc (fci, sizeof (struct frame_extra_info));
@@ -2571,17 +2547,24 @@ mips_init_extra_frame_info (int fromleaf, struct frame_info *fci)
interrupted by a signal at it's very start. */
if (get_frame_pc (fci) == PROC_LOW_ADDR (proc_desc)
&& !PROC_DESC_IS_DUMMY (proc_desc))
- deprecated_update_frame_base_hack (fci, read_next_frame_reg (get_next_frame (fci), NUM_REGS + SP_REGNUM));
+ deprecated_update_frame_base_hack (fci,
+ read_next_frame_reg (get_next_frame
+ (fci),
+ NUM_REGS +
+ SP_REGNUM));
else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fci), 0, 0))
/* Do not ``fix'' fci->frame. It will have the value of the
- generic dummy frame's top-of-stack (since the draft
- fci->frame is obtained by returning the unwound stack
- pointer) and that is what we want. That way the fci->frame
- value will match the top-of-stack value that was saved as
- part of the dummy frames data. */
- /* Do nothing. */;
+ generic dummy frame's top-of-stack (since the draft
+ fci->frame is obtained by returning the unwound stack
+ pointer) and that is what we want. That way the fci->frame
+ value will match the top-of-stack value that was saved as
+ part of the dummy frames data. */
+ /* Do nothing. */ ;
else
- deprecated_update_frame_base_hack (fci, get_frame_pointer (get_next_frame (fci), proc_desc));
+ deprecated_update_frame_base_hack (fci,
+ get_frame_pointer (get_next_frame
+ (fci),
+ proc_desc));
if (proc_desc == &temp_proc_desc)
{
@@ -2592,8 +2575,8 @@ mips_init_extra_frame_info (int fromleaf, struct frame_info *fci)
use (get_frame_type (fci) == SIGTRAMP_FRAME), it is not
yet set. */
/* FIXME: cagney/2002-11-18: This problem will go away once
- frame.c:get_prev_frame() is modified to set the frame's
- type before calling functions like this. */
+ frame.c:get_prev_frame() is modified to set the frame's
+ type before calling functions like this. */
find_pc_partial_function (get_frame_pc (fci), &name,
(CORE_ADDR *) NULL, (CORE_ADDR *) NULL);
if (!PC_IN_SIGTRAMP (get_frame_pc (fci), name))
@@ -2663,7 +2646,8 @@ fp_register_arg_p (enum type_code typecode, struct type *arg_type)
{
return ((typecode == TYPE_CODE_FLT
|| (MIPS_EABI
- && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
+ && (typecode == TYPE_CODE_STRUCT
+ || typecode == TYPE_CODE_UNION)
&& TYPE_NFIELDS (arg_type) == 1
&& TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT))
&& MIPS_FPU_TYPE != MIPS_FPU_NONE);
@@ -2706,11 +2690,150 @@ mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
return align_down (addr, 16);
}
+/* Determine how a return value is stored within the MIPS register
+ file, given the return type `valtype'. */
+
+struct return_value_word
+{
+ int len;
+ int reg;
+ int reg_offset;
+ int buf_offset;
+};
+
+static void
+return_value_location (struct type *valtype,
+ struct return_value_word *hi,
+ struct return_value_word *lo)
+{
+ int len = TYPE_LENGTH (valtype);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ if (TYPE_CODE (valtype) == TYPE_CODE_FLT
+ && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8))
+ || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4)))
+ {
+ if (!FP_REGISTER_DOUBLE && len == 8)
+ {
+ /* We need to break a 64bit float in two 32 bit halves and
+ spread them across a floating-point register pair. */
+ lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
+ hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4;
+ lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
+ && register_size (current_gdbarch,
+ mips_regnum (current_gdbarch)->
+ fp0) == 8) ? 4 : 0);
+ hi->reg_offset = lo->reg_offset;
+ lo->reg = mips_regnum (current_gdbarch)->fp0 + 0;
+ hi->reg = mips_regnum (current_gdbarch)->fp0 + 1;
+ lo->len = 4;
+ hi->len = 4;
+ }
+ else
+ {
+ /* The floating point value fits in a single floating-point
+ register. */
+ lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
+ && register_size (current_gdbarch,
+ mips_regnum (current_gdbarch)->
+ fp0) == 8
+ && len == 4) ? 4 : 0);
+ lo->reg = mips_regnum (current_gdbarch)->fp0;
+ lo->len = len;
+ lo->buf_offset = 0;
+ hi->len = 0;
+ hi->reg_offset = 0;
+ hi->buf_offset = 0;
+ hi->reg = 0;
+ }
+ }
+ else
+ {
+ /* Locate a result possibly spread across two registers. */
+ int regnum = 2;
+ lo->reg = regnum + 0;
+ hi->reg = regnum + 1;
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
+ && len < mips_saved_regsize (tdep))
+ {
+ /* "un-left-justify" the value in the low register */
+ lo->reg_offset = mips_saved_regsize (tdep) - len;
+ lo->len = len;
+ hi->reg_offset = 0;
+ hi->len = 0;
+ }
+ else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG && len > mips_saved_regsize (tdep) /* odd-size structs */
+ && len < mips_saved_regsize (tdep) * 2
+ && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT ||
+ TYPE_CODE (valtype) == TYPE_CODE_UNION))
+ {
+ /* "un-left-justify" the value spread across two registers. */
+ lo->reg_offset = 2 * mips_saved_regsize (tdep) - len;
+ lo->len = mips_saved_regsize (tdep) - lo->reg_offset;
+ hi->reg_offset = 0;
+ hi->len = len - lo->len;
+ }
+ else
+ {
+ /* Only perform a partial copy of the second register. */
+ lo->reg_offset = 0;
+ hi->reg_offset = 0;
+ if (len > mips_saved_regsize (tdep))
+ {
+ lo->len = mips_saved_regsize (tdep);
+ hi->len = len - mips_saved_regsize (tdep);
+ }
+ else
+ {
+ lo->len = len;
+ hi->len = 0;
+ }
+ }
+ if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
+ && register_size (current_gdbarch, regnum) == 8
+ && mips_saved_regsize (tdep) == 4)
+ {
+ /* Account for the fact that only the least-signficant part
+ of the register is being used */
+ lo->reg_offset += 4;
+ hi->reg_offset += 4;
+ }
+ lo->buf_offset = 0;
+ hi->buf_offset = lo->len;
+ }
+}
+
+/* Should call_function allocate stack space for a struct return? */
+
+static int
+mips_eabi_use_struct_convention (int gcc_p, struct type *type)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+ return (TYPE_LENGTH (type) > 2 * mips_saved_regsize (tdep));
+}
+
+/* Should call_function pass struct by reference?
+ For each architecture, structs are passed either by
+ value or by reference, depending on their size. */
+
+static int
+mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type)
+{
+ enum type_code typecode = TYPE_CODE (check_typedef (type));
+ int len = TYPE_LENGTH (check_typedef (type));
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
+ return (len > mips_saved_regsize (tdep));
+
+ return 0;
+}
+
static CORE_ADDR
mips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
- struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
- struct value **args, CORE_ADDR sp, int struct_return,
- CORE_ADDR struct_addr)
+ struct regcache *regcache, CORE_ADDR bp_addr,
+ int nargs, struct value **args, CORE_ADDR sp,
+ int struct_return, CORE_ADDR struct_addr)
{
int argreg;
int float_argreg;
@@ -2740,12 +2863,12 @@ mips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
than necessary for EABI, because the first few arguments are
passed in registers, but that's OK. */
for (argnum = 0; argnum < nargs; argnum++)
- len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
+ len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
mips_stack_argsize (tdep));
sp -= align_up (len, 16);
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog,
+ fprintf_unfiltered (gdb_stdlog,
"mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
paddr_nz (sp), (long) align_up (len, 16));
@@ -2801,8 +2924,7 @@ mips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
up before the check to see if there are any FP registers
left. Non MIPS_EABI targets also pass the FP in the integer
registers so also round up normal registers. */
- if (!FP_REGISTER_DOUBLE
- && fp_register_arg_p (typecode, arg_type))
+ if (!FP_REGISTER_DOUBLE && fp_register_arg_p (typecode, arg_type))
{
if ((float_argreg & 1))
float_argreg++;
@@ -2847,7 +2969,7 @@ mips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
/* This is a floating point value that fits entirely
in a single register. */
/* On 32 bit ABI's the float_argreg is further adjusted
- above to ensure that it is even register aligned. */
+ above to ensure that it is even register aligned. */
LONGEST regval = extract_unsigned_integer (val, len);
if (mips_debug)
fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
@@ -2869,7 +2991,7 @@ mips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
&& (len % mips_saved_regsize (tdep) != 0));
/* Note: Floating-point values that didn't fit into an FP
- register are only written to memory. */
+ register are only written to memory. */
while (len > 0)
{
/* Remember if the argument was written to the stack. */
@@ -2896,8 +3018,7 @@ mips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
if (mips_stack_argsize (tdep) == 8
&& (typecode == TYPE_CODE_INT
|| typecode == TYPE_CODE_PTR
- || typecode == TYPE_CODE_FLT)
- && len <= 4)
+ || typecode == TYPE_CODE_FLT) && len <= 4)
longword_offset = mips_stack_argsize (tdep) - len;
else if ((typecode == TYPE_CODE_STRUCT
|| typecode == TYPE_CODE_UNION)
@@ -2919,11 +3040,11 @@ mips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
if (mips_debug)
{
int i;
- fprintf_unfiltered (gdb_stdlog, " @0x%s ",
+ fprintf_unfiltered (gdb_stdlog, " @0x%s ",
paddr_nz (addr));
for (i = 0; i < partial_len; i++)
{
- fprintf_unfiltered (gdb_stdlog, "%02x",
+ fprintf_unfiltered (gdb_stdlog, "%02x",
val[i] & 0xff);
}
}
@@ -2934,16 +3055,18 @@ mips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
structs may go thru BOTH paths. Floating point
arguments will not. */
/* Write this portion of the argument to a general
- purpose register. */
+ purpose register. */
if (argreg <= MIPS_LAST_ARG_REGNUM
&& !fp_register_arg_p (typecode, arg_type))
{
- LONGEST regval = extract_unsigned_integer (val, partial_len);
+ LONGEST regval =
+ extract_unsigned_integer (val, partial_len);
if (mips_debug)
fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
argreg,
- phex (regval, mips_saved_regsize (tdep)));
+ phex (regval,
+ mips_saved_regsize (tdep)));
write_register (argreg, regval);
argreg++;
}
@@ -2952,7 +3075,7 @@ mips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
val += partial_len;
/* Compute the the offset into the stack at which we
- will copy the next parameter.
+ will copy the next parameter.
In the new EABI (and the NABI32), the stack_offset
only needs to be adjusted when it has been used. */
@@ -2972,13 +3095,62 @@ mips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
return sp;
}
-/* N32/N64 version of push_dummy_call. */
+/* Given a return value in `regbuf' with a type `valtype', extract and
+ copy its value into `valbuf'. */
+
+static void
+mips_eabi_extract_return_value (struct type *valtype,
+ char regbuf[], char *valbuf)
+{
+ struct return_value_word lo;
+ struct return_value_word hi;
+ return_value_location (valtype, &hi, &lo);
+
+ memcpy (valbuf + lo.buf_offset,
+ regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) +
+ lo.reg_offset, lo.len);
+
+ if (hi.len > 0)
+ memcpy (valbuf + hi.buf_offset,
+ regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) +
+ hi.reg_offset, hi.len);
+}
+
+/* Given a return value in `valbuf' with a type `valtype', write it's
+ value into the appropriate register. */
+
+static void
+mips_eabi_store_return_value (struct type *valtype, char *valbuf)
+{
+ char raw_buffer[MAX_REGISTER_SIZE];
+ struct return_value_word lo;
+ struct return_value_word hi;
+ return_value_location (valtype, &hi, &lo);
+
+ memset (raw_buffer, 0, sizeof (raw_buffer));
+ memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len);
+ deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg),
+ raw_buffer, register_size (current_gdbarch,
+ lo.reg));
+
+ if (hi.len > 0)
+ {
+ memset (raw_buffer, 0, sizeof (raw_buffer));
+ memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len);
+ deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg),
+ raw_buffer,
+ register_size (current_gdbarch,
+ hi.reg));
+ }
+}
+
+/* N32/N64 ABI stuff. */
static CORE_ADDR
mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
- struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
- struct value **args, CORE_ADDR sp, int struct_return,
- CORE_ADDR struct_addr)
+ struct regcache *regcache, CORE_ADDR bp_addr,
+ int nargs, struct value **args, CORE_ADDR sp,
+ int struct_return, CORE_ADDR struct_addr)
{
int argreg;
int float_argreg;
@@ -3006,12 +3178,12 @@ mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
/* Now make space on the stack for the args. */
for (argnum = 0; argnum < nargs; argnum++)
- len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
+ len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
mips_stack_argsize (tdep));
sp -= align_up (len, 16);
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog,
+ fprintf_unfiltered (gdb_stdlog,
"mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
paddr_nz (sp), (long) align_up (len, 16));
@@ -3080,7 +3252,7 @@ mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
int odd_sized_struct = ((len > mips_saved_regsize (tdep))
&& (len % mips_saved_regsize (tdep) != 0));
/* Note: Floating-point values that didn't fit into an FP
- register are only written to memory. */
+ register are only written to memory. */
while (len > 0)
{
/* Rememer if the argument was written to the stack. */
@@ -3107,8 +3279,7 @@ mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
if (mips_stack_argsize (tdep) == 8
&& (typecode == TYPE_CODE_INT
|| typecode == TYPE_CODE_PTR
- || typecode == TYPE_CODE_FLT)
- && len <= 4)
+ || typecode == TYPE_CODE_FLT) && len <= 4)
longword_offset = mips_stack_argsize (tdep) - len;
}
@@ -3125,11 +3296,11 @@ mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
if (mips_debug)
{
int i;
- fprintf_unfiltered (gdb_stdlog, " @0x%s ",
+ fprintf_unfiltered (gdb_stdlog, " @0x%s ",
paddr_nz (addr));
for (i = 0; i < partial_len; i++)
{
- fprintf_unfiltered (gdb_stdlog, "%02x",
+ fprintf_unfiltered (gdb_stdlog, "%02x",
val[i] & 0xff);
}
}
@@ -3140,11 +3311,12 @@ mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
structs may go thru BOTH paths. Floating point
arguments will not. */
/* Write this portion of the argument to a general
- purpose register. */
+ purpose register. */
if (argreg <= MIPS_LAST_ARG_REGNUM
&& !fp_register_arg_p (typecode, arg_type))
{
- LONGEST regval = extract_unsigned_integer (val, partial_len);
+ LONGEST regval =
+ extract_unsigned_integer (val, partial_len);
/* A non-floating-point argument being passed in a
general register. If a struct or union, and if
@@ -3179,7 +3351,8 @@ mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
if (mips_debug)
fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
argreg,
- phex (regval, mips_saved_regsize (tdep)));
+ phex (regval,
+ mips_saved_regsize (tdep)));
write_register (argreg, regval);
argreg++;
}
@@ -3188,7 +3361,7 @@ mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
val += partial_len;
/* Compute the the offset into the stack at which we
- will copy the next parameter.
+ will copy the next parameter.
In N32 (N64?), the stack_offset only needs to be
adjusted when it has been used. */
@@ -3208,13 +3381,117 @@ mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
return sp;
}
-/* O32 version of push_dummy_call. */
+static enum return_value_convention
+mips_n32n64_return_value (struct gdbarch *gdbarch,
+ struct type *type, struct regcache *regcache,
+ void *readbuf, const void *writebuf)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+ if (TYPE_CODE (type) == TYPE_CODE_STRUCT
+ || TYPE_CODE (type) == TYPE_CODE_UNION
+ || TYPE_CODE (type) == TYPE_CODE_ARRAY
+ || TYPE_LENGTH (type) > 2 * mips_saved_regsize (tdep))
+ return RETURN_VALUE_STRUCT_CONVENTION;
+ else if (TYPE_CODE (type) == TYPE_CODE_FLT
+ && tdep->mips_fpu_type != MIPS_FPU_NONE)
+ {
+ /* A floating-point value belongs in the least significant part
+ of FP0. */
+ if (mips_debug)
+ fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
+ mips_xfer_register (regcache,
+ NUM_REGS + mips_regnum (current_gdbarch)->fp0,
+ TYPE_LENGTH (type),
+ TARGET_BYTE_ORDER, readbuf, writebuf, 0);
+ return RETURN_VALUE_REGISTER_CONVENTION;
+ }
+ else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
+ && TYPE_NFIELDS (type) <= 2
+ && TYPE_NFIELDS (type) >= 1
+ && ((TYPE_NFIELDS (type) == 1
+ && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
+ == TYPE_CODE_FLT))
+ || (TYPE_NFIELDS (type) == 2
+ && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
+ == TYPE_CODE_FLT)
+ && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
+ == TYPE_CODE_FLT)))
+ && tdep->mips_fpu_type != MIPS_FPU_NONE)
+ {
+ /* A struct that contains one or two floats. Each value is part
+ in the least significant part of their floating point
+ register.. */
+ bfd_byte reg[MAX_REGISTER_SIZE];
+ int regnum;
+ int field;
+ for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0;
+ field < TYPE_NFIELDS (type); field++, regnum += 2)
+ {
+ int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
+ / TARGET_CHAR_BIT);
+ if (mips_debug)
+ fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
+ offset);
+ mips_xfer_register (regcache, NUM_REGS + regnum,
+ TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
+ TARGET_BYTE_ORDER, readbuf, writebuf, offset);
+ }
+ return RETURN_VALUE_REGISTER_CONVENTION;
+ }
+ else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
+ || TYPE_CODE (type) == TYPE_CODE_UNION)
+ {
+ /* A structure or union. Extract the left justified value,
+ regardless of the byte order. I.e. DO NOT USE
+ mips_xfer_lower. */
+ int offset;
+ int regnum;
+ for (offset = 0, regnum = V0_REGNUM;
+ offset < TYPE_LENGTH (type);
+ offset += register_size (current_gdbarch, regnum), regnum++)
+ {
+ int xfer = register_size (current_gdbarch, regnum);
+ if (offset + xfer > TYPE_LENGTH (type))
+ xfer = TYPE_LENGTH (type) - offset;
+ if (mips_debug)
+ fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
+ offset, xfer, regnum);
+ mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
+ BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset);
+ }
+ return RETURN_VALUE_REGISTER_CONVENTION;
+ }
+ else
+ {
+ /* A scalar extract each part but least-significant-byte
+ justified. */
+ int offset;
+ int regnum;
+ for (offset = 0, regnum = V0_REGNUM;
+ offset < TYPE_LENGTH (type);
+ offset += register_size (current_gdbarch, regnum), regnum++)
+ {
+ int xfer = register_size (current_gdbarch, regnum);
+ int pos = 0;
+ if (offset + xfer > TYPE_LENGTH (type))
+ xfer = TYPE_LENGTH (type) - offset;
+ if (mips_debug)
+ fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
+ offset, xfer, regnum);
+ mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
+ TARGET_BYTE_ORDER, readbuf, writebuf, offset);
+ }
+ return RETURN_VALUE_REGISTER_CONVENTION;
+ }
+}
+
+/* O32 ABI stuff. */
static CORE_ADDR
mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
- struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
- struct value **args, CORE_ADDR sp, int struct_return,
- CORE_ADDR struct_addr)
+ struct regcache *regcache, CORE_ADDR bp_addr,
+ int nargs, struct value **args, CORE_ADDR sp,
+ int struct_return, CORE_ADDR struct_addr)
{
int argreg;
int float_argreg;
@@ -3242,12 +3519,12 @@ mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
/* Now make space on the stack for the args. */
for (argnum = 0; argnum < nargs; argnum++)
- len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
+ len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
mips_stack_argsize (tdep));
sp -= align_up (len, 16);
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog,
+ fprintf_unfiltered (gdb_stdlog,
"mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
paddr_nz (sp), (long) align_up (len, 16));
@@ -3290,8 +3567,7 @@ mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
up before the check to see if there are any FP registers
left. O32/O64 targets also pass the FP in the integer
registers so also round up normal registers. */
- if (!FP_REGISTER_DOUBLE
- && fp_register_arg_p (typecode, arg_type))
+ if (!FP_REGISTER_DOUBLE && fp_register_arg_p (typecode, arg_type))
{
if ((float_argreg & 1))
float_argreg++;
@@ -3343,16 +3619,16 @@ mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
/* This is a floating point value that fits entirely
in a single register. */
/* On 32 bit ABI's the float_argreg is further adjusted
- above to ensure that it is even register aligned. */
+ above to ensure that it is even register aligned. */
LONGEST regval = extract_unsigned_integer (val, len);
if (mips_debug)
fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
float_argreg, phex (regval, len));
write_register (float_argreg++, regval);
/* CAGNEY: 32 bit MIPS ABI's always reserve two FP
- registers for each argument. The below is (my
- guess) to ensure that the corresponding integer
- register has reserved the same space. */
+ registers for each argument. The below is (my
+ guess) to ensure that the corresponding integer
+ register has reserved the same space. */
if (mips_debug)
fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
argreg, phex (regval, len));
@@ -3380,10 +3656,10 @@ mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
&& mips_type_needs_double_align (arg_type))
{
if ((argreg & 1))
- argreg++;
+ argreg++;
}
/* Note: Floating-point values that didn't fit into an FP
- register are only written to memory. */
+ register are only written to memory. */
while (len > 0)
{
/* Remember if the argument was written to the stack. */
@@ -3410,8 +3686,7 @@ mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
if (mips_stack_argsize (tdep) == 8
&& (typecode == TYPE_CODE_INT
|| typecode == TYPE_CODE_PTR
- || typecode == TYPE_CODE_FLT)
- && len <= 4)
+ || typecode == TYPE_CODE_FLT) && len <= 4)
longword_offset = mips_stack_argsize (tdep) - len;
}
@@ -3428,11 +3703,11 @@ mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
if (mips_debug)
{
int i;
- fprintf_unfiltered (gdb_stdlog, " @0x%s ",
+ fprintf_unfiltered (gdb_stdlog, " @0x%s ",
paddr_nz (addr));
for (i = 0; i < partial_len; i++)
{
- fprintf_unfiltered (gdb_stdlog, "%02x",
+ fprintf_unfiltered (gdb_stdlog, "%02x",
val[i] & 0xff);
}
}
@@ -3443,7 +3718,7 @@ mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
structs may go thru BOTH paths. Floating point
arguments will not. */
/* Write this portion of the argument to a general
- purpose register. */
+ purpose register. */
if (argreg <= MIPS_LAST_ARG_REGNUM
&& !fp_register_arg_p (typecode, arg_type))
{
@@ -3487,7 +3762,8 @@ mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
if (mips_debug)
fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
argreg,
- phex (regval, mips_saved_regsize (tdep)));
+ phex (regval,
+ mips_saved_regsize (tdep)));
write_register (argreg, regval);
argreg++;
@@ -3500,12 +3776,12 @@ mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
val += partial_len;
/* Compute the the offset into the stack at which we
- will copy the next parameter.
+ will copy the next parameter.
- In older ABIs, the caller reserved space for
- registers that contained arguments. This was loosely
- refered to as their "home". Consequently, space is
- always allocated. */
+ In older ABIs, the caller reserved space for
+ registers that contained arguments. This was loosely
+ refered to as their "home". Consequently, space is
+ always allocated. */
stack_offset += align_up (partial_len,
mips_stack_argsize (tdep));
@@ -3521,13 +3797,155 @@ mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
return sp;
}
-/* O64 version of push_dummy_call. */
+static enum return_value_convention
+mips_o32_return_value (struct gdbarch *gdbarch, struct type *type,
+ struct regcache *regcache,
+ void *readbuf, const void *writebuf)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+ if (TYPE_CODE (type) == TYPE_CODE_STRUCT
+ || TYPE_CODE (type) == TYPE_CODE_UNION
+ || TYPE_CODE (type) == TYPE_CODE_ARRAY)
+ return RETURN_VALUE_STRUCT_CONVENTION;
+ else if (TYPE_CODE (type) == TYPE_CODE_FLT
+ && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE)
+ {
+ /* A single-precision floating-point value. It fits in the
+ least significant part of FP0. */
+ if (mips_debug)
+ fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
+ mips_xfer_register (regcache,
+ NUM_REGS + mips_regnum (current_gdbarch)->fp0,
+ TYPE_LENGTH (type),
+ TARGET_BYTE_ORDER, readbuf, writebuf, 0);
+ return RETURN_VALUE_REGISTER_CONVENTION;
+ }
+ else if (TYPE_CODE (type) == TYPE_CODE_FLT
+ && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE)
+ {
+ /* A double-precision floating-point value. The most
+ significant part goes in FP1, and the least significant in
+ FP0. */
+ if (mips_debug)
+ fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n");
+ switch (TARGET_BYTE_ORDER)
+ {
+ case BFD_ENDIAN_LITTLE:
+ mips_xfer_register (regcache,
+ NUM_REGS + mips_regnum (current_gdbarch)->fp0 +
+ 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0);
+ mips_xfer_register (regcache,
+ NUM_REGS + mips_regnum (current_gdbarch)->fp0 +
+ 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4);
+ break;
+ case BFD_ENDIAN_BIG:
+ mips_xfer_register (regcache,
+ NUM_REGS + mips_regnum (current_gdbarch)->fp0 +
+ 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0);
+ mips_xfer_register (regcache,
+ NUM_REGS + mips_regnum (current_gdbarch)->fp0 +
+ 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4);
+ break;
+ default:
+ internal_error (__FILE__, __LINE__, "bad switch");
+ }
+ return RETURN_VALUE_REGISTER_CONVENTION;
+ }
+#if 0
+ else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
+ && TYPE_NFIELDS (type) <= 2
+ && TYPE_NFIELDS (type) >= 1
+ && ((TYPE_NFIELDS (type) == 1
+ && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
+ == TYPE_CODE_FLT))
+ || (TYPE_NFIELDS (type) == 2
+ && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
+ == TYPE_CODE_FLT)
+ && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
+ == TYPE_CODE_FLT)))
+ && tdep->mips_fpu_type != MIPS_FPU_NONE)
+ {
+ /* A struct that contains one or two floats. Each value is part
+ in the least significant part of their floating point
+ register.. */
+ bfd_byte reg[MAX_REGISTER_SIZE];
+ int regnum;
+ int field;
+ for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0;
+ field < TYPE_NFIELDS (type); field++, regnum += 2)
+ {
+ int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
+ / TARGET_CHAR_BIT);
+ if (mips_debug)
+ fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
+ offset);
+ mips_xfer_register (regcache, NUM_REGS + regnum,
+ TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
+ TARGET_BYTE_ORDER, readbuf, writebuf, offset);
+ }
+ return RETURN_VALUE_REGISTER_CONVENTION;
+ }
+#endif
+#if 0
+ else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
+ || TYPE_CODE (type) == TYPE_CODE_UNION)
+ {
+ /* A structure or union. Extract the left justified value,
+ regardless of the byte order. I.e. DO NOT USE
+ mips_xfer_lower. */
+ int offset;
+ int regnum;
+ for (offset = 0, regnum = V0_REGNUM;
+ offset < TYPE_LENGTH (type);
+ offset += register_size (current_gdbarch, regnum), regnum++)
+ {
+ int xfer = register_size (current_gdbarch, regnum);
+ if (offset + xfer > TYPE_LENGTH (type))
+ xfer = TYPE_LENGTH (type) - offset;
+ if (mips_debug)
+ fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
+ offset, xfer, regnum);
+ mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
+ BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset);
+ }
+ return RETURN_VALUE_REGISTER_CONVENTION;
+ }
+#endif
+ else
+ {
+ /* A scalar extract each part but least-significant-byte
+ justified. o32 thinks registers are 4 byte, regardless of
+ the ISA. mips_stack_argsize controls this. */
+ int offset;
+ int regnum;
+ for (offset = 0, regnum = V0_REGNUM;
+ offset < TYPE_LENGTH (type);
+ offset += mips_stack_argsize (tdep), regnum++)
+ {
+ int xfer = mips_stack_argsize (tdep);
+ int pos = 0;
+ if (offset + xfer > TYPE_LENGTH (type))
+ xfer = TYPE_LENGTH (type) - offset;
+ if (mips_debug)
+ fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
+ offset, xfer, regnum);
+ mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
+ TARGET_BYTE_ORDER, readbuf, writebuf, offset);
+ }
+ return RETURN_VALUE_REGISTER_CONVENTION;
+ }
+}
+
+/* O64 ABI. This is a hacked up kind of 64-bit version of the o32
+ ABI. */
static CORE_ADDR
mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
- struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
- struct value **args, CORE_ADDR sp, int struct_return,
- CORE_ADDR struct_addr)
+ struct regcache *regcache, CORE_ADDR bp_addr,
+ int nargs,
+ struct value **args, CORE_ADDR sp,
+ int struct_return, CORE_ADDR struct_addr)
{
int argreg;
int float_argreg;
@@ -3555,12 +3973,12 @@ mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
/* Now make space on the stack for the args. */
for (argnum = 0; argnum < nargs; argnum++)
- len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
+ len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
mips_stack_argsize (tdep));
sp -= align_up (len, 16);
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog,
+ fprintf_unfiltered (gdb_stdlog,
"mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
paddr_nz (sp), (long) align_up (len, 16));
@@ -3603,8 +4021,7 @@ mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
up before the check to see if there are any FP registers
left. O32/O64 targets also pass the FP in the integer
registers so also round up normal registers. */
- if (!FP_REGISTER_DOUBLE
- && fp_register_arg_p (typecode, arg_type))
+ if (!FP_REGISTER_DOUBLE && fp_register_arg_p (typecode, arg_type))
{
if ((float_argreg & 1))
float_argreg++;
@@ -3656,16 +4073,16 @@ mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
/* This is a floating point value that fits entirely
in a single register. */
/* On 32 bit ABI's the float_argreg is further adjusted
- above to ensure that it is even register aligned. */
+ above to ensure that it is even register aligned. */
LONGEST regval = extract_unsigned_integer (val, len);
if (mips_debug)
fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
float_argreg, phex (regval, len));
write_register (float_argreg++, regval);
/* CAGNEY: 32 bit MIPS ABI's always reserve two FP
- registers for each argument. The below is (my
- guess) to ensure that the corresponding integer
- register has reserved the same space. */
+ registers for each argument. The below is (my
+ guess) to ensure that the corresponding integer
+ register has reserved the same space. */
if (mips_debug)
fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
argreg, phex (regval, len));
@@ -3693,10 +4110,10 @@ mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
&& mips_type_needs_double_align (arg_type))
{
if ((argreg & 1))
- argreg++;
+ argreg++;
}
/* Note: Floating-point values that didn't fit into an FP
- register are only written to memory. */
+ register are only written to memory. */
while (len > 0)
{
/* Remember if the argument was written to the stack. */
@@ -3723,8 +4140,7 @@ mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
if (mips_stack_argsize (tdep) == 8
&& (typecode == TYPE_CODE_INT
|| typecode == TYPE_CODE_PTR
- || typecode == TYPE_CODE_FLT)
- && len <= 4)
+ || typecode == TYPE_CODE_FLT) && len <= 4)
longword_offset = mips_stack_argsize (tdep) - len;
}
@@ -3741,11 +4157,11 @@ mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
if (mips_debug)
{
int i;
- fprintf_unfiltered (gdb_stdlog, " @0x%s ",
+ fprintf_unfiltered (gdb_stdlog, " @0x%s ",
paddr_nz (addr));
for (i = 0; i < partial_len; i++)
{
- fprintf_unfiltered (gdb_stdlog, "%02x",
+ fprintf_unfiltered (gdb_stdlog, "%02x",
val[i] & 0xff);
}
}
@@ -3756,7 +4172,7 @@ mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
structs may go thru BOTH paths. Floating point
arguments will not. */
/* Write this portion of the argument to a general
- purpose register. */
+ purpose register. */
if (argreg <= MIPS_LAST_ARG_REGNUM
&& !fp_register_arg_p (typecode, arg_type))
{
@@ -3800,7 +4216,8 @@ mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
if (mips_debug)
fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
argreg,
- phex (regval, mips_saved_regsize (tdep)));
+ phex (regval,
+ mips_saved_regsize (tdep)));
write_register (argreg, regval);
argreg++;
@@ -3813,12 +4230,12 @@ mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
val += partial_len;
/* Compute the the offset into the stack at which we
- will copy the next parameter.
+ will copy the next parameter.
- In older ABIs, the caller reserved space for
- registers that contained arguments. This was loosely
- refered to as their "home". Consequently, space is
- always allocated. */
+ In older ABIs, the caller reserved space for
+ registers that contained arguments. This was loosely
+ refered to as their "home". Consequently, space is
+ always allocated. */
stack_offset += align_up (partial_len,
mips_stack_argsize (tdep));
@@ -3835,6 +4252,49 @@ mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
}
static void
+mips_o64_extract_return_value (struct type *valtype,
+ char regbuf[], char *valbuf)
+{
+ struct return_value_word lo;
+ struct return_value_word hi;
+ return_value_location (valtype, &hi, &lo);
+
+ memcpy (valbuf + lo.buf_offset,
+ regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) +
+ lo.reg_offset, lo.len);
+
+ if (hi.len > 0)
+ memcpy (valbuf + hi.buf_offset,
+ regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) +
+ hi.reg_offset, hi.len);
+}
+
+static void
+mips_o64_store_return_value (struct type *valtype, char *valbuf)
+{
+ char raw_buffer[MAX_REGISTER_SIZE];
+ struct return_value_word lo;
+ struct return_value_word hi;
+ return_value_location (valtype, &hi, &lo);
+
+ memset (raw_buffer, 0, sizeof (raw_buffer));
+ memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len);
+ deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg),
+ raw_buffer, register_size (current_gdbarch,
+ lo.reg));
+
+ if (hi.len > 0)
+ {
+ memset (raw_buffer, 0, sizeof (raw_buffer));
+ memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len);
+ deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg),
+ raw_buffer,
+ register_size (current_gdbarch,
+ hi.reg));
+ }
+}
+
+static void
mips_pop_frame (void)
{
int regnum;
@@ -3860,13 +4320,16 @@ mips_pop_frame (void)
/* Floating point registers must not be sign extended, in case
mips_saved_regsize() = 4 but sizeof (FP0_REGNUM) == 8. */
- if (mips_regnum (current_gdbarch)->fp0 <= regnum && regnum < mips_regnum (current_gdbarch)->fp0 + 32)
+ if (mips_regnum (current_gdbarch)->fp0 <= regnum
+ && regnum < mips_regnum (current_gdbarch)->fp0 + 32)
write_register (regnum,
- read_memory_unsigned_integer (deprecated_get_frame_saved_regs (frame)[regnum],
- mips_saved_regsize (tdep)));
+ read_memory_unsigned_integer
+ (deprecated_get_frame_saved_regs (frame)[regnum],
+ mips_saved_regsize (tdep)));
else
write_register (regnum,
- read_memory_integer (deprecated_get_frame_saved_regs (frame)[regnum],
+ read_memory_integer (deprecated_get_frame_saved_regs
+ (frame)[regnum],
mips_saved_regsize (tdep)));
}
@@ -3878,8 +4341,7 @@ mips_pop_frame (void)
struct linked_proc_info *pi_ptr, *prev_ptr;
for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL;
- pi_ptr != NULL;
- prev_ptr = pi_ptr, pi_ptr = pi_ptr->next)
+ pi_ptr != NULL; prev_ptr = pi_ptr, pi_ptr = pi_ptr->next)
{
if (&pi_ptr->info == proc_desc)
break;
@@ -3906,7 +4368,8 @@ mips_pop_frame (void)
if (MIPS_FPU_TYPE != MIPS_FPU_NONE)
write_register (mips_regnum (current_gdbarch)->fp_control_status,
read_memory_integer ((new_sp
- - 4 * mips_saved_regsize (tdep)),
+ -
+ 4 * mips_saved_regsize (tdep)),
mips_saved_regsize (tdep)));
}
}
@@ -3974,7 +4437,7 @@ mips_read_fp_register_single (struct frame_info *frame, int regno,
if (raw_size == 8)
{
/* We have a 64-bit value for this register. Find the low-order
- 32 bits. */
+ 32 bits. */
int offset;
if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
@@ -4003,7 +4466,7 @@ mips_read_fp_register_double (struct frame_info *frame, int regno,
if (raw_size == 8 && !mips2_fp_compat ())
{
/* We have a 64-bit value for this register, and we should use
- all 64 bits. */
+ all 64 bits. */
if (!frame_register_read (frame, regno, rare_buffer))
error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
}
@@ -4015,7 +4478,7 @@ mips_read_fp_register_double (struct frame_info *frame, int regno,
"odd-numbered FP register");
/* mips_read_fp_register_single will find the correct 32 bits from
- each register. */
+ each register. */
if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
{
mips_read_fp_register_single (frame, regno, rare_buffer + 4);
@@ -4037,7 +4500,10 @@ mips_print_fp_register (struct ui_file *file, struct frame_info *frame,
double doub, flt1, flt2; /* doubles extracted from raw hex data */
int inv1, inv2, namelen;
- raw_buffer = (char *) alloca (2 * register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0));
+ raw_buffer =
+ (char *) alloca (2 *
+ register_size (current_gdbarch,
+ mips_regnum (current_gdbarch)->fp0));
fprintf_filtered (file, "%s:", REGISTER_NAME (regnum));
fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)),
@@ -4050,7 +4516,8 @@ mips_print_fp_register (struct ui_file *file, struct frame_info *frame,
mips_read_fp_register_single (frame, regnum, raw_buffer);
flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
- print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', file);
+ print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w',
+ file);
fprintf_filtered (file, " flt: ");
if (inv1)
@@ -4062,7 +4529,7 @@ mips_print_fp_register (struct ui_file *file, struct frame_info *frame,
{
mips_read_fp_register_double (frame, regnum, raw_buffer);
doub = unpack_double (mips_double_register_type (), raw_buffer,
- &inv2);
+ &inv2);
fprintf_filtered (file, " dbl: ");
if (inv2)
@@ -4081,7 +4548,8 @@ mips_print_fp_register (struct ui_file *file, struct frame_info *frame,
doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2);
- print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', file);
+ print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g',
+ file);
fprintf_filtered (file, " flt: ");
if (inv1)
@@ -4130,12 +4598,15 @@ mips_print_register (struct ui_file *file, struct frame_info *frame,
fprintf_filtered (file, ": ");
if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
- offset = register_size (current_gdbarch, regnum) - register_size (current_gdbarch, regnum);
+ offset =
+ register_size (current_gdbarch,
+ regnum) - register_size (current_gdbarch, regnum);
else
offset = 0;
- print_scalar_formatted (raw_buffer + offset, gdbarch_register_type (gdbarch, regnum),
- 'x', 0, file);
+ print_scalar_formatted (raw_buffer + offset,
+ gdbarch_register_type (gdbarch, regnum), 'x', 0,
+ file);
}
/* Replacement for generic do_registers_info.
@@ -4168,14 +4639,15 @@ print_gp_register_row (struct ui_file *file, struct frame_info *frame,
/* For GP registers, we print a separate row of names above the vals */
fprintf_filtered (file, " ");
for (col = 0, regnum = start_regnum;
- col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS;
- regnum++)
+ col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
{
if (*REGISTER_NAME (regnum) == '\0')
continue; /* unused register */
- if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
+ if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
+ TYPE_CODE_FLT)
break; /* end the row: reached FP register */
- fprintf_filtered (file, mips_regsize (current_gdbarch) == 8 ? "%17s" : "%9s",
+ fprintf_filtered (file,
+ mips_regsize (current_gdbarch) == 8 ? "%17s" : "%9s",
REGISTER_NAME (regnum));
col++;
}
@@ -4187,12 +4659,12 @@ print_gp_register_row (struct ui_file *file, struct frame_info *frame,
/* now print the values in hex, 4 or 8 to the row */
for (col = 0, regnum = start_regnum;
- col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS;
- regnum++)
+ col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
{
if (*REGISTER_NAME (regnum) == '\0')
continue; /* unused register */
- if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
+ if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
+ TYPE_CODE_FLT)
break; /* end row: reached FP register */
/* OK: get the data in raw format. */
if (!frame_register_read (frame, regnum, raw_buffer))
@@ -4200,19 +4672,18 @@ print_gp_register_row (struct ui_file *file, struct frame_info *frame,
/* pad small registers */
for (byte = 0;
byte < (mips_regsize (current_gdbarch)
- - register_size (current_gdbarch, regnum));
- byte++)
+ - register_size (current_gdbarch, regnum)); byte++)
printf_filtered (" ");
/* Now print the register value in hex, endian order. */
if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
- for (byte = register_size (current_gdbarch, regnum) - register_size (current_gdbarch, regnum);
- byte < register_size (current_gdbarch, regnum);
- byte++)
+ for (byte =
+ register_size (current_gdbarch,
+ regnum) - register_size (current_gdbarch, regnum);
+ byte < register_size (current_gdbarch, regnum); byte++)
fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]);
else
for (byte = register_size (current_gdbarch, regnum) - 1;
- byte >= 0;
- byte--)
+ byte >= 0; byte--)
fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]);
fprintf_filtered (file, " ");
col++;
@@ -4244,7 +4715,8 @@ mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
regnum = NUM_REGS;
while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
{
- if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
+ if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
+ TYPE_CODE_FLT)
{
if (all) /* true for "INFO ALL-REGISTERS" command */
regnum = print_fp_register_row (file, frame, regnum);
@@ -4287,7 +4759,8 @@ mips_step_skips_delay (CORE_ADDR pc)
if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0)
/* If error reading memory, guess that it is not a delayed branch. */
return 0;
- return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN));
+ return is_delayed ((unsigned long)
+ extract_unsigned_integer (buf, MIPS_INSTLEN));
}
@@ -4330,7 +4803,7 @@ skip_prologue_using_sal (CORE_ADDR func_addr)
if (sal.line == 0)
break;
/* Assume that a consecutive SAL for the same (or larger)
- line mark the prologue -> body transition. */
+ line mark the prologue -> body transition. */
if (sal.line >= prologue_sal.line)
break;
/* The case in which compiler's optimizer/scheduler has
@@ -4360,7 +4833,7 @@ mips32_skip_prologue (CORE_ADDR pc)
/* Find an upper bound on the prologue. */
end_pc = skip_prologue_using_sal (pc);
if (end_pc == 0)
- end_pc = pc + 100; /* Magic. */
+ end_pc = pc + 100; /* Magic. */
/* Skip the typical prologue instructions. These are the stack adjustment
instruction and the instructions that save registers on the stack
@@ -4420,7 +4893,7 @@ mips32_skip_prologue (CORE_ADDR pc)
else if (high_word == 0x3421 || /* ori $at,$at,n */
high_word == 0x3508 || /* ori $t0,$t0,n */
high_word == 0x3401 || /* ori $at,$zero,n */
- high_word == 0x3408) /* ori $t0,$zero,n */
+ high_word == 0x3408) /* ori $t0,$zero,n */
{
load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
continue;
@@ -4452,65 +4925,53 @@ mips16_skip_prologue (CORE_ADDR pc)
/* Table of instructions likely to be found in a function prologue. */
static struct
- {
- unsigned short inst;
- unsigned short mask;
- }
+ {
+ unsigned short inst;
+ unsigned short mask;
+ }
table[] =
{
{
- 0x6300, 0xff00
- }
+ 0x6300, 0xff00}
, /* addiu $sp,offset */
{
- 0xfb00, 0xff00
- }
+ 0xfb00, 0xff00}
, /* daddiu $sp,offset */
{
- 0xd000, 0xf800
- }
+ 0xd000, 0xf800}
, /* sw reg,n($sp) */
{
- 0xf900, 0xff00
- }
+ 0xf900, 0xff00}
, /* sd reg,n($sp) */
{
- 0x6200, 0xff00
- }
+ 0x6200, 0xff00}
, /* sw $ra,n($sp) */
{
- 0xfa00, 0xff00
- }
+ 0xfa00, 0xff00}
, /* sd $ra,n($sp) */
{
- 0x673d, 0xffff
- }
+ 0x673d, 0xffff}
, /* move $s1,sp */
{
- 0xd980, 0xff80
- }
+ 0xd980, 0xff80}
, /* sw $a0-$a3,n($s1) */
{
- 0x6704, 0xff1c
- }
+ 0x6704, 0xff1c}
, /* move reg,$a0-$a3 */
{
- 0xe809, 0xf81f
- }
+ 0xe809, 0xf81f}
, /* entry pseudo-op */
{
- 0x0100, 0xff00
- }
+ 0x0100, 0xff00}
, /* addiu $s1,$sp,n */
{
- 0, 0
- } /* end of table marker */
+ 0, 0} /* end of table marker */
};
/* Find an upper bound on the prologue. */
end_pc = skip_prologue_using_sal (pc);
if (end_pc == 0)
- end_pc = pc + 100; /* Magic. */
+ end_pc = pc + 100; /* Magic. */
/* Skip the typical prologue instructions. These are the stack adjustment
instruction and the instructions that save registers on the stack
@@ -4581,456 +5042,6 @@ mips_skip_prologue (CORE_ADDR pc)
return mips32_skip_prologue (pc);
}
-/* Determine how a return value is stored within the MIPS register
- file, given the return type `valtype'. */
-
-struct return_value_word
-{
- int len;
- int reg;
- int reg_offset;
- int buf_offset;
-};
-
-static void
-return_value_location (struct type *valtype,
- struct return_value_word *hi,
- struct return_value_word *lo)
-{
- int len = TYPE_LENGTH (valtype);
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
-
- if (TYPE_CODE (valtype) == TYPE_CODE_FLT
- && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8))
- || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4)))
- {
- if (!FP_REGISTER_DOUBLE && len == 8)
- {
- /* We need to break a 64bit float in two 32 bit halves and
- spread them across a floating-point register pair. */
- lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
- hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4;
- lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
- && register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == 8)
- ? 4 : 0);
- hi->reg_offset = lo->reg_offset;
- lo->reg = mips_regnum (current_gdbarch)->fp0 + 0;
- hi->reg = mips_regnum (current_gdbarch)->fp0 + 1;
- lo->len = 4;
- hi->len = 4;
- }
- else
- {
- /* The floating point value fits in a single floating-point
- register. */
- lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
- && register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == 8
- && len == 4)
- ? 4 : 0);
- lo->reg = mips_regnum (current_gdbarch)->fp0;
- lo->len = len;
- lo->buf_offset = 0;
- hi->len = 0;
- hi->reg_offset = 0;
- hi->buf_offset = 0;
- hi->reg = 0;
- }
- }
- else
- {
- /* Locate a result possibly spread across two registers. */
- int regnum = 2;
- lo->reg = regnum + 0;
- hi->reg = regnum + 1;
- if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
- && len < mips_saved_regsize (tdep))
- {
- /* "un-left-justify" the value in the low register */
- lo->reg_offset = mips_saved_regsize (tdep) - len;
- lo->len = len;
- hi->reg_offset = 0;
- hi->len = 0;
- }
- else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
- && len > mips_saved_regsize (tdep) /* odd-size structs */
- && len < mips_saved_regsize (tdep) * 2
- && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT ||
- TYPE_CODE (valtype) == TYPE_CODE_UNION))
- {
- /* "un-left-justify" the value spread across two registers. */
- lo->reg_offset = 2 * mips_saved_regsize (tdep) - len;
- lo->len = mips_saved_regsize (tdep) - lo->reg_offset;
- hi->reg_offset = 0;
- hi->len = len - lo->len;
- }
- else
- {
- /* Only perform a partial copy of the second register. */
- lo->reg_offset = 0;
- hi->reg_offset = 0;
- if (len > mips_saved_regsize (tdep))
- {
- lo->len = mips_saved_regsize (tdep);
- hi->len = len - mips_saved_regsize (tdep);
- }
- else
- {
- lo->len = len;
- hi->len = 0;
- }
- }
- if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
- && register_size (current_gdbarch, regnum) == 8
- && mips_saved_regsize (tdep) == 4)
- {
- /* Account for the fact that only the least-signficant part
- of the register is being used */
- lo->reg_offset += 4;
- hi->reg_offset += 4;
- }
- lo->buf_offset = 0;
- hi->buf_offset = lo->len;
- }
-}
-
-/* Given a return value in `regbuf' with a type `valtype', extract and
- copy its value into `valbuf'. */
-
-static void
-mips_eabi_extract_return_value (struct type *valtype,
- char regbuf[],
- char *valbuf)
-{
- struct return_value_word lo;
- struct return_value_word hi;
- return_value_location (valtype, &hi, &lo);
-
- memcpy (valbuf + lo.buf_offset,
- regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) + lo.reg_offset,
- lo.len);
-
- if (hi.len > 0)
- memcpy (valbuf + hi.buf_offset,
- regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) + hi.reg_offset,
- hi.len);
-}
-
-static void
-mips_o64_extract_return_value (struct type *valtype,
- char regbuf[],
- char *valbuf)
-{
- struct return_value_word lo;
- struct return_value_word hi;
- return_value_location (valtype, &hi, &lo);
-
- memcpy (valbuf + lo.buf_offset,
- regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) + lo.reg_offset,
- lo.len);
-
- if (hi.len > 0)
- memcpy (valbuf + hi.buf_offset,
- regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) + hi.reg_offset,
- hi.len);
-}
-
-/* Given a return value in `valbuf' with a type `valtype', write it's
- value into the appropriate register. */
-
-static void
-mips_eabi_store_return_value (struct type *valtype, char *valbuf)
-{
- char raw_buffer[MAX_REGISTER_SIZE];
- struct return_value_word lo;
- struct return_value_word hi;
- return_value_location (valtype, &hi, &lo);
-
- memset (raw_buffer, 0, sizeof (raw_buffer));
- memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len);
- deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), raw_buffer,
- register_size (current_gdbarch, lo.reg));
-
- if (hi.len > 0)
- {
- memset (raw_buffer, 0, sizeof (raw_buffer));
- memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len);
- deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), raw_buffer,
- register_size (current_gdbarch, hi.reg));
- }
-}
-
-static void
-mips_o64_store_return_value (struct type *valtype, char *valbuf)
-{
- char raw_buffer[MAX_REGISTER_SIZE];
- struct return_value_word lo;
- struct return_value_word hi;
- return_value_location (valtype, &hi, &lo);
-
- memset (raw_buffer, 0, sizeof (raw_buffer));
- memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len);
- deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg), raw_buffer,
- register_size (current_gdbarch, lo.reg));
-
- if (hi.len > 0)
- {
- memset (raw_buffer, 0, sizeof (raw_buffer));
- memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len);
- deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg), raw_buffer,
- register_size (current_gdbarch, hi.reg));
- }
-}
-
-/* O32 ABI stuff. */
-
-static enum return_value_convention
-mips_o32_return_value (struct gdbarch *gdbarch, struct type *type,
- struct regcache *regcache,
- void *readbuf, const void *writebuf)
-{
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
-
- if (TYPE_CODE (type)== TYPE_CODE_STRUCT
- || TYPE_CODE (type)== TYPE_CODE_UNION
- || TYPE_CODE (type)== TYPE_CODE_ARRAY)
- return RETURN_VALUE_STRUCT_CONVENTION;
- else if (TYPE_CODE (type) == TYPE_CODE_FLT
- && TYPE_LENGTH (type) == 4
- && tdep->mips_fpu_type != MIPS_FPU_NONE)
- {
- /* A single-precision floating-point value. It fits in the
- least significant part of FP0. */
- if (mips_debug)
- fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
- mips_xfer_register (regcache,
- NUM_REGS + mips_regnum (current_gdbarch)->fp0,
- TYPE_LENGTH (type),
- TARGET_BYTE_ORDER, readbuf, writebuf, 0);
- return RETURN_VALUE_REGISTER_CONVENTION;
- }
- else if (TYPE_CODE (type) == TYPE_CODE_FLT
- && TYPE_LENGTH (type) == 8
- && tdep->mips_fpu_type != MIPS_FPU_NONE)
- {
- /* A double-precision floating-point value. The most
- significant part goes in FP1, and the least significant in
- FP0. */
- if (mips_debug)
- fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n");
- switch (TARGET_BYTE_ORDER)
- {
- case BFD_ENDIAN_LITTLE:
- mips_xfer_register (regcache,
- NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 0,
- 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0);
- mips_xfer_register (regcache,
- NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 1,
- 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4);
- break;
- case BFD_ENDIAN_BIG:
- mips_xfer_register (regcache,
- NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 1,
- 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0);
- mips_xfer_register (regcache,
- NUM_REGS + mips_regnum (current_gdbarch)->fp0 + 0,
- 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4);
- break;
- default:
- internal_error (__FILE__, __LINE__, "bad switch");
- }
- return RETURN_VALUE_REGISTER_CONVENTION;
- }
-#if 0
- else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
- && TYPE_NFIELDS (type) <= 2
- && TYPE_NFIELDS (type) >= 1
- && ((TYPE_NFIELDS (type) == 1
- && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
- == TYPE_CODE_FLT))
- || (TYPE_NFIELDS (type) == 2
- && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
- == TYPE_CODE_FLT)
- && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
- == TYPE_CODE_FLT)))
- && tdep->mips_fpu_type != MIPS_FPU_NONE)
- {
- /* A struct that contains one or two floats. Each value is part
- in the least significant part of their floating point
- register.. */
- bfd_byte reg[MAX_REGISTER_SIZE];
- int regnum;
- int field;
- for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0;
- field < TYPE_NFIELDS (type);
- field++, regnum += 2)
- {
- int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
- / TARGET_CHAR_BIT);
- if (mips_debug)
- fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset);
- mips_xfer_register (regcache, NUM_REGS + regnum,
- TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
- TARGET_BYTE_ORDER, readbuf, writebuf, offset);
- }
- return RETURN_VALUE_REGISTER_CONVENTION;
- }
-#endif
-#if 0
- else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
- || TYPE_CODE (type) == TYPE_CODE_UNION)
- {
- /* A structure or union. Extract the left justified value,
- regardless of the byte order. I.e. DO NOT USE
- mips_xfer_lower. */
- int offset;
- int regnum;
- for (offset = 0, regnum = V0_REGNUM;
- offset < TYPE_LENGTH (type);
- offset += register_size (current_gdbarch, regnum), regnum++)
- {
- int xfer = register_size (current_gdbarch, regnum);
- if (offset + xfer > TYPE_LENGTH (type))
- xfer = TYPE_LENGTH (type) - offset;
- if (mips_debug)
- fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
- offset, xfer, regnum);
- mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
- BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset);
- }
- return RETURN_VALUE_REGISTER_CONVENTION;
- }
-#endif
- else
- {
- /* A scalar extract each part but least-significant-byte
- justified. o32 thinks registers are 4 byte, regardless of
- the ISA. mips_stack_argsize controls this. */
- int offset;
- int regnum;
- for (offset = 0, regnum = V0_REGNUM;
- offset < TYPE_LENGTH (type);
- offset += mips_stack_argsize (tdep), regnum++)
- {
- int xfer = mips_stack_argsize (tdep);
- int pos = 0;
- if (offset + xfer > TYPE_LENGTH (type))
- xfer = TYPE_LENGTH (type) - offset;
- if (mips_debug)
- fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
- offset, xfer, regnum);
- mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
- TARGET_BYTE_ORDER, readbuf, writebuf, offset);
- }
- return RETURN_VALUE_REGISTER_CONVENTION;
- }
-}
-
-/* N32/N44 ABI stuff. */
-
-static enum return_value_convention
-mips_n32n64_return_value (struct gdbarch *gdbarch,
- struct type *type, struct regcache *regcache,
- void *readbuf, const void *writebuf)
-{
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
- if (TYPE_CODE (type)== TYPE_CODE_STRUCT
- || TYPE_CODE (type)== TYPE_CODE_UNION
- || TYPE_CODE (type)== TYPE_CODE_ARRAY
- || TYPE_LENGTH (type) > 2 * mips_saved_regsize (tdep))
- return RETURN_VALUE_STRUCT_CONVENTION;
- else if (TYPE_CODE (type) == TYPE_CODE_FLT
- && tdep->mips_fpu_type != MIPS_FPU_NONE)
- {
- /* A floating-point value belongs in the least significant part
- of FP0. */
- if (mips_debug)
- fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
- mips_xfer_register (regcache,
- NUM_REGS + mips_regnum (current_gdbarch)->fp0,
- TYPE_LENGTH (type),
- TARGET_BYTE_ORDER, readbuf, writebuf, 0);
- return RETURN_VALUE_REGISTER_CONVENTION;
- }
- else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
- && TYPE_NFIELDS (type) <= 2
- && TYPE_NFIELDS (type) >= 1
- && ((TYPE_NFIELDS (type) == 1
- && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
- == TYPE_CODE_FLT))
- || (TYPE_NFIELDS (type) == 2
- && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
- == TYPE_CODE_FLT)
- && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
- == TYPE_CODE_FLT)))
- && tdep->mips_fpu_type != MIPS_FPU_NONE)
- {
- /* A struct that contains one or two floats. Each value is part
- in the least significant part of their floating point
- register.. */
- bfd_byte reg[MAX_REGISTER_SIZE];
- int regnum;
- int field;
- for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0;
- field < TYPE_NFIELDS (type);
- field++, regnum += 2)
- {
- int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
- / TARGET_CHAR_BIT);
- if (mips_debug)
- fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", offset);
- mips_xfer_register (regcache, NUM_REGS + regnum,
- TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
- TARGET_BYTE_ORDER, readbuf, writebuf, offset);
- }
- return RETURN_VALUE_REGISTER_CONVENTION;
- }
- else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
- || TYPE_CODE (type) == TYPE_CODE_UNION)
- {
- /* A structure or union. Extract the left justified value,
- regardless of the byte order. I.e. DO NOT USE
- mips_xfer_lower. */
- int offset;
- int regnum;
- for (offset = 0, regnum = V0_REGNUM;
- offset < TYPE_LENGTH (type);
- offset += register_size (current_gdbarch, regnum), regnum++)
- {
- int xfer = register_size (current_gdbarch, regnum);
- if (offset + xfer > TYPE_LENGTH (type))
- xfer = TYPE_LENGTH (type) - offset;
- if (mips_debug)
- fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
- offset, xfer, regnum);
- mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
- BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset);
- }
- return RETURN_VALUE_REGISTER_CONVENTION;
- }
- else
- {
- /* A scalar extract each part but least-significant-byte
- justified. */
- int offset;
- int regnum;
- for (offset = 0, regnum = V0_REGNUM;
- offset < TYPE_LENGTH (type);
- offset += register_size (current_gdbarch, regnum), regnum++)
- {
- int xfer = register_size (current_gdbarch, regnum);
- int pos = 0;
- if (offset + xfer > TYPE_LENGTH (type))
- xfer = TYPE_LENGTH (type) - offset;
- if (mips_debug)
- fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
- offset, xfer, regnum);
- mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
- TARGET_BYTE_ORDER, readbuf, writebuf, offset);
- }
- return RETURN_VALUE_REGISTER_CONVENTION;
- }
-}
-
/* Exported procedure: Is PC in the signal trampoline code */
static int
@@ -5053,7 +5064,8 @@ show_mips_command (char *args, int from_tty)
static void
set_mips_command (char *args, int from_tty)
{
- printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
+ printf_unfiltered
+ ("\"set mips\" must be followed by an appropriate subcommand.\n");
help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
}
@@ -5078,18 +5090,20 @@ show_mipsfpu_command (char *args, int from_tty)
internal_error (__FILE__, __LINE__, "bad switch");
}
if (mips_fpu_type_auto)
- printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
- fpu);
+ printf_unfiltered
+ ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
+ fpu);
else
- printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
- fpu);
+ printf_unfiltered
+ ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu);
}
static void
set_mipsfpu_command (char *args, int from_tty)
{
- printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
+ printf_unfiltered
+ ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
show_mipsfpu_command (args, from_tty);
}
@@ -5194,23 +5208,22 @@ gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info)
if (proc_desc)
{
if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc)))
- info->mach = bfd_mach_mips16;
+ info->mach = bfd_mach_mips16;
}
else
{
if (pc_is_mips16 (memaddr))
- info->mach = bfd_mach_mips16;
- }
+ info->mach = bfd_mach_mips16;
+ }
/* Round down the instruction address to the appropriate boundary. */
memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3);
/* Set the disassembler options. */
- if (tdep->mips_abi == MIPS_ABI_N32
- || tdep->mips_abi == MIPS_ABI_N64)
+ if (tdep->mips_abi == MIPS_ABI_N32 || tdep->mips_abi == MIPS_ABI_N64)
{
/* Set up the disassembler info, so that we get the right
- register names from libopcodes. */
+ register names from libopcodes. */
if (tdep->mips_abi == MIPS_ABI_N32)
info->disassembler_options = "gpr-names=n32";
else
@@ -5240,13 +5253,13 @@ gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info)
breakpoint should be inserted. */
static const unsigned char *
-mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr)
+mips_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
{
if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
{
if (pc_is_mips16 (*pcptr))
{
- static unsigned char mips16_big_breakpoint[] = {0xe8, 0xa5};
+ static unsigned char mips16_big_breakpoint[] = { 0xe8, 0xa5 };
*pcptr = unmake_mips16_addr (*pcptr);
*lenptr = sizeof (mips16_big_breakpoint);
return mips16_big_breakpoint;
@@ -5256,9 +5269,9 @@ mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr)
/* The IDT board uses an unusual breakpoint value, and
sometimes gets confused when it sees the usual MIPS
breakpoint instruction. */
- static unsigned char big_breakpoint[] = {0, 0x5, 0, 0xd};
- static unsigned char pmon_big_breakpoint[] = {0, 0, 0, 0xd};
- static unsigned char idt_big_breakpoint[] = {0, 0, 0x0a, 0xd};
+ static unsigned char big_breakpoint[] = { 0, 0x5, 0, 0xd };
+ static unsigned char pmon_big_breakpoint[] = { 0, 0, 0, 0xd };
+ static unsigned char idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd };
*lenptr = sizeof (big_breakpoint);
@@ -5276,16 +5289,16 @@ mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr)
{
if (pc_is_mips16 (*pcptr))
{
- static unsigned char mips16_little_breakpoint[] = {0xa5, 0xe8};
+ static unsigned char mips16_little_breakpoint[] = { 0xa5, 0xe8 };
*pcptr = unmake_mips16_addr (*pcptr);
*lenptr = sizeof (mips16_little_breakpoint);
return mips16_little_breakpoint;
}
else
{
- static unsigned char little_breakpoint[] = {0xd, 0, 0x5, 0};
- static unsigned char pmon_little_breakpoint[] = {0xd, 0, 0, 0};
- static unsigned char idt_little_breakpoint[] = {0xd, 0x0a, 0, 0};
+ static unsigned char little_breakpoint[] = { 0xd, 0, 0x5, 0 };
+ static unsigned char pmon_little_breakpoint[] = { 0xd, 0, 0, 0 };
+ static unsigned char idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 };
*lenptr = sizeof (little_breakpoint);
@@ -5368,7 +5381,8 @@ mips_skip_stub (CORE_ADDR pc)
int i;
/* See if the name of the target function is __fn_stub_*. */
- if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0)
+ if (find_pc_partial_function (target_pc, &name, NULL, NULL) ==
+ 0)
return target_pc;
if (strncmp (name, "__fn_stub_", 10) != 0
&& strcmp (name, "etext") != 0
@@ -5410,7 +5424,8 @@ mips_in_call_stub (CORE_ADDR pc, char *name)
/* Find the starting address of the function containing the PC. If the
caller didn't give us a name, look it up at the same time. */
- if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0)
+ if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) ==
+ 0)
return 0;
if (strncmp (name, "__mips16_call_stub_", 19) == 0)
@@ -5448,8 +5463,7 @@ mips_in_return_stub (CORE_ADDR pc, char *name)
/* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
i.e. after the jal instruction, this is effectively a return stub. */
if (strncmp (name, "__mips16_call_stub_", 19) == 0
- && (name[19] == 's' || name[19] == 'd')
- && pc != start_addr)
+ && (name[19] == 's' || name[19] == 'd') && pc != start_addr)
return 1;
return 0; /* not a stub */
@@ -5489,8 +5503,7 @@ mips_get_saved_register (char *raw_buffer,
int *optimizedp,
CORE_ADDR *addrp,
struct frame_info *frame,
- int regnum,
- enum lval_type *lvalp)
+ int regnum, enum lval_type *lvalp)
{
CORE_ADDR addrx;
enum lval_type lvalx;
@@ -5592,7 +5605,7 @@ mips_register_sim_regno (int regnum)
&& REGISTER_NAME (NUM_REGS + regnum)[0] != '\0')
return regnum;
else
- return LEGACY_SIM_REGNO_IGNORE;
+ return LEGACY_SIM_REGNO_IGNORE;
}
@@ -5647,13 +5660,11 @@ global_mips_abi (void)
if (mips_abi_strings[i] == mips_abi_string)
return (enum mips_abi) i;
- internal_error (__FILE__, __LINE__,
- "unknown ABI string");
+ internal_error (__FILE__, __LINE__, "unknown ABI string");
}
static struct gdbarch *
-mips_gdbarch_init (struct gdbarch_info info,
- struct gdbarch_list *arches)
+mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
{
struct gdbarch *gdbarch;
struct gdbarch_tdep *tdep;
@@ -5671,8 +5682,7 @@ mips_gdbarch_init (struct gdbarch_info info,
elf_flags = 0;
if (gdbarch_debug)
fprintf_unfiltered (gdb_stdlog,
- "mips_gdbarch_init: elf_flags = 0x%08x\n",
- elf_flags);
+ "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags);
/* Check ELF_FLAGS to see if it specifies the ABI being used. */
switch ((elf_flags & EF_MIPS_ABI))
@@ -5787,8 +5797,7 @@ mips_gdbarch_init (struct gdbarch_info info,
fpu_type = MIPS_FPU_DOUBLE;
if (gdbarch_debug)
fprintf_unfiltered (gdb_stdlog,
- "mips_gdbarch_init: fpu_type = %d\n",
- fpu_type);
+ "mips_gdbarch_init: fpu_type = %d\n", fpu_type);
/* try to find a pre-existing architecture */
for (arches = gdbarch_list_lookup_by_info (arches, &info);
@@ -5831,7 +5840,7 @@ mips_gdbarch_init (struct gdbarch_info info,
set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read);
set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write);
- set_gdbarch_elf_make_msymbol_special (gdbarch,
+ set_gdbarch_elf_make_msymbol_special (gdbarch,
mips_elf_make_msymbol_special);
/* Fill in the OS dependant register numbers and names. */
@@ -5897,8 +5906,10 @@ mips_gdbarch_init (struct gdbarch_info info,
break;
case MIPS_ABI_O64:
set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call);
- set_gdbarch_deprecated_store_return_value (gdbarch, mips_o64_store_return_value);
- set_gdbarch_deprecated_extract_return_value (gdbarch, mips_o64_extract_return_value);
+ set_gdbarch_deprecated_store_return_value (gdbarch,
+ mips_o64_store_return_value);
+ set_gdbarch_deprecated_extract_return_value (gdbarch,
+ mips_o64_extract_return_value);
tdep->mips_default_saved_regsize = 8;
tdep->mips_default_stack_argsize = 8;
tdep->mips_fp_register_double = 1;
@@ -5908,12 +5919,15 @@ mips_gdbarch_init (struct gdbarch_info info,
set_gdbarch_long_bit (gdbarch, 32);
set_gdbarch_ptr_bit (gdbarch, 32);
set_gdbarch_long_long_bit (gdbarch, 64);
- set_gdbarch_use_struct_convention (gdbarch, always_use_struct_convention);
+ set_gdbarch_use_struct_convention (gdbarch,
+ always_use_struct_convention);
break;
case MIPS_ABI_EABI32:
set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
- set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value);
- set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value);
+ set_gdbarch_deprecated_store_return_value (gdbarch,
+ mips_eabi_store_return_value);
+ set_gdbarch_deprecated_extract_return_value (gdbarch,
+ mips_eabi_extract_return_value);
tdep->mips_default_saved_regsize = 4;
tdep->mips_default_stack_argsize = 4;
tdep->mips_fp_register_double = 0;
@@ -5925,13 +5939,15 @@ mips_gdbarch_init (struct gdbarch_info info,
set_gdbarch_long_long_bit (gdbarch, 64);
set_gdbarch_deprecated_reg_struct_has_addr
(gdbarch, mips_eabi_reg_struct_has_addr);
- set_gdbarch_use_struct_convention (gdbarch,
+ set_gdbarch_use_struct_convention (gdbarch,
mips_eabi_use_struct_convention);
break;
case MIPS_ABI_EABI64:
set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
- set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value);
- set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value);
+ set_gdbarch_deprecated_store_return_value (gdbarch,
+ mips_eabi_store_return_value);
+ set_gdbarch_deprecated_extract_return_value (gdbarch,
+ mips_eabi_extract_return_value);
tdep->mips_default_saved_regsize = 8;
tdep->mips_default_stack_argsize = 8;
tdep->mips_fp_register_double = 1;
@@ -5943,7 +5959,7 @@ mips_gdbarch_init (struct gdbarch_info info,
set_gdbarch_long_long_bit (gdbarch, 64);
set_gdbarch_deprecated_reg_struct_has_addr
(gdbarch, mips_eabi_reg_struct_has_addr);
- set_gdbarch_use_struct_convention (gdbarch,
+ set_gdbarch_use_struct_convention (gdbarch,
mips_eabi_use_struct_convention);
break;
case MIPS_ABI_N32:
@@ -5973,8 +5989,7 @@ mips_gdbarch_init (struct gdbarch_info info,
set_gdbarch_long_long_bit (gdbarch, 64);
break;
default:
- internal_error (__FILE__, __LINE__,
- "unknown ABI in switch");
+ internal_error (__FILE__, __LINE__, "unknown ABI in switch");
}
/* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
@@ -6000,7 +6015,7 @@ mips_gdbarch_init (struct gdbarch_info info,
set_gdbarch_read_pc (gdbarch, mips_read_pc);
set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
- set_gdbarch_deprecated_target_read_fp (gdbarch, mips_read_sp); /* Draft FRAME base. */
+ set_gdbarch_deprecated_target_read_fp (gdbarch, mips_read_sp); /* Draft FRAME base. */
set_gdbarch_read_sp (gdbarch, mips_read_sp);
/* Add/remove bits from an address. The MIPS needs be careful to
@@ -6009,18 +6024,24 @@ mips_gdbarch_init (struct gdbarch_info info,
/* There's a mess in stack frame creation. See comments in
blockframe.c near reference to DEPRECATED_INIT_FRAME_PC_FIRST. */
- set_gdbarch_deprecated_init_frame_pc_first (gdbarch, mips_init_frame_pc_first);
+ set_gdbarch_deprecated_init_frame_pc_first (gdbarch,
+ mips_init_frame_pc_first);
/* Map debug register numbers onto internal register numbers. */
set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum);
- set_gdbarch_ecoff_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum);
- set_gdbarch_dwarf_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum);
- set_gdbarch_dwarf2_reg_to_regnum (gdbarch, mips_dwarf_dwarf2_ecoff_reg_to_regnum);
+ set_gdbarch_ecoff_reg_to_regnum (gdbarch,
+ mips_dwarf_dwarf2_ecoff_reg_to_regnum);
+ set_gdbarch_dwarf_reg_to_regnum (gdbarch,
+ mips_dwarf_dwarf2_ecoff_reg_to_regnum);
+ set_gdbarch_dwarf2_reg_to_regnum (gdbarch,
+ mips_dwarf_dwarf2_ecoff_reg_to_regnum);
set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno);
/* Initialize a frame */
- set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, mips_find_saved_regs);
- set_gdbarch_deprecated_init_extra_frame_info (gdbarch, mips_init_extra_frame_info);
+ set_gdbarch_deprecated_frame_init_saved_regs (gdbarch,
+ mips_find_saved_regs);
+ set_gdbarch_deprecated_init_extra_frame_info (gdbarch,
+ mips_init_extra_frame_info);
/* MIPS version of CALL_DUMMY */
@@ -6030,25 +6051,28 @@ mips_gdbarch_init (struct gdbarch_info info,
set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL);
set_gdbarch_deprecated_pop_frame (gdbarch, mips_pop_frame);
set_gdbarch_frame_align (gdbarch, mips_frame_align);
- set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos);
+ set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch,
+ generic_save_dummy_frame_tos);
set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p);
set_gdbarch_register_to_value (gdbarch, mips_register_to_value);
set_gdbarch_value_to_register (gdbarch, mips_value_to_register);
set_gdbarch_deprecated_frame_chain (gdbarch, mips_frame_chain);
- set_gdbarch_frameless_function_invocation (gdbarch,
+ set_gdbarch_frameless_function_invocation (gdbarch,
generic_frameless_function_invocation_not);
set_gdbarch_deprecated_frame_saved_pc (gdbarch, mips_frame_saved_pc);
set_gdbarch_frame_args_skip (gdbarch, 0);
- set_gdbarch_deprecated_get_saved_register (gdbarch, mips_get_saved_register);
+ set_gdbarch_deprecated_get_saved_register (gdbarch,
+ mips_get_saved_register);
set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
- set_gdbarch_deprecated_saved_pc_after_call (gdbarch, mips_saved_pc_after_call);
+ set_gdbarch_deprecated_saved_pc_after_call (gdbarch,
+ mips_saved_pc_after_call);
set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
@@ -6081,8 +6105,7 @@ mips_gdbarch_init (struct gdbarch_info info,
}
static void
-mips_abi_update (char *ignore_args, int from_tty,
- struct cmd_list_element *c)
+mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c)
{
struct gdbarch_info info;
@@ -6098,8 +6121,8 @@ static void
show_mips_abi (char *ignore_args, int from_tty)
{
if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips)
- printf_filtered (
- "The MIPS ABI is unknown because the current architecture is not MIPS.\n");
+ printf_filtered
+ ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
else
{
enum mips_abi global_abi = global_mips_abi ();
@@ -6107,19 +6130,19 @@ show_mips_abi (char *ignore_args, int from_tty)
const char *actual_abi_str = mips_abi_strings[actual_abi];
if (global_abi == MIPS_ABI_UNKNOWN)
- printf_filtered ("The MIPS ABI is set automatically (currently \"%s\").\n",
- actual_abi_str);
+ printf_filtered
+ ("The MIPS ABI is set automatically (currently \"%s\").\n",
+ actual_abi_str);
else if (global_abi == actual_abi)
- printf_filtered (
- "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
- actual_abi_str);
+ printf_filtered
+ ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
+ actual_abi_str);
else
{
/* Probably shouldn't happen... */
- printf_filtered (
- "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
- actual_abi_str,
- mips_abi_strings[global_abi]);
+ printf_filtered
+ ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
+ actual_abi_str, mips_abi_strings[global_abi]);
}
}
}
@@ -6164,8 +6187,7 @@ mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
ef_mips_arch);
fprintf_unfiltered (file,
"mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
- tdep->mips_abi,
- mips_abi_strings[tdep->mips_abi]);
+ tdep->mips_abi, mips_abi_strings[tdep->mips_abi]);
fprintf_unfiltered (file,
"mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
mips_mask_address_p (tdep),
@@ -6181,9 +6203,7 @@ mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
: MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
: MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
: "???"));
- fprintf_unfiltered (file,
- "mips_dump_tdep: MIPS_EABI = %d\n",
- MIPS_EABI);
+ fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI);
fprintf_unfiltered (file,
"mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
MIPS_FPU_TYPE,
@@ -6197,12 +6217,10 @@ mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
fprintf_unfiltered (file,
"mips_dump_tdep: mips_stack_argsize() = %d\n",
mips_stack_argsize (tdep));
- fprintf_unfiltered (file,
- "mips_dump_tdep: A0_REGNUM = %d\n",
- A0_REGNUM);
+ fprintf_unfiltered (file, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM);
fprintf_unfiltered (file,
"mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
- XSTRING (ADDR_BITS_REMOVE(ADDR)));
+ XSTRING (ADDR_BITS_REMOVE (ADDR)));
fprintf_unfiltered (file,
"mips_dump_tdep: ATTACH_DETACH # %s\n",
XSTRING (ATTACH_DETACH));
@@ -6245,70 +6263,48 @@ mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
fprintf_unfiltered (file,
"mips_dump_tdep: MIPS16_INSTLEN = %d\n",
MIPS16_INSTLEN);
- fprintf_unfiltered (file,
- "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
+ fprintf_unfiltered (file, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
fprintf_unfiltered (file,
"mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
fprintf_unfiltered (file,
- "mips_dump_tdep: MIPS_INSTLEN = %d\n",
- MIPS_INSTLEN);
+ "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN);
fprintf_unfiltered (file,
"mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
MIPS_LAST_ARG_REGNUM,
MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1);
fprintf_unfiltered (file,
- "mips_dump_tdep: MIPS_NUMREGS = %d\n",
- MIPS_NUMREGS);
+ "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS);
fprintf_unfiltered (file,
"mips_dump_tdep: mips_saved_regsize() = %d\n",
mips_saved_regsize (tdep));
fprintf_unfiltered (file,
- "mips_dump_tdep: PRID_REGNUM = %d\n",
- PRID_REGNUM);
+ "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM);
fprintf_unfiltered (file,
"mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
fprintf_unfiltered (file,
"mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
fprintf_unfiltered (file,
"mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
- fprintf_unfiltered (file,
- "mips_dump_tdep: PROC_FRAME_REG = function?\n");
- fprintf_unfiltered (file,
- "mips_dump_tdep: PROC_FREG_MASK = function?\n");
- fprintf_unfiltered (file,
- "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
- fprintf_unfiltered (file,
- "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
- fprintf_unfiltered (file,
- "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
- fprintf_unfiltered (file,
- "mips_dump_tdep: PROC_PC_REG = function?\n");
- fprintf_unfiltered (file,
- "mips_dump_tdep: PROC_REG_MASK = function?\n");
- fprintf_unfiltered (file,
- "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
- fprintf_unfiltered (file,
- "mips_dump_tdep: PROC_SYMBOL = function?\n");
- fprintf_unfiltered (file,
- "mips_dump_tdep: PS_REGNUM = %d\n",
- PS_REGNUM);
- fprintf_unfiltered (file,
- "mips_dump_tdep: RA_REGNUM = %d\n",
- RA_REGNUM);
+ fprintf_unfiltered (file, "mips_dump_tdep: PROC_FRAME_REG = function?\n");
+ fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_MASK = function?\n");
+ fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
+ fprintf_unfiltered (file, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
+ fprintf_unfiltered (file, "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
+ fprintf_unfiltered (file, "mips_dump_tdep: PROC_PC_REG = function?\n");
+ fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_MASK = function?\n");
+ fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
+ fprintf_unfiltered (file, "mips_dump_tdep: PROC_SYMBOL = function?\n");
+ fprintf_unfiltered (file, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM);
+ fprintf_unfiltered (file, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM);
#ifdef SAVED_BYTES
fprintf_unfiltered (file,
- "mips_dump_tdep: SAVED_BYTES = %d\n",
- SAVED_BYTES);
+ "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES);
#endif
#ifdef SAVED_FP
- fprintf_unfiltered (file,
- "mips_dump_tdep: SAVED_FP = %d\n",
- SAVED_FP);
+ fprintf_unfiltered (file, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP);
#endif
#ifdef SAVED_PC
- fprintf_unfiltered (file,
- "mips_dump_tdep: SAVED_PC = %d\n",
- SAVED_PC);
+ fprintf_unfiltered (file, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC);
#endif
fprintf_unfiltered (file,
"mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
@@ -6316,8 +6312,7 @@ mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
fprintf_unfiltered (file,
"mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
fprintf_unfiltered (file,
- "mips_dump_tdep: SIGFRAME_BASE = %d\n",
- SIGFRAME_BASE);
+ "mips_dump_tdep: SIGFRAME_BASE = %d\n", SIGFRAME_BASE);
fprintf_unfiltered (file,
"mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
SIGFRAME_FPREGSAVE_OFF);
@@ -6353,14 +6348,13 @@ mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
fprintf_unfiltered (file,
"mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
XSTRING (STOPPED_BY_WATCHPOINT (WS)));
- fprintf_unfiltered (file,
- "mips_dump_tdep: T9_REGNUM = %d\n",
- T9_REGNUM);
+ fprintf_unfiltered (file, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM);
fprintf_unfiltered (file,
"mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
fprintf_unfiltered (file,
"mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
- XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE,CNT,OTHERTYPE)));
+ XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT
+ (TYPE, CNT, OTHERTYPE)));
fprintf_unfiltered (file,
"mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS));
@@ -6371,8 +6365,7 @@ mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
#endif
#ifdef TRACE_FLAVOR
fprintf_unfiltered (file,
- "mips_dump_tdep: TRACE_FLAVOR = %d\n",
- TRACE_FLAVOR);
+ "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR);
#endif
#ifdef TRACE_FLAVOR_SIZE
fprintf_unfiltered (file,
@@ -6382,28 +6375,23 @@ mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
#ifdef TRACE_SET
fprintf_unfiltered (file,
"mips_dump_tdep: TRACE_SET # %s\n",
- XSTRING (TRACE_SET (X,STATE)));
+ XSTRING (TRACE_SET (X, STATE)));
#endif
#ifdef UNUSED_REGNUM
fprintf_unfiltered (file,
- "mips_dump_tdep: UNUSED_REGNUM = %d\n",
- UNUSED_REGNUM);
+ "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM);
#endif
- fprintf_unfiltered (file,
- "mips_dump_tdep: V0_REGNUM = %d\n",
- V0_REGNUM);
+ fprintf_unfiltered (file, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM);
fprintf_unfiltered (file,
"mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
(long) VM_MIN_ADDRESS);
fprintf_unfiltered (file,
- "mips_dump_tdep: ZERO_REGNUM = %d\n",
- ZERO_REGNUM);
+ "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM);
fprintf_unfiltered (file,
- "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
- _PROC_MAGIC_);
+ "mips_dump_tdep: _PROC_MAGIC_ = %d\n", _PROC_MAGIC_);
}
-extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */
+extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */
void
_initialize_mips_tdep (void)
@@ -6411,7 +6399,7 @@ _initialize_mips_tdep (void)
static struct cmd_list_element *mipsfpulist = NULL;
struct cmd_list_element *c;
- mips_abi_string = mips_abi_strings [MIPS_ABI_UNKNOWN];
+ mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN];
if (MIPS_ABI_LAST + 1
!= sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0]))
internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync");
@@ -6438,9 +6426,7 @@ This option can be set to one of:\n\
64 - Force GDB to treat saved GP registers as 64-bit\n\
auto - Allow GDB to use the target's default setting or autodetect the\n\
saved GP register size from information contained in the executable.\n\
- (default: auto)",
- &setmipscmdlist),
- &showmipscmdlist);
+ (default: auto)", &setmipscmdlist), &showmipscmdlist);
/* Allow the user to override the argument stack size. */
add_show_from_set (add_set_enum_cmd ("stack-arg-size",
@@ -6452,9 +6438,7 @@ This option can be set to one of:\n\
32 - Force GDB to allocate 32-bit chunks per argument\n\
64 - Force GDB to allocate 64-bit chunks per argument\n\
auto - Allow GDB to determine the correct setting from the current\n\
- target and executable (default)",
- &setmipscmdlist),
- &showmipscmdlist);
+ target and executable (default)", &setmipscmdlist), &showmipscmdlist);
/* Allow the user to override the ABI. */
c = add_set_enum_cmd
@@ -6463,15 +6447,10 @@ This option can be set to one of:\n\
"This option can be set to one of:\n"
" auto - the default ABI associated with the current binary\n"
" o32\n"
- " o64\n"
- " n32\n"
- " n64\n"
- " eabi32\n"
- " eabi64",
- &setmipscmdlist);
+ " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist);
set_cmd_sfunc (c, mips_abi_update);
add_cmd ("abi", class_obscure, show_mips_abi,
- "Show ABI in use by MIPS target", &showmipscmdlist);
+ "Show ABI in use by MIPS target", &showmipscmdlist);
/* Let the user turn off floating point and set the fence post for
heuristic_proc_start. */
@@ -6489,8 +6468,7 @@ This option can be set to one of:\n\
add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
add_cmd ("none", class_support, set_mipsfpu_none_command,
- "Select no MIPS floating-point coprocessor.",
- &mipsfpulist);
+ "Select no MIPS floating-point coprocessor.", &mipsfpulist);
add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
@@ -6505,13 +6483,11 @@ This option can be set to one of:\n\
command.c doesn't deal with that. So make it a var_zinteger
because the user can always use "999999" or some such for unlimited. */
c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger,
- (char *) &heuristic_fence_post,
- "\
+ (char *) &heuristic_fence_post, "\
Set the distance searched for the start of a function.\n\
If you are debugging a stripped executable, GDB needs to search through the\n\
program for the start of a function. This command sets the distance of the\n\
-search. The only need to set it is when debugging a stripped executable.",
- &setlist);
+search. The only need to set it is when debugging a stripped executable.", &setlist);
/* We need to throw away the frame cache when we set this, since it
might change our ability to get backtraces. */
set_cmd_sfunc (c, reinit_frame_cache_sfunc);
@@ -6524,8 +6500,7 @@ Set zeroing of upper 32 bits of 64-bit addresses.\n\
Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
allow GDB to determine the correct value.\n", "\
Show zeroing of upper 32 bits of 64-bit addresses.",
- NULL, show_mask_address,
- &setmipscmdlist, &showmipscmdlist);
+ NULL, show_mask_address, &setmipscmdlist, &showmipscmdlist);
/* Allow the user to control the size of 32 bit registers within the
raw remote packet. */
@@ -6534,17 +6509,14 @@ Show zeroing of upper 32 bits of 64-bit addresses.",
Set compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
-64 bits for others. Use \"off\" to disable compatibility mode", "\
+64 bits for others. Use \"off\" to disable compatibility mode", "\
Show compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
-64 bits for others. Use \"off\" to disable compatibility mode",
- set_mips64_transfers_32bit_regs, NULL,
- &setlist, &showlist);
+64 bits for others. Use \"off\" to disable compatibility mode", set_mips64_transfers_32bit_regs, NULL, &setlist, &showlist);
/* Debug this files internals. */
add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger,
&mips_debug, "Set mips debugging.\n\
-When non-zero, mips specific debugging is enabled.", &setdebuglist),
- &showdebuglist);
+When non-zero, mips specific debugging is enabled.", &setdebuglist), &showdebuglist);
}
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