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author | Ulrich Weigand <uweigand@de.ibm.com> | 2007-05-31 20:57:41 +0000 |
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committer | Ulrich Weigand <uweigand@de.ibm.com> | 2007-05-31 20:57:41 +0000 |
commit | 6424e4c5e06afc6922b90fad6ab56d248c15e7cc (patch) | |
tree | 01f08ecf9c1d3d00fb4866d86cfe8ad73cf15c35 /gdb/xtensa-tdep.c | |
parent | b4e286e1441cad8fe476caec78c73fd2f68d4232 (diff) | |
download | gdb-6424e4c5e06afc6922b90fad6ab56d248c15e7cc.tar.gz |
2007-05-31 Markus Deuling <deuling@de.ibm.com>
* xtensa-tdep.c (XTENSA_IS_ENTRY, extract_call_winsize)
(xtensa_register_write_masked, xtensa_register_read_masked)
(xtensa_extract_return_value, xtensa_store_return_value
(xtensa_push_dummy_call, xtensa_breakpoint_from_pc): Replace
TARGET_BYTE_ORDER by gdbarch_byte_order.
* sh-tdep.c (sh_breakpoint_from_pc, gdb_print_insn_sh)
(sh_justify_value_in_reg, sh_next_flt_argreg, sh_push_dummy_call_fpu)
(sh_extract_return_value_fpu, sh_store_return_value_fpu): Likewise.
* sh64-tdep.c (sh64_breakpoint_from_pc, gdb_print_insn_sh64)
(sh64_push_dummy_call, sh64_extract_return_value)
(sh64_store_return_value, sh64_register_convert_to_virtual)
(sh64_register_convert_to_raw, sh64_pseudo_register_read)
(sh64_pseudo_register_write, sh64_do_fp_register)
(sh64_frame_prev_register): Likewise.
* score-tdep.c (score_print_insn, score_breakpoint_from_pc)
(score_return_value, score_push_dummy_call, score_fetch_inst): Likewise.
* rs6000-tdep.c (rs6000_breakpoint_from_pc, rs6000_push_dummy_call)
(e500_move_ev_register,gdb_print_insn_powerpc): Likewise.
* remote-m32r-sdi.c (m32r_resume, m32r_wait): Likewise.
* ppc-linux-nat.c (store_register): Likewise.
* nto-tdep.c (nto_find_and_open_solib)
(nto_init_solib_absolute_prefix): Likewise.
* mips-tdep.c (mips_pseudo_register_read, mips_pseudo_register_write)
(mips_convert_register_p, mips_eabi_push_dummy_call)
(mips_n32n64_push_dummy_call, mips_n32n64_return_value)
(mips_o32_push_dummy_call, mips_o32_return_value)
(mips_o64_push_dummy_call, mips_o64_return_value, mips_o64_return_value)
(mips_read_fp_register_single, mips_read_fp_register_double)
(mips_print_register, print_gp_register_row, gdb_print_insn_mips)
(mips_breakpoint_from_pc): Likewise.
* mipsnbsd-tdep.c (mipsnbsd_sigtramp_offset): Likewise.
* mips-linux-tdep.c (mips64_supply_fpregset, mips64_fill_fpregset)
(mips_linux_o32_sigframe_init): Likewise.
* m32r-tdep.c (m32r_memory_insert_breakpoint)
(m32r_memory_remove_breakpoint, m32r_breakpoint_from_pc): Likewise.
* libunwind-frame.c (libunwind_frame_cache, libunwind_frame_sniffer)
(libunwind_sigtramp_frame_sniffer, libunwind_get_reg_special): Likewise.
* iq2000-tdep.c (iq2000_breakpoint_from_pc): Likewise.
* coffread.c (process_coff_symbol): Likewise.
* arm-tdep.c (convert_from_extended, convert_to_extended)
(gdb_print_insn_arm): Likewise.
Diffstat (limited to 'gdb/xtensa-tdep.c')
-rw-r--r-- | gdb/xtensa-tdep.c | 23 |
1 files changed, 13 insertions, 10 deletions
diff --git a/gdb/xtensa-tdep.c b/gdb/xtensa-tdep.c index ef9fa244a3f..77de43a339d 100644 --- a/gdb/xtensa-tdep.c +++ b/gdb/xtensa-tdep.c @@ -109,7 +109,8 @@ extern int xtensa_config_byte_order (struct gdbarch_info *); indicates that the instruction is an ENTRY instruction. */ #define XTENSA_IS_ENTRY(op1) \ - ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) ? ((op1) == 0x6c) : ((op1) == 0x36)) + ((gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) \ + ? ((op1) == 0x6c) : ((op1) == 0x36)) #define XTENSA_ENTRY_LENGTH 3 @@ -159,7 +160,7 @@ extract_call_winsize (CORE_ADDR pc) /* Lookup call insn. (Return the default value (4) if we can't find a valid call insn. */ - if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) + if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) { if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0)) winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12 */ @@ -332,7 +333,7 @@ xtensa_register_write_masked (xtensa_register_t *reg, unsigned char *buffer) DEBUGTRACE ("xtensa_register_write_masked ()\n"); /* Copy the masked register to host byte-order. */ - if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) + if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) for (i = 0; i < bytesize; i++) { mem >>= 8; @@ -452,7 +453,7 @@ xtensa_register_read_masked (xtensa_register_t *reg, unsigned char *buffer) ptr = value; mem = *ptr; - if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) + if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) for (i = 0; i < bytesize; i++) { if ((i & 3) == 0) @@ -1172,7 +1173,7 @@ xtensa_extract_return_value (struct type *type, DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len); - if (len < 4 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) + if (len < 4 && gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) offset = 4 - len; for (; len > 0; len -= 4, areg++, valbuf += 4) @@ -1211,7 +1212,7 @@ xtensa_store_return_value (struct type *type, DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n", callsize, (int) wb); - if (len < 4 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) + if (len < 4 && gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) offset = 4 - len; areg = AREG_NUMBER (A2_REGNUM + callsize, wb); @@ -1428,7 +1429,8 @@ xtensa_push_dummy_call (struct gdbarch *gdbarch, word in big-endian mode and require a shift. This only applies for structures smaller than one word. */ - if (n < REGISTER_SIZE && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) + if (n < REGISTER_SIZE + && gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) offset += (REGISTER_SIZE - n); write_memory (offset, info->contents, info->length); @@ -1446,7 +1448,8 @@ xtensa_push_dummy_call (struct gdbarch *gdbarch, than REGISTER_SIZE; for larger odd-sized structures the excess will be left-aligned in the register on both endiannesses. */ - if (n < REGISTER_SIZE && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) + if (n < REGISTER_SIZE + && gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) { ULONGEST v = extract_unsigned_integer (cp, REGISTER_SIZE); v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT); @@ -1511,7 +1514,7 @@ xtensa_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) if (ISA_USE_DENSITY_INSTRUCTIONS) { - if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) + if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) { *lenptr = sizeof (density_big_breakpoint); return density_big_breakpoint; @@ -1524,7 +1527,7 @@ xtensa_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) } else { - if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) + if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) { *lenptr = sizeof (big_breakpoint); return big_breakpoint; |