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| author | Chris Demetriou <cgd@google.com> | 2001-10-18 01:50:26 +0000 |
|---|---|---|
| committer | Chris Demetriou <cgd@google.com> | 2001-10-18 01:50:26 +0000 |
| commit | 541b4b475078104cede5c9a0dbe1fa7632410f88 (patch) | |
| tree | e5749423ea386914919bd8707b1a08a7fab1f306 /include/opcode/mips.h | |
| parent | 0adaee045e9d8d9ec24546db0d577659f64e5410 (diff) | |
| download | gdb-541b4b475078104cede5c9a0dbe1fa7632410f88.tar.gz | |
2001-10-17 Chris Demetriou <cgd@broadcom.com>
* mips.h: Sort coprocessor instruction argument characters
in comment, add a few more words of description for "H".
Diffstat (limited to 'include/opcode/mips.h')
| -rw-r--r-- | include/opcode/mips.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/opcode/mips.h b/include/opcode/mips.h index b7a0fed88ce..8c24c85f917 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -209,8 +209,8 @@ struct mips_opcode Coprocessor instructions: "E" 5 bit target register (OP_*_RT) "G" 5 bit destination register (OP_*_RD) + "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) "P" 5 bit performance-monitor register (OP_*_PERFREG) - "H" 3 bit sel field (OP_*_SEL) Macro instructions: "A" General 32 bit expression |