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authorDoug Evans <dje@google.com>2009-02-06 23:14:34 +0000
committerDoug Evans <dje@google.com>2009-02-06 23:14:34 +0000
commite9073a2e083d941860355640391801ef6348007c (patch)
treea084cc7b03979e896e929babe398119e31309d04 /include/opcode
parent6f2bad6c505482623ae39733fca82ad82847e432 (diff)
downloadgdb-e9073a2e083d941860355640391801ef6348007c.tar.gz
* i386.h: Add comment regarding sse* insns and prefixes.
Diffstat (limited to 'include/opcode')
-rw-r--r--include/opcode/ChangeLog4
-rw-r--r--include/opcode/i386.h5
2 files changed, 9 insertions, 0 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index e256e6ebd5a..adf39400cf3 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,7 @@
+2009-02-06 Doug Evans <dje@google.com>
+
+ * i386.h: Add comment regarding sse* insns and prefixes.
+
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* mips.h (INSN_XLR): Define.
diff --git a/include/opcode/i386.h b/include/opcode/i386.h
index 4311cd6401b..d60db76b7d6 100644
--- a/include/opcode/i386.h
+++ b/include/opcode/i386.h
@@ -59,6 +59,11 @@
/* The opcode for the fwait instruction, which disassembler treats as a
prefix when it can. */
#define FWAIT_OPCODE 0x9b
+
+/* Instruction prefixes.
+ NOTE: For certain SSE* instructions, 0x66,0xf2,0xf3 are treated as
+ part of the opcode. Other prefixes may still appear between them
+ and the 0x0f part of the opcode. */
#define ADDR_PREFIX_OPCODE 0x67
#define DATA_PREFIX_OPCODE 0x66
#define LOCK_PREFIX_OPCODE 0xf0