2002-12-23 David Carlton <carlton@math.stanford.edu>

	* Merge from mainline; tag is carlton_dictionary-20021223-merge.

24 files changed, 1270 insertions, 1918 deletions

diff --git a/include/ChangeLog b/include/ChangeLog
index 2dfed5ae4ce..5b46e44124f 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,13 +1,35 @@
+2002-12-23  Alan Modra  <amodra@bigpond.net.au>
+
+	* bfdlink.h (struct bfd_link_info): Add "strip_discarded".
+
+2002-12-20  Alan Modra  <amodra@bigpond.net.au>
+
+	* bfdlink.h (struct bfd_link_info): Replace bfd_boolean fields with
+	bit-fields.  Rearrange to put all like types together.
+
+2002-11-30  Alan Modra  <amodra@bigpond.net.au>
+
+	* bfdlink.h: Replace boolean with bfd_boolean.  Formatting.
+
+2002-11-23  Simon Burge  <simonb@wasabisystems.com>
+
+	* libiberty.h (basename): Add NetBSD to the list.
+
+2002-11-22  Daniel Jacobowitz  <drow@mvista.com>
+
+	* libiberty.h (make_relative_prefix): Add prototype.
+
+2002-11-16  Klee Dienes  <kdienes@apple.com>
+
+	* opcode/m88k.h (INSTAB): Remove 'next' field.
+	(instruction): Remove definition; replace with extern declaration
+	and mark as const.
+
 2002-11-14  Egor Duda  <deo@logos-m.ru>
 
 	* bfdlink.h (struct bfd_link_info): Add new boolean
 	field pei386_runtime_pseudo_reloc.
 
-2002-11-11  Svein E. Seldal  <Svein.Seldal@solidas.com>
-
-	* opcode/tic4x.h: Added new opcodes and corrected some bugs.  Add
-	support for new DSP types.
-
 2002-10-26  Roger Sayle  <roger@eyesopen.com>
 
 	* partition.h:  Close the extern "C" scope when compiling with C++.
diff --git a/include/bfdlink.h b/include/bfdlink.h
index 9263bcc126d..c25826207c5 100644
--- a/include/bfdlink.h
+++ b/include/bfdlink.h
@@ -128,14 +128,14 @@ struct bfd_link_hash_entry
       struct
 	{
 	  /* The linker needs to know three things about common
-             symbols: the size, the alignment, and the section in
-             which the symbol should be placed.  We store the size
-             here, and we allocate a small structure to hold the
-             section and the alignment.  The alignment is stored as a
-             power of two.  We don't store all the information
-             directly because we don't want to increase the size of
-             the union; this structure is a major space user in the
-             linker.  */
+	     symbols: the size, the alignment, and the section in
+	     which the symbol should be placed.  We store the size
+	     here, and we allocate a small structure to hold the
+	     section and the alignment.  The alignment is stored as a
+	     power of two.  We don't store all the information
+	     directly because we don't want to increase the size of
+	     the union; this structure is a major space user in the
+	     linker.  */
 	  bfd_size_type size;	/* Common symbol size.  */
 	  struct bfd_link_hash_common_entry
 	    {
@@ -167,25 +167,25 @@ struct bfd_link_hash_table
   enum bfd_link_hash_table_type type;
 };
 
-/* Look up an entry in a link hash table.  If FOLLOW is true, this
+/* Look up an entry in a link hash table.  If FOLLOW is TRUE, this
    follows bfd_link_hash_indirect and bfd_link_hash_warning links to
    the real symbol.  */
 extern struct bfd_link_hash_entry *bfd_link_hash_lookup
-  PARAMS ((struct bfd_link_hash_table *, const char *, boolean create,
-	   boolean copy, boolean follow));
+  PARAMS ((struct bfd_link_hash_table *, const char *, bfd_boolean create,
+	   bfd_boolean copy, bfd_boolean follow));
 
 /* Look up an entry in the main linker hash table if the symbol might
    be wrapped.  This should only be used for references to an
    undefined symbol, not for definitions of a symbol.  */
 
 extern struct bfd_link_hash_entry *bfd_wrapped_link_hash_lookup
-  PARAMS ((bfd *, struct bfd_link_info *, const char *, boolean, boolean,
-	   boolean));
+  PARAMS ((bfd *, struct bfd_link_info *, const char *, bfd_boolean,
+	   bfd_boolean, bfd_boolean));
 
 /* Traverse a link hash table.  */
 extern void bfd_link_hash_traverse
   PARAMS ((struct bfd_link_hash_table *,
-	   boolean (*) (struct bfd_link_hash_entry *, PTR),
+	   bfd_boolean (*) (struct bfd_link_hash_entry *, PTR),
 	   PTR));
 
 /* Add an entry to the undefs list.  */
@@ -203,49 +203,46 @@ struct bfd_sym_chain
 
 struct bfd_link_info
 {
-  /* Function callbacks.  */
-  const struct bfd_link_callbacks *callbacks;
-
-  /* true if BFD should generate a relocateable object file.  */
-  boolean relocateable;
+  /* TRUE if BFD should generate a relocatable object file.  */
+  unsigned int relocateable: 1;
 
-  /* true if BFD should generate relocation information in the final
+  /* TRUE if BFD should generate relocation information in the final
      executable.  */
-  boolean emitrelocations;
+  unsigned int emitrelocations: 1;
 
-  /* true if BFD should generate a "task linked" object file,
+  /* TRUE if BFD should generate a "task linked" object file,
      similar to relocatable but also with globals converted to
      statics.  */
-  boolean task_link;
+  unsigned int task_link: 1;
 
-  /* true if BFD should generate a shared object.  */
-  boolean shared;
+  /* TRUE if BFD should generate a shared object.  */
+  unsigned int shared: 1;
 
-  /* true if BFD should pre-bind symbols in a shared object.  */
-  boolean symbolic;
+  /* TRUE if BFD should pre-bind symbols in a shared object.  */
+  unsigned int symbolic: 1;
 
-  /* true if BFD should export all symbols in the dynamic symbol table
+  /* TRUE if BFD should export all symbols in the dynamic symbol table
      of an executable, rather than only those used.  */
-  boolean export_dynamic;
+  unsigned int export_dynamic: 1;
 
-  /* true if shared objects should be linked directly, not shared.  */
-  boolean static_link;
+  /* TRUE if shared objects should be linked directly, not shared.  */
+  unsigned int static_link: 1;
 
-  /* true if the output file should be in a traditional format.  This
+  /* TRUE if the output file should be in a traditional format.  This
      is equivalent to the setting of the BFD_TRADITIONAL_FORMAT flag
      on the output file, but may be checked when reading the input
      files.  */
-  boolean traditional_format;
+  unsigned int traditional_format: 1;
 
-  /* true if we want to produced optimized output files.  This might
+  /* TRUE if we want to produced optimized output files.  This might
      need much more time and therefore must be explicitly selected.  */
-  boolean optimize;
+  unsigned int optimize: 1;
 
-  /* true if BFD should generate errors for undefined symbols
+  /* TRUE if BFD should generate errors for undefined symbols
      even if generating a shared object.  */
-  boolean no_undefined;
+  unsigned int no_undefined: 1;
 
-  /* true if BFD should allow undefined symbols in shared objects even
+  /* TRUE if BFD should allow undefined symbols in shared objects even
      when no_undefined is set to disallow undefined symbols.  The net
      result will be that undefined symbols in regular objects will
      still trigger an error, but undefined symbols in shared objects
@@ -257,13 +254,39 @@ struct bfd_link_info
      appropriate for the current architecture.  I.E. dynamically
      select an appropriate memset function.  Apparently it is also
      normal for HPPA shared libraries to have undefined symbols.  */
-  boolean allow_shlib_undefined;
+  unsigned int allow_shlib_undefined: 1;
+
+  /* TRUE if ok to have multiple definition.  */
+  unsigned int allow_multiple_definition: 1;
+
+  /* TRUE if ok to have version with no definition.  */
+  unsigned int allow_undefined_version: 1;
+
+  /* TRUE if symbols should be retained in memory, FALSE if they
+     should be freed and reread.  */
+  unsigned int keep_memory: 1;
+
+  /* TRUE if every symbol should be reported back via the notice
+     callback.  */
+  unsigned int notice_all: 1;
+
+  /* TRUE if executable should not contain copy relocs.
+     Setting this true may result in a non-sharable text segment.  */
+  unsigned int nocopyreloc: 1;
+
+  /* TRUE if the new ELF dynamic tags are enabled. */
+  unsigned int new_dtags: 1;
 
-  /* true if ok to have multiple definition.  */
-  boolean allow_multiple_definition;
+  /* TRUE if non-PLT relocs should be merged into one reloc section
+     and sorted so that relocs against the same symbol come together.  */
+  unsigned int combreloc: 1;
+
+  /* TRUE if .eh_frame_hdr section and PT_GNU_EH_FRAME ELF segment
+     should be created.  */
+  unsigned int eh_frame_hdr: 1;
 
-  /* true if ok to have version with no definition.  */
-  boolean allow_undefined_version;
+  /* TRUE if global symbols in discarded sections should be stripped.  */
+  unsigned int strip_discarded: 1;
 
   /* Which symbols to strip.  */
   enum bfd_link_strip strip;
@@ -271,24 +294,12 @@ struct bfd_link_info
   /* Which local symbols to discard.  */
   enum bfd_link_discard discard;
 
-  /* true if symbols should be retained in memory, false if they
-     should be freed and reread.  */
-  boolean keep_memory;
-
-  /* The list of input BFD's involved in the link.  These are chained
-     together via the link_next field.  */
-  bfd *input_bfds;
-
-  /* If a symbol should be created for each input BFD, this is section
-     where those symbols should be placed.  It must be a section in
-     the output BFD.  It may be NULL, in which case no such symbols
-     will be created.  This is to support CREATE_OBJECT_SYMBOLS in the
-     linker command language.  */
-  asection *create_object_symbols_section;
+  /* Criteria for skipping symbols when detemining
+     whether to include an object from an archive. */
+  enum bfd_link_common_skip_ar_aymbols common_skip_ar_aymbols;
 
-  /* List of global symbol names that are starting points for marking
-     sections against garbage collection.  */
-  struct bfd_sym_chain *gc_sym_list;
+  /* Function callbacks.  */
+  const struct bfd_link_callbacks *callbacks;
 
   /* Hash table handled by BFD.  */
   struct bfd_link_hash_table *hash;
@@ -297,12 +308,8 @@ struct bfd_link_info
      strip_some.  */
   struct bfd_hash_table *keep_hash;
 
-  /* true if every symbol should be reported back via the notice
-     callback.  */
-  boolean notice_all;
-
   /* Hash table of symbols to report back via the notice callback.  If
-     this is NULL, and notice_all is false, then no symbols are
+     this is NULL, and notice_all is FALSE, then no symbols are
      reported back.  */
   struct bfd_hash_table *notice_hash;
 
@@ -310,14 +317,24 @@ struct bfd_link_info
      option).  If this is NULL, no symbols are being wrapped.  */
   struct bfd_hash_table *wrap_hash;
 
+  /* The list of input BFD's involved in the link.  These are chained
+     together via the link_next field.  */
+  bfd *input_bfds;
+
+  /* If a symbol should be created for each input BFD, this is section
+     where those symbols should be placed.  It must be a section in
+     the output BFD.  It may be NULL, in which case no such symbols
+     will be created.  This is to support CREATE_OBJECT_SYMBOLS in the
+     linker command language.  */
+  asection *create_object_symbols_section;
+
+  /* List of global symbol names that are starting points for marking
+     sections against garbage collection.  */
+  struct bfd_sym_chain *gc_sym_list;
+
   /* If a base output file is wanted, then this points to it */
   PTR base_file;
 
-  /* If non-zero, specifies that branches which are problematic for the
-  MPC860 C0 (or earlier) should be checked for and modified.  It gives the
-  number of bytes that should be checked at the end of each text page. */
-  int mpc860c0;
-
   /* The function to call when the executable or shared object is
      loaded.  */
   const char *init_function;
@@ -326,16 +343,12 @@ struct bfd_link_info
      unloaded.  */
   const char *fini_function;
 
-  /* true if the new ELF dynamic tags are enabled. */ 
-  boolean new_dtags;
-
-  /* May be used to set DT_FLAGS for ELF. */
-  bfd_vma flags;
-
-  /* May be used to set DT_FLAGS_1 for ELF. */
-  bfd_vma flags_1;
+  /* If non-zero, specifies that branches which are problematic for the
+     MPC860 C0 (or earlier) should be checked for and modified.  It gives the
+     number of bytes that should be checked at the end of each text page.  */
+  int mpc860c0;
 
-  /* Non-zero if auto-import thunks for DATA items in pei386 DLLs 
+  /* Non-zero if auto-import thunks for DATA items in pei386 DLLs
      should be generated/linked against.  Set to 1 if this feature
      is explicitly requested by the user, -1 if enabled by default.  */
   int pei386_auto_import;
@@ -345,30 +358,20 @@ struct bfd_link_info
      is explicitly requested by the user, -1 if enabled by default.  */
   int pei386_runtime_pseudo_reloc;
 
-  /* True if non-PLT relocs should be merged into one reloc section
-     and sorted so that relocs against the same symbol come together.  */
-  boolean combreloc;
-
-  /* True if executable should not contain copy relocs.
-     Setting this true may result in a non-sharable text segment.  */
-  boolean nocopyreloc;
-
-  /* True if .eh_frame_hdr section and PT_GNU_EH_FRAME ELF segment
-     should be created.  */
-  boolean eh_frame_hdr;
-
   /* How many spare .dynamic DT_NULL entries should be added?  */
   unsigned int spare_dynamic_tags;
 
-  /* Criteria for skipping symbols when detemining
-     whether to include an object from an archive. */
-  enum bfd_link_common_skip_ar_aymbols common_skip_ar_aymbols;
+  /* May be used to set DT_FLAGS for ELF. */
+  bfd_vma flags;
+
+  /* May be used to set DT_FLAGS_1 for ELF. */
+  bfd_vma flags_1;
 };
 
 /* This structures holds a set of callback functions.  These are
    called by the BFD linker routines.  The first argument to each
    callback function is the bfd_link_info structure being used.  Each
-   function returns a boolean value.  If the function returns false,
+   function returns a boolean value.  If the function returns FALSE,
    then the BFD function which called it will return with a failure
    indication.  */
 
@@ -378,23 +381,18 @@ struct bfd_link_callbacks
      archive.  ABFD is the archive element being added.  NAME is the
      name of the symbol which caused the archive element to be pulled
      in.  */
-  boolean (*add_archive_element) PARAMS ((struct bfd_link_info *,
-					  bfd *abfd,
-					  const char *name));
+  bfd_boolean (*add_archive_element)
+    PARAMS ((struct bfd_link_info *, bfd *abfd, const char *name));
   /* A function which is called when a symbol is found with multiple
      definitions.  NAME is the symbol which is defined multiple times.
      OBFD is the old BFD, OSEC is the old section, OVAL is the old
      value, NBFD is the new BFD, NSEC is the new section, and NVAL is
      the new value.  OBFD may be NULL.  OSEC and NSEC may be
      bfd_com_section or bfd_ind_section.  */
-  boolean (*multiple_definition) PARAMS ((struct bfd_link_info *,
-					  const char *name,
-					  bfd *obfd,
-					  asection *osec,
-					  bfd_vma oval,
-					  bfd *nbfd,
-					  asection *nsec,
-					  bfd_vma nval));
+  bfd_boolean (*multiple_definition)
+    PARAMS ((struct bfd_link_info *, const char *name,
+	     bfd *obfd, asection *osec, bfd_vma oval,
+	     bfd *nbfd, asection *nsec, bfd_vma nval));
   /* A function which is called when a common symbol is defined
      multiple times.  NAME is the symbol appearing multiple times.
      OBFD is the BFD of the existing symbol; it may be NULL if this is
@@ -406,34 +404,29 @@ struct bfd_link_callbacks
      symbol, one of bfd_link_hash_defined, bfd_link_hash_common, or
      bfd_link_hash_indirect.  If NTYPE is bfd_link_hash_common, NSIZE
      is the size of the new symbol.  */
-  boolean (*multiple_common) PARAMS ((struct bfd_link_info *,
-				      const char *name,
-				      bfd *obfd,
-				      enum bfd_link_hash_type otype,
-				      bfd_vma osize,
-				      bfd *nbfd,
-				      enum bfd_link_hash_type ntype,
-				      bfd_vma nsize));
+  bfd_boolean (*multiple_common)
+    PARAMS ((struct bfd_link_info *, const char *name,
+	     bfd *obfd, enum bfd_link_hash_type otype, bfd_vma osize,
+	     bfd *nbfd, enum bfd_link_hash_type ntype, bfd_vma nsize));
   /* A function which is called to add a symbol to a set.  ENTRY is
      the link hash table entry for the set itself (e.g.,
      __CTOR_LIST__).  RELOC is the relocation to use for an entry in
      the set when generating a relocateable file, and is also used to
      get the size of the entry when generating an executable file.
      ABFD, SEC and VALUE identify the value to add to the set.  */
-  boolean (*add_to_set) PARAMS ((struct bfd_link_info *,
-				 struct bfd_link_hash_entry *entry,
-				 bfd_reloc_code_real_type reloc,
-				 bfd *abfd, asection *sec, bfd_vma value));
+  bfd_boolean (*add_to_set)
+    PARAMS ((struct bfd_link_info *, struct bfd_link_hash_entry *entry,
+	     bfd_reloc_code_real_type reloc, bfd *abfd, asection *sec,
+	     bfd_vma value));
   /* A function which is called when the name of a g++ constructor or
      destructor is found.  This is only called by some object file
-     formats.  CONSTRUCTOR is true for a constructor, false for a
+     formats.  CONSTRUCTOR is TRUE for a constructor, FALSE for a
      destructor.  This will use BFD_RELOC_CTOR when generating a
      relocateable file.  NAME is the name of the symbol found.  ABFD,
      SECTION and VALUE are the value of the symbol.  */
-  boolean (*constructor) PARAMS ((struct bfd_link_info *,
-				  boolean constructor,
-				  const char *name, bfd *abfd, asection *sec,
-				  bfd_vma value));
+  bfd_boolean (*constructor)
+    PARAMS ((struct bfd_link_info *, bfd_boolean constructor,
+	     const char *name, bfd *abfd, asection *sec, bfd_vma value));
   /* A function which is called to issue a linker warning.  For
      example, this is called when there is a reference to a warning
      symbol.  WARNING is the warning to be issued.  SYMBOL is the name
@@ -441,20 +434,17 @@ struct bfd_link_callbacks
      there is none.  ABFD, SECTION and ADDRESS identify the location
      which trigerred the warning; either ABFD or SECTION or both may
      be NULL if the location is not known.  */
-  boolean (*warning) PARAMS ((struct bfd_link_info *,
-			      const char *warning, const char *symbol,
-			      bfd *abfd, asection *section,
-			      bfd_vma address));
+  bfd_boolean (*warning)
+    PARAMS ((struct bfd_link_info *, const char *warning, const char *symbol,
+	     bfd *abfd, asection *section, bfd_vma address));
   /* A function which is called when a relocation is attempted against
      an undefined symbol.  NAME is the symbol which is undefined.
      ABFD, SECTION and ADDRESS identify the location from which the
      reference is made. FATAL indicates whether an undefined symbol is
      a fatal error or not. In some cases SECTION may be NULL.  */
-  boolean (*undefined_symbol) PARAMS ((struct bfd_link_info *,
-				       const char *name, bfd *abfd,
-				       asection *section,
-				       bfd_vma address,
-				       boolean fatal));
+  bfd_boolean (*undefined_symbol)
+    PARAMS ((struct bfd_link_info *, const char *name, bfd *abfd,
+	     asection *section, bfd_vma address, bfd_boolean fatal));
   /* A function which is called when a reloc overflow occurs.  NAME is
      the name of the symbol or section the reloc is against,
      RELOC_NAME is the name of the relocation, and ADDEND is any
@@ -462,11 +452,9 @@ struct bfd_link_callbacks
      location at which the overflow occurs; if this is the result of a
      bfd_section_reloc_link_order or bfd_symbol_reloc_link_order, then
      ABFD will be NULL.  */
-  boolean (*reloc_overflow) PARAMS ((struct bfd_link_info *,
-				     const char *name,
-				     const char *reloc_name, bfd_vma addend,
-				     bfd *abfd, asection *section,
-				     bfd_vma address));
+  bfd_boolean (*reloc_overflow)
+    PARAMS ((struct bfd_link_info *, const char *name, const char *reloc_name,
+	     bfd_vma addend, bfd *abfd, asection *section, bfd_vma address));
   /* A function which is called when a dangerous reloc is performed.
      The canonical example is an a29k IHCONST reloc which does not
      follow an IHIHALF reloc.  MESSAGE is an appropriate message.
@@ -474,26 +462,25 @@ struct bfd_link_callbacks
      problem occurred; if this is the result of a
      bfd_section_reloc_link_order or bfd_symbol_reloc_link_order, then
      ABFD will be NULL.  */
-  boolean (*reloc_dangerous) PARAMS ((struct bfd_link_info *,
-				      const char *message,
-				      bfd *abfd, asection *section,
-				      bfd_vma address));
+  bfd_boolean (*reloc_dangerous)
+    PARAMS ((struct bfd_link_info *, const char *message,
+	     bfd *abfd, asection *section, bfd_vma address));
   /* A function which is called when a reloc is found to be attached
      to a symbol which is not being written out.  NAME is the name of
      the symbol.  ABFD, SECTION and ADDRESS identify the location of
      the reloc; if this is the result of a
      bfd_section_reloc_link_order or bfd_symbol_reloc_link_order, then
      ABFD will be NULL.  */
-  boolean (*unattached_reloc) PARAMS ((struct bfd_link_info *,
-				       const char *name,
-				       bfd *abfd, asection *section,
-				       bfd_vma address));
+  bfd_boolean (*unattached_reloc)
+    PARAMS ((struct bfd_link_info *, const char *name,
+	     bfd *abfd, asection *section, bfd_vma address));
   /* A function which is called when a symbol in notice_hash is
      defined or referenced.  NAME is the symbol.  ABFD, SECTION and
      ADDRESS are the value of the symbol.  If SECTION is
      bfd_und_section, this is a reference.  */
-  boolean (*notice) PARAMS ((struct bfd_link_info *, const char *name,
-			     bfd *abfd, asection *section, bfd_vma address));
+  bfd_boolean (*notice)
+    PARAMS ((struct bfd_link_info *, const char *name,
+	     bfd *abfd, asection *section, bfd_vma address));
 };
 
 /* The linker builds link_order structures which tell the code how to
@@ -513,20 +500,20 @@ enum bfd_link_order_type
 /* This is the link_order structure itself.  These form a chain
    attached to the section whose contents they are describing.  */
 
-struct bfd_link_order 
+struct bfd_link_order
 {
   /* Next link_order in chain.  */
   struct bfd_link_order *next;
   /* Type of link_order.  */
   enum bfd_link_order_type type;
   /* Offset within output section.  */
-  bfd_vma offset;  
+  bfd_vma offset;
   /* Size within output section.  */
   bfd_size_type size;
   /* Type specific information.  */
-  union 
+  union
     {
-      struct 
+      struct
 	{
 	  /* Section to include.  If this is used, then
 	     section->output_section must be the section the
@@ -609,7 +596,7 @@ struct bfd_elf_version_expr
   /* Regular expression.  */
   const char *pattern;
   /* Matching function.  */
-  int (*match) PARAMS((struct bfd_elf_version_expr *, const char *));
+  int (*match) PARAMS ((struct bfd_elf_version_expr *, const char *));
   /* Defined by ".symver".  */
   unsigned int symver: 1;
   /* Defined by version script.  */
diff --git a/include/coff/ChangeLog b/include/coff/ChangeLog
index 23b062735f0..b2eec4cbe93 100644
--- a/include/coff/ChangeLog
+++ b/include/coff/ChangeLog
@@ -1,3 +1,8 @@
+2002-11-30  Alan Modra  <amodra@bigpond.net.au>
+
+	* ecoff.h: Replace boolean with bfd_boolean.
+	* xcoff.h: Likewise.
+
 2002-03-18  Tom Rix  <trix@redhat.com>
 
 	* rs6k64.h: Add U64_TOCMAGIC, AIX 5 64 bit magic number.
diff --git a/include/coff/ecoff.h b/include/coff/ecoff.h
index 076fdf5bef5..00d2f240086 100644
--- a/include/coff/ecoff.h
+++ b/include/coff/ecoff.h
@@ -2,22 +2,22 @@
    This does not include symbol information, found in sym.h and
    symconst.h.
 
-   Copyright 2001 Free Software Foundation, Inc.
+   Copyright 2001, 2002 Free Software Foundation, Inc.
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.
-   
+
    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
-   
+
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-   
+
 #ifndef ECOFF_H
 #define ECOFF_H
 
@@ -430,8 +430,8 @@ struct ecoff_debug_swap
   /* Function to read symbol data and set up pointers in
      ecoff_debug_info structure.  The section argument is used for
      ELF, not straight ECOFF.  */
-  boolean (*read_debug_info) PARAMS ((bfd *, asection *,
-				      struct ecoff_debug_info *));
+  bfd_boolean (*read_debug_info)
+    PARAMS ((bfd *, asection *, struct ecoff_debug_info *));
 };
 
 #endif /* ! defined (ECOFF_H) */
diff --git a/include/coff/xcoff.h b/include/coff/xcoff.h
index 0bb9d6c1e48..b27cececb0d 100644
--- a/include/coff/xcoff.h
+++ b/include/coff/xcoff.h
@@ -1,6 +1,6 @@
 /* Internal format of XCOFF object file data structures for BFD.
 
-   Copyright 1995, 1996, 1997, 1998, 1999, 2000, 2001
+   Copyright 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
    Free Software Foundation, Inc.
    Written by Ian Lance Taylor <ian@cygnus.com>, Cygnus Support.
 
@@ -366,10 +366,10 @@ struct xcoff_link_hash_table
   unsigned long file_align;
 
   /* Whether the .text section must be read-only.  */
-  boolean textro;
+  bfd_boolean textro;
 
   /* Whether garbage collection was done.  */
-  boolean gc;
+  bfd_boolean gc;
 
   /* A linked list of symbols for which we have size information.  */
   struct xcoff_link_size_list
@@ -391,7 +391,7 @@ struct xcoff_link_hash_table
 struct xcoff_loader_info
 {
   /* Set if a problem occurred.  */
-  boolean failed;
+  bfd_boolean failed;
 
   /* Output BFD.  */
   bfd *output_bfd;
@@ -400,7 +400,7 @@ struct xcoff_loader_info
   struct bfd_link_info *info;
 
   /* Whether all defined symbols should be exported.  */
-  boolean export_defineds;
+  bfd_boolean export_defineds;
 
   /* Number of ldsym structures.  */
   size_t ldsym_count;
@@ -604,7 +604,7 @@ struct xcoff_ar_hdr_big
 /* We often have to distinguish between the old and big file format.
    Make it a bit cleaner.  We can use `xcoff_ardata' here because the
    `hdr' member has the same size and position in both formats.  
-   <bigaf> is the default format, return true even when xcoff_ardata is 
+   <bigaf> is the default format, return TRUE even when xcoff_ardata is 
    NULL. */
 #ifndef SMALL_ARCHIVE
 /* Creates big archives by default */
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index 65f3160af38..de95f20c5a8 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,51 @@
+2002-12-20  DJ Delorie  <dj@redhat.com>
+
+	* xstormy16.h: Add XSTORMY16_12.
+
+2002-12-16  Andrew MacLeod  <amacleod@redhat.com>
+
+	* xstormy16.h (START_RELOC_NUMBERS) Add relocation numbers
+	for R_XSTORMY16_LO16 and R_XSTORMY16_HI16.
+
+2002-12-10  James Cownie <jcownie@etnus.com>
+
+	* dwarf2.h (DW_TAG_upc_shared_type, DW_TAG_upc_strict_type,
+	DW_TAG_upc_relaxed_type, DW_AT_upc_threads_scaled, DW_LANG_Upc):
+	Define.
+
+2002-12-01  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* m68hc11.h (EF_M68HC12_MACH, EF_M68HCS12_MACH): Define.
+	(EF_M68HC11_MACH_MASK, EF_M68HC11_MACH): Define.
+	(EF_M68HC11_MERGE_MACH, EF_M68HC11_CAN_MERGE_MACH): Define.
+
+2002-11-30  Alan Modra  <amodra@bigpond.net.au>
+
+	* mmix.h: Replace boolean with bfd_boolean.
+	* sh.h: Likewise.
+
+2002-11-28  Alan Modra  <amodra@bigpond.net.au>
+
+	* internal.h (elf32_internal_ehdr, Elf32_Internal_Ehdr,
+	elf64_internal_ehdr, Elf64_Internal_Ehdr, elf32_internal_phdr,
+	Elf32_Internal_Phdr, elf64_internal_phdr, Elf64_Internal_Phdr,
+	elf32_internal_shdr, Elf32_Internal_Shdr, elf64_internal_shdr,
+	Elf64_Internal_Shdr, elf32_internal_sym, elf64_internal_sym,
+	Elf32_Internal_Sym, Elf64_Internal_Sym, Elf32_Internal_Note,
+	elf32_internal_note, elf32_internal_rel, Elf32_Internal_Rel,
+	elf64_internal_rel, Elf64_Internal_Rel, elf32_internal_rela,
+	elf64_internal_rela, Elf32_Internal_Rela, Elf64_Internal_Rela,
+	elf32_internal_dyn, elf64_internal_dyn, Elf32_Internal_Dyn,
+	Elf64_Internal_Dyn, elf32_internal_verdef, elf64_internal_verdef,
+	elf32_internal_verdaux, elf64_internal_verdaux, elf32_internal_verneed,
+	elf64_internal_verneed, elf32_internal_vernaux, elf64_internal_vernaux,
+	elf32_internal_versym, elf64_internal_versym, Elf32_Internal_Verdef,
+	Elf64_Internal_Verdef, Elf32_Internal_Verdaux, Elf64_Internal_Verdaux,
+	Elf32_Internal_Verneed, Elf64_Internal_Verneed, Elf32_Internal_Vernaux,
+	Elf64_Internal_Vernaux, Elf32_Internal_Versym, Elf64_Internal_Versym,
+	Elf32_Internal_Syminfo, Elf64_Internal_Syminfo): Delete.
+	(Elf_Internal_Rel): Delete.
+
 2002-10-11  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
 
 	* sh.h: Add SH TLS relocs.
diff --git a/include/elf/dwarf2.h b/include/elf/dwarf2.h
index 6463b5a9082..9c8ce4e0063 100644
--- a/include/elf/dwarf2.h
+++ b/include/elf/dwarf2.h
@@ -87,7 +87,7 @@ typedef struct
 }
 DWARF2_Internal_PubNames;
 
-/* Strcuture found in .debug_info section.  */
+/* Structure found in .debug_info section.  */
 typedef struct
 {
   unsigned char  cu_length        [4];
@@ -194,7 +194,11 @@ enum dwarf_tag
     DW_TAG_function_template = 0x4102,	/* For C++.  */
     DW_TAG_class_template = 0x4103,	/* For C++.  */
     DW_TAG_GNU_BINCL = 0x4104,
-    DW_TAG_GNU_EINCL = 0x4105
+    DW_TAG_GNU_EINCL = 0x4105,
+    /* Extensions for UPC.  See: http://upc.gwu.edu/~upc.  */
+    DW_TAG_upc_shared_type = 0x8765,
+    DW_TAG_upc_strict_type = 0x8766,
+    DW_TAG_upc_relaxed_type = 0x8767
   };
 
 #define DW_TAG_lo_user	0x4080
@@ -309,7 +313,7 @@ enum dwarf_attribute
     DW_AT_call_column   = 0x57,
     DW_AT_call_file     = 0x58,
     DW_AT_call_line     = 0x59,
-    /* SGI/MIPS Extensions.  */
+    /* SGI/MIPS extensions.  */
     DW_AT_MIPS_fde = 0x2001,
     DW_AT_MIPS_loop_begin = 0x2002,
     DW_AT_MIPS_tail_loop_begin = 0x2003,
@@ -329,8 +333,10 @@ enum dwarf_attribute
     DW_AT_body_begin = 0x2105,
     DW_AT_body_end   = 0x2106,
     DW_AT_GNU_vector = 0x2107,
-    /* VMS Extensions.  */
-    DW_AT_VMS_rtnbeg_pd_address = 0x2201
+    /* VMS extensions.  */
+    DW_AT_VMS_rtnbeg_pd_address = 0x2201,
+    /* UPC extension.  */
+    DW_AT_upc_threads_scaled = 0x3210
   };
 
 #define DW_AT_lo_user	0x2000	/* Implementation-defined range start.  */
@@ -678,7 +684,9 @@ enum dwarf_source_language
     DW_LANG_Ada95 = 0x000d,
     DW_LANG_Fortran95 = 0x000e,
     /* MIPS.  */
-    DW_LANG_Mips_Assembler = 0x8001
+    DW_LANG_Mips_Assembler = 0x8001,
+    /* UPC.  */
+    DW_LANG_Upc = 0x8765
   };
 
 #define DW_LANG_lo_user 0x8000	/* Implementation-defined range start.  */
diff --git a/include/elf/internal.h b/include/elf/internal.h
index 5d39d3ae7ce..45d682a2256 100644
--- a/include/elf/internal.h
+++ b/include/elf/internal.h
@@ -1,5 +1,5 @@
 /* ELF support for BFD.
-   Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1998, 2000, 2001
+   Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002
    Free Software Foundation, Inc.
 
    Written by Fred Fish @ Cygnus Support, from information published
@@ -58,11 +58,6 @@ typedef struct elf_internal_ehdr {
   unsigned int		e_shstrndx;	/* Section header string table index */
 } Elf_Internal_Ehdr;
 
-#define elf32_internal_ehdr elf_internal_ehdr
-#define Elf32_Internal_Ehdr Elf_Internal_Ehdr
-#define elf64_internal_ehdr elf_internal_ehdr
-#define Elf64_Internal_Ehdr Elf_Internal_Ehdr
-
 /* Program header */
 
 struct elf_internal_phdr {
@@ -77,10 +72,6 @@ struct elf_internal_phdr {
 };
 
 typedef struct elf_internal_phdr Elf_Internal_Phdr;
-#define elf32_internal_phdr elf_internal_phdr
-#define Elf32_Internal_Phdr Elf_Internal_Phdr
-#define elf64_internal_phdr elf_internal_phdr
-#define Elf64_Internal_Phdr Elf_Internal_Phdr
 
 /* Section header */
 
@@ -101,11 +92,6 @@ typedef struct elf_internal_shdr {
   unsigned char *contents;		/* Section contents.  */
 } Elf_Internal_Shdr;
 
-#define elf32_internal_shdr elf_internal_shdr
-#define Elf32_Internal_Shdr Elf_Internal_Shdr
-#define elf64_internal_shdr elf_internal_shdr
-#define Elf64_Internal_Shdr Elf_Internal_Shdr
-
 /* Symbol table entry */
 
 struct elf_internal_sym {
@@ -119,11 +105,6 @@ struct elf_internal_sym {
 
 typedef struct elf_internal_sym Elf_Internal_Sym;
 
-#define elf32_internal_sym elf_internal_sym
-#define elf64_internal_sym elf_internal_sym
-#define Elf32_Internal_Sym Elf_Internal_Sym
-#define Elf64_Internal_Sym Elf_Internal_Sym
-
 /* Note segments */
 
 typedef struct elf_internal_note {
@@ -134,33 +115,15 @@ typedef struct elf_internal_note {
   char *	descdata;		/* Start of the desc data */
   bfd_vma	descpos;		/* File offset of the descdata */
 } Elf_Internal_Note;
-#define Elf32_Internal_Note	Elf_Internal_Note
-#define elf32_internal_note	elf_internal_note
 
 /* Relocation Entries */
 
-typedef struct elf_internal_rel {
-  bfd_vma	r_offset;	/* Location at which to apply the action */
-  /* This needs to support 64-bit values in elf64.  */
-  bfd_vma	r_info;		/* index and type of relocation */
-} Elf_Internal_Rel;
-
-#define elf32_internal_rel elf_internal_rel
-#define Elf32_Internal_Rel Elf_Internal_Rel
-#define elf64_internal_rel elf_internal_rel
-#define Elf64_Internal_Rel Elf_Internal_Rel
-
 typedef struct elf_internal_rela {
   bfd_vma	r_offset;	/* Location at which to apply the action */
   bfd_vma	r_info;		/* Index and Type of relocation */
   bfd_vma	r_addend;	/* Constant addend used to compute value */
 } Elf_Internal_Rela;
 
-#define elf32_internal_rela elf_internal_rela
-#define elf64_internal_rela elf_internal_rela
-#define Elf32_Internal_Rela Elf_Internal_Rela
-#define Elf64_Internal_Rela Elf_Internal_Rela
-
 /* dynamic section structure */
 
 typedef struct elf_internal_dyn {
@@ -173,11 +136,6 @@ typedef struct elf_internal_dyn {
   } d_un;
 } Elf_Internal_Dyn;
 
-#define elf32_internal_dyn elf_internal_dyn
-#define elf64_internal_dyn elf_internal_dyn
-#define Elf32_Internal_Dyn Elf_Internal_Dyn
-#define Elf64_Internal_Dyn Elf_Internal_Dyn
-
 /* This structure appears in a SHT_GNU_verdef section.  */
 
 typedef struct elf_internal_verdef {
@@ -257,30 +215,6 @@ typedef struct
 } Elf_Internal_Syminfo;
 
 
-#define elf32_internal_verdef elf_internal_verdef
-#define elf64_internal_verdef elf_internal_verdef
-#define elf32_internal_verdaux elf_internal_verdaux
-#define elf64_internal_verdaux elf_internal_verdaux
-#define elf32_internal_verneed elf_internal_verneed
-#define elf64_internal_verneed elf_internal_verneed
-#define elf32_internal_vernaux elf_internal_vernaux
-#define elf64_internal_vernaux elf_internal_vernaux
-#define elf32_internal_versym elf_internal_versym
-#define elf64_internal_versym elf_internal_versym
-
-#define Elf32_Internal_Verdef Elf_Internal_Verdef
-#define Elf64_Internal_Verdef Elf_Internal_Verdef
-#define Elf32_Internal_Verdaux Elf_Internal_Verdaux
-#define Elf64_Internal_Verdaux Elf_Internal_Verdaux
-#define Elf32_Internal_Verneed Elf_Internal_Verneed
-#define Elf64_Internal_Verneed Elf_Internal_Verneed
-#define Elf32_Internal_Vernaux Elf_Internal_Vernaux
-#define Elf64_Internal_Vernaux Elf_Internal_Vernaux
-#define Elf32_Internal_Versym Elf_Internal_Versym
-#define Elf64_Internal_Versym Elf_Internal_Versym
-#define Elf32_Internal_Syminfo Elf_Internal_Syminfo
-#define Elf64_Internal_Syminfo Elf_Internal_Syminfo
-
 /* This structure is used to describe how sections should be assigned
    to program segments.  */
 
diff --git a/include/elf/m68hc11.h b/include/elf/m68hc11.h
index c4ef37d979e..1902f7fa678 100644
--- a/include/elf/m68hc11.h
+++ b/include/elf/m68hc11.h
@@ -64,6 +64,24 @@ END_RELOC_NUMBERS (R_M68HC11_max)
 /* Uses 68HC12 memory banks.  */
 #define E_M68HC12_BANKS 0x000000004
 
+#define EF_M68HC11_MACH_MASK 0xF0
+#define EF_M68HC11_GENERIC   0x00 /* Generic 68HC12/backward compatibility.  */
+#define EF_M68HC12_MACH      0x10 /* 68HC12 microcontroller.  */
+#define EF_M68HCS12_MACH     0x20 /* 68HCS12 microcontroller.  */
+#define EF_M68HC11_MACH(mach) ((mach) & EF_M68HC11_MACH_MASK)
+
+/* True if we can merge machines.  A generic HC12 can work on any proc
+   but once we have specific code, merge is not possible.  */
+#define EF_M68HC11_CAN_MERGE_MACH(mach1, mach2) \
+  ((EF_M68HC11_MACH (mach1) == EF_M68HC11_MACH (mach2)) \
+   || (EF_M68HC11_MACH (mach1) == EF_M68HC11_GENERIC) \
+   || (EF_M68HC11_MACH (mach2) == EF_M68HC11_GENERIC))
+
+#define EF_M68HC11_MERGE_MACH(mach1, mach2) \
+  (((EF_M68HC11_MACH (mach1) == EF_M68HC11_MACH (mach2)) \
+    || (EF_M68HC11_MACH (mach1) == EF_M68HC11_GENERIC)) ? \
+      EF_M68HC11_MACH (mach2) : EF_M68HC11_MACH (mach1))
+
 
 /* Special values for the st_other field in the symbol table.  These
    are used for 68HC12 to identify far functions (must be called with
diff --git a/include/elf/mmix.h b/include/elf/mmix.h
index e3be26b0f79..98536e2465c 100644
--- a/include/elf/mmix.h
+++ b/include/elf/mmix.h
@@ -1,5 +1,5 @@
 /* MMIX support for BFD.
-   Copyright (C) 2001, 2002 Free Software Foundation, Inc.
+   Copyright 2001, 2002 Free Software Foundation, Inc.
 
 This file is part of BFD, the Binary File Descriptor library.
 
@@ -157,11 +157,11 @@ END_RELOC_NUMBERS (R_MMIX_max)
 #define MMO_SEC_DEBUGGING 0x10000
 
 #ifdef BFD_ARCH_SIZE
-extern boolean _bfd_mmix_prepare_linker_allocated_gregs
+extern bfd_boolean _bfd_mmix_prepare_linker_allocated_gregs
  PARAMS ((bfd *, struct bfd_link_info *));
-extern boolean _bfd_mmix_finalize_linker_allocated_gregs
+extern bfd_boolean _bfd_mmix_finalize_linker_allocated_gregs
  PARAMS ((bfd *, struct bfd_link_info *));
-extern boolean _bfd_mmix_check_all_relocs
+extern bfd_boolean _bfd_mmix_check_all_relocs
  PARAMS ((bfd *, struct bfd_link_info *));
 #endif
 
diff --git a/include/elf/sh.h b/include/elf/sh.h
index ef964d685e8..68a2c542e66 100644
--- a/include/elf/sh.h
+++ b/include/elf/sh.h
@@ -106,7 +106,7 @@ extern enum sh64_elf_cr_type sh64_get_contents_type
 
 /* Simpler interface.
    FIXME: This seems redundant now that we export the interface above.  */
-extern boolean sh64_address_is_shmedia PARAMS ((asection *, bfd_vma));
+extern bfd_boolean sh64_address_is_shmedia PARAMS ((asection *, bfd_vma));
 
 extern int _bfd_sh64_crange_qsort_cmpb PARAMS ((const void *, const void *));
 extern int _bfd_sh64_crange_qsort_cmpl PARAMS ((const void *, const void *));
diff --git a/include/elf/xstormy16.h b/include/elf/xstormy16.h
index ee6c551a059..6b1e98f5774 100644
--- a/include/elf/xstormy16.h
+++ b/include/elf/xstormy16.h
@@ -1,5 +1,5 @@
 /* XSTORMY16 ELF support for BFD.
-   Copyright (C) 2001 Free Software Foundation, Inc.
+   Copyright (C) 2001, 2002 Free Software Foundation, Inc.
 
 This file is part of BFD, the Binary File Descriptor library.
 
@@ -37,6 +37,10 @@ START_RELOC_NUMBERS (elf_xstormy16_reloc_type)
   RELOC_NUMBER (R_XSTORMY16_24, 8)
   RELOC_NUMBER (R_XSTORMY16_FPTR16, 9)
 
+  RELOC_NUMBER (R_XSTORMY16_LO16, 10)
+  RELOC_NUMBER (R_XSTORMY16_HI16, 11)
+  RELOC_NUMBER (R_XSTORMY16_12, 12)
+
   RELOC_NUMBER (R_XSTORMY16_GNU_VTINHERIT, 128)
   RELOC_NUMBER (R_XSTORMY16_GNU_VTENTRY, 129)
 END_RELOC_NUMBERS (R_XSTORMY16_max)
diff --git a/include/libiberty.h b/include/libiberty.h
index 983fd96e5ae..f9916c58c73 100644
--- a/include/libiberty.h
+++ b/include/libiberty.h
@@ -74,7 +74,7 @@ extern char **dupargv PARAMS ((char **)) ATTRIBUTE_MALLOC;
    to find the declaration so provide a fully prototyped one.  If it
    is 1, we found it so don't provide any declaration at all.  */
 #if !HAVE_DECL_BASENAME
-#if defined (__GNU_LIBRARY__ ) || defined (__linux__) || defined (__FreeBSD__) || defined (__OpenBSD__) || defined (__CYGWIN__) || defined (__CYGWIN32__) || defined (HAVE_DECL_BASENAME)
+#if defined (__GNU_LIBRARY__ ) || defined (__linux__) || defined (__FreeBSD__) || defined (__OpenBSD__) || defined(__NetBSD__) || defined (__CYGWIN__) || defined (__CYGWIN32__) || defined (HAVE_DECL_BASENAME)
 extern char *basename PARAMS ((const char *));
 #else
 extern char *basename ();
@@ -145,6 +145,12 @@ extern char * getpwd PARAMS ((void));
 
 extern long get_run_time PARAMS ((void));
 
+/* Generate a relocated path to some installation directory.  Allocates
+   return value using malloc.  */
+
+extern char *make_relative_prefix PARAMS ((const char *, const char *,
+					   const char *));
+
 /* Choose a temporary directory to use for scratch files.  */
 
 extern char *choose_temp_base PARAMS ((void)) ATTRIBUTE_MALLOC;
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index af5707e8e88..5aa92e9ab23 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,70 @@
+2002-12-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* hppa.h (completer_chars): #if 0 out.
+
+	* ns32k.h (struct ns32k_opcode): Constify "name", "operands" and
+	"default_args".
+	(struct not_wot): Constify "args".
+	(struct not): Constify "name".
+	(numopcodes): Delete.
+	(endop): Delete.
+
+2002-12-13  Alan Modra  <amodra@bigpond.net.au>
+
+	* pj.h (pj_opc_info_t): Add union.
+
+2002-12-04  David Mosberger  <davidm@hpl.hp.com>
+
+	* ia64.h: Fix copyright message.
+	(IA64_OPND_AR_CSD): New operand kind.
+
+2002-12-03  Richard Henderson  <rth@redhat.com>
+
+	* ia64.h (enum ia64_opnd): Add IA64_OPND_LDXMOV.
+
+2002-12-03  Alan Modra  <amodra@bigpond.net.au>
+
+	* cgen.h (struct cgen_maybe_multi_ifield): Add "const PTR p" to union.
+	Constify "leaf" and "multi".
+
+2002-11-19  Klee Dienes  <kdienes@apple.com>
+
+	* h8300.h (h8_opcode): Remove 'noperands', 'idx', and 'size'
+	fields.
+	(h8_opcodes). Modify initializer and initializer macros to no
+	longer initialize the removed fields.
+	
+2002-11-19  Svein E. Seldal  <Svein.Seldal@solidas.com>
+
+	* tic4x.h (c4x_insts): Fixed LDHI constraint
+
+2002-11-18  Klee Dienes  <kdienes@apple.com>
+
+	* h8300.h (h8_opcode): Remove 'length' field.
+	(h8_opcodes): Mark as 'const' (both the declaration and
+	definition).  Modify initializer and initializer macros to no
+	longer initialize the length field.
+
+2002-11-18  Klee Dienes  <kdienes@apple.com>
+
+	* arc.h (arc_ext_opcodes): Declare as extern.
+	(arc_ext_operands): Declare as extern.
+	* i860.h (i860_opcodes): Declare as const.
+
+2002-11-18  Svein E. Seldal  <Svein.Seldal@solidas.com>
+
+	* tic4x.h: File reordering. Added enhanced opcodes.
+
+2002-11-16  Svein E. Seldal  <Svein.Seldal@solidas.com>
+
+	* tic4x.h: Major rewrite of entire file. Define instruction
+	  classes, and put each instruction into a class.
+
+2002-11-11  Svein E. Seldal  <Svein.Seldal@solidas.com>
+
+	* tic4x.h: Added new opcodes and corrected some bugs.  Add support
+	for new DSP types.
+
 2002-10-14  Alan Modra  <amodra@bigpond.net.au>
 
 	* cgen.h: Test __BFD_H_SEEN__ rather than BFD_VERSION_DATE.
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index b137840156c..3da68ec80f3 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -98,7 +98,7 @@ struct arc_opcode {
 
 /* this is an "insert at front" linked list per Metaware spec
    that new definitions override older ones.  */
-struct arc_opcode *arc_ext_opcodes;
+extern struct arc_opcode *arc_ext_opcodes;
 
 struct arc_operand_value {
   char *name;          /* eg: "eq"  */
@@ -117,7 +117,9 @@ struct arc_operand_value {
 struct arc_ext_operand_value {
   struct arc_ext_operand_value *next;
   struct arc_operand_value operand;
-} *arc_ext_operands;
+};
+
+extern struct arc_ext_operand_value *arc_ext_operands;
 
 struct arc_operand {
 /* One of the insn format chars.  */
diff --git a/include/opcode/cgen.h b/include/opcode/cgen.h
index 89477985e5d..76a0af47b5d 100644
--- a/include/opcode/cgen.h
+++ b/include/opcode/cgen.h
@@ -1,6 +1,7 @@
 /* Header file for targets using CGEN: Cpu tools GENerator.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002
+Free Software Foundation, Inc.
 
 This file is part of GDB, the GNU debugger, and the GNU Binutils.
 
@@ -620,8 +621,9 @@ typedef struct cgen_maybe_multi_ifield
 		n: indexed by array of more cgen_maybe_multi_ifields.  */
   union
   {
-    struct cgen_maybe_multi_ifield * multi;
-    struct cgen_ifld * leaf;
+    const PTR p;
+    const struct cgen_maybe_multi_ifield * multi;
+    const struct cgen_ifld * leaf;
   } val;
 }
 CGEN_MAYBE_MULTI_IFLD;
diff --git a/include/opcode/h8300.h b/include/opcode/h8300.h
index 18d17c537dc..d5404c2c2ff 100644
--- a/include/opcode/h8300.h
+++ b/include/opcode/h8300.h
@@ -151,20 +151,16 @@ struct h8_opcode
   char *name;
   struct arg args;
   struct code data;
-  int length;
-  int noperands;
-  int idx;
-  int size;
 };
 
 #ifdef DEFINE_TABLE
 
 #define BITOP(code, imm, name, op00, op01,op10,op11, op20,op21,op30)\
-{ code, 1, 2, name,	{{imm,RD8,E}},	{{op00, op01, imm, RD8, E, 0, 0, 0, 0}}, 0, 0, 0, 0},\
-{ code, 1, 6, name,	{{imm,RDIND,E}},{{op10, op11, B30|RDIND, 0, op00,op01, imm, 0, E}}, 0, 0, 0, 0},\
-{ code, 1, 6, name,	{{imm,ABS8DST,E}},{{op20, op21, ABS8DST, IGNORE, op00,op01, imm, 0,E}}, 0, 0, 0, 0}\
-,{ code, 0, 6, name,	{{imm,ABS16DST,E}},{{0x6,0xa,0x1,op30,ABS16DST,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}}, 0, 0, 0, 0},\
-{ code, 0, 6, name,	{{imm,ABS32DST,E}},{{0x6,0xa,0x3,op30,ABS32DST,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}}, 0, 0, 0, 0}
+{ code, 1, 2, name,	{{imm,RD8,E}},	{{op00, op01, imm, RD8, E, 0, 0, 0, 0}}},\
+{ code, 1, 6, name,	{{imm,RDIND,E}},{{op10, op11, B30|RDIND, 0, op00,op01, imm, 0, E}}},\
+{ code, 1, 6, name,	{{imm,ABS8DST,E}},{{op20, op21, ABS8DST, IGNORE, op00,op01, imm, 0,E}}}\
+,{ code, 0, 6, name,	{{imm,ABS16DST,E}},{{0x6,0xa,0x1,op30,ABS16DST,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}}},\
+{ code, 0, 6, name,	{{imm,ABS32DST,E}},{{0x6,0xa,0x3,op30,ABS32DST,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}}}
 
 
 #define EBITOP(code, imm, name, op00, op01,op10,op11, op20,op21,op30)\
@@ -172,33 +168,33 @@ struct h8_opcode
    BITOP(code,RS8,  name, op00, op01, op10,op11, op20,op21,op30)
 
 #define WTWOP(code,name, op1, op2) \
-{ code, 1, 2, name, {{RS16, RD16, E}}, {{ op1, op2, RS16, RD16, E, 0, 0, 0, 0}}, 0, 0, 0, 0}
+{ code, 1, 2, name, {{RS16, RD16, E}}, {{ op1, op2, RS16, RD16, E, 0, 0, 0, 0}}}
 
 #define BRANCH(code, name, op) \
-{ code, 1, 4,name,{{DISP8,E,0}}, {{ 0x4, op, DISP8, IGNORE, E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \
-{ code, 0, 6,name,{{DISP16,E,0}}, {{ 0x5, 0x8, op, 0x0, DISP16, IGNORE, IGNORE, IGNORE, E,0}}, 0, 0, 0, 0} 
+{ code, 1, 4,name,{{DISP8,E,0}}, {{ 0x4, op, DISP8, IGNORE, E, 0, 0, 0, 0}}}, \
+{ code, 0, 6,name,{{DISP16,E,0}}, {{ 0x5, 0x8, op, 0x0, DISP16, IGNORE, IGNORE, IGNORE, E,0}}} 
 
 #define SOP(code, x,name) \
 {code, 1, x,  name 
 
 #define NEW_SOP(code, in,x,name) \
 {code, in, x,  name 
-#define EOP  ,0,0,0,0 }
+#define EOP  }
 
 #define TWOOP(code, name, op1, op2,op3) \
-{ code,1, 2,name, {{IMM8, RD8, E}},	{{ op1, RD8, IMM8, IGNORE, E, 0, 0, 0, 0}}, 0, 0, 0, 0},\
-{ code, 1, 2,name, {{RS8, RD8, E}},	{{ op2, op3, RS8, RD8, E, 0, 0, 0, 0}}, 0, 0, 0, 0} 
+{ code,1, 2,name, {{IMM8, RD8, E}},	{{ op1, RD8, IMM8, IGNORE, E, 0, 0, 0, 0}}},\
+{ code, 1, 2,name, {{RS8, RD8, E}},	{{ op2, op3, RS8, RD8, E, 0, 0, 0, 0}}} 
 
 #define UNOP(code,name, op1, op2) \
-{ code, 1, 2, name, {{OR8, E, 0}}, {{ op1, op2, 0, OR8, E, 0, 0, 0, 0}}, 0, 0, 0, 0}
+{ code, 1, 2, name, {{OR8, E, 0}}, {{ op1, op2, 0, OR8, E, 0, 0, 0, 0}}}
 
 #define UNOP3(code, name, op1, op2, op3) \
-{ O(code,SB), 1, 2, name, {{OR8,  E, 0}}, {{op1, op2, op3+0, OR8,  E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \
-{ O(code,SW), 0, 2, name, {{OR16, E, 0}}, {{op1, op2, op3+1, OR16, E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \
-{ O(code,SL), 0, 2, name, {{OR32, E, 0}}, {{op1, op2, op3+3, OR32|B30, E, 0, 0, 0, 0}}, 0, 0, 0, 0} \
-,{ O(code,SB), 1, 2, name, {{IMM, OR8 | SRC_IN_DST,  E}}, {{op1, op2, op3+4, OR8 | SRC_IN_DST,  E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \
-{ O(code,SW), 0, 2, name, {{IMM, OR16 | SRC_IN_DST, E}}, {{op1, op2, op3+5, OR16 | SRC_IN_DST, E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \
-{ O(code,SL), 0, 2, name, {{IMM, OR32 | SRC_IN_DST, E}}, {{op1, op2, op3+7, OR32 | SRC_IN_DST|B30 , E, 0, 0, 0, 0}}, 0, 0, 0, 0}
+{ O(code,SB), 1, 2, name, {{OR8,  E, 0}}, {{op1, op2, op3+0, OR8,  E, 0, 0, 0, 0}}}, \
+{ O(code,SW), 0, 2, name, {{OR16, E, 0}}, {{op1, op2, op3+1, OR16, E, 0, 0, 0, 0}}}, \
+{ O(code,SL), 0, 2, name, {{OR32, E, 0}}, {{op1, op2, op3+3, OR32|B30, E, 0, 0, 0, 0}}} \
+,{ O(code,SB), 1, 2, name, {{IMM, OR8 | SRC_IN_DST,  E}}, {{op1, op2, op3+4, OR8 | SRC_IN_DST,  E, 0, 0, 0, 0}}}, \
+{ O(code,SW), 0, 2, name, {{IMM, OR16 | SRC_IN_DST, E}}, {{op1, op2, op3+5, OR16 | SRC_IN_DST, E, 0, 0, 0, 0}}}, \
+{ O(code,SL), 0, 2, name, {{IMM, OR32 | SRC_IN_DST, E}}, {{op1, op2, op3+7, OR32 | SRC_IN_DST|B30 , E, 0, 0, 0, 0}}}
 
 
 #define IMM32LIST IMM32,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
@@ -314,7 +310,7 @@ struct h8_opcode
 /* FIXME: Lots of insns have "E, 0, 0, 0, 0" in the nibble code sequences.
    Methinks the zeroes aren't necessary.  Once confirmed, nuke 'em.  */
 
-struct h8_opcode h8_opcodes[] = 
+const struct h8_opcode h8_opcodes[] = 
 {
   TWOOP(O(O_ADD,SB),"add.b", 0x8, 0x0,0x8),
   
@@ -594,8 +590,8 @@ struct h8_opcode h8_opcodes[] =
   NEW_SOP(O(O_STMAC,SL),1,2,"stmac"),{{MACREG,RD32,E}},{{0x0,0x2,MACREG,RD32,E}} EOP,
   NEW_SOP(O(O_LDM,SL),0,6,"ldm.l"),{{RSINC, RS32, E}},{{ 0x0,0x1,IGNORE,0x0,0x6,0xD,0x7,IGNORE,E}}EOP,
   NEW_SOP(O(O_STM,SL),0,6,"stm.l"),{{RS32, RDDEC, E}},{{0x0,0x1,IGNORE,0x0,0x6,0xD,0xF,IGNORE,E}}EOP,
-  {0, 0, 0, NULL, {{0,0,0}}, {{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}}, 0, 0, 0, 0}
+  {0, 0, 0, NULL, {{0,0,0}}, {{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}}}
 };
 #else
-extern struct h8_opcode h8_opcodes[];
+extern const struct h8_opcode h8_opcodes[];
 #endif
diff --git a/include/opcode/hppa.h b/include/opcode/hppa.h
index e9070914271..471161788ad 100644
--- a/include/opcode/hppa.h
+++ b/include/opcode/hppa.h
@@ -1,6 +1,6 @@
 /* Table of opcodes for the PA-RISC.
    Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000,
-   2001
+   2001, 2002
    Free Software Foundation, Inc.
 
    Contributed by the Center for Software Science at the
@@ -271,10 +271,12 @@ Float registers for fmpyadd and fmpysub:
 */
 
 
+#if 0
 /* List of characters not to put a space after.  Note that
    "," is included, as the "spopN" operations use literal
    commas in their completer sections.  */
 static const char *const completer_chars = ",CcY<>?!@+&U~FfGHINnOoZMadu|/=0123%e$m}";
+#endif
 
 /* The order of the opcodes in this table is significant:
 
diff --git a/include/opcode/i860.h b/include/opcode/i860.h
index 9f10cd86b89..2d6ea19abea 100644
--- a/include/opcode/i860.h
+++ b/include/opcode/i860.h
@@ -96,7 +96,7 @@ Kinds of operands:
  
    The order of opcodes does not affect the disassembler.  */
 
-static struct i860_opcode i860_opcodes[] =
+static const struct i860_opcode i860_opcodes[] =
 {
 /* REG-Format Instructions.  */
 { "ld.c",	0x30000000, 0xcc000000, "c,d", 0 },	/* ld.c csrc2,idest */
diff --git a/include/opcode/ia64.h b/include/opcode/ia64.h
index d4e6d108137..0d33fc61b2c 100644
--- a/include/opcode/ia64.h
+++ b/include/opcode/ia64.h
@@ -1,7 +1,6 @@
 /* ia64.h -- Header file for ia64 opcode table
-   Copyright (C) 1998, 1999, 2002 David Mosberger-Tang <davidm@hpl.hp.com>
-
-   See the file HP-COPYRIGHT for additional information.  */
+   Copyright (C) 1998, 1999, 2002 Free Software Foundation, Inc.
+	Contributed by David Mosberger-Tang <davidm@hpl.hp.com> */
 
 #ifndef opcode_ia64_h
 #define opcode_ia64_h
@@ -39,13 +38,14 @@ enum ia64_unit
   };
 
 /* Changes to this enumeration must be propagated to the operand table in
-   bfd/cpu-ia64-opc.c 
- */ 
+   bfd/cpu-ia64-opc.c
+ */
 enum ia64_opnd
   {
     IA64_OPND_NIL,	/* no operand---MUST BE FIRST!*/
 
     /* constants */
+    IA64_OPND_AR_CSD,	/* application register csd (ar.csd) */
     IA64_OPND_AR_CCV,	/* application register ccv (ar.ccv) */
     IA64_OPND_AR_PFS,	/* application register pfs (ar.pfs) */
     IA64_OPND_C1,	/* the constant 1 */
@@ -133,6 +133,7 @@ enum ia64_opnd
     IA64_OPND_TGT25b,	/* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */
     IA64_OPND_TGT25c,	/* signed 25-bit (ip + 16*bits 13-32, 36) */
     IA64_OPND_TGT64,    /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */
+    IA64_OPND_LDXMOV,	/* any symbol, generates R_IA64_LDXMOV.  */
 
     IA64_OPND_COUNT	/* # of operand types (MUST BE LAST!) */
   };
@@ -287,7 +288,7 @@ struct ia64_opcode
     /* Used by ia64_find_next_opcode (). */
     short ent_index;
 
-    /* Opcode dependencies. */ 
+    /* Opcode dependencies. */
     const struct ia64_opcode_dependency *dependencies;
   };
 
diff --git a/include/opcode/m88k.h b/include/opcode/m88k.h
index 3dd5b733d84..6a163bbe934 100644
--- a/include/opcode/m88k.h
+++ b/include/opcode/m88k.h
@@ -439,496 +439,12 @@ typedef struct INSTRUCTAB {
   char          *mnemonic;
   OPSPEC        op1,op2,op3;
   struct SIM_FLAGS flgs;
-  struct INSTRUCTAB    *next;
 } INSTAB;
 
 
 #define NO_OPERAND {0,0,0}
 
-/* Opcode     Mnemonic       Op 1 Spec     Op 2 Spec    Op 3 Spec         Simflags             Next  */
-
-static INSTAB  instructions[] = {
-  {0xf400c800,"jsr         ",{0,5,REG}   ,NO_OPERAND      ,NO_OPERAND   , {2,2,NA,JSR ,          0,0,1,0,0,0,0,1,0,0,0,0}, NULL },
-  {0xf400cc00,"jsr.n       ",{0,5,REG}   ,NO_OPERAND      ,NO_OPERAND   , {1,1,NA,JSR ,          0,0,1,0,0,0,1,1,0,0,0,0}, NULL },
-  {0xf400c000,"jmp         ",{0,5,REG}   ,NO_OPERAND      ,NO_OPERAND   , {2,2,NA,JMP ,          0,0,1,0,0,0,0,1,0,0,0,0}, NULL },
-  {0xf400c400,"jmp.n       ",{0,5,REG}   ,NO_OPERAND      ,NO_OPERAND   , {1,1,NA,JMP ,          0,0,1,0,0,0,1,1,0,0,0,0}, NULL },
-  {0xc8000000,"bsr         ",{0,26,PCREL},NO_OPERAND      ,NO_OPERAND   , {2,2,NA,BSR ,     i26bit,0,0,0,0,0,0,1,0,0,0,0}, NULL },
-  {0xcc000000,"bsr.n       ",{0,26,PCREL},NO_OPERAND      ,NO_OPERAND   , {1,1,NA,BSR ,     i26bit,0,0,0,0,0,1,1,0,0,0,0}, NULL },
-  {0xc0000000,"br          ",{0,26,PCREL},NO_OPERAND      ,NO_OPERAND   , {2,2,NA,BR  ,     i26bit,0,0,0,0,0,0,1,0,0,0,0}, NULL },
-  {0xc4000000,"br.n        ",{0,26,PCREL},NO_OPERAND      ,NO_OPERAND   , {1,1,NA,BR  ,     i26bit,0,0,0,0,0,1,1,0,0,0,0}, NULL },
-  {0xd0000000,"bb0         ",{21,5,HEX}  ,{16,5,REG}   ,{0,16,PCREL},{2,2,NA,BB0,     i16bit,0,1,0,0,0,0,1,0,0,0,0}, NULL },
-  {0xd4000000,"bb0.n       ",{21,5,HEX}  ,{16,5,REG}   ,{0,16,PCREL},{1,1,NA,BB0,     i16bit,0,1,0,0,0,1,1,0,0,0,0}, NULL },
-  {0xd8000000,"bb1         ",{21,5,HEX},{16,5,REG}     ,{0,16,PCREL},{2,2,NA,BB1,     i16bit,0,1,0,0,0,0,1,0,0,0,0}, NULL },
-  {0xdc000000,"bb1.n       ",{21,5,HEX},{16,5,REG}     ,{0,16,PCREL},{1,1,NA,BB1,     i16bit,0,1,0,0,0,1,1,0,0,0,0}, NULL },
-  {0xf000d000,"tb0         ",{21,5,HEX}  ,{16,5,REG}   ,{0,10,HEX}, {2,2,NA,TB0 ,     i10bit,0,1,0,0,0,0,1,0,0,0,0}, NULL },
-  {0xf000d800,"tb1         ",{21,5,HEX}  ,{16,5,REG}   ,{0,10,HEX}, {2,2,NA,TB1 ,     i10bit,0,1,0,0,0,0,1,0,0,0,0}, NULL },
-  {0xe8000000,"bcnd        ",{21,5,CONDMASK},{16,5,REG},{0,16,PCREL},{2,2,NA,BCND,    i16bit,0,1,0,0,0,0,1,0,0,0,0}, NULL },
-  {0xec000000,"bcnd.n      ",{21,5,CONDMASK},{16,5,REG},{0,16,PCREL},{1,1,NA,BCND,    i16bit,0,1,0,0,0,1,1,0,0,0,0}, NULL },
-  {0xf000e800,"tcnd        ",{21,5,CONDMASK},{16,5,REG},{0,10,HEX}, {2,2,NA,TCND,     i10bit,0,1,0,0,0,0,1,0,0,0,0}, NULL },
-  {0xf8000000,"tbnd        ",{16,5,REG}  ,{0,16,HEX}   ,NO_OPERAND   , {2,2,NA,TBND,     i10bit,1,0,0,0,0,0,1,0,0,0,0}, NULL },
-  {0xf400f800,"tbnd        ",{16,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {2,2,NA,TBND,          0,1,1,0,0,0,0,1,0,0,0,0}, NULL },
-  {0xf400fc00,"rte         ",NO_OPERAND     ,NO_OPERAND      ,NO_OPERAND   , {2,2,NA,RTE ,          0,0,0,0,0,0,0,1,0,0,0,0}, NULL },
-  {0x1c000000,"ld.b        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,LDB    ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4001c00,"ld.b        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,LDB     ,    0,1,1,1,0,0,0,1,0,0,0,0}, NULL },
-  {0x0c000000,"ld.bu       ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,LDBU,   i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4000c00,"ld.bu       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,LDBU        ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL },
-  {0x18000000,"ld.h        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,LDH    ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4001800,"ld.h        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,LDH         ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4001a00,"ld.h        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{3,1,PMEM,LDH         ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL },
-  {0x08000000,"ld.hu       ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,LDHU,   i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4000800,"ld.hu       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,LDHU        ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4000a00,"ld.hu       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{3,1,PMEM,LDHU        ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL },
-  {0x14000000,"ld          ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,LD     ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4001400,"ld          ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,LD          ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4001600,"ld          ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{3,1,PMEM,LD          ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL },
-  {0x10000000,"ld.d        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,LDD    ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4001000,"ld.d        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,LDD         ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4001200,"ld.d        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{3,1,PMEM,LDD         ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL },
-  {0xf4001500,"ld.usr      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,LD          ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4001700,"ld.usr      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{3,1,PMEM,LD          ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL },
-  {0x2c000000,"st.b        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,NA,STB      ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4002c00,"st.b        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,NA,STB           ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL },
-  {0x28000000,"st.h        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,NA,STH      ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4002800,"st.h        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,NA,STH           ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4002a00,"st.h        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,NA,STH           ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL },
-  {0x24000000,"st          ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,NA,ST       ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4002400,"st          ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,NA,ST            ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0xf4002600,"st          ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,NA,ST            ,0,1,1,1,0,0,0,1,0,0,0,1}   ,NULL },
-  {0x20000000,"st.d        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,NA,STD      ,i16bit,0,1,0,0,0,0,1,0,0,0,0}   ,NULL },
-  {0xf4002000,"st.d        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,NA,STD           ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0xf4002200,"st.d        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,NA,STD           ,0,1,1,1,0,0,0,1,0,0,0,1}   ,NULL },
-  {0xf4002500,"st.usr      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,NA,ST            ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0xf4002700,"st.usr      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,NA,ST            ,0,1,1,1,0,0,0,1,0,0,0,1}   ,NULL },
-/*  m88100 only:
-  {0x00000000,"xmem.bu     ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,XMEMBU ,i16bit,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
- */
-  {0xf4000000,"xmem.bu     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,XMEM        ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-/*  m88100 only:
-  {0x04000000,"xmem        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,XMEM   ,i16bit,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
- */
-  {0xf4000400,"xmem        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,XMEM        ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0xf4000600,"xmem        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{3,1,PMEM,XMEM        ,0,1,1,1,0,0,0,1,0,0,0,1}   ,NULL },
-  {0xf4000500,"xmem.usr    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,XMEM        ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0xf4000700,"xmem.usr    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{3,1,PMEM,XMEM        ,0,1,1,1,0,0,0,1,0,0,0,1}   ,NULL },
-/* m88100 only:
-  {0xf4003e00,"lda.b       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,PINT,LDAH,        0,1,1,1,0,0,0,0,0,0,0,1}   ,NULL },
- */
-  {0xf4003e00,"lda.x       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,PINT,LDAH,        0,1,1,1,0,0,0,0,0,0,0,1}   ,NULL },
-  {0xf4003a00,"lda.h       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,PINT,LDAH,        0,1,1,1,0,0,0,0,0,0,0,1}   ,NULL },
-  {0xf4003600,"lda         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,PINT,LDA ,        0,1,1,1,0,0,0,0,0,0,0,1}   ,NULL },
-  {0xf4003200,"lda.d       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,PINT,LDAD,        0,1,1,1,0,0,0,0,0,0,0,1}   ,NULL },
-
-  {0x80004000,"ldcr        ",{21,5,REG}  ,{5,6,CRREG}  ,NO_OPERAND    ,{1,1,PINT,LDCR,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0x80008000,"stcr        ",{16,5,REG}  ,{5,6,CRREG}  ,NO_OPERAND    ,{1,1,PINT,STCR,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0x8000c000,"xcr         ",{21,5,REG}  ,{16,5,REG}   ,{5,6,CRREG},{1,1,PINT,XCR,         0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-
-  {0xf4006000,"addu        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADDU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4006200,"addu.ci     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADDU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4006100,"addu.co     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADDU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4006300,"addu.cio    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADDU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4006400,"subu        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUBU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4006600,"subu.ci     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUBU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4006500,"subu.co     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUBU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4006700,"subu.cio    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUBU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4006800,"divu        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {32,32,PINT,DIVU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4006900,"divu.d      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,}, NULL },
-  {0xf4006e00,"muls        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,}, NULL },
-  {0xf4006c00,"mulu        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,4,PINT,MUL,      0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4007000,"add         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADD ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4007200,"add.ci      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADD ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4007100,"add.co      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADD ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4007300,"add.cio     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADD ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4007400,"sub         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUB ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4007600,"sub.ci      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUB ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4007500,"sub.co      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUB ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4007700,"sub.cio     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUB ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4007800,"divs        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {32,32,PINT,DIV ,      0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4007c00,"cmp         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,CMP,         0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-
-  {0x60000000,"addu        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,ADDU,   i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0x64000000,"subu        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,SUBU,   i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-
-  {0x68000000,"divu        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {32,32,PINT,DIVU, i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0x6c000000,"mulu        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {4,1,PINT,MUL,    i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0x70000000,"add         ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,ADD,    i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0x74000000,"sub         ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,SUB,    i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0x78000000,"divs        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {32,32,PINT,DIV,  i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0x7c000000,"cmp         ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,CMP,    i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-
-  {0xf4004000,"and         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,AND_        ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4004400,"and.c       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,AND_        ,0,1,1,1,1,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4005800,"or          ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,OR          ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4005c00,"or.c        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,OR          ,0,1,1,1,1,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4005000,"xor         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,XOR         ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4005400,"xor.c       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,XOR         ,0,1,1,1,1,0,0,0,0,0,0,0}   ,NULL },
-  {0x40000000,"and         ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,AND_   ,i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0x44000000,"and.u       ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,AND_   ,i16bit,1,0,1,0,1,0,0,0,0,0,0}   ,NULL },
-  {0x58000000,"or          ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,OR     ,i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0x5c000000,"or.u        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,OR     ,i16bit,1,0,1,0,1,0,0,0,0,0,0}   ,NULL },
-  {0x50000000,"xor         ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,XOR    ,i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0x54000000,"xor.u       ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,XOR    ,i16bit,1,0,1,0,1,0,0,0,0,0,0}   ,NULL },
-  {0x48000000,"mask        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,MASK   ,i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0x4c000000,"mask.u      ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,MASK   ,i16bit,1,0,1,0,1,0,0,0,0,0,0}   ,NULL },
-  {0xf400ec00,"ff0         ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {1,1,PINT,FF0         ,0,0,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf400e800,"ff1         ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {1,1,PINT,FF1         ,0,0,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf0008000,"clr         ",{21,5,REG}  ,{16,5,REG}   ,{0,10,BF} , {1,1,PINT,CLR    ,i10bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf0008800,"set         ",{21,5,REG}  ,{16,5,REG}   ,{0,10,BF} , {1,1,PINT,SET    ,i10bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf0009000,"ext         ",{21,5,REG}  ,{16,5,REG}   ,{0,10,BF} , {1,1,PINT,EXT    ,i10bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf0009800,"extu        ",{21,5,REG}  ,{16,5,REG}   ,{0,10,BF} , {1,1,PINT,EXTU   ,i10bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf000a000,"mak         ",{21,5,REG}  ,{16,5,REG}   ,{0,10,BF} , {1,1,PINT,MAK    ,i10bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf000a800,"rot         ",{21,5,REG}  ,{16,5,REG}   ,{0,10,BF} , {1,1,PINT,ROT    ,i10bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4008000,"clr         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,CLR         ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4008800,"set         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SET         ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4009000,"ext         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,EXT         ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4009800,"extu        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,EXTU        ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf400a000,"mak         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,MAK         ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf400a800,"rot         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ROT         ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-
-  {0x84002800,"fadd.sss    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {5,1,PFLT,FADD        ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0x84002880,"fadd.ssd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FADD        ,0,1,1,1,0,0,0,1,0,0,1,0}   ,NULL },
-  {0x84002a00,"fadd.sds    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FADD        ,0,1,1,1,0,0,0,1,0,1,0,0}   ,NULL },
-  {0x84002a80,"fadd.sdd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FADD        ,0,1,1,1,0,0,0,1,0,1,1,0}   ,NULL },
-  {0x84002820,"fadd.dss    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FADD        ,0,1,1,1,0,0,0,1,1,0,0,0}   ,NULL },
-  {0x840028a0,"fadd.dsd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FADD        ,0,1,1,1,0,0,0,1,1,0,1,0}   ,NULL },
-  {0x84002a20,"fadd.dds    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FADD        ,0,1,1,1,0,0,0,1,1,1,0,0}   ,NULL },
-  {0x84002aa0,"fadd.ddd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FADD        ,0,1,1,1,0,0,0,1,1,1,1,0}   ,NULL },
-  {0x84003000,"fsub.sss    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {5,1,PFLT,FSUB        ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0x84003080,"fsub.ssd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FSUB        ,0,1,1,1,0,0,0,1,0,0,1,0}   ,NULL },
-  {0x84003200,"fsub.sds    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FSUB        ,0,1,1,1,0,0,0,1,0,1,0,0}   ,NULL },
-  {0x84003280,"fsub.sdd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FSUB        ,0,1,1,1,0,0,0,1,0,1,1,0}   ,NULL },
-  {0x84003020,"fsub.dss    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FSUB        ,0,1,1,1,0,0,0,1,1,0,0,0}   ,NULL },
-  {0x840030a0,"fsub.dsd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FSUB        ,0,1,1,1,0,0,0,1,1,0,1,0}   ,NULL },
-  {0x84003220,"fsub.dds    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FSUB        ,0,1,1,1,0,0,0,1,1,1,0,0}   ,NULL },
-  {0x840032a0,"fsub.ddd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FSUB        ,0,1,1,1,0,0,0,1,1,1,1,0}   ,NULL },
-  {0x84000000,"fmul.sss    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,1,PFLT,FMUL        ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0x84000080,"fmul.ssd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {9,2,PFLT,FMUL        ,0,1,1,1,0,0,0,1,0,0,1,0}   ,NULL },
-  {0x84000200,"fmul.sds    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {9,2,PFLT,FMUL        ,0,1,1,1,0,0,0,1,0,1,0,0}   ,NULL },
-  {0x84000280,"fmul.sdd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {9,2,PFLT,FMUL        ,0,1,1,1,0,0,0,1,0,1,1,0}   ,NULL },
-  {0x84000020,"fmul.dss    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {9,2,PFLT,FMUL        ,0,1,1,1,0,0,0,1,1,0,0,0}   ,NULL },
-  {0x840000a0,"fmul.dsd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {9,2,PFLT,FMUL        ,0,1,1,1,0,0,0,1,1,0,1,0}   ,NULL },
-  {0x84000220,"fmul.dds    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {9,2,PFLT,FMUL        ,0,1,1,1,0,0,0,1,1,1,0,0}   ,NULL },
-  {0x840002a0,"fmul.ddd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {9,2,PFLT,FMUL        ,0,1,1,1,0,0,0,1,1,1,1,0}   ,NULL },
-  {0x84007000,"fdiv.sss    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {30,30,PFLT,FDIV      ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0x84007080,"fdiv.ssd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {60,60,PFLT,FDIV      ,0,1,1,1,0,0,0,1,0,0,1,0}   ,NULL },
-  {0x84007200,"fdiv.sds    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {60,60,PFLT,FDIV      ,0,1,1,1,0,0,0,1,0,1,0,0}   ,NULL },
-  {0x84007280,"fdiv.sdd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {60,60,PFLT,FDIV      ,0,1,1,1,0,0,0,1,0,1,1,0}   ,NULL },
-  {0x84007020,"fdiv.dss    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {60,60,PFLT,FDIV      ,0,1,1,1,0,0,0,1,1,0,0,0}   ,NULL },
-  {0x840070a0,"fdiv.dsd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {60,60,PFLT,FDIV      ,0,1,1,1,0,0,0,1,1,0,1,0}   ,NULL },
-  {0x84007220,"fdiv.dds    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {60,60,PFLT,FDIV      ,0,1,1,1,0,0,0,1,1,1,0,0}   ,NULL },
-  {0x840072a0,"fdiv.ddd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {60,60,PFLT,FDIV      ,0,1,1,1,0,0,0,1,1,1,1,0}   ,NULL },
-  {0x84007800,"fsqrt.ss    ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {5,1,PFLT,FLT         ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0x84007820,"fsqrt.sd    ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {5,1,PFLT,FLT         ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0x84007880,"fsqrt.ds    ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {5,1,PFLT,FLT         ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0x840078a0,"fsqrt.dd    ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {6,1,PFLT,FLT         ,0,0,1,1,0,0,0,1,1,0,0,0}   ,NULL },
-  {0x84003800,"fcmp.ss     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {5,1,PFLT,FCMP        ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0x84003880,"fcmp.sd     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,1,PFLT,FCMP        ,0,1,1,1,0,0,0,1,0,1,0,0}   ,NULL },
-  {0x84003a00,"fcmp.ds     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,1,PFLT,FCMP        ,0,1,1,1,0,0,0,1,1,0,0,0}   ,NULL },
-  {0x84003a80,"fcmp.dd     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,1,PFLT,FCMP        ,0,1,1,1,0,0,0,1,1,1,0,0}   ,NULL },
-  {0x84002000,"flt.s       ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {5,1,PFLT,FLT         ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0x84002020,"flt.d       ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {6,1,PFLT,FLT         ,0,0,1,1,0,0,0,1,1,0,0,0}   ,NULL },
-  {0x84004800,"int.s       ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {5,1,PFLT,INT         ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0x84004880,"int.d       ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {6,1,PFLT,INT         ,0,0,1,1,0,0,0,1,1,0,0,0}   ,NULL },
-  {0x84005000,"nint.s      ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {5,1,PFLT,INT         ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0x84005080,"nint.d      ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {6,1,PFLT,INT         ,0,0,1,1,0,0,0,1,1,0,0,0}   ,NULL },
-  {0x84005800,"trnc.s      ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {5,1,PFLT,TRNC        ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0x84005880,"trnc.d      ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {6,1,PFLT,TRNC        ,0,0,1,1,0,0,0,1,1,0,0,0}   ,NULL },
-
-  {0x80004800,"fldcr       ",{21,5,REG}  ,{5,6,FCRREG} ,NO_OPERAND   , {1,1,PFLT,FLDC        ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0x80008800,"fstcr       ",{16,5,REG}  ,{5,6,FCRREG} ,NO_OPERAND   , {1,1,PFLT,FSTC        ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0x8000c800,"fxcr        ",{21,5,REG}  ,{16,5,REG}   ,{5,6,FCRREG} , {1,1,PFLT,FXC         ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-
-/* The following are new for the 88110.  */
-
-  {0x8400aaa0,"fadd.ddd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400aa80,"fadd.dds    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400aac0,"fadd.ddx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400aa20,"fadd.dsd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400aa00,"fadd.dss    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400aa40,"fadd.dsx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400ab20,"fadd.dxd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400ab00,"fadd.dxs    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400ab40,"fadd.dxx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400a8a0,"fadd.sdd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400a880,"fadd.sds    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400a8c0,"fadd.sdx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400a820,"fadd.ssd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400a800,"fadd.sss    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400a840,"fadd.ssx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400a920,"fadd.sxd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400a900,"fadd.sxs    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400a940,"fadd.sxx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400aca0,"fadd.xdd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400ac80,"fadd.xds    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400acc0,"fadd.xdx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400ac20,"fadd.xsd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400ac00,"fadd.xss    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400ac40,"fadd.xsx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400ad20,"fadd.xxd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400ad00,"fadd.xxs    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400ad40,"fadd.xxx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x8400ba80,"fcmp.sdd    ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400ba00,"fcmp.sds    ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400bb00,"fcmp.sdx    ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400b880,"fcmp.ssd    ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400b800,"fcmp.sss    ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400b900,"fcmp.ssx    ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400bc80,"fcmp.sxd    ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400bc00,"fcmp.sxs    ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400bd00,"fcmp.sxx    ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x8400baa0,"fcmpu.sdd   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400ba20,"fcmpu.sds   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400bb20,"fcmpu.sdx   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400b8a0,"fcmpu.ssd   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400b820,"fcmpu.sss   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400b920,"fcmpu.ssx   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400bca0,"fcmpu.sxd   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400bc20,"fcmpu.sxs   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400bd20,"fcmpu.sxx   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x84000820,"fcvt.sd     ",{21,5,REG} ,{0,5,REG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x84000880,"fcvt.ds     ",{21,5,REG} ,{0,5,REG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x84008880,"fcvt.ds     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x840088c0,"fcvt.dx     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x84008820,"fcvt.sd     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x84008840,"fcvt.sx     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x84008920,"fcvt.xd     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x84008900,"fcvt.xs     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x8400f2a0,"fdiv.ddd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400f280,"fdiv.dds    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400f2c0,"fdiv.ddx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400f220,"fdiv.dsd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400f200,"fdiv.dss    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400f240,"fdiv.dsx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400f320,"fdiv.dxd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400f300,"fdiv.dxs    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400f340,"fdiv.dxx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400f0a0,"fdiv.sdd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400f080,"fdiv.sds    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400f0c0,"fdiv.sdx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400f020,"fdiv.ssd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400f000,"fdiv.sss    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
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-  {0x84008480,"fmul.xds    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x840084c0,"fmul.xdx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
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-  {0x8400f900,"fsqrt.xs    ",{21,5,XREG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
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-  {0x8400b2a0,"fsub.ddd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
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-  {0xf0001500,"ld.usr      ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
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-  {0xf0001900,"ld.x.usr    ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
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-  {0xf0001600,"ld          ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0001200,"ld.d        ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
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-  {0xf0001700,"ld.usr      ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
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-  {0xf0001b00,"ld.x.usr    ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
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-  {0x8400c000,"mov.s       ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400c080,"mov.d       ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x84004200,"mov.s       ", {21,5,XREG}, {0,5,REG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x84004280,"mov.d       ", {21,5,XREG}, {0,5,REG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400c300,"mov         ", {21,5,XREG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0xf4006d00,"mulu.d      ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x8400d080,"nint.sd     ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400d000,"nint.ss     ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400d100,"nint.sx     ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x88002020,"padd.b      ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88002040,"padd.h      ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88002060,"padd        ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x880021e0,"padds.s     ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x880021a0,"padds.s.b   ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x880021c0,"padds.s.h   ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x880020e0,"padds.u     ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x880020a0,"padds.u.b   ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x880020c0,"padds.u.h   ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88002160,"padds.us    ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88002120,"padds.us.b  ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88002140,"padds.us.h  ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x88003860,"pcmp        ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x88000000,"pmul        ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x88006260,"ppack.16    ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88006240,"ppack.16.h  ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88006460,"ppack.32    ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88006420,"ppack.32.b  ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88006440,"ppack.32.h  ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88006160,"ppack.8     ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x88007200,"prot        ", {21,5,REG}, {16,5,REG}, {5,6,HEX}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88007800,"prot        ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x88003020,"psub.b      ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88003040,"psub.h      ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88003060,"psub        ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x880031e0,"psubs.s     ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x880031a0,"psubs.s.b   ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x880031c0,"psubs.s.h   ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x880030e0,"psubs.u     ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x880030a0,"psubs.u.b   ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x880030c0,"psubs.u.h   ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88003160,"psubs.us    ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88003120,"psubs.us.b  ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88003140,"psubs.us.h  ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x88006800,"punpk.n     ", {21,5,REG}, {16,5,REG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88006820,"punpk.b     ", {21,5,REG}, {16,5,REG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x34000000,"st          ", {21,5,XREG}, {16,5,REG}, {0,16,HEX}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x30000000,"st.d        ", {21,5,XREG}, {16,5,REG}, {0,16,HEX}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x38000000,"st.x        ", {21,5,XREG}, {16,5,REG}, {0,16,HEX}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0xf4002c80,"st.b.wt     ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf4002880,"st.h.wt     ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf4002480,"st.wt       ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf4002080,"st.d.wt     ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf4002d80,"st.b.usr.wt ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf4002980,"st.h.usr.wt ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf4002580,"st.usr.wt   ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf4002180,"st.d.usr.wt ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0xf0002400,"st          ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002000,"st.d        ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002100,"st.d.usr    ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002180,"st.d.usr.wt ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002080,"st.d.wt     ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002500,"st.usr      ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002580,"st.usr.wt   ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002480,"st.wt       ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002800,"st.x        ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002900,"st.x.usr    ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002980,"st.x.usr.wt ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002880,"st.x.wt     ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0xf4002f80,"st.b.usr.wt ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf4002e80,"st.b.wt     ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf4002380,"st.d.usr.wt ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf4002280,"st.d.wt     ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf4002b80,"st.h.usr.wt ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf4002a80,"st.h.wt     ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf4002780,"st.usr.wt   ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf4002680,"st.wt       ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0xf0002600,"st          ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002200,"st.d        ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002300,"st.d.usr    ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002380,"st.d.usr.wt ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002280,"st.d.wt     ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002700,"st.usr      ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002780,"st.usr.wt   ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002680,"st.wt       ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002a00,"st.x        ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002b00,"st.x.usr    ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002b80,"st.x.usr.wt ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002a80,"st.x.wt     ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x8400d880,"trnc.sd     ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400d800,"trnc.ss     ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400d900,"trnc.sx     ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-};
+extern const INSTAB  instructions[];
 
 /*
  * Local Variables:
diff --git a/include/opcode/ns32k.h b/include/opcode/ns32k.h
index 6b3fc5ea180..68a0dbaa4bd 100644
--- a/include/opcode/ns32k.h
+++ b/include/opcode/ns32k.h
@@ -1,5 +1,5 @@
 /* ns32k-opcode.h -- Opcode table for National Semi 32k processor
-   Copyright 1987, 1991, 1994 Free Software Foundation, Inc.
+   Copyright 1987, 1991, 1994, 2002 Free Software Foundation, Inc.
 
 This file is part of GAS, the GNU Assembler.
 
@@ -37,7 +37,7 @@ the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307
    the opcode or the addition of data to the opcode.
    The operands in the source instruction are checked for inconsistent
    semantics.
- 
+
 	F : 32 bit float	general form
 	L : 64 bit float	    "
 	B : byte		    "
@@ -80,13 +80,13 @@ column	1 	instructions
 	6 	size in bytes of immediate
 */
 struct ns32k_opcode {
-  char *name;
+  const char *name;
   unsigned char opcode_id_size; /* not used by the assembler */
   unsigned char opcode_size;
   unsigned long opcode_seed;
-  char *operands;
+  const char *operands;
   unsigned char im_size;	/* not used by dissassembler */
-  char *default_args;		/* default to those args when none given */
+  const char *default_args;	/* default to those args when none given */
   char default_modec;		/* default to this addr-mode when ambigous
 				   ie when the argument of a general addr-mode
 				   is a plain constant */
@@ -103,20 +103,20 @@ struct ns32k_opcode {
 struct not_wot			/* ns32k opcode table: wot to do with this */
 				/* particular opcode */
 {
-  int obits;		/* number of opcode bits */
-  int ibits;		/* number of instruction bits */
-  ns32k_opcodeT	code;	/* op-code (may be > 8 bits!) */
-  char *args;		/* how to compile said opcode */
+  int obits;			/* number of opcode bits */
+  int ibits;			/* number of instruction bits */
+  ns32k_opcodeT code;		/* op-code (may be > 8 bits!) */
+  const char *args;		/* how to compile said opcode */
 };
 
 struct not			/* ns32k opcode text */
 {
-  char *            name;	/* opcode name: lowercase string  [key]  */
-  struct not_wot    detail;	/* rest of opcode table          [datum] */
+  const char *name;		/* opcode name: lowercase string  [key]  */
+  struct not_wot detail;	/* rest of opcode table          [datum] */
 };
 
 /* Instructions look like this:
-    
+
    basic instruction--1, 2, or 3 bytes
    index byte for operand A, if operand A is indexed--1 byte
    index byte for operand B, if operand B is indexed--1 byte
@@ -130,7 +130,7 @@ struct not			/* ns32k opcode text */
    The implied operands are associated with operands other than A and B.
 
    Each operand has a digit and a letter.
-   
+
    The digit gives the position in the assembly language.  The letter,
    one of the following, tells us what kind of operand it is.  */
 
@@ -482,10 +482,6 @@ static const struct ns32k_opcode ns32k_opcodes[]=
   { "scalbl",	14,24,  0x10fe, "1L2Z",		8,	"",	DEF_MODEC,DEF_MODEL	},
 };
 
-static const int numopcodes=sizeof(ns32k_opcodes)/sizeof(ns32k_opcodes[0]);
-
-static const struct ns32k_opcode *const endop = ns32k_opcodes+sizeof(ns32k_opcodes)/sizeof(ns32k_opcodes[0]);
-
 #define MAX_ARGS 4
 #define ARG_LEN 50
 
diff --git a/include/opcode/pj.h b/include/opcode/pj.h
index b768f11bdb9..5779507be80 100644
--- a/include/opcode/pj.h
+++ b/include/opcode/pj.h
@@ -36,11 +36,14 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 #define UNS(x)    (!!((x) & (1<<3)))
 
                   
-typedef struct 
+typedef struct pj_opc_info_t
 {
   short opcode;
   short opcode_next;
   char len;
   unsigned char arg[2];
-  const char *name;
+  union {
+    const char *name;
+    void (*func) PARAMS ((struct pj_opc_info_t *, char *));
+  } u;
 } pj_opc_info_t;
diff --git a/include/opcode/tic4x.h b/include/opcode/tic4x.h
index 18df7f19c8a..214965df3dc 100644
--- a/include/opcode/tic4x.h
+++ b/include/opcode/tic4x.h
@@ -16,16 +16,10 @@
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
-   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+*/
 
-
-/* FIXME:  Only allow floating point registers for floating point
-   instructions.  Use another field in the instruction table?
-   This field could also flag which instructions are valid for
-   which architectures...
-   e.g., OP_FP | OP_C40  or OP_C40_FP  */
-
-#define IS_CPU_C3X(v) ((v) == 30 || (v) == 31 || (v) == 32)
+#define IS_CPU_C3X(v) ((v) == 30 || (v) == 31 || (v) == 32 || (v) == 33)
 #define IS_CPU_C4X(v) ((v) ==  0 || (v) == 40 || (v) == 44)
 
 /* Define some bitfield extraction/insertion macros.  */
@@ -135,1123 +129,6 @@ static const c4x_register_t c4x_registers[] =
 
 const unsigned int c4x_num_registers = (((sizeof c4x_registers) / (sizeof c4x_registers[0])) - 1);
 
-/* Instruction template.  */
-struct c4x_inst
-{
-  char *        name;
-  unsigned long opcode;
-  unsigned long opmask;
-  char *        args;
-};
-
-typedef struct c4x_inst c4x_inst_t;
-
-/* B  condition             16--20
-   C  condition             23--27
-   ,  required arg follows
-   ;  optional arg follows
-   General addressing modes
-   *  indirect               0--15 
-   #  direct (for ldp only)  0--15 
-   @  direct                 0--15 
-   F  short float immediate  0--15 
-   Q  register               0--15 
-   R  register              16--20 
-   S  short int immediate    0--15 
-   D  src and dst same reg
-   Three operand addressing modes
-   E  register               0--7 
-   G  register               8--15 
-   I  indirect(short)        0--7 
-   J  indirect(short)        8--15 
-   R  register              16--20
-   W  short int (C4x)        0--7
-   C  indirect(short) (C4x)  0--7
-   O  indirect(short) (C4x)  8--15
-   Parallel instruction addressing modes
-   E  register               0--7 
-   G  register               8--15
-   I  indirect(short)        0--7 
-   J  indirect(short)        8--15 
-   K  register              19--21
-   L  register              22--24
-   M  register (R2,R3)      22--22
-   N  register (R0,R1)      23--23
-   Misc. addressing modes
-   A  address register      22--24
-   B  unsigned integer       0--23  (absolute on C3x, relative on C4x)
-   P  displacement (PC Rel)  0--15 
-   U  unsigned integer       0--15
-   V  vector                 0--4   (C4x 0--8) 
-   T  integer (C4x stik)    16--20
-   Y  address reg (C4x)     16--20   
-   X  expansion reg (C4x)    0--4
-   Z  expansion reg (C4x)   16--20.  */
-
-#define C4X_OPERANDS_MAX 7	/* Max number of operands for an inst.  */
-#define C4X_NAME_MAX 16		/* Max number of chars in parallel name.  */
-
-/* General (two) operand group.  */
-#define G_F_r "F,R"
-#define G_I_r "S,R"
-#define G_L_r "U,R"
-#define G_Q_r "*,R"
-#define G_T_r "@,R"
-#define G_r_r "Q;R"
-
-/* Three operand group (Type 1 with missing third operand).  */
-#define T_rr_ "E,G"
-#define T_rS_ "E,J"
-#define T_Sr_ "I,G"
-#define T_SS_ "I,J"
-
-/* Three operand group (Type 2 with missing third operand).  */
-#define T_Jr_ "W,G"		/* C4x only */
-#define T_rJ_ "G,W"		/* C4x only (commutative insns only) */
-#define T_Rr_ "C,G"		/* C4x only */
-#define T_rR_ "G,C"		/* C4x only (commutative insns only) */
-#define T_JR_ "W,O"		/* C4x only */
-#define T_RJ_ "O,W"		/* C4x only (commutative insns only) */
-#define T_RR_ "C,O"		/* C4x only */
-
-/* Three operand group (Type 1).  */
-#define T_rrr "E,G;R"
-#define T_Srr "E,J,R"
-#define T_rSr "I,G;R"
-#define T_SSr "I,J,R"
-
-/* Three operand group (Type 2).  */
-#define T_Jrr "W,G;R"		/* C4x only */
-#define T_rJr "G,W,R"		/* C4x only (commutative insns only) */
-#define T_Rrr "C,G;R"		/* C4x only */
-#define T_rRr "G,C,R"		/* C4x only (commutative insns only) */
-#define T_JRr "W,O,R"		/* C4x only */
-#define T_RJr "O,W,R"		/* C4x only (commutative insns only) */
-#define T_RRr "C,O,R"		/* C4x only */
-
-/* Parallel group (store || op).  */
-#define Q_rS_rSr "H,J|K,I,L"
-#define Q_rS_Sr  "H,J|I,L"
-#define Q_rS_Srr "H,J|I,K;L"
-
-/* Parallel group (op || store).  */
-#define P_rSr_rS "K,I,L|H,J"
-#define P_Srr_rS "I,K;L|H,J"
-#define P_rS_rS  "L,I|H,J"
-
-/* Parallel group (load || load).  */
-#define P_Sr_Sr "I,L|J,K"
-#define Q_Sr_Sr "J,K|I,L"
-
-/* Parallel group (store || store).  */
-#define P_Sr_rS "I,L|H,J"
-#define Q_rS_rS "H,J|L,I"
-
-/* Parallel group (multiply || add/sub).  */
-#define P_SSr_rrr "I,J,N|H,K;M"	/* 00 (User manual transposes I,J) */
-#define P_Srr_rSr "J,K;N|H,I,M"	/* 01 */
-#define P_rSr_rSr "K,J,N|H,I,M"	/* 01 */
-#define P_rrr_SSr "H,K;N|I,J,M"	/* 10 (User manual transposes H,K) */
-#define P_Srr_Srr "J,K;N|I,H;M"	/* 11 */
-#define P_rSr_Srr "K,J,N|I,H;M"	/* 11 */
-
-#define Q_rrr_SSr "H,K;M|I,J,N"	/* 00 (User manual transposes I,J) */
-#define Q_rSr_Srr "H,I,M|J,K;N"	/* 01 */
-#define Q_rSr_rSr "H,I,M|K,J,N"	/* 01 */
-#define Q_SSr_rrr "I,J,M|H,K;N"	/* 10 (User manual transposes H,K) */
-#define Q_Srr_Srr "I,H;M|J,K;N"	/* 11 */
-#define Q_Srr_rSr "I,H;M|K,J,N"	/* 11 */
-
-/* Define c3x opcodes for assembler and disassembler.  */
-static const c4x_inst_t c3x_insts[] =
-{
-  /* Put synonyms after the desired forms in table so that they get
-     overwritten in the lookup table.  The disassembler will thus
-     print the `proper' mnemonics.  Note that the disassembler
-     only decodes the 11 MSBs, so instructions like ldp @0x500 will
-     be printed as ldiu 5, dp.  Note that with parallel instructions,
-     the second part is executed before the first part, unless
-     the sti1||sti2 form is used.  We also allow sti2||sti1
-     which is equivalent to the default sti||sti form.
-
-     Put most common forms first to speed up assembler.
-     
-     FIXME:  Add all the other parallel/load forms, like absf1_stf2
-     Perhaps I should have used a few macros...especially with
-     all the bloat after adding the C4x opcodes...too late now!  */
-
-    /* Parallel instructions.  */
-  { "absf_stf",     0xc8000000, 0xfe000000, P_Sr_rS },
-  { "absi_sti",     0xca000000, 0xfe000000, P_Sr_rS },
-  { "addf_mpyf",    0x80000000, 0xff000000, Q_rrr_SSr },
-  { "addf_mpyf",    0x81000000, 0xff000000, Q_rSr_Srr },
-  { "addf_mpyf",    0x81000000, 0xff000000, Q_rSr_rSr },
-  { "addf_mpyf",    0x82000000, 0xff000000, Q_SSr_rrr },
-  { "addf_mpyf",    0x83000000, 0xff000000, Q_Srr_Srr },
-  { "addf_mpyf",    0x83000000, 0xff000000, Q_Srr_rSr },
-  { "addf3_mpyf3",  0x80000000, 0xff000000, Q_rrr_SSr },
-  { "addf3_mpyf3",  0x81000000, 0xff000000, Q_rSr_Srr },
-  { "addf3_mpyf3",  0x81000000, 0xff000000, Q_rSr_rSr },
-  { "addf3_mpyf3",  0x82000000, 0xff000000, Q_SSr_rrr },
-  { "addf3_mpyf3",  0x83000000, 0xff000000, Q_Srr_Srr },
-  { "addf3_mpyf3",  0x83000000, 0xff000000, Q_Srr_rSr },
-  { "addf_stf",     0xcc000000, 0xfe000000, P_Srr_rS },
-  { "addf_stf",     0xcc000000, 0xfe000000, P_rSr_rS },
-  { "addf3_stf",    0xcc000000, 0xfe000000, P_Srr_rS },
-  { "addf3_stf",    0xcc000000, 0xfe000000, P_rSr_rS },
-  { "addi_mpyi",    0x88000000, 0xff000000, Q_rrr_SSr },
-  { "addi_mpyi",    0x89000000, 0xff000000, Q_rSr_Srr },
-  { "addi_mpyi",    0x89000000, 0xff000000, Q_rSr_rSr },
-  { "addi_mpyi",    0x8a000000, 0xff000000, Q_SSr_rrr },
-  { "addi_mpyi",    0x8b000000, 0xff000000, Q_Srr_Srr },
-  { "addi_mpyi",    0x8b000000, 0xff000000, Q_Srr_rSr },
-  { "addi3_mpyi3",  0x88000000, 0xff000000, Q_rrr_SSr },
-  { "addi3_mpyi3",  0x89000000, 0xff000000, Q_rSr_Srr },
-  { "addi3_mpyi3",  0x89000000, 0xff000000, Q_rSr_rSr },
-  { "addi3_mpyi3",  0x8a000000, 0xff000000, Q_SSr_rrr },
-  { "addi3_mpyi3",  0x8b000000, 0xff000000, Q_Srr_Srr },
-  { "addi3_mpyi3",  0x8b000000, 0xff000000, Q_Srr_rSr },
-  { "addi_sti",     0xce000000, 0xfe000000, P_Srr_rS },
-  { "addi_sti",     0xce000000, 0xfe000000, P_rSr_rS },
-  { "addi3_sti",    0xce000000, 0xfe000000, P_Srr_rS },
-  { "addi3_sti",    0xce000000, 0xfe000000, P_rSr_rS },
-  { "and_sti",      0xd0000000, 0xfe000000, P_Srr_rS },
-  { "and_sti",      0xd0000000, 0xfe000000, P_rSr_rS },
-  { "and3_sti",     0xd0000000, 0xfe000000, P_Srr_rS },
-  { "and3_sti",     0xd0000000, 0xfe000000, P_rSr_rS },
-  { "ash_sti",      0xd2000000, 0xfe000000, P_rSr_rS },
-  { "ash3_sti",     0xd2000000, 0xfe000000, P_rSr_rS },
-  { "fix_sti",      0xd4000000, 0xfe000000, P_Sr_rS },
-  { "float_stf",    0xd6000000, 0xfe000000, P_Sr_rS },
-  { "ldf_ldf",      0xc4000000, 0xfe000000, P_Sr_Sr },
-  { "ldf1_ldf2",    0xc4000000, 0xfe000000, Q_Sr_Sr }, /* synonym */
-  { "ldf2_ldf1",    0xc4000000, 0xfe000000, P_Sr_Sr }, /* synonym */
-  { "ldf_stf",      0xd8000000, 0xfe000000, P_Sr_rS },
-  { "ldi_ldi",      0xc6000000, 0xfe000000, P_Sr_Sr },
-  { "ldi1_ldi2",    0xc6000000, 0xfe000000, Q_Sr_Sr }, /* synonym  */
-  { "ldi2_ldi1",    0xc6000000, 0xfe000000, P_Sr_Sr }, /* synonym  */
-  { "ldi_sti",      0xda000000, 0xfe000000, P_Sr_rS },
-  { "lsh_sti",      0xdc000000, 0xfe000000, P_rSr_rS },
-  { "lsh3_sti",     0xdc000000, 0xfe000000, P_rSr_rS },
-  { "mpyf_addf",    0x80000000, 0xff000000, P_SSr_rrr },
-  { "mpyf_addf",    0x81000000, 0xff000000, P_Srr_rSr },
-  { "mpyf_addf",    0x81000000, 0xff000000, P_rSr_rSr },
-  { "mpyf_addf",    0x82000000, 0xff000000, P_rrr_SSr },
-  { "mpyf_addf",    0x83000000, 0xff000000, P_Srr_Srr },
-  { "mpyf_addf",    0x83000000, 0xff000000, P_rSr_Srr },
-  { "mpyf3_addf3",  0x80000000, 0xff000000, P_SSr_rrr },
-  { "mpyf3_addf3",  0x81000000, 0xff000000, P_Srr_rSr },
-  { "mpyf3_addf3",  0x81000000, 0xff000000, P_rSr_rSr },
-  { "mpyf3_addf3",  0x82000000, 0xff000000, P_rrr_SSr },
-  { "mpyf3_addf3",  0x83000000, 0xff000000, P_Srr_Srr },
-  { "mpyf3_addf3",  0x83000000, 0xff000000, P_rSr_Srr },
-  { "mpyf_stf",     0xde000000, 0xfe000000, P_Srr_rS },
-  { "mpyf_stf",     0xde000000, 0xfe000000, P_rSr_rS },
-  { "mpyf3_stf",    0xde000000, 0xfe000000, P_Srr_rS },
-  { "mpyf3_stf",    0xde000000, 0xfe000000, P_rSr_rS },
-  { "mpyf_subf",    0x84000000, 0xff000000, P_SSr_rrr },
-  { "mpyf_subf",    0x85000000, 0xff000000, P_Srr_rSr },
-  { "mpyf_subf",    0x85000000, 0xff000000, P_rSr_rSr },
-  { "mpyf_subf",    0x86000000, 0xff000000, P_rrr_SSr },
-  { "mpyf_subf",    0x87000000, 0xff000000, P_Srr_Srr },
-  { "mpyf_subf",    0x87000000, 0xff000000, P_rSr_Srr },
-  { "mpyf3_subf3",  0x84000000, 0xff000000, P_SSr_rrr },
-  { "mpyf3_subf3",  0x85000000, 0xff000000, P_Srr_rSr },
-  { "mpyf3_subf3",  0x85000000, 0xff000000, P_rSr_rSr },
-  { "mpyf3_subf3",  0x86000000, 0xff000000, P_rrr_SSr },
-  { "mpyf3_subf3",  0x87000000, 0xff000000, P_Srr_Srr },
-  { "mpyf3_subf3",  0x87000000, 0xff000000, P_rSr_Srr },
-  { "mpyi_addi",    0x88000000, 0xff000000, P_SSr_rrr },
-  { "mpyi_addi",    0x89000000, 0xff000000, P_Srr_rSr },
-  { "mpyi_addi",    0x89000000, 0xff000000, P_rSr_rSr },
-  { "mpyi_addi",    0x8a000000, 0xff000000, P_rrr_SSr },
-  { "mpyi_addi",    0x8b000000, 0xff000000, P_Srr_Srr },
-  { "mpyi_addi",    0x8b000000, 0xff000000, P_rSr_Srr },
-  { "mpyi3_addi3",  0x88000000, 0xff000000, P_SSr_rrr },
-  { "mpyi3_addi3",  0x89000000, 0xff000000, P_Srr_rSr },
-  { "mpyi3_addi3",  0x89000000, 0xff000000, P_rSr_rSr },
-  { "mpyi3_addi3",  0x8a000000, 0xff000000, P_rrr_SSr },
-  { "mpyi3_addi3",  0x8b000000, 0xff000000, P_Srr_Srr },
-  { "mpyi3_addi3",  0x8b000000, 0xff000000, P_rSr_Srr },
-  { "mpyi_sti",     0xe0000000, 0xfe000000, P_Srr_rS },
-  { "mpyi_sti",     0xe0000000, 0xfe000000, P_rSr_rS },
-  { "mpyi3_sti",    0xe0000000, 0xfe000000, P_Srr_rS },
-  { "mpyi3_sti",    0xe0000000, 0xfe000000, P_rSr_rS },
-  { "mpyi_subi",    0x8c000000, 0xff000000, P_SSr_rrr },
-  { "mpyi_subi",    0x8d000000, 0xff000000, P_Srr_rSr },
-  { "mpyi_subi",    0x8d000000, 0xff000000, P_rSr_rSr },
-  { "mpyi_subi",    0x8e000000, 0xff000000, P_rrr_SSr },
-  { "mpyi_subi",    0x8f000000, 0xff000000, P_Srr_Srr },
-  { "mpyi_subi",    0x8f000000, 0xff000000, P_rSr_Srr },
-  { "mpyi3_subi3",  0x8c000000, 0xff000000, P_SSr_rrr },
-  { "mpyi3_subi3",  0x8d000000, 0xff000000, P_Srr_rSr },
-  { "mpyi3_subi3",  0x8d000000, 0xff000000, P_rSr_rSr },
-  { "mpyi3_subi3",  0x8e000000, 0xff000000, P_rrr_SSr },
-  { "mpyi3_subi3",  0x8f000000, 0xff000000, P_Srr_Srr },
-  { "mpyi3_subi3",  0x8f000000, 0xff000000, P_rSr_Srr },
-  { "negf_stf",     0xe2000000, 0xfe000000, P_Sr_rS },
-  { "negi_sti",     0xe4000000, 0xfe000000, P_Sr_rS },
-  { "not_sti",      0xe6000000, 0xfe000000, P_Sr_rS },
-  { "or_sti",       0xe8000000, 0xfe000000, P_Srr_rS },
-  { "or_sti",       0xe8000000, 0xfe000000, P_rSr_rS },
-  { "or3_sti",      0xe8000000, 0xfe000000, P_Srr_rS },
-  { "or3_sti",      0xe8000000, 0xfe000000, P_rSr_rS },
-  { "stf_absf",     0xc8000000, 0xfe000000, Q_rS_Sr },
-  { "stf_addf",     0xcc000000, 0xfe000000, Q_rS_Srr },
-  { "stf_addf",     0xcc000000, 0xfe000000, Q_rS_rSr },
-  { "stf_addf3",    0xcc000000, 0xfe000000, Q_rS_Srr },
-  { "stf_addf3",    0xcc000000, 0xfe000000, Q_rS_rSr },
-  { "stf_float",    0xd6000000, 0xfe000000, Q_rS_Sr },
-  { "stf_mpyf",     0xde000000, 0xfe000000, Q_rS_Srr },
-  { "stf_mpyf",     0xde000000, 0xfe000000, Q_rS_rSr },
-  { "stf_mpyf3",    0xde000000, 0xfe000000, Q_rS_Srr },
-  { "stf_mpyf3",    0xde000000, 0xfe000000, Q_rS_rSr },
-  { "stf_ldf",      0xd8000000, 0xfe000000, Q_rS_Sr  },
-  { "stf_negf",     0xe2000000, 0xfe000000, Q_rS_Sr },
-  { "stf_stf",      0xc0000000, 0xfe000000, P_rS_rS },
-  { "stf1_stf2",    0xc0000000, 0xfe000000, Q_rS_rS }, /* synonym */
-  { "stf2_stf1",    0xc0000000, 0xfe000000, P_rS_rS }, /* synonym */
-  { "stf_subf",     0xea000000, 0xfe000000, Q_rS_rSr },
-  { "stf_subf3",    0xea000000, 0xfe000000, Q_rS_rSr },
-  { "sti_absi",     0xca000000, 0xfe000000, Q_rS_Sr },
-  { "sti_addi",     0xce000000, 0xfe000000, Q_rS_Srr },
-  { "sti_addi",     0xce000000, 0xfe000000, Q_rS_rSr },
-  { "sti_addi3",    0xce000000, 0xfe000000, Q_rS_Srr },
-  { "sti_addi3",    0xce000000, 0xfe000000, Q_rS_rSr },
-  { "sti_and",      0xd0000000, 0xfe000000, Q_rS_Srr },
-  { "sti_and",      0xd0000000, 0xfe000000, Q_rS_rSr },
-  { "sti_and3",     0xd0000000, 0xfe000000, Q_rS_Srr },
-  { "sti_and3",     0xd0000000, 0xfe000000, Q_rS_rSr },
-  { "sti_ash",      0xd2000000, 0xfe000000, Q_rS_rSr },
-  { "sti_ash3",     0xd2000000, 0xfe000000, Q_rS_rSr },
-  { "sti_fix",      0xd4000000, 0xfe000000, Q_rS_Sr },
-  { "sti_ldi",      0xda000000, 0xfe000000, Q_rS_Sr },
-  { "sti_lsh",      0xdc000000, 0xfe000000, Q_rS_rSr },
-  { "sti_lsh3",     0xdc000000, 0xfe000000, Q_rS_rSr },
-  { "sti_mpyi",     0xe0000000, 0xfe000000, Q_rS_Srr },
-  { "sti_mpyi",     0xe0000000, 0xfe000000, Q_rS_rSr },
-  { "sti_mpyi3",    0xe0000000, 0xfe000000, Q_rS_Srr },
-  { "sti_mpyi3",    0xe0000000, 0xfe000000, Q_rS_rSr },
-  { "sti_negi",     0xe4000000, 0xfe000000, Q_rS_Sr },
-  { "sti_not",      0xe6000000, 0xfe000000, Q_rS_Sr },
-  { "sti_or",       0xe8000000, 0xfe000000, Q_rS_Srr },
-  { "sti_or",       0xe8000000, 0xfe000000, Q_rS_rSr },
-  { "sti_or3",      0xe8000000, 0xfe000000, Q_rS_Srr },
-  { "sti_or3",      0xe8000000, 0xfe000000, Q_rS_rSr },
-  { "sti_sti",      0xc2000000, 0xfe000000, P_rS_rS },
-  { "sti1_sti2",    0xc2000000, 0xfe000000, Q_rS_rS }, /* synonym */
-  { "sti2_sti1",    0xc2000000, 0xfe000000, P_rS_rS }, /* synonym */
-  { "sti_subi",     0xec000000, 0xfe000000, Q_rS_rSr },    
-  { "sti_subi3",    0xec000000, 0xfe000000, Q_rS_rSr },
-  { "sti_xor",      0xee000000, 0xfe000000, Q_rS_Srr },
-  { "sti_xor",      0xee000000, 0xfe000000, Q_rS_rSr },
-  { "sti_xor3",     0xee000000, 0xfe000000, Q_rS_Srr },
-  { "sti_xor3",     0xee000000, 0xfe000000, Q_rS_rSr },
-  { "subf_mpyf",    0x84000000, 0xff000000, Q_rrr_SSr },
-  { "subf_mpyf",    0x85000000, 0xff000000, Q_rSr_Srr },
-  { "subf_mpyf",    0x85000000, 0xff000000, Q_rSr_rSr },
-  { "subf_mpyf",    0x86000000, 0xff000000, Q_SSr_rrr },
-  { "subf_mpyf",    0x87000000, 0xff000000, Q_Srr_Srr },
-  { "subf_mpyf",    0x87000000, 0xff000000, Q_Srr_rSr },
-  { "subf3_mpyf3",  0x84000000, 0xff000000, Q_rrr_SSr },
-  { "subf3_mpyf3",  0x85000000, 0xff000000, Q_rSr_Srr },
-  { "subf3_mpyf3",  0x85000000, 0xff000000, Q_rSr_rSr },
-  { "subf3_mpyf3",  0x86000000, 0xff000000, Q_SSr_rrr },
-  { "subf3_mpyf3",  0x87000000, 0xff000000, Q_Srr_Srr },
-  { "subf3_mpyf3",  0x87000000, 0xff000000, Q_Srr_rSr },
-  { "subf_stf",     0xea000000, 0xfe000000, P_rSr_rS },
-  { "subf3_stf",    0xea000000, 0xfe000000, P_rSr_rS },
-  { "subi_mpyi",    0x8c000000, 0xff000000, Q_rrr_SSr },
-  { "subi_mpyi",    0x8d000000, 0xff000000, Q_rSr_Srr },
-  { "subi_mpyi",    0x8d000000, 0xff000000, Q_rSr_rSr },
-  { "subi_mpyi",    0x8e000000, 0xff000000, Q_SSr_rrr },
-  { "subi_mpyi",    0x8f000000, 0xff000000, Q_Srr_Srr },
-  { "subi_mpyi",    0x8f000000, 0xff000000, Q_Srr_rSr },
-  { "subi3_mpyi3",  0x8c000000, 0xff000000, Q_rrr_SSr },
-  { "subi3_mpyi3",  0x8d000000, 0xff000000, Q_rSr_Srr },
-  { "subi3_mpyi3",  0x8d000000, 0xff000000, Q_rSr_rSr },
-  { "subi3_mpyi3",  0x8e000000, 0xff000000, Q_SSr_rrr },
-  { "subi3_mpyi3",  0x8f000000, 0xff000000, Q_Srr_Srr },
-  { "subi3_mpyi3",  0x8f000000, 0xff000000, Q_Srr_rSr },
-  { "subi_sti",     0xec000000, 0xfe000000, P_rSr_rS },    
-  { "subi3_sti",    0xec000000, 0xfe000000, P_rSr_rS },
-  { "xor_sti",      0xee000000, 0xfe000000, P_Srr_rS },
-  { "xor_sti",      0xee000000, 0xfe000000, P_rSr_rS },
-  { "xor3_sti",     0xee000000, 0xfe000000, P_Srr_rS },
-  { "xor3_sti",     0xee000000, 0xfe000000, P_rSr_rS },
-
-  { "absf",   0x00000000, 0xffe00000, G_r_r },
-  { "absf",   0x00200000, 0xffe00000, G_T_r },
-  { "absf",   0x00400000, 0xffe00000, G_Q_r },
-  { "absf",   0x00600000, 0xffe00000, G_F_r },
-  { "absi",   0x00800000, 0xffe00000, G_r_r },
-  { "absi",   0x00a00000, 0xffe00000, G_T_r },
-  { "absi",   0x00c00000, 0xffe00000, G_Q_r },
-  { "absi",   0x00e00000, 0xffe00000, G_I_r },
-  { "addc",   0x01000000, 0xffe00000, G_r_r },
-  { "addc",   0x01200000, 0xffe00000, G_T_r },
-  { "addc",   0x01400000, 0xffe00000, G_Q_r },
-  { "addc",   0x01600000, 0xffe00000, G_I_r },
-  { "addc",   0x20000000, 0xffe00000, T_rrr },
-  { "addc",   0x20200000, 0xffe00000, T_Srr },
-  { "addc",   0x20400000, 0xffe00000, T_rSr },
-  { "addc",   0x20600000, 0xffe00000, T_SSr },
-  { "addc",   0x30000000, 0xffe00000, T_Jrr }, /* C4x */
-  { "addc",   0x30000000, 0xffe00000, T_rJr }, /* C4x */
-  { "addc",   0x30200000, 0xffe00000, T_rRr }, /* C4x */
-  { "addc",   0x30200000, 0xffe00000, T_Rrr }, /* C4x */
-  { "addc",   0x30400000, 0xffe00000, T_JRr }, /* C4x */
-  { "addc",   0x30400000, 0xffe00000, T_RJr }, /* C4x */
-  { "addc",   0x30600000, 0xffe00000, T_RRr }, /* C4x */
-  { "addc3",  0x20000000, 0xffe00000, T_rrr },
-  { "addc3",  0x20200000, 0xffe00000, T_Srr },
-  { "addc3",  0x20400000, 0xffe00000, T_rSr },
-  { "addc3",  0x20600000, 0xffe00000, T_SSr },
-  { "addc3",  0x30000000, 0xffe00000, T_Jrr }, /* C4x */
-  { "addc3",  0x30000000, 0xffe00000, T_rJr }, /* C4x */
-  { "addc3",  0x30200000, 0xffe00000, T_rRr }, /* C4x */
-  { "addc3",  0x30200000, 0xffe00000, T_Rrr }, /* C4x */
-  { "addc3",  0x30400000, 0xffe00000, T_JRr }, /* C4x */
-  { "addc3",  0x30400000, 0xffe00000, T_RJr }, /* C4x */
-  { "addc3",  0x30600000, 0xffe00000, T_RRr }, /* C4x */
-  { "addf",   0x01800000, 0xffe00000, G_r_r },
-  { "addf",   0x01a00000, 0xffe00000, G_T_r },
-  { "addf",   0x01c00000, 0xffe00000, G_Q_r },
-  { "addf",   0x01e00000, 0xffe00000, G_F_r },
-  { "addf",   0x20800000, 0xffe00000, T_rrr },
-  { "addf",   0x20a00000, 0xffe00000, T_Srr },
-  { "addf",   0x20c00000, 0xffe00000, T_rSr },
-  { "addf",   0x20e00000, 0xffe00000, T_SSr },
-  { "addf",   0x30800000, 0xffe00000, T_Jrr }, /* C4x */
-  { "addf",   0x30800000, 0xffe00000, T_rJr }, /* C4x */
-  { "addf",   0x30a00000, 0xffe00000, T_rRr }, /* C4x */
-  { "addf",   0x30a00000, 0xffe00000, T_Rrr }, /* C4x */
-  { "addf",   0x30c00000, 0xffe00000, T_JRr }, /* C4x */
-  { "addf",   0x30c00000, 0xffe00000, T_RJr }, /* C4x */
-  { "addf",   0x30e00000, 0xffe00000, T_RRr }, /* C4x */
-  { "addf3",  0x20800000, 0xffe00000, T_rrr },
-  { "addf3",  0x20a00000, 0xffe00000, T_Srr },
-  { "addf3",  0x20c00000, 0xffe00000, T_rSr },
-  { "addf3",  0x20e00000, 0xffe00000, T_SSr },
-  { "addf3",  0x30800000, 0xffe00000, T_Jrr }, /* C4x */
-  { "addf3",  0x30800000, 0xffe00000, T_rJr }, /* C4x */
-  { "addf3",  0x30a00000, 0xffe00000, T_rRr }, /* C4x */
-  { "addf3",  0x30a00000, 0xffe00000, T_Rrr }, /* C4x */
-  { "addf3",  0x30c00000, 0xffe00000, T_JRr }, /* C4x */
-  { "addf3",  0x30c00000, 0xffe00000, T_RJr }, /* C4x */
-  { "addf3",  0x30e00000, 0xffe00000, T_RRr }, /* C4x */
-  { "addi",   0x02000000, 0xffe00000, G_r_r },
-  { "addi",   0x02200000, 0xffe00000, G_T_r },
-  { "addi",   0x02400000, 0xffe00000, G_Q_r },
-  { "addi",   0x02600000, 0xffe00000, G_I_r },
-  { "addi",   0x21000000, 0xffe00000, T_rrr },
-  { "addi",   0x21200000, 0xffe00000, T_Srr },
-  { "addi",   0x21400000, 0xffe00000, T_rSr },
-  { "addi",   0x21600000, 0xffe00000, T_SSr },
-  { "addi",   0x31000000, 0xffe00000, T_Jrr }, /* C4x */
-  { "addi",   0x31000000, 0xffe00000, T_rJr }, /* C4x */
-  { "addi",   0x31200000, 0xffe00000, T_rRr }, /* C4x */
-  { "addi",   0x31200000, 0xffe00000, T_Rrr }, /* C4x */
-  { "addi",   0x31400000, 0xffe00000, T_JRr }, /* C4x */
-  { "addi",   0x31400000, 0xffe00000, T_RJr }, /* C4x */
-  { "addi",   0x31600000, 0xffe00000, T_RRr }, /* C4x */
-  { "addi3",  0x21000000, 0xffe00000, T_rrr },
-  { "addi3",  0x21200000, 0xffe00000, T_Srr },
-  { "addi3",  0x21400000, 0xffe00000, T_rSr },
-  { "addi3",  0x21600000, 0xffe00000, T_SSr },
-  { "addi3",  0x31000000, 0xffe00000, T_Jrr }, /* C4x */
-  { "addi3",  0x31000000, 0xffe00000, T_rJr }, /* C4x */
-  { "addi3",  0x31200000, 0xffe00000, T_rRr }, /* C4x */
-  { "addi3",  0x31200000, 0xffe00000, T_Rrr }, /* C4x */
-  { "addi3",  0x31400000, 0xffe00000, T_JRr }, /* C4x */
-  { "addi3",  0x31400000, 0xffe00000, T_RJr }, /* C4x */
-  { "addi3",  0x31600000, 0xffe00000, T_RRr }, /* C4x */
-  { "and",    0x02800000, 0xffe00000, G_r_r },
-  { "and",    0x02a00000, 0xffe00000, G_T_r },
-  { "and",    0x02c00000, 0xffe00000, G_Q_r },
-  { "and",    0x02e00000, 0xffe00000, G_L_r },
-  { "and",    0x21800000, 0xffe00000, T_rrr },
-  { "and",    0x21a00000, 0xffe00000, T_Srr },
-  { "and",    0x21c00000, 0xffe00000, T_rSr },
-  { "and",    0x21e00000, 0xffe00000, T_SSr },
-  { "and",    0x31800000, 0xffe00000, T_Jrr }, /* C4x */
-  { "and",    0x31800000, 0xffe00000, T_rJr }, /* C4x */
-  { "and",    0x31a00000, 0xffe00000, T_rRr }, /* C4x */
-  { "and",    0x31a00000, 0xffe00000, T_Rrr }, /* C4x */
-  { "and",    0x31c00000, 0xffe00000, T_JRr }, /* C4x */
-  { "and",    0x31c00000, 0xffe00000, T_RJr }, /* C4x */
-  { "and",    0x31e00000, 0xffe00000, T_RRr }, /* C4x */
-  { "and3",   0x21800000, 0xffe00000, T_rrr },
-  { "and3",   0x21a00000, 0xffe00000, T_Srr },
-  { "and3",   0x21c00000, 0xffe00000, T_rSr },
-  { "and3",   0x21e00000, 0xffe00000, T_SSr },
-  { "and3",   0x31800000, 0xffe00000, T_Jrr }, /* C4x */
-  { "and3",   0x31800000, 0xffe00000, T_rJr }, /* C4x */
-  { "and3",   0x31a00000, 0xffe00000, T_rRr }, /* C4x */
-  { "and3",   0x31a00000, 0xffe00000, T_Rrr }, /* C4x */
-  { "and3",   0x31c00000, 0xffe00000, T_JRr }, /* C4x */
-  { "and3",   0x31c00000, 0xffe00000, T_RJr }, /* C4x */
-  { "and3",   0x31e00000, 0xffe00000, T_RRr }, /* C4x */
-  { "andn",   0x03000000, 0xffe00000, G_r_r },
-  { "andn",   0x03200000, 0xffe00000, G_T_r },
-  { "andn",   0x03400000, 0xffe00000, G_Q_r },
-  { "andn",   0x03600000, 0xffe00000, G_L_r },
-  { "andn",   0x22000000, 0xffe00000, T_rrr },
-  { "andn",   0x22200000, 0xffe00000, T_Srr },
-  { "andn",   0x22400000, 0xffe00000, T_rSr },
-  { "andn",   0x22600000, 0xffe00000, T_SSr },
-  { "andn",   0x32000000, 0xffe00000, T_Jrr }, /* C4x */
-  { "andn",   0x32200000, 0xffe00000, T_Rrr }, /* C4x */
-  { "andn",   0x32400000, 0xffe00000, T_JRr }, /* C4x */
-  { "andn",   0x32600000, 0xffe00000, T_RRr }, /* C4x */
-  { "andn3",  0x22000000, 0xffe00000, T_rrr },
-  { "andn3",  0x22200000, 0xffe00000, T_Srr },
-  { "andn3",  0x22400000, 0xffe00000, T_rSr },
-  { "andn3",  0x22600000, 0xffe00000, T_SSr },
-  { "andn3",  0x32000000, 0xffe00000, T_Jrr }, /* C4x */
-  { "andn3",  0x32200000, 0xffe00000, T_Rrr }, /* C4x */
-  { "andn3",  0x32400000, 0xffe00000, T_JRr }, /* C4x */
-  { "andn3",  0x32600000, 0xffe00000, T_RRr }, /* C4x */
-  { "ash",    0x03800000, 0xffe00000, G_r_r },
-  { "ash",    0x03a00000, 0xffe00000, G_T_r },
-  { "ash",    0x03c00000, 0xffe00000, G_Q_r },
-  { "ash",    0x03e00000, 0xffe00000, G_I_r },
-  { "ash",    0x22800000, 0xffe00000, T_rrr },
-  { "ash",    0x22a00000, 0xffe00000, T_Srr },
-  { "ash",    0x22c00000, 0xffe00000, T_rSr },
-  { "ash",    0x22e00000, 0xffe00000, T_SSr },
-  { "ash",    0x32800000, 0xffe00000, T_Jrr }, /* C4x */
-  { "ash",    0x32a00000, 0xffe00000, T_Rrr }, /* C4x */
-  { "ash",    0x32c00000, 0xffe00000, T_JRr }, /* C4x */
-  { "ash",    0x32e00000, 0xffe00000, T_RRr }, /* C4x */
-  { "ash3",   0x22800000, 0xffe00000, T_rrr },
-  { "ash3",   0x22a00000, 0xffe00000, T_Srr },
-  { "ash3",   0x22c00000, 0xffe00000, T_rSr },
-  { "ash3",   0x22e00000, 0xffe00000, T_SSr },
-  { "ash3",   0x32800000, 0xffe00000, T_Jrr }, /* C4x */
-  { "ash3",   0x32a00000, 0xffe00000, T_Rrr }, /* C4x */
-  { "ash3",   0x32c00000, 0xffe00000, T_JRr }, /* C4x */
-  { "ash3",   0x32e00000, 0xffe00000, T_RRr }, /* C4x */
-  { "bB",     0x68000000, 0xffe00000, "Q" },
-  { "bB",     0x6a000000, 0xffe00000, "P" }, 
-  { "b",      0x68000000, 0xffe00000, "Q" }, /* synonym for bu */
-  { "b",      0x6a000000, 0xffe00000, "P" }, /* synonym for bu */
-  { "bBd",    0x68200000, 0xffe00000, "Q" },
-  { "bBd",    0x6a200000, 0xffe00000, "P" },
-  { "bd",     0x68200000, 0xffe00000, "Q" }, /* synonym for bud */
-  { "bd",     0x6a200000, 0xffe00000, "P" }, /* synonym for bud */
-  { "br",     0x60000000, 0xff000000, "B" },
-  { "brd",    0x61000000, 0xff000000, "B" },
-  { "call",   0x62000000, 0xff000000, "B" },
-  { "callB",  0x70000000, 0xffe00000, "Q" },
-  { "callB",  0x72000000, 0xffe00000, "P" },
-  { "cmpf",   0x04000000, 0xffe00000, G_r_r },
-  { "cmpf",   0x04200000, 0xffe00000, G_T_r },
-  { "cmpf",   0x04400000, 0xffe00000, G_Q_r },
-  { "cmpf",   0x04600000, 0xffe00000, G_F_r },
-  { "cmpf",   0x23000000, 0xffe00000, T_rr_ },
-  { "cmpf",   0x23200000, 0xffe00000, T_rS_ },
-  { "cmpf",   0x23400000, 0xffe00000, T_Sr_ },
-  { "cmpf",   0x23600000, 0xffe00000, T_SS_ },
-  { "cmpf",   0x33200000, 0xffe00000, T_Rr_ }, /* C4x */
-  { "cmpf",   0x33600000, 0xffe00000, T_RR_ }, /* C4x */
-  { "cmpf3",  0x23000000, 0xffe00000, T_rr_ },
-  { "cmpf3",  0x23200000, 0xffe00000, T_rS_ },
-  { "cmpf3",  0x23400000, 0xffe00000, T_Sr_ },
-  { "cmpf3",  0x23600000, 0xffe00000, T_SS_ },
-  { "cmpf3",  0x33200000, 0xffe00000, T_Rr_ }, /* C4x */
-  { "cmpf3",  0x33600000, 0xffe00000, T_RR_ }, /* C4x */
-  { "cmpi",   0x04800000, 0xffe00000, G_r_r },
-  { "cmpi",   0x04a00000, 0xffe00000, G_T_r },
-  { "cmpi",   0x04c00000, 0xffe00000, G_Q_r },
-  { "cmpi",   0x04e00000, 0xffe00000, G_I_r },
-  { "cmpi",   0x23800000, 0xffe00000, T_rr_ },
-  { "cmpi",   0x23a00000, 0xffe00000, T_rS_ },
-  { "cmpi",   0x23c00000, 0xffe00000, T_Sr_ },
-  { "cmpi",   0x23e00000, 0xffe00000, T_SS_ },
-  { "cmpi",   0x33800000, 0xffe00000, T_Jr_ }, /* C4x */
-  { "cmpi",   0x33a00000, 0xffe00000, T_Rr_ }, /* C4x */
-  { "cmpi",   0x33c00000, 0xffe00000, T_JR_ }, /* C4x */
-  { "cmpi",   0x33e00000, 0xffe00000, T_RR_ }, /* C4x */
-  { "cmpi3",  0x23800000, 0xffe00000, T_rr_ },
-  { "cmpi3",  0x23a00000, 0xffe00000, T_rS_ },
-  { "cmpi3",  0x23c00000, 0xffe00000, T_Sr_ },
-  { "cmpi3",  0x23e00000, 0xffe00000, T_SS_ },
-  { "cmpi3",  0x33800000, 0xffe00000, T_Jr_ }, /* C4x */
-  { "cmpi3",  0x33a00000, 0xffe00000, T_Rr_ }, /* C4x */
-  { "cmpi3",  0x33c00000, 0xffe00000, T_JR_ }, /* C4x */
-  { "cmpi3",  0x33e00000, 0xffe00000, T_RR_ }, /* C4x */
-  { "dbB",    0x6c000000, 0xfe200000, "A,Q" },
-  { "dbB",    0x6e000000, 0xfe200000, "A,P" },
-  { "db",     0x6c000000, 0xfe200000, "A,Q" }, /* synonym for dbu */
-  { "db",     0x6e000000, 0xfe200000, "A,P" }, /* synonym for dbu */
-  { "dbBd",   0x6c200000, 0xfe200000, "A,Q" },
-  { "dbBd",   0x6e200000, 0xfe200000, "A,P" },
-  { "dbd",    0x6c200000, 0xfe200000, "A,Q" }, /* synonym for dbud */
-  { "dbd",    0x6e200000, 0xfe200000, "A,P" }, /* synonym for dbud */
-  { "fix",    0x05000000, 0xffe00000, G_r_r },
-  { "fix",    0x05200000, 0xffe00000, G_T_r },
-  { "fix",    0x05400000, 0xffe00000, G_Q_r },
-  { "fix",    0x05600000, 0xffe00000, G_F_r },
-  { "float",  0x05800000, 0xffe00000, G_r_r },
-  { "float",  0x05a00000, 0xffe00000, G_T_r },
-  { "float",  0x05c00000, 0xffe00000, G_Q_r },
-  { "float",  0x05e00000, 0xffe00000, G_I_r },
-  { "iack",   0x1b200000, 0xffe00000, "@" },
-  { "iack",   0x1b400000, 0xffe00000, "*" },
-  { "idle",   0x06000000, 0xffffffff, "" },
-  { "lde",    0x06800000, 0xffe00000, G_r_r },
-  { "lde",    0x06a00000, 0xffe00000, G_T_r },
-  { "lde",    0x06c00000, 0xffe00000, G_Q_r },
-  { "lde",    0x06e00000, 0xffe00000, G_F_r },
-  { "ldf",    0x07000000, 0xffe00000, G_r_r },
-  { "ldf",    0x07200000, 0xffe00000, G_T_r },
-  { "ldf",    0x07400000, 0xffe00000, G_Q_r },
-  { "ldf",    0x07600000, 0xffe00000, G_F_r },
-  { "ldfC",   0x40000000, 0xf0600000, G_r_r },
-  { "ldfC",   0x40200000, 0xf0600000, G_T_r },
-  { "ldfC",   0x40400000, 0xf0600000, G_Q_r },
-  { "ldfC",   0x40600000, 0xf0600000, G_F_r },
-  { "ldfi",   0x07a00000, 0xffe00000, G_T_r },
-  { "ldfi",   0x07c00000, 0xffe00000, G_Q_r },
-  { "ldi",    0x08000000, 0xffe00000, G_r_r },
-  { "ldi",    0x08200000, 0xffe00000, G_T_r },
-  { "ldi",    0x08400000, 0xffe00000, G_Q_r },
-  { "ldi",    0x08600000, 0xffe00000, G_I_r },
-  { "ldiC",   0x50000000, 0xf0600000, G_r_r },
-  { "ldiC",   0x50200000, 0xf0600000, G_T_r },
-  { "ldiC",   0x50400000, 0xf0600000, G_Q_r },
-  { "ldiC",   0x50600000, 0xf0600000, G_I_r },
-  { "ldii",   0x08a00000, 0xffe00000, G_T_r },
-  { "ldii",   0x08c00000, 0xffe00000, G_Q_r },
-  { "ldp",    0x50700000, 0xffff0000, "#" }, /* synonym for ldiu #,dp */
-  { "ldm",    0x09000000, 0xffe00000, G_r_r },
-  { "ldm",    0x09200000, 0xffe00000, G_T_r },
-  { "ldm",    0x09400000, 0xffe00000, G_Q_r },
-  { "ldm",    0x09600000, 0xffe00000, G_F_r },
-  { "lsh",    0x09800000, 0xffe00000, G_r_r },
-  { "lsh",    0x09a00000, 0xffe00000, G_T_r },
-  { "lsh",    0x09c00000, 0xffe00000, G_Q_r },
-  { "lsh",    0x09e00000, 0xffe00000, G_I_r },
-  { "lsh",    0x24000000, 0xffe00000, T_rrr },
-  { "lsh",    0x24200000, 0xffe00000, T_Srr },
-  { "lsh",    0x24400000, 0xffe00000, T_rSr },
-  { "lsh",    0x24600000, 0xffe00000, T_SSr },
-  { "lsh",    0x34000000, 0xffe00000, T_Jrr }, /* C4x */
-  { "lsh",    0x34200000, 0xffe00000, T_Rrr }, /* C4x */
-  { "lsh",    0x34400000, 0xffe00000, T_JRr }, /* C4x */
-  { "lsh",    0x34600000, 0xffe00000, T_RRr }, /* C4x */
-  { "lsh3",   0x24000000, 0xffe00000, T_rrr },
-  { "lsh3",   0x24200000, 0xffe00000, T_Srr },
-  { "lsh3",   0x24400000, 0xffe00000, T_rSr },
-  { "lsh3",   0x24600000, 0xffe00000, T_SSr },
-  { "lsh3",   0x34000000, 0xffe00000, T_Jrr }, /* C4x */
-  { "lsh3",   0x34200000, 0xffe00000, T_Rrr }, /* C4x */
-  { "lsh3",   0x34400000, 0xffe00000, T_JRr }, /* C4x */
-  { "lsh3",   0x34600000, 0xffe00000, T_RRr }, /* C4x */
-  { "mpyf",   0x0a000000, 0xffe00000, G_r_r },
-  { "mpyf",   0x0a200000, 0xffe00000, G_T_r },
-  { "mpyf",   0x0a400000, 0xffe00000, G_Q_r },
-  { "mpyf",   0x0a600000, 0xffe00000, G_F_r },
-  { "mpyf",   0x24800000, 0xffe00000, T_rrr },
-  { "mpyf",   0x24a00000, 0xffe00000, T_Srr },
-  { "mpyf",   0x24c00000, 0xffe00000, T_rSr },
-  { "mpyf",   0x24e00000, 0xffe00000, T_SSr },
-  { "mpyf",   0x34800000, 0xffe00000, T_Jrr }, /* C4x */
-  { "mpyf",   0x34800000, 0xffe00000, T_rJr }, /* C4x */
-  { "mpyf",   0x34a00000, 0xffe00000, T_rRr }, /* C4x */
-  { "mpyf",   0x34a00000, 0xffe00000, T_Rrr }, /* C4x */
-  { "mpyf",   0x34c00000, 0xffe00000, T_JRr }, /* C4x */
-  { "mpyf",   0x34c00000, 0xffe00000, T_RJr }, /* C4x */
-  { "mpyf",   0x34e00000, 0xffe00000, T_RRr }, /* C4x */
-  { "mpyf3",  0x24800000, 0xffe00000, T_rrr },
-  { "mpyf3",  0x24a00000, 0xffe00000, T_Srr },
-  { "mpyf3",  0x24c00000, 0xffe00000, T_rSr },
-  { "mpyf3",  0x24e00000, 0xffe00000, T_SSr },
-  { "mpyf3",  0x34800000, 0xffe00000, T_Jrr }, /* C4x */
-  { "mpyf3",  0x34800000, 0xffe00000, T_rJr }, /* C4x */
-  { "mpyf3",  0x34a00000, 0xffe00000, T_rRr }, /* C4x */
-  { "mpyf3",  0x34a00000, 0xffe00000, T_Rrr }, /* C4x */
-  { "mpyf3",  0x34c00000, 0xffe00000, T_JRr }, /* C4x */
-  { "mpyf3",  0x34c00000, 0xffe00000, T_RJr }, /* C4x */
-  { "mpyf3",  0x34e00000, 0xffe00000, T_RRr }, /* C4x */
-  { "mpyi",   0x0a800000, 0xffe00000, G_r_r },
-  { "mpyi",   0x0aa00000, 0xffe00000, G_T_r },
-  { "mpyi",   0x0ac00000, 0xffe00000, G_Q_r },
-  { "mpyi",   0x0ae00000, 0xffe00000, G_I_r },
-  { "mpyi",   0x25000000, 0xffe00000, T_rrr },
-  { "mpyi",   0x25200000, 0xffe00000, T_Srr },
-  { "mpyi",   0x25400000, 0xffe00000, T_rSr },
-  { "mpyi",   0x25600000, 0xffe00000, T_SSr },
-  { "mpyi",   0x35000000, 0xffe00000, T_Jrr }, /* C4x */
-  { "mpyi",   0x35000000, 0xffe00000, T_rJr }, /* C4x */
-  { "mpyi",   0x35200000, 0xffe00000, T_rRr }, /* C4x */
-  { "mpyi",   0x35200000, 0xffe00000, T_Rrr }, /* C4x */
-  { "mpyi",   0x35400000, 0xffe00000, T_JRr }, /* C4x */
-  { "mpyi",   0x35400000, 0xffe00000, T_RJr }, /* C4x */
-  { "mpyi",   0x35600000, 0xffe00000, T_RRr }, /* C4x */
-  { "mpyi3",  0x25000000, 0xffe00000, T_rrr },
-  { "mpyi3",  0x25200000, 0xffe00000, T_Srr },
-  { "mpyi3",  0x25400000, 0xffe00000, T_rSr },
-  { "mpyi3",  0x25600000, 0xffe00000, T_SSr },
-  { "mpyi3",  0x35000000, 0xffe00000, T_Jrr }, /* C4x */
-  { "mpyi3",  0x35000000, 0xffe00000, T_rJr }, /* C4x */
-  { "mpyi3",  0x35200000, 0xffe00000, T_rRr }, /* C4x */
-  { "mpyi3",  0x35200000, 0xffe00000, T_Rrr }, /* C4x */
-  { "mpyi3",  0x35400000, 0xffe00000, T_JRr }, /* C4x */
-  { "mpyi3",  0x35400000, 0xffe00000, T_RJr }, /* C4x */
-  { "mpyi3",  0x35600000, 0xffe00000, T_RRr }, /* C4x */
-  { "negb",   0x0b000000, 0xffe00000, G_r_r },
-  { "negb",   0x0b200000, 0xffe00000, G_T_r },
-  { "negb",   0x0b400000, 0xffe00000, G_Q_r },
-  { "negb",   0x0b600000, 0xffe00000, G_I_r },
-  { "negf",   0x0b800000, 0xffe00000, G_r_r },
-  { "negf",   0x0ba00000, 0xffe00000, G_T_r },
-  { "negf",   0x0bc00000, 0xffe00000, G_Q_r },
-  { "negf",   0x0be00000, 0xffe00000, G_F_r },
-  { "negi",   0x0c000000, 0xffe00000, G_r_r },
-  { "negi",   0x0c200000, 0xffe00000, G_T_r },
-  { "negi",   0x0c400000, 0xffe00000, G_Q_r },
-  { "negi",   0x0c600000, 0xffe00000, G_I_r },
-  { "nop",    0x0c800000, 0xffe00000, "Q" },
-  { "nop",    0x0cc00000, 0xffe00000, "*" },
-  { "nop",    0x0c800000, 0xffe00000, "" },
-  { "norm",   0x0d000000, 0xffe00000, G_r_r },
-  { "norm",   0x0d200000, 0xffe00000, G_T_r },
-  { "norm",   0x0d400000, 0xffe00000, G_Q_r },
-  { "norm",   0x0d600000, 0xffe00000, G_F_r },
-  { "not",    0x0d800000, 0xffe00000, G_r_r },
-  { "not",    0x0da00000, 0xffe00000, G_T_r },
-  { "not",    0x0dc00000, 0xffe00000, G_Q_r },
-  { "not",    0x0de00000, 0xffe00000, G_L_r },
-  { "or",     0x10000000, 0xffe00000, G_r_r },
-  { "or",     0x10200000, 0xffe00000, G_T_r },
-  { "or",     0x10400000, 0xffe00000, G_Q_r },
-  { "or",     0x10600000, 0xffe00000, G_L_r },
-  { "or",     0x25800000, 0xffe00000, T_rrr },
-  { "or",     0x25a00000, 0xffe00000, T_Srr },
-  { "or",     0x25c00000, 0xffe00000, T_rSr },
-  { "or",     0x25e00000, 0xffe00000, T_SSr },
-  { "or",     0x35800000, 0xffe00000, T_Jrr }, /* C4x */
-  { "or",     0x35800000, 0xffe00000, T_rJr }, /* C4x */
-  { "or",     0x35a00000, 0xffe00000, T_rRr }, /* C4x */
-  { "or",     0x35a00000, 0xffe00000, T_Rrr }, /* C4x */
-  { "or",     0x35c00000, 0xffe00000, T_JRr }, /* C4x */
-  { "or",     0x35c00000, 0xffe00000, T_RJr }, /* C4x */
-  { "or",     0x35e00000, 0xffe00000, T_RRr }, /* C4x */
-  { "or3",    0x25800000, 0xffe00000, T_rrr },
-  { "or3",    0x25a00000, 0xffe00000, T_Srr },
-  { "or3",    0x25c00000, 0xffe00000, T_rSr },
-  { "or3",    0x25e00000, 0xffe00000, T_SSr },
-  { "or3",    0x35800000, 0xffe00000, T_Jrr }, /* C4x */
-  { "or3",    0x35800000, 0xffe00000, T_rJr }, /* C4x */
-  { "or3",    0x35a00000, 0xffe00000, T_rRr }, /* C4x */
-  { "or3",    0x35a00000, 0xffe00000, T_Rrr }, /* C4x */
-  { "or3",    0x35c00000, 0xffe00000, T_JRr }, /* C4x */
-  { "or3",    0x35c00000, 0xffe00000, T_RJr }, /* C4x */
-  { "or3",    0x35e00000, 0xffe00000, T_RRr }, /* C4x */
-  { "pop",    0x0e200000, 0xffe00000, "R" },
-  { "popf",   0x0ea00000, 0xffe00000, "R" },
-  { "push",   0x0f200000, 0xffe00000, "R" },
-  { "pushf",  0x0fa00000, 0xffe00000, "R" },
-  { "retiB",  0x78000000, 0xffe00000, "" },
-  { "reti",   0x78000000, 0xffe00000, "" }, /* synonym for reti */
-  { "retsB",  0x78800000, 0xffe00000, "" },
-  { "rets",   0x78800000, 0xffe00000, "" }, /* synonym for rets */
-  { "rnd",    0x11000000, 0xffe00000, G_r_r },
-  { "rnd",    0x11200000, 0xffe00000, G_T_r },
-  { "rnd",    0x11400000, 0xffe00000, G_Q_r },
-  { "rnd",    0x11600000, 0xffe00000, G_F_r },
-  { "rol",    0x11e00000, 0xffe00000, "R" },
-  { "rolc",   0x12600000, 0xffe00000, "R" },
-  { "ror",    0x12e00000, 0xffe00000, "R" },
-  { "rorc",   0x13600000, 0xffe00000, "R" },
-  { "rptb",   0x64000000, 0xff000000, "B" },
-  { "rptb",   0x79000000, 0xff000000, "Q" }, /* C4x */
-  { "rpts",   0x139b0000, 0xffff0000, "Q" },
-  { "rpts",   0x13bb0000, 0xffff0000, "@" },
-  { "rpts",   0x13db0000, 0xffff0000, "*" },
-  { "rpts",   0x13fb0000, 0xffff0000, "U" },
-  { "sigi",   0x16000000, 0xffe00000, "" },  /* C3x */
-  { "sigi",   0x16200000, 0xffe00000, G_T_r }, /* C4x */
-  { "sigi",   0x16400000, 0xffe00000, G_Q_r }, /* C4x */
-  { "stf",    0x14200000, 0xffe00000, "R,@" },
-  { "stf",    0x14400000, 0xffe00000, "R,*" },
-  { "stfi",   0x14a00000, 0xffe00000, "R,@" },
-  { "stfi",   0x14c00000, 0xffe00000, "R,*" },
-  { "sti",    0x15000000, 0xffe00000, "T,@" }, /* C4x only */
-  { "sti",    0x15200000, 0xffe00000, "R,@" },
-  { "sti",    0x15400000, 0xffe00000, "R,*" },
-  { "sti",    0x15600000, 0xffe00000, "T,*" }, /* C4x only */
-  { "stii",   0x15a00000, 0xffe00000, "R,@" },
-  { "stii",   0x15c00000, 0xffe00000, "R,*" },
-  { "subb",   0x16800000, 0xffe00000, G_r_r },
-  { "subb",   0x16a00000, 0xffe00000, G_T_r },
-  { "subb",   0x16c00000, 0xffe00000, G_Q_r },
-  { "subb",   0x16e00000, 0xffe00000, G_I_r },
-  { "subb",   0x26000000, 0xffe00000, T_rrr },
-  { "subb",   0x26200000, 0xffe00000, T_Srr },
-  { "subb",   0x26400000, 0xffe00000, T_rSr },
-  { "subb",   0x26600000, 0xffe00000, T_SSr },
-  { "subb",   0x36000000, 0xffe00000, T_Jrr }, /* C4x */
-  { "subb",   0x36200000, 0xffe00000, T_Rrr }, /* C4x */
-  { "subb",   0x36400000, 0xffe00000, T_JRr }, /* C4x */
-  { "subb",   0x36600000, 0xffe00000, T_RRr }, /* C4x */
-  { "subb3",  0x26000000, 0xffe00000, T_rrr },
-  { "subb3",  0x26200000, 0xffe00000, T_Srr },
-  { "subb3",  0x26400000, 0xffe00000, T_rSr },
-  { "subb3",  0x26600000, 0xffe00000, T_SSr },
-  { "subb3",  0x36000000, 0xffe00000, T_Jrr }, /* C4x */
-  { "subb3",  0x36200000, 0xffe00000, T_Rrr }, /* C4x */
-  { "subb3",  0x36400000, 0xffe00000, T_JRr }, /* C4x */
-  { "subb3",  0x36600000, 0xffe00000, T_RRr }, /* C4x */
-  { "subc",   0x17000000, 0xffe00000, G_r_r },
-  { "subc",   0x17200000, 0xffe00000, G_T_r },
-  { "subc",   0x17400000, 0xffe00000, G_Q_r },
-  { "subc",   0x17600000, 0xffe00000, G_I_r },
-  { "subf",   0x17800000, 0xffe00000, G_r_r },
-  { "subf",   0x17a00000, 0xffe00000, G_T_r },
-  { "subf",   0x17c00000, 0xffe00000, G_Q_r },
-  { "subf",   0x17e00000, 0xffe00000, G_F_r },
-  { "subf",   0x26800000, 0xffe00000, T_rrr },
-  { "subf",   0x26a00000, 0xffe00000, T_Srr },
-  { "subf",   0x26c00000, 0xffe00000, T_rSr },
-  { "subf",   0x26e00000, 0xffe00000, T_SSr },
-  { "subf",   0x36800000, 0xffe00000, T_Jrr }, /* C4x */
-  { "subf",   0x36a00000, 0xffe00000, T_Rrr }, /* C4x */
-  { "subf",   0x36c00000, 0xffe00000, T_JRr }, /* C4x */
-  { "subf",   0x36e00000, 0xffe00000, T_RRr }, /* C4x */
-  { "subf3",  0x26800000, 0xffe00000, T_rrr },
-  { "subf3",  0x26a00000, 0xffe00000, T_Srr },
-  { "subf3",  0x26c00000, 0xffe00000, T_rSr },
-  { "subf3",  0x26e00000, 0xffe00000, T_SSr },
-  { "subf3",  0x36800000, 0xffe00000, T_Jrr }, /* C4x */
-  { "subf3",  0x36a00000, 0xffe00000, T_Rrr }, /* C4x */
-  { "subf3",  0x36c00000, 0xffe00000, T_JRr }, /* C4x */
-  { "subf3",  0x36e00000, 0xffe00000, T_RRr }, /* C4x */
-  { "subi",   0x18000000, 0xffe00000, G_r_r },
-  { "subi",   0x18200000, 0xffe00000, G_T_r },
-  { "subi",   0x18400000, 0xffe00000, G_Q_r },
-  { "subi",   0x18600000, 0xffe00000, G_I_r },
-  { "subi",   0x27000000, 0xffe00000, T_rrr },
-  { "subi",   0x27200000, 0xffe00000, T_Srr },
-  { "subi",   0x27400000, 0xffe00000, T_rSr },
-  { "subi",   0x27600000, 0xffe00000, T_SSr },
-  { "subi",   0x37000000, 0xffe00000, T_Jrr }, /* C4x */
-  { "subi",   0x37200000, 0xffe00000, T_Rrr }, /* C4x */
-  { "subi",   0x37400000, 0xffe00000, T_JRr }, /* C4x */
-  { "subi",   0x37600000, 0xffe00000, T_RRr }, /* C4x */
-  { "subi3",  0x27000000, 0xffe00000, T_rrr },
-  { "subi3",  0x27200000, 0xffe00000, T_Srr },
-  { "subi3",  0x27400000, 0xffe00000, T_rSr },
-  { "subi3",  0x27600000, 0xffe00000, T_SSr },
-  { "subi3",  0x37000000, 0xffe00000, T_Jrr }, /* C4x */
-  { "subi3",  0x37200000, 0xffe00000, T_Rrr }, /* C4x */
-  { "subi3",  0x37400000, 0xffe00000, T_JRr }, /* C4x */
-  { "subi3",  0x37600000, 0xffe00000, T_RRr }, /* C4x */
-  { "subrb",  0x18800000, 0xffe00000, G_r_r },
-  { "subrb",  0x18a00000, 0xffe00000, G_T_r },
-  { "subrb",  0x18c00000, 0xffe00000, G_Q_r },
-  { "subrb",  0x18e00000, 0xffe00000, G_I_r },
-  { "subrf",  0x19000000, 0xffe00000, G_r_r },
-  { "subrf",  0x19200000, 0xffe00000, G_T_r },
-  { "subrf",  0x19400000, 0xffe00000, G_Q_r },
-  { "subrf",  0x19600000, 0xffe00000, G_F_r },
-  { "subri",  0x19800000, 0xffe00000, G_r_r },
-  { "subri",  0x19a00000, 0xffe00000, G_T_r },
-  { "subri",  0x19c00000, 0xffe00000, G_Q_r },
-  { "subri",  0x19e00000, 0xffe00000, G_I_r },
-  { "swi",    0x66000000, 0xffffffff, "" },
-  { "trapB",  0x74000000, 0xffe00000, "V" },
-  { "trap",   0x74000000, 0xffe00000, "V" }, /* synonym for trapu */
-  { "tstb",   0x1a000000, 0xffe00000, G_r_r },
-  { "tstb",   0x1a200000, 0xffe00000, G_T_r },
-  { "tstb",   0x1a400000, 0xffe00000, G_Q_r },
-  { "tstb",   0x1a600000, 0xffe00000, G_L_r },
-  { "tstb",   0x27800000, 0xffe00000, T_rr_ },
-  { "tstb",   0x27a00000, 0xffe00000, T_rS_ },
-  { "tstb",   0x27c00000, 0xffe00000, T_Sr_ },
-  { "tstb",   0x27e00000, 0xffe00000, T_SS_ },
-  { "tstb",   0x37800000, 0xffe00000, T_Jr_ }, /* C4x */
-  { "tstb",   0x37800000, 0xffe00000, T_rJ_ }, /* C4x */
-  { "tstb",   0x37a00000, 0xffe00000, T_rR_ }, /* C4x */
-  { "tstb",   0x37a00000, 0xffe00000, T_Rr_ }, /* C4x */
-  { "tstb",   0x37c00000, 0xffe00000, T_JR_ }, /* C4x */
-  { "tstb",   0x37c00000, 0xffe00000, T_RJ_ }, /* C4x */
-  { "tstb",   0x37e00000, 0xffe00000, T_RR_ }, /* C4x */
-  { "tstb3",  0x27800000, 0xffe00000, T_rr_ },
-  { "tstb3",  0x27a00000, 0xffe00000, T_rS_ },
-  { "tstb3",  0x27c00000, 0xffe00000, T_Sr_ },
-  { "tstb3",  0x27e00000, 0xffe00000, T_SS_ },
-  { "tstb3",  0x37800000, 0xffe00000, T_Jr_ }, /* C4x */
-  { "tstb3",  0x37800000, 0xffe00000, T_rJ_ }, /* C4x */
-  { "tstb3",  0x37a00000, 0xffe00000, T_rR_ }, /* C4x */
-  { "tstb3",  0x37a00000, 0xffe00000, T_Rr_ }, /* C4x */
-  { "tstb3",  0x37c00000, 0xffe00000, T_JR_ }, /* C4x */
-  { "tstb3",  0x37c00000, 0xffe00000, T_RJ_ }, /* C4x */
-  { "tstb3",  0x37e00000, 0xffe00000, T_RR_ }, /* C4x */
-  { "xor",    0x1a800000, 0xffe00000, G_r_r },
-  { "xor",    0x1aa00000, 0xffe00000, G_T_r },
-  { "xor",    0x1ac00000, 0xffe00000, G_Q_r },
-  { "xor",    0x1ae00000, 0xffe00000, G_L_r },
-  { "xor",    0x28000000, 0xffe00000, T_rrr },
-  { "xor",    0x28200000, 0xffe00000, T_Srr },
-  { "xor",    0x28400000, 0xffe00000, T_rSr },
-  { "xor",    0x28600000, 0xffe00000, T_SSr },
-  { "xor",    0x38000000, 0xffe00000, T_Jrr }, /* C4x */
-  { "xor",    0x38000000, 0xffe00000, T_rJr }, /* C4x */
-  { "xor",    0x38200000, 0xffe00000, T_rRr }, /* C4x */
-  { "xor",    0x38200000, 0xffe00000, T_Rrr }, /* C4x */
-  { "xor",    0x3c400000, 0xffe00000, T_JRr }, /* C4x */
-  { "xor",    0x3c400000, 0xffe00000, T_RJr }, /* C4x */
-  { "xor",    0x3c600000, 0xffe00000, T_RRr }, /* C4x */
-  { "xor3",   0x28000000, 0xffe00000, T_rrr },
-  { "xor3",   0x28200000, 0xffe00000, T_Srr },
-  { "xor3",   0x28400000, 0xffe00000, T_rSr },
-  { "xor3",   0x28600000, 0xffe00000, T_SSr },
-  { "xor3",   0x38000000, 0xffe00000, T_Jrr }, /* C4x */
-  { "xor3",   0x38000000, 0xffe00000, T_rJr }, /* C4x */
-  { "xor3",   0x38200000, 0xffe00000, T_rRr }, /* C4x */
-  { "xor3",   0x38200000, 0xffe00000, T_Rrr }, /* C4x */
-  { "xor3",   0x38400000, 0xffe00000, T_JRr }, /* C4x */
-  { "xor3",   0x38400000, 0xffe00000, T_RJr }, /* C4x */
-  { "xor3",   0x38600000, 0xffe00000, T_RRr }, /* C4x */
-    
-  /* Dummy entry, not included in c3x_num_insts.  This
-     lets code examine entry i + 1 without checking
-     if we've run off the end of the table.  */
-  { "",      0x0, 0x00, "" }
-};
-
-const unsigned int c3x_num_insts = (((sizeof c3x_insts) / (sizeof c3x_insts[0])) - 1);
-
-/* Define c4x additional opcodes for assembler and disassembler.  */
-static const c4x_inst_t c4x_insts[] =
-{
-  /* Parallel instructions.  */
-  { "frieee_stf",    0xf2000000, 0xfe000000, P_Sr_rS },
-  { "toieee_stf",    0xf0000000, 0xfe000000, P_Sr_rS },
-  { "stf_frieee",    0xf2000000, 0xfe000000, Q_rS_Sr },
-  { "stf_toieee",    0xf0000000, 0xfe000000, Q_rS_Sr },
-
-  { "bBaf",    0x68a00000, 0xffe00000, "Q" },
-  { "bBaf",    0x6aa00000, 0xffe00000, "P" },
-  { "baf",     0x68a00000, 0xffe00000, "Q" }, /* synonym for buaf */
-  { "baf",     0x6aa00000, 0xffe00000, "P" }, /* synonym for buaf */
-  { "bBat",    0x68600000, 0xffe00000, "Q" },
-  { "bBat",    0x6a600000, 0xffe00000, "P" },
-  { "bat",     0x68600000, 0xffe00000, "Q" }, /* synonym for buat */
-  { "bat",     0x6a600000, 0xffe00000, "P" }, /* synonym for buat */
-  { "laj",     0x63000000, 0xff000000, "B" },
-  { "lajB",    0x70200000, 0xffe00000, "Q" },
-  { "lajB",    0x72200000, 0xffe00000, "P" },
-  { "latB",    0x74800000, 0xffe00000, "V" },
-  { "frieee",  0x1c000000, 0xffe00000, G_r_r },
-  { "frieee",  0x1c200000, 0xffe00000, G_T_r },
-  { "frieee",  0x1c400000, 0xffe00000, G_Q_r },
-  { "frieee",  0x1c600000, 0xffe00000, G_F_r },
-  { "lb0",     0xb0000000, 0xffe00000, G_r_r },
-  { "lb0",     0xb0200000, 0xffe00000, G_T_r },
-  { "lb0",     0xb0400000, 0xffe00000, G_Q_r },
-  { "lb0",     0xb0600000, 0xffe00000, G_I_r },
-  { "lbu0",    0xb2000000, 0xffe00000, G_r_r },
-  { "lbu0",    0xb2200000, 0xffe00000, G_T_r },
-  { "lbu0",    0xb2400000, 0xffe00000, G_Q_r },
-  { "lbu0",    0xb2600000, 0xffe00000, G_L_r },
-  { "lb1",     0xb0800000, 0xffe00000, G_r_r },
-  { "lb1",     0xb0a00000, 0xffe00000, G_T_r },
-  { "lb1",     0xb0c00000, 0xffe00000, G_Q_r },
-  { "lb1",     0xb0e00000, 0xffe00000, G_I_r },
-  { "lbu1",    0xb2800000, 0xffe00000, G_r_r },
-  { "lbu1",    0xb2a00000, 0xffe00000, G_T_r },
-  { "lbu1",    0xb2c00000, 0xffe00000, G_Q_r },
-  { "lbu1",    0xb2e00000, 0xffe00000, G_L_r },
-  { "lb2",     0xb1000000, 0xffe00000, G_r_r },
-  { "lb2",     0xb1200000, 0xffe00000, G_T_r },
-  { "lb2",     0xb1400000, 0xffe00000, G_Q_r },
-  { "lb2",     0xb1600000, 0xffe00000, G_I_r },
-  { "lbu2",    0xb3000000, 0xffe00000, G_r_r },
-  { "lbu2",    0xb3200000, 0xffe00000, G_T_r },
-  { "lbu2",    0xb3400000, 0xffe00000, G_Q_r },
-  { "lbu2",    0xb3600000, 0xffe00000, G_L_r },
-  { "lb3",     0xb1800000, 0xffe00000, G_r_r },
-  { "lb3",     0xb1a00000, 0xffe00000, G_T_r },
-  { "lb3",     0xb1c00000, 0xffe00000, G_Q_r },
-  { "lb3",     0xb1e00000, 0xffe00000, G_I_r },
-  { "lbu3",    0xb3800000, 0xffe00000, G_r_r },
-  { "lbu3",    0xb3a00000, 0xffe00000, G_T_r },
-  { "lbu3",    0xb3c00000, 0xffe00000, G_Q_r },
-  { "lbu3",    0xb3e00000, 0xffe00000, G_L_r },
-  { "lda",     0x1e800000, 0xffe00000, "Q,Y" }, 
-  { "lda",     0x1ea00000, 0xffe00000, "@,Y" }, 
-  { "lda",     0x1ec00000, 0xffe00000, "*,Y" }, 
-  { "lda",     0x1ee00000, 0xffe00000, "S,Y" }, 
-  { "ldep",    0x76000000, 0xffe00000, "X,R" }, 
-  { "ldhi",    0x1fe00000, 0xffe00000, G_L_r },
-  { "ldhi",    0x1fe00000, 0xffe00000, "#,R" },
-  { "ldpe",    0x76800000, 0xffe00000, "Q,Z" }, 
-  { "ldpk",    0x1F700000, 0xffff0000, "#" },
-  { "lh0",     0xba000000, 0xffe00000, G_r_r },
-  { "lh0",     0xba200000, 0xffe00000, G_T_r },
-  { "lh0",     0xba400000, 0xffe00000, G_Q_r },
-  { "lh0",     0xba600000, 0xffe00000, G_I_r },
-  { "lhu0",    0xbb000000, 0xffe00000, G_r_r },
-  { "lhu0",    0xbb200000, 0xffe00000, G_T_r },
-  { "lhu0",    0xbb400000, 0xffe00000, G_Q_r },
-  { "lhu0",    0xbb600000, 0xffe00000, G_L_r },
-  { "lh1",     0xba800000, 0xffe00000, G_r_r },
-  { "lh1",     0xbaa00000, 0xffe00000, G_T_r },
-  { "lh1",     0xbac00000, 0xffe00000, G_Q_r },
-  { "lh1",     0xbae00000, 0xffe00000, G_I_r },
-  { "lhu1",    0xbb800000, 0xffe00000, G_r_r },
-  { "lhu1",    0xbba00000, 0xffe00000, G_T_r },
-  { "lhu1",    0xbbc00000, 0xffe00000, G_Q_r },
-  { "lhu1",    0xbbe00000, 0xffe00000, G_L_r },
-  { "lwl0",    0xb4000000, 0xffe00000, G_r_r },
-  { "lwl0",    0xb4200000, 0xffe00000, G_T_r },
-  { "lwl0",    0xb4400000, 0xffe00000, G_Q_r },
-  { "lwl0",    0xb4600000, 0xffe00000, G_I_r },
-  { "lwl1",    0xb4800000, 0xffe00000, G_r_r },
-  { "lwl1",    0xb4a00000, 0xffe00000, G_T_r },
-  { "lwl1",    0xb4c00000, 0xffe00000, G_Q_r },
-  { "lwl1",    0xb4e00000, 0xffe00000, G_I_r },
-  { "lwl2",    0xb5000000, 0xffe00000, G_r_r },
-  { "lwl2",    0xb5200000, 0xffe00000, G_T_r },
-  { "lwl2",    0xb5400000, 0xffe00000, G_Q_r },
-  { "lwl2",    0xb5600000, 0xffe00000, G_I_r },
-  { "lwl3",    0xb5800000, 0xffe00000, G_r_r },
-  { "lwl3",    0xb5a00000, 0xffe00000, G_T_r },
-  { "lwl3",    0xb5c00000, 0xffe00000, G_Q_r },
-  { "lwl3",    0xb5e00000, 0xffe00000, G_I_r },
-  { "lwr0",    0xb6000000, 0xffe00000, G_r_r },
-  { "lwr0",    0xb6200000, 0xffe00000, G_T_r },
-  { "lwr0",    0xb6400000, 0xffe00000, G_Q_r },
-  { "lwr0",    0xb6600000, 0xffe00000, G_I_r },
-  { "lwr1",    0xb6800000, 0xffe00000, G_r_r },
-  { "lwr1",    0xb6a00000, 0xffe00000, G_T_r },
-  { "lwr1",    0xb6c00000, 0xffe00000, G_Q_r },
-  { "lwr1",    0xb6e00000, 0xffe00000, G_I_r },
-  { "lwr2",    0xb7000000, 0xffe00000, G_r_r },
-  { "lwr2",    0xb7200000, 0xffe00000, G_T_r },
-  { "lwr2",    0xb7400000, 0xffe00000, G_Q_r },
-  { "lwr2",    0xb7600000, 0xffe00000, G_I_r },
-  { "lwr3",    0xb7800000, 0xffe00000, G_r_r },
-  { "lwr3",    0xb7a00000, 0xffe00000, G_T_r },
-  { "lwr3",    0xb7c00000, 0xffe00000, G_Q_r },
-  { "lwr3",    0xb7e00000, 0xffe00000, G_I_r },
-  { "mb0",     0xb8000000, 0xffe00000, G_r_r },
-  { "mb0",     0xb8200000, 0xffe00000, G_T_r },
-  { "mb0",     0xb8400000, 0xffe00000, G_Q_r },
-  { "mb0",     0xb8600000, 0xffe00000, G_I_r },
-  { "mb1",     0xb8800000, 0xffe00000, G_r_r },
-  { "mb1",     0xb8a00000, 0xffe00000, G_T_r },
-  { "mb1",     0xb8c00000, 0xffe00000, G_Q_r },
-  { "mb1",     0xb8e00000, 0xffe00000, G_I_r },
-  { "mb2",     0xb9000000, 0xffe00000, G_r_r },
-  { "mb2",     0xb9200000, 0xffe00000, G_T_r },
-  { "mb2",     0xb9400000, 0xffe00000, G_Q_r },
-  { "mb2",     0xb9600000, 0xffe00000, G_I_r },
-  { "mb3",     0xb9800000, 0xffe00000, G_r_r },
-  { "mb3",     0xb9a00000, 0xffe00000, G_T_r },
-  { "mb3",     0xb9c00000, 0xffe00000, G_Q_r },
-  { "mb3",     0xb9e00000, 0xffe00000, G_I_r },
-  { "mh0",     0xbc000000, 0xffe00000, G_r_r },
-  { "mh0",     0xbc200000, 0xffe00000, G_T_r },
-  { "mh0",     0xbc400000, 0xffe00000, G_Q_r },
-  { "mh0",     0xbc600000, 0xffe00000, G_I_r },
-  { "mh1",     0xbc800000, 0xffe00000, G_r_r },
-  { "mh1",     0xbca00000, 0xffe00000, G_T_r },
-  { "mh1",     0xbcc00000, 0xffe00000, G_Q_r },
-  { "mh1",     0xbce00000, 0xffe00000, G_I_r },
-  { "mh2",     0xbd000000, 0xffe00000, G_r_r },
-  { "mh2",     0xbd200000, 0xffe00000, G_T_r },
-  { "mh2",     0xbd400000, 0xffe00000, G_Q_r },
-  { "mh2",     0xbd600000, 0xffe00000, G_I_r },
-  { "mh3",     0xbd800000, 0xffe00000, G_r_r },
-  { "mh3",     0xbda00000, 0xffe00000, G_T_r },
-  { "mh3",     0xbdc00000, 0xffe00000, G_Q_r },
-  { "mh3",     0xbde00000, 0xffe00000, G_I_r },
-  { "mpyshi",  0x1d800000, 0xffe00000, G_r_r },
-  { "mpyshi",  0x1da00000, 0xffe00000, G_T_r },
-  { "mpyshi",  0x1dc00000, 0xffe00000, G_Q_r },
-  { "mpyshi",  0x1de00000, 0xffe00000, G_I_r },
-  { "mpyshi",  0x28800000, 0xffe00000, T_rrr },
-  { "mpyshi",  0x28a00000, 0xffe00000, T_Srr },
-  { "mpyshi",  0x28c00000, 0xffe00000, T_rSr },
-  { "mpyshi",  0x28e00000, 0xffe00000, T_SSr },
-  { "mpyshi",  0x38800000, 0xffe00000, T_Jrr }, /* C4x */
-  { "mpyshi",  0x38800000, 0xffe00000, T_rJr }, /* C4x */
-  { "mpyshi",  0x38a00000, 0xffe00000, T_rRr }, /* C4x */
-  { "mpyshi",  0x38a00000, 0xffe00000, T_Rrr }, /* C4x */
-  { "mpyshi",  0x38c00000, 0xffe00000, T_JRr }, /* C4x */
-  { "mpyshi",  0x38c00000, 0xffe00000, T_RJr }, /* C4x */
-  { "mpyshi",  0x38e00000, 0xffe00000, T_RRr }, /* C4x */
-  { "mpyshi3", 0x28800000, 0xffe00000, T_rrr },
-  { "mpyshi3", 0x28a00000, 0xffe00000, T_Srr },
-  { "mpyshi3", 0x28c00000, 0xffe00000, T_rSr },
-  { "mpyshi3", 0x28e00000, 0xffe00000, T_SSr },
-  { "mpyshi3", 0x38800000, 0xffe00000, T_Jrr }, /* C4x */
-  { "mpyshi3", 0x38800000, 0xffe00000, T_rJr }, /* C4x */
-  { "mpyshi3", 0x38a00000, 0xffe00000, T_rRr }, /* C4x */
-  { "mpyshi3", 0x38a00000, 0xffe00000, T_Rrr }, /* C4x */
-  { "mpyshi3", 0x38c00000, 0xffe00000, T_JRr }, /* C4x */
-  { "mpyshi3", 0x38c00000, 0xffe00000, T_RJr }, /* C4x */
-  { "mpyshi3", 0x38e00000, 0xffe00000, T_RRr }, /* C4x */
-  { "mpyuhi",  0x1e000000, 0xffe00000, G_r_r },
-  { "mpyuhi",  0x1e200000, 0xffe00000, G_T_r },
-  { "mpyuhi",  0x1e400000, 0xffe00000, G_Q_r },
-  { "mpyuhi",  0x1e600000, 0xffe00000, G_I_r },
-  { "mpyuhi",  0x29000000, 0xffe00000, T_rrr },
-  { "mpyuhi",  0x29200000, 0xffe00000, T_Srr },
-  { "mpyuhi",  0x29400000, 0xffe00000, T_rSr },
-  { "mpyuhi",  0x29600000, 0xffe00000, T_SSr },
-  { "mpyuhi",  0x39000000, 0xffe00000, T_Jrr }, /* C4x */
-  { "mpyuhi",  0x39000000, 0xffe00000, T_rJr }, /* C4x */
-  { "mpyuhi",  0x39200000, 0xffe00000, T_rRr }, /* C4x */
-  { "mpyuhi",  0x39200000, 0xffe00000, T_Rrr }, /* C4x */
-  { "mpyuhi",  0x39400000, 0xffe00000, T_JRr }, /* C4x */
-  { "mpyuhi",  0x39400000, 0xffe00000, T_RJr }, /* C4x */
-  { "mpyuhi",  0x39600000, 0xffe00000, T_RRr }, /* C4x */
-  { "mpyuhi3", 0x29000000, 0xffe00000, T_rrr },
-  { "mpyuhi3", 0x29200000, 0xffe00000, T_Srr },
-  { "mpyuhi3", 0x29400000, 0xffe00000, T_rSr },
-  { "mpyuhi3", 0x29600000, 0xffe00000, T_SSr },
-  { "mpyuhi3", 0x39000000, 0xffe00000, T_Jrr }, /* C4x */
-  { "mpyuhi3", 0x39000000, 0xffe00000, T_rJr }, /* C4x */
-  { "mpyuhi3", 0x39200000, 0xffe00000, T_rRr }, /* C4x */
-  { "mpyuhi3", 0x39200000, 0xffe00000, T_Rrr }, /* C4x */
-  { "mpyuhi3", 0x39400000, 0xffe00000, T_JRr }, /* C4x */
-  { "mpyuhi3", 0x39400000, 0xffe00000, T_RJr }, /* C4x */
-  { "mpyuhi3", 0x39600000, 0xffe00000, T_RRr }, /* C4x */
-  { "rcpf",    0x1d000000, 0xffe00000, G_r_r },
-  { "rcpf",    0x1d200000, 0xffe00000, G_T_r },
-  { "rcpf",    0x1d400000, 0xffe00000, G_Q_r },
-  { "rcpf",    0x1d600000, 0xffe00000, G_F_r },
-  { "retiBd",  0x78200000, 0xffe00000, "" },
-  { "retid",   0x78200000, 0xffe00000, "" }, /* synonym for retiud */
-  { "rptbd",   0x79800000, 0xff000000, "Q" },  
-  { "rptbd",   0x65000000, 0xff000000, "B" },  
-  { "rsqrf",   0x1c800000, 0xffe00000, G_r_r },
-  { "rsqrf",   0x1ca00000, 0xffe00000, G_T_r },
-  { "rsqrf",   0x1cc00000, 0xffe00000, G_Q_r },
-  { "rsqrf",   0x1ce00000, 0xffe00000, G_F_r },
-  { "stik",    0x15000000, 0xffe00000, "T,@" },
-  { "stik",    0x15600000, 0xffe00000, "T,*" },
-  { "toieee",  0x1b800000, 0xffe00000, G_r_r },
-  { "toieee",  0x1ba00000, 0xffe00000, G_T_r },
-  { "toieee",  0x1bc00000, 0xffe00000, G_Q_r },
-  { "toieee",  0x1be00000, 0xffe00000, G_F_r },
-  { "idle2",   0x06000001, 0xffffffff, "" }, 
-    
-  /* Dummy entry, not included in num_insts.  This
-     lets code examine entry i+1 without checking
-     if we've run off the end of the table.  */
-  { "",      0x0, 0x00, "" }
-};
-
-const unsigned int c4x_num_insts = (((sizeof c4x_insts) / (sizeof c4x_insts[0])) - 1);
-    
-
 struct c4x_cond
 {
   char *        name;
@@ -1341,4 +218,862 @@ static const c4x_indirect_t c4x_indirects[] =
 
 #define C3X_MODN_MAX 0x19
 
-const unsigned int num_indirects = (((sizeof c4x_indirects) / (sizeof c4x_indirects[0])) - 1);
+const unsigned int c4x_num_indirects = (((sizeof c4x_indirects) / (sizeof c4x_indirects[0])) - 1);
+
+/* Instruction template.  */
+struct c4x_inst
+{
+  char *        name;
+  unsigned long opcode;
+  unsigned long opmask;
+  char *        args;
+  unsigned long oplevel;
+};
+
+typedef struct c4x_inst c4x_inst_t;
+
+/* Opcode infix
+   B  condition              16--20   U,C,Z,LO,HI, etc.
+   C  condition              23--27   U,C,Z,LO,HI, etc.
+
+   Arguments
+   ,  required arg follows
+   ;  optional arg follows
+
+   Argument types             bits    [classes] - example
+   -----------------------------------------------------------
+   *  indirect (all)          0--15   [A,AB,AU,AF,A2,A3,A6,A7,AY,B,BA,BB,BI,B6,B7] - *+AR0(5), *++AR0(IR0)
+   #  direct (for LDP)        0--15   [Z] - @start, start
+   @  direct                  0--15   [A,AB,AU,AF,A3,A6,A7,AY,B,BA,BB,BI,B6,B7] - @start, start
+   A  address register       22--24   [D] - AR0, AR7
+   B  unsigned integer        0--23   [I,I2] - @start, start  (absolute on C3x, relative on C4x)
+   C  indirect (disp - C4x)   0--7    [S,SC,S2,T,TC,T2,T2C] - *+AR0(5)
+   E  register (all)          0--7    [T,TC,T2,T2C] - R0, R7, R11, AR0, DP
+   e  register (0-11)         0--7    [S,SC,S2] - R0, R7, R11
+   F  short float immediate   0--15   [AF,B,BA,BB] - 3.5, 0e-3.5e-1
+   G  register (all)          8--15   [T,TC,T2,T2C] - R0, R7, R11, AR0, DP
+   g  register (0-11)         0--7    [S,SC,S2] - R0, R7, R11
+   H  register (0-7)         18--16   [LS,M,P,Q] - R0, R7
+   I  indirect (no disp)      0--7    [S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0)
+   i  indirect (enhanced)     0--7    [LL,LS,M,P,Q,QC] - *+AR0(1), R5
+   J  indirect (no disp)      8--15   [LL,LS,P,Q,QC,S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0)
+   j  indirect (enhanced)     8--15   [M] - *+AR0(1), R5
+   K  register               19--21   [LL,M,Q,QC] - R0, R7
+   L  register               22--24   [LL,LS,P,Q,QC] - R0, R7
+   M  register (R2,R3)       22--22   [M] R2, R3
+   N  register (R0,R1)       23--23   [M] R0, R1
+   O  indirect(disp - C4x)    8--15   [S,SC,S2,T,TC,T2] - *+AR0(5)
+   P  displacement (PC Rel)   0--15   [D,J,JS] - @start, start
+   Q  register (all)          0--15   [A,AB,AU,A2,A3,AY,BA,BI,D,I2,J,JS] - R0, AR0, DP, SP
+   q  register (0-11)         0--15   [AF,B,BB] - R0, R7, R11
+   R  register (all)         16--20   [A,AB,AU,AF,A6,A7,R,T,TC] - R0, AR0, DP, SP
+   r  register (0-11)        16--20   [B,BA,BB,BI,B6,B7,RF,S,SC] - R0, R1, R11
+   S  short int immediate     0--15   [A,AB,AY,BI] - -5, 5
+   T  integer (C4x)          16--20   [Z] - -5, 12
+   U  unsigned integer        0--15   [AU,A3] - 0, 65535
+   V  vector (C4x: 0--8)      0--4    [Z] - 25, 7
+   W  short int (C4x)         0--7    [T,TC,T2,T2C] - -3, 5
+   X  expansion reg (C4x)     0--4    [Z] - IVTP, TVTP
+   Y  address reg (C4x)      16--20   [Z] - AR0, DP, SP, IR0
+   Z  expansion reg (C4x)    16--20   [Z] - IVTP, TVTP
+*/
+
+#define C4X_OPERANDS_MAX 7	/* Max number of operands for an inst.  */
+#define C4X_NAME_MAX 16		/* Max number of chars in parallel name.  */
+
+/* Define the instruction level */
+#define OP_C3X   0x1   /* C30 support - supported by all */
+#define OP_C4X   0x2   /* C40 support - C40, C44 */
+#define OP_ENH   0x4   /* Class LL,LS,M,P,Q,QC enhancements. Argument type
+                          I and J is enhanced in these classes - C31>=6.0,
+                          C32>=2.0, C33 */
+#define OP_LPWR  0x8   /* Low power support (LOPOWER, MAXSPEED) - C30>=7.0,
+                          LC31, C31>=5.0, C32 */
+#define OP_IDLE2 0x10  /* Idle2 support (IDLE2) - C30>=7.0, LC31, C31>=5.0,
+                          C32, C33, C40>=5.0, C44 */
+
+/* The following class definition is a classification scheme for
+   putting instructions with similar type of arguments together. It
+   simplifies the op-code definitions significantly, as we then only
+   need to use the class macroes for 95% of the DSP's opcodes.
+*/
+
+/* A: General 2-operand integer operations
+   Syntax: <i> src, dst
+      src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
+      dst = Register (R)
+   Instr: 15/8 - ABSI, ADDC, ADDI, ASH, CMPI, LDI, LSH, MPYI, NEGB, NEGI,
+                SUBB, SUBC, SUBI, SUBRB, SUBRI, C4x: LBn, LHn, LWLn, LWRn,
+                MBn, MHn, MPYSHI, MPYUHI
+*/
+#define A_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x00000000, 0xffe00000, "Q;R", level }, \
+  { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
+  { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \
+  { name, opcode|0x00600000, 0xffe00000, "S,R", level }
+
+/* AB: General 2-operand integer operation with condition
+   Syntax: <i>c src, dst
+       c   = Condition
+       src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
+       dst = Register (R)
+   Instr: 1/0 - LDIc
+*/
+#define AB_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x40000000, 0xf0600000, "Q;R", level }, \
+  { name, opcode|0x40200000, 0xf0600000, "@,R", level }, \
+  { name, opcode|0x40400000, 0xf0600000, "*,R", level }, \
+  { name, opcode|0x40600000, 0xf0600000, "S,R", level }
+
+/* AU: General 2-operand unsigned integer operation
+   Syntax: <i> src, dst
+        src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U)
+        dst = Register (R)
+   Instr: 6/2 - AND, ANDN, NOT, OR, TSTB, XOR, C4x: LBUn, LHUn
+*/
+#define AU_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x00000000, 0xffe00000, "Q;R", level }, \
+  { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
+  { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \
+  { name, opcode|0x00600000, 0xffe00000, "U,R", level }
+
+/* AF: General 2-operand float to integer operation
+   Syntax: <i> src, dst
+        src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F)
+        dst = Register (R)
+   Instr: 1/0 - FIX
+*/
+#define AF_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x00000000, 0xffe00000, "q;R", level }, \
+  { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
+  { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \
+  { name, opcode|0x00600000, 0xffe00000, "F,R", level }
+
+/* A2: Limited 1-operand (integer) operation
+   Syntax: <i> src
+       src = Register (Q), Indirect (*), None
+   Instr: 1/0 - NOP
+*/
+#define A2_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x00000000, 0xffe00000, "Q", level }, \
+  { name, opcode|0x00400000, 0xffe00000, "*", level }, \
+  { name, opcode|0x00000000, 0xffe00000, "" , level }
+
+/* A3: General 1-operand unsigned integer operation
+   Syntax: <i> src
+        src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U)
+   Instr: 1/0 - RPTS
+*/
+#define A3_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x00000000, 0xffff0000, "Q", level }, \
+  { name, opcode|0x00200000, 0xffff0000, "@", level }, \
+  { name, opcode|0x00400000, 0xffff0000, "*", level }, \
+  { name, opcode|0x00600000, 0xffff0000, "U", level }
+
+/* A6: Limited 2-operand integer operation
+   Syntax: <i> src, dst
+       src = Direct (@), Indirect (*)
+       dst = Register (R)
+   Instr: 1/1 - LDII, C4x: SIGI
+*/
+#define A6_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
+  { name, opcode|0x00400000, 0xffe00000, "*,R", level }
+
+/* A7: Limited 2-operand integer store operation
+   Syntax: <i> src, dst
+       src = Register (R)
+       dst = Direct (@), Indirect (*)
+   Instr: 2/0 - STI, STII
+*/
+#define A7_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x00200000, 0xffe00000, "R,@", level }, \
+  { name, opcode|0x00400000, 0xffe00000, "R,*", level }
+
+/* AY: General 2-operand signed address load operation
+   Syntax: <i> src, dst
+        src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
+        dst = Address register - ARx, IRx, DP, BK, SP (Y)
+   Instr: 0/1 - C4x: LDA
+   Note: Q and Y should *never* be the same register
+*/
+#define AY_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x00000000, 0xffe00000, "Q,Y", level }, \
+  { name, opcode|0x00200000, 0xffe00000, "@,Y", level }, \
+  { name, opcode|0x00400000, 0xffe00000, "*,Y", level }, \
+  { name, opcode|0x00600000, 0xffe00000, "S,Y", level }
+
+/* B: General 2-operand float operation
+   Syntax: <i> src, dst
+       src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F)
+       dst = Register 0-11 (r)
+   Instr: 12/2 - ABSF, ADDF, CMPF, LDE, LDF, LDM, MPYF, NEGF, NORM, RND,
+                 SUBF, SUBRF, C4x: RSQRF, TOIEEE
+*/
+#define B_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x00000000, 0xffe00000, "q;r", level }, \
+  { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \
+  { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \
+  { name, opcode|0x00600000, 0xffe00000, "F,r", level }
+
+/* BA: General 2-operand integer to float operation
+   Syntax: <i> src, dst
+       src = Register (Q), Direct (@), Indirect (*), Float immediate (F)
+       dst = Register 0-11 (r)
+   Instr: 0/1 - C4x: CRCPF
+*/
+#define BA_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x00000000, 0xffe00000, "Q;r", level }, \
+  { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \
+  { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \
+  { name, opcode|0x00600000, 0xffe00000, "F,r", level }
+
+/* BB: General 2-operand conditional float operation
+   Syntax: <i>c src, dst
+       c   = Condition
+       src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F)
+       dst = Register 0-11 (r)
+   Instr: 1/0 - LDFc
+*/
+#define BB_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x40000000, 0xf0600000, "q;r", level }, \
+  { name, opcode|0x40200000, 0xf0600000, "@,r", level }, \
+  { name, opcode|0x40400000, 0xf0600000, "*,r", level }, \
+  { name, opcode|0x40600000, 0xf0600000, "F,r", level }
+
+/* BI: General 2-operand integer to float operation (yet different to BA)
+   Syntax: <i> src, dst
+       src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
+       dst = Register 0-11 (r)
+   Instr: 1/0 - FLOAT
+*/
+#define BI_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x00000000, 0xffe00000, "Q;r", level }, \
+  { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \
+  { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \
+  { name, opcode|0x00600000, 0xffe00000, "S,r", level }
+
+/* B6: Limited 2-operand float operation 
+   Syntax: <i> src, dst
+       src = Direct (@), Indirect (*)
+       dst = Register 0-11 (r)
+   Instr: 1/1 - LDFI, C4x: FRIEEE
+*/
+#define B6_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \
+  { name, opcode|0x00400000, 0xffe00000, "*,r", level }
+
+/* B7: Limited 2-operand float store operation
+   Syntax: <i> src, dst
+       src = Register 0-11 (r)
+       dst = Direct (@), Indirect (*)
+   Instr: 2/0 - STF, STFI
+*/
+#define B7_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x00200000, 0xffe00000, "r,@", level }, \
+  { name, opcode|0x00400000, 0xffe00000, "r,*", level }
+
+/* D: Decrement and brach operations
+   Syntax: <i>c ARn, dst
+       c   = condition
+       ARn = AR register 0-7 (A)
+       dst = Register (Q), PC-relative (P)
+   Instr: 2/0 - DBc, DBcD
+   Alias: <name1> <name2>
+*/
+#define D_CLASS_INSN(name1, name2, opcode, level) \
+  { name1, opcode|0x00000000, 0xfe200000, "A,Q", level }, \
+  { name1, opcode|0x02000000, 0xfe200000, "A,P", level }, \
+  { name2, opcode|0x00000000, 0xfe200000, "A,Q", level }, \
+  { name2, opcode|0x02000000, 0xfe200000, "A,P", level }
+
+/* I: General branch operations
+   Syntax: <i> dst
+       dst = Address (B)
+   Instr: 3/1 - BR, BRD, CALL, C4x: LAJ
+*/
+
+/* I2: General branch operations (C4x addition)
+   Syntax: <i> dst
+       dst = Address (B), C4x: Register (Q)
+   Instr: 2/0 - RPTB, RPTBD
+*/
+
+/* J: General conditional branch operations
+   Syntax: <i>c dst
+       c   = Condition
+       dst = Register (Q), PC-relative (P)
+   Instr: 2/3 - Bc, BcD, C4x: BcAF, BcAT, LAJc
+   Alias: <name1> <name2>
+*/
+#define J_CLASS_INSN(name1, name2, opcode, level) \
+  { name1, opcode|0x00000000, 0xffe00000, "Q", level }, \
+  { name1, opcode|0x02000000, 0xffe00000, "P", level }, \
+  { name2, opcode|0x00000000, 0xffe00000, "Q", level }, \
+  { name2, opcode|0x02000000, 0xffe00000, "P", level }
+
+/* JS: General conditional branch operations
+   Syntax: <i>c dst
+       c   = Condition
+       dst = Register (Q), PC-relative (P)
+   Instr: 1/1 - CALLc, C4X: LAJc
+*/
+
+/* LL: Load-load parallell operation
+   Syntax: <i> src2, dst2 || <i> src1, dst1
+       src1 = Indirect 0,1,IR0,IR1 (J)
+       dst1 = Register 0-7 (K)
+       src2 = Indirect 0,1,IR0,IR1, ENH: Register (i)
+       dst2 = Register 0-7 (L)
+   Instr: 2/0 - LDF||LDF, LDI||LDI
+   Alias: i||i, i1||i2, i2||i1
+*/
+#define LL_CLASS_INSN(name, opcode, level) \
+  { name "_"  name    , opcode, 0xfe000000, "i;L|J,K", level }, \
+  { name "2_" name "1", opcode, 0xfe000000, "i;L|J,K", level }, \
+  { name "1_" name "2", opcode, 0xfe000000, "J,K|i;L", level }
+
+/* LS: Store-store parallell operation
+   Syntax: <i> src2, dst2 || <i> src1, dst1
+       src1 = Register 0-7 (H)
+       dst1 = Indirect 0,1,IR0,IR1 (J)
+       src2 = Register 0-7 (L)
+       dst2 = Indirect 0,1,IR0,IR1, ENH: register (i)
+   Instr: 2/0 - STF||STF, STI||STI
+   Alias: i||i, i1||i2, i2||i1.
+*/
+#define LS_CLASS_INSN(name, opcode, level) \
+  { name "_"  name    , opcode, 0xfe000000, "L;i|H,J", level }, \
+  { name "2_" name "1", opcode, 0xfe000000, "L;i|H,J", level }, \
+  { name "1_" name "2", opcode, 0xfe000000, "H,J|L;i", level }
+
+/* M: General multiply and add/sub operations
+   Syntax: <ia> src3,src4,dst1 || <ib> src2,src1,dst2 [00] - Manual
+           <ia> src3,src1,dst1 || <ib> src2,src4,dst2 [01] - Manual
+           <ia> src1,src3,dst1 || <ib> src2,src4,dst2 [01]
+           <ia> src1,src2,dst1 || <ib> src4,src3,dst2 [02] - Manual
+           <ia> src3,src1,dst1 || <ib> src4,src2,dst2 [03] - Manual
+           <ia> src1,src3,dst1 || <ib> src4,src2,dst2 [03]
+       src1 = Register 0-7 (K)
+       src2 = Register 0-7 (H)
+       src3 = Indirect 0,1,IR0,IR1, ENH: register (j)
+       src4 = Indirect 0,1,IR0,IR1, ENH: register (i)
+       dst1 = Register 0-1 (N)
+       dst2 = Register 2-3 (M)
+   Instr: 4/0 - MPYF3||ADDF3, MPYF3||SUBF3, MPYI3||ADDI3, MPYI3||SUBI3
+   Alias: a||b, a3||n, a||b3, a3||b3, b||a, b3||a, b||a3, b3||a3
+*/
+#define M_CLASS_INSN(namea, nameb, opcode, level) \
+  { namea "_" nameb, opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \
+  { namea "_" nameb, opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \
+  { namea "_" nameb, opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \
+  { namea "_" nameb, opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \
+  { namea "_" nameb, opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \
+  { namea "_" nameb, opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \
+  { namea "3_" nameb, opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \
+  { namea "3_" nameb, opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \
+  { namea "3_" nameb, opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \
+  { namea "3_" nameb, opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \
+  { namea "3_" nameb, opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \
+  { namea "3_" nameb, opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \
+  { namea "_" nameb "3", opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \
+  { namea "_" nameb "3", opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \
+  { namea "_" nameb "3", opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \
+  { namea "_" nameb "3", opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \
+  { namea "_" nameb "3", opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \
+  { namea "_" nameb "3", opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \
+  { namea "3_" nameb "3", opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \
+  { namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \
+  { namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \
+  { namea "3_" nameb "3", opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \
+  { namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \
+  { namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \
+  { nameb "_" namea, opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \
+  { nameb "_" namea, opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \
+  { nameb "_" namea, opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \
+  { nameb "_" namea, opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \
+  { nameb "_" namea, opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \
+  { nameb "_" namea, opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \
+  { nameb "3_" namea, opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \
+  { nameb "3_" namea, opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \
+  { nameb "3_" namea, opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \
+  { nameb "3_" namea, opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \
+  { nameb "3_" namea, opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \
+  { nameb "3_" namea, opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \
+  { nameb "_" namea "3", opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \
+  { nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \
+  { nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \
+  { nameb "_" namea "3", opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \
+  { nameb "_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \
+  { nameb "_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \
+  { nameb "3_" namea "3", opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \
+  { nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \
+  { nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \
+  { nameb "3_" namea "3", opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \
+  { nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \
+  { nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }
+
+/* P: General 2-operand operation with parallell store
+   Syntax: <ia> src2, dst1 || <ib> src3, dst2
+       src2 = Indirect 0,1,IR0,IR1, ENH: register (i)
+       dst1 = Register 0-7 (L)
+       src3 = Register 0-7 (H)
+       dst2 = Indirect 0,1,IR0,IR1 (J)
+   Instr: 9/2 - ABSF||STF, ABSI||STI, FIX||STI, FLOAT||STF, LDF||STF,
+                LDI||STI, NEGF||STF, NEGI||STI, NOT||STI, C4x: FRIEEE||STF,
+                TOIEEE||STF
+   Alias: a||b, b||a
+*/
+#define P_CLASS_INSN(namea, nameb, opcode, level) \
+  { namea "_" nameb, opcode, 0xfe000000, "i;L|H,J", level }, \
+  { nameb "_" namea, opcode, 0xfe000000, "H,J|i;L", level }
+
+/* Q: General 3-operand operation with parallell store
+   Syntax: <ia> src1, src2, dst1 || <ib> src3, dst2
+       src1 = Register 0-7 (K)
+       src2 = Indirect 0,1,IR0,IR1, ENH: register (i)
+       dst1 = Register 0-7 (L)
+       src3 = Register 0-7 (H)
+       dst2 = Indirect 0,1,IR0,IR1 (J)
+   Instr: 4/0 - ASH3||STI, LSH3||STI, SUBF3||STF, SUBI3||STI
+   Alias: a||b, b||a, a3||b, b||a3
+*/
+#define Q_CLASS_INSN(namea, nameb, opcode, level) \
+  { namea "_"  nameb    , opcode, 0xfe000000, "K,i;L|H,J", level }, \
+  { nameb "_"  namea    , opcode, 0xfe000000, "H,J|K,i;L", level }, \
+  { namea "3_" nameb    , opcode, 0xfe000000, "K,i;L|H,J", level }, \
+  { nameb "_"  namea "3", opcode, 0xfe000000, "H,J|K,i;L", level }
+
+/* QC: General commutative 3-operand operation with parallell store
+   Syntax: <ia> src2, src1, dst1 || <ib> src3, dst2
+           <ia> src1, src2, dst1 || <ib> src3, dst2 - Manual
+       src1 = Register 0-7 (K)
+       src2 = Indirect 0,1,IR0,IR1, ENH: register (i)
+       dst1 = Register 0-7 (L)
+       src3 = Register 0-7 (H)
+       dst2 = Indirect 0,1,IR0,IR1 (J)
+   Instr: 7/0 - ADDF3||STF, ADDI3||STI, AND3||STI, MPYF3||STF, MPYI3||STI,
+                OR3||STI, XOR3||STI
+   Alias: a||b, b||a, a3||b, b||a3
+*/
+#define QC_CLASS_INSN(namea, nameb, opcode, level) \
+  { namea "_"  nameb    , opcode, 0xfe000000, "i;K;L|H,J", level }, \
+  { namea "_"  nameb    , opcode, 0xfe000000, "K;i;L|H,J", level }, \
+  { nameb "_"  namea    , opcode, 0xfe000000, "H,J|i;K;L", level }, \
+  { nameb "_"  namea    , opcode, 0xfe000000, "H,J|K;i;L", level }, \
+  { namea "3_" nameb    , opcode, 0xfe000000, "i;K;L|H,J", level }, \
+  { namea "3_" nameb    , opcode, 0xfe000000, "K;i;L|H,J", level }, \
+  { nameb "_"  namea "3", opcode, 0xfe000000, "H,J|i;K;L", level }, \
+  { nameb "_"  namea "3", opcode, 0xfe000000, "H,J|K;i;L", level }
+
+/* R: General register integer operation
+   Syntax: <i> dst
+       dst = Register (R)
+   Instr: 6/0 - POP, PUSH, ROL, ROLC, ROR, RORC
+*/
+#define R_CLASS_INSN(name, opcode, level) \
+  { name, opcode, 0xffe0ffff, "R", level }
+
+/* RF: General register float operation
+   Syntax: <i> dst
+       dst = Register 0-11 (r)
+   Instr: 2/0 - POPF, PUSHF
+*/
+#define RF_CLASS_INSN(name, opcode, level) \
+  { name, opcode, 0xffe0ffff, "r", level }
+
+/* S: General 3-operand float operation
+   Syntax: <i> src2, src1, dst
+       src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
+       src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
+       dst  = Register 0-11 (r)
+   Instr: 1/0 - SUBF3
+   Alias: i, i3
+*/
+#define S_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x20000000, 0xffe00000, "e,g;r", level  }, \
+  { name, opcode|0x20200000, 0xffe00000, "e,J,r", level  }, \
+  { name, opcode|0x20400000, 0xffe00000, "I,g;r", level  }, \
+  { name, opcode|0x20600000, 0xffe00000, "I,J,r", level  }, \
+  { name, opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \
+  { name, opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }, \
+  { name "3", opcode|0x20000000, 0xffe00000, "e,g;r", level  }, \
+  { name "3", opcode|0x20200000, 0xffe00000, "e,J,r", level  }, \
+  { name "3", opcode|0x20400000, 0xffe00000, "I,g;r", level  }, \
+  { name "3", opcode|0x20600000, 0xffe00000, "I,J,r", level  }, \
+  { name "3", opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \
+  { name "3", opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }
+
+/* SC: General commutative 3-operand float operation
+   Syntax: <i> src2, src1, dst - Manual
+           <i> src1, src2, dst
+       src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
+       src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
+       dst  = Register 0-11 (r)
+   Instr: 2/0 - ADDF3, MPYF3
+   Alias: i, i3
+*/
+#define SC_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x20000000, 0xffe00000, "e,g;r", level  }, \
+  { name, opcode|0x20200000, 0xffe00000, "e,J,r", level  }, \
+  { name, opcode|0x20400000, 0xffe00000, "I,g;r", level  }, \
+  { name, opcode|0x20600000, 0xffe00000, "I,J,r", level  }, \
+  { name, opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \
+  { name, opcode|0x30200000, 0xffe00000, "g,C,r", OP_C4X }, \
+  { name, opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }, \
+  { name "3", opcode|0x20000000, 0xffe00000, "e,g;r", level  }, \
+  { name "3", opcode|0x20200000, 0xffe00000, "e,J,r", level  }, \
+  { name "3", opcode|0x20400000, 0xffe00000, "I,g;r", level  }, \
+  { name "3", opcode|0x20600000, 0xffe00000, "I,J,r", level  }, \
+  { name "3", opcode|0x30200000, 0xffe00000, "g,C,r", OP_C4X }, \
+  { name "3", opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \
+  { name "3", opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }
+
+/* S2: General 3-operand float operation with 2 args
+   Syntax: <i> src2, src1
+       src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
+       src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
+   Instr: 1/0 - CMPF3
+   Alias: i, i3
+*/
+#define S2_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x20000000, 0xffe00000, "e,g", level  }, \
+  { name, opcode|0x20200000, 0xffe00000, "e,J", level  }, \
+  { name, opcode|0x20400000, 0xffe00000, "I,g", level  }, \
+  { name, opcode|0x20600000, 0xffe00000, "I,J", level  }, \
+  { name, opcode|0x30200000, 0xffe00000, "C,g", OP_C4X }, \
+  { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \
+  { name "3", opcode|0x20000000, 0xffe00000, "e,g", level  }, \
+  { name "3", opcode|0x20200000, 0xffe00000, "e,J", level  }, \
+  { name "3", opcode|0x20400000, 0xffe00000, "I,g", level  }, \
+  { name "3", opcode|0x20600000, 0xffe00000, "I,J", level  }, \
+  { name "3", opcode|0x30200000, 0xffe00000, "C,g", OP_C4X }, \
+  { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }
+
+/* T: General 3-operand integer operand
+   Syntax: <i> src2, src1, dst
+       src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
+       src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
+       dst  = Register (R)
+   Instr: 5/0 - ANDN3, ASH3, LSH3, SUBB3, SUBI3
+   Alias: i, i3
+*/
+#define T_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x20000000, 0xffe00000, "E,G;R", level  }, \
+  { name, opcode|0x20200000, 0xffe00000, "E,J,R", level  }, \
+  { name, opcode|0x20400000, 0xffe00000, "I,G;R", level  }, \
+  { name, opcode|0x20600000, 0xffe00000, "I,J,R", level  }, \
+  { name, opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \
+  { name, opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \
+  { name, opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \
+  { name, opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }, \
+  { name "3", opcode|0x20000000, 0xffe00000, "E,G;R", level  }, \
+  { name "3", opcode|0x20200000, 0xffe00000, "E,J,R", level  }, \
+  { name "3", opcode|0x20400000, 0xffe00000, "I,G;R", level  }, \
+  { name "3", opcode|0x20600000, 0xffe00000, "I,J,R", level  }, \
+  { name "3", opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \
+  { name "3", opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \
+  { name "3", opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \
+  { name "3", opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }
+
+/* TC: General commutative 3-operand integer operation
+   Syntax: <i> src2, src1, dst
+           <i> src1, src2, dst
+       src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
+       src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
+       dst  = Register (R)
+   Instr: 6/2 - ADDC3, ADDI3, AND3, MPYI3, OR3, XOR3, C4x: MPYSHI, MPYUHI
+   Alias: i, i3
+*/
+#define TC_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x20000000, 0xffe00000, "E,G;R", level  }, \
+  { name, opcode|0x20200000, 0xffe00000, "E,J,R", level  }, \
+  { name, opcode|0x20400000, 0xffe00000, "I,G;R", level  }, \
+  { name, opcode|0x20600000, 0xffe00000, "I,J,R", level  }, \
+  { name, opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \
+  { name, opcode|0x30000000, 0xffe00000, "G,W,R", OP_C4X }, \
+  { name, opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \
+  { name, opcode|0x30200000, 0xffe00000, "G,C,R", OP_C4X }, \
+  { name, opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \
+  { name, opcode|0x30400000, 0xffe00000, "O,W,R", OP_C4X }, \
+  { name, opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }, \
+  { name "3", opcode|0x20000000, 0xffe00000, "E,G;R", level  }, \
+  { name "3", opcode|0x20200000, 0xffe00000, "E,J,R", level  }, \
+  { name "3", opcode|0x20400000, 0xffe00000, "I,G;R", level  }, \
+  { name "3", opcode|0x20600000, 0xffe00000, "I,J,R", level  }, \
+  { name "3", opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \
+  { name "3", opcode|0x30000000, 0xffe00000, "G,W,R", OP_C4X }, \
+  { name "3", opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \
+  { name "3", opcode|0x30200000, 0xffe00000, "G,C,R", OP_C4X }, \
+  { name "3", opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \
+  { name "3", opcode|0x30400000, 0xffe00000, "O,W,R", OP_C4X }, \
+  { name "3", opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }
+
+/* T2: General 3-operand integer operation with 2 args
+   Syntax: <i> src2, src1
+       src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
+       src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
+   Instr: 1/0 - CMPI3
+   Alias: i, i3
+*/
+#define T2_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x20000000, 0xffe00000, "E,G", level  }, \
+  { name, opcode|0x20200000, 0xffe00000, "E,J", level  }, \
+  { name, opcode|0x20400000, 0xffe00000, "I,G", level  }, \
+  { name, opcode|0x20600000, 0xffe00000, "I,J", level  }, \
+  { name, opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \
+  { name, opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \
+  { name, opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \
+  { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \
+  { name "3", opcode|0x20000000, 0xffe00000, "E,G", level  }, \
+  { name "3", opcode|0x20200000, 0xffe00000, "E,J", level  }, \
+  { name "3", opcode|0x20400000, 0xffe00000, "I,G", level  }, \
+  { name "3", opcode|0x20600000, 0xffe00000, "I,J", level  }, \
+  { name "3", opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \
+  { name "3", opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \
+  { name "3", opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \
+  { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }
+
+/* T2C: General commutative 3-operand integer operation with 2 args 
+   Syntax: <i> src2, src1 - Manual
+           <i> src1, src2 
+       src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
+       src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (0)
+   Instr: 1/0 - TSTB3
+   Alias: i, i3
+*/
+#define T2C_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x20000000, 0xffe00000, "E,G", level  }, \
+  { name, opcode|0x20200000, 0xffe00000, "E,J", level  }, \
+  { name, opcode|0x20400000, 0xffe00000, "I,G", level  }, \
+  { name, opcode|0x20600000, 0xffe00000, "I,J", level  }, \
+  { name, opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \
+  { name, opcode|0x30000000, 0xffe00000, "G,W", OP_C4X }, \
+  { name, opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \
+  { name, opcode|0x30200000, 0xffe00000, "G,C", OP_C4X }, \
+  { name, opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \
+  { name, opcode|0x30400000, 0xffe00000, "O,W", OP_C4X }, \
+  { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \
+  { name "3", opcode|0x20000000, 0xffe00000, "E,G", level  }, \
+  { name "3", opcode|0x20200000, 0xffe00000, "E,J", level  }, \
+  { name "3", opcode|0x20400000, 0xffe00000, "I,G", level  }, \
+  { name "3", opcode|0x20600000, 0xffe00000, "I,J", level  }, \
+  { name "3", opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \
+  { name "3", opcode|0x30000000, 0xffe00000, "G,W", OP_C4X }, \
+  { name "3", opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \
+  { name "3", opcode|0x30200000, 0xffe00000, "G,C", OP_C4X }, \
+  { name "3", opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \
+  { name "3", opcode|0x30400000, 0xffe00000, "O,W", OP_C4X }, \
+  { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }
+
+/* Z: Misc operations with or without arguments
+   Syntax: <i> <arg1>,...
+   Instr: 16 - RETIc, RETSc, SIGI(c3X), SWI, IDLE, IDLE2, RETIcD, 
+               TRAPc, LATc, LDEP, LDEHI, LDEPE, LDPK, STIK, LDP, IACK
+*/
+
+
+/* Define c3x opcodes for assembler and disassembler.  */
+static const c4x_inst_t c4x_insts[] =
+{
+  /* Put synonyms after the desired forms in table so that they get
+     overwritten in the lookup table.  The disassembler will thus
+     print the `proper' mnemonics.  Note that the disassembler
+     only decodes the 11 MSBs, so instructions like ldp @0x500 will
+     be printed as ldiu 5, dp.  Note that with parallel instructions,
+     the second part is executed before the first part, unless
+     the sti1||sti2 form is used.  We also allow sti2||sti1
+     which is equivalent to the default sti||sti form.
+  */
+  B_CLASS_INSN(  "absf",          0x00000000, OP_C3X   ),
+  P_CLASS_INSN(  "absf",  "stf",  0xc8000000, OP_C3X   ),
+  A_CLASS_INSN(  "absi",          0x00800000, OP_C3X   ),
+  P_CLASS_INSN(  "absi",  "sti",  0xca000000, OP_C3X   ),
+  A_CLASS_INSN(  "addc",          0x01000000, OP_C3X   ),
+  TC_CLASS_INSN( "addc",          0x00000000, OP_C3X   ),
+  B_CLASS_INSN(  "addf",          0x01800000, OP_C3X   ),
+  SC_CLASS_INSN( "addf",          0x00800000, OP_C3X   ),
+  QC_CLASS_INSN( "addf",  "stf",  0xcc000000, OP_C3X   ),
+  A_CLASS_INSN(  "addi",          0x02000000, OP_C3X   ),
+  TC_CLASS_INSN( "addi",          0x01000000, OP_C3X   ),
+  QC_CLASS_INSN( "addi",  "sti",  0xce000000, OP_C3X   ),
+  AU_CLASS_INSN( "and",           0x02800000, OP_C3X   ),
+  TC_CLASS_INSN( "and",           0x01800000, OP_C3X   ),
+  QC_CLASS_INSN( "and",   "sti",  0xd0000000, OP_C3X   ),
+  AU_CLASS_INSN( "andn",          0x03000000, OP_C3X   ),
+  T_CLASS_INSN(  "andn",          0x02000000, OP_C3X   ),
+  A_CLASS_INSN(  "ash",           0x03800000, OP_C3X   ),
+  T_CLASS_INSN(  "ash",           0x02800000, OP_C3X   ),
+  Q_CLASS_INSN(  "ash",   "sti",  0xd2000000, OP_C3X   ),
+  J_CLASS_INSN(  "bB",    "b",    0x68000000, OP_C3X   ),
+  J_CLASS_INSN(  "bBd",   "bd",   0x68200000, OP_C3X   ),
+  J_CLASS_INSN(  "bBaf",  "baf",  0x68a00000, OP_C4X   ),
+  J_CLASS_INSN(  "bBat",  "bat",  0x68600000, OP_C4X   ),
+  { "br",     0x60000000, 0xff000000, "B"   , OP_C3X   },  /* I_CLASS */
+  { "brd",    0x61000000, 0xff000000, "B"   , OP_C3X   },  /* I_CLASS */
+  { "call",   0x62000000, 0xff000000, "B"   , OP_C3X   },  /* I_CLASS */
+  { "callB",  0x70000000, 0xffe00000, "Q"   , OP_C3X   },  /* JS_CLASS */
+  { "callB",  0x72000000, 0xffe00000, "P"   , OP_C3X   },  /* JS_CLASS */
+  B_CLASS_INSN(  "cmpf",          0x04000000, OP_C3X   ),
+  S2_CLASS_INSN( "cmpf",          0x03000000, OP_C3X   ),
+  A_CLASS_INSN(  "cmpi",          0x04800000, OP_C3X   ),
+  T2_CLASS_INSN( "cmpi",          0x03800000, OP_C3X   ),
+  D_CLASS_INSN(  "dbB",   "db",   0x6c000000, OP_C3X   ),
+  D_CLASS_INSN(  "dbBd",  "dbd",  0x6c200000, OP_C3X   ),
+  AF_CLASS_INSN( "fix",           0x05000000, OP_C3X   ),
+  P_CLASS_INSN(  "fix",   "sti",  0xd4000000, OP_C3X   ),
+  BI_CLASS_INSN( "float",         0x05800000, OP_C3X   ),
+  P_CLASS_INSN(  "float", "stf",  0xd6000000, OP_C3X   ),
+  B6_CLASS_INSN( "frieee",        0x1c000000, OP_C4X   ),
+  P_CLASS_INSN(  "frieee","stf",  0xf2000000, OP_C4X   ),
+  { "iack",   0x1b200000, 0xffe00000, "@"   , OP_C3X   },  /* Z_CLASS */
+  { "iack",   0x1b400000, 0xffe00000, "*"   , OP_C3X   },  /* Z_CLASS */
+  { "idle",   0x06000000, 0xffffffff, ""    , OP_C3X   },  /* Z_CLASS */
+  { "idlez",  0x06000000, 0xffffffff, ""    , OP_C3X   },  /* Z_CLASS */
+  { "idle2",  0x06000001, 0xffffffff, ""    , OP_IDLE2 },  /* Z_CLASS */
+  { "laj",    0x63000000, 0xff000000, "B"   , OP_C4X   },  /* I_CLASS */
+  { "lajB",   0x70200000, 0xffe00000, "Q"   , OP_C4X   },  /* JS_CLASS */
+  { "lajB",   0x72200000, 0xffe00000, "P"   , OP_C4X   },  /* JS_CLASS */
+  { "latB",   0x74800000, 0xffe00000, "V"   , OP_C4X   },  /* Z_CLASS */
+  A_CLASS_INSN(  "lb0",           0xb0000000, OP_C4X   ),
+  A_CLASS_INSN(  "lb1",           0xb0800000, OP_C4X   ),
+  A_CLASS_INSN(  "lb2",           0xb1000000, OP_C4X   ),
+  A_CLASS_INSN(  "lb3",           0xb1800000, OP_C4X   ),
+  AU_CLASS_INSN( "lbu0",          0xb2000000, OP_C4X   ),
+  AU_CLASS_INSN( "lbu1",          0xb2800000, OP_C4X   ),
+  AU_CLASS_INSN( "lbu2",          0xb3000000, OP_C4X   ),
+  AU_CLASS_INSN( "lbu3",          0xb3800000, OP_C4X   ),
+  AY_CLASS_INSN( "lda",           0x1e800000, OP_C4X   ),
+  B_CLASS_INSN(  "lde",           0x06800000, OP_C3X   ),
+  { "ldep",   0x76000000, 0xffe00000, "X,R" , OP_C4X   },  /* Z_CLASS */
+  B_CLASS_INSN(  "ldf",           0x07000000, OP_C3X   ),
+  LL_CLASS_INSN( "ldf",           0xc4000000, OP_C3X   ),
+  P_CLASS_INSN(  "ldf",   "stf",  0xd8000000, OP_C3X   ),
+  BB_CLASS_INSN( "ldfC",          0x00000000, OP_C3X   ),
+  B6_CLASS_INSN( "ldfi",          0x07800000, OP_C3X   ),
+  { "ldhi",   0x1fe00000, 0xffe00000, "U,R" , OP_C4X   },  /* Z_CLASS */
+  { "ldhi",   0x1fe00000, 0xffe00000, "#,R" , OP_C4X   },  /* Z_CLASS */
+  A_CLASS_INSN(  "ldi",           0x08000000, OP_C3X   ),
+  LL_CLASS_INSN( "ldi",           0xc6000000, OP_C3X   ),
+  P_CLASS_INSN(  "ldi",   "sti",  0xda000000, OP_C3X   ),
+  AB_CLASS_INSN( "ldiC",          0x10000000, OP_C3X   ),
+  A6_CLASS_INSN( "ldii",          0x08800000, OP_C3X   ),
+  { "ldp",    0x50700000, 0xffff0000, "#"   , OP_C3X   },  /* Z_CLASS - synonym for ldiu #,dp */
+  B_CLASS_INSN(  "ldm",           0x09000000, OP_C3X   ),
+  { "ldpe",   0x76800000, 0xffe00000, "Q,Z" , OP_C4X   },  /* Z_CLASS */
+  { "ldpk",   0x1F700000, 0xffff0000, "#"   , OP_C4X   },  /* Z_CLASS */
+  A_CLASS_INSN(  "lh0",           0xba000000, OP_C4X   ),
+  A_CLASS_INSN(  "lh1",           0xba800000, OP_C4X   ),
+  AU_CLASS_INSN( "lhu0",          0xbb000000, OP_C4X   ),
+  AU_CLASS_INSN( "lhu1",          0xbb800000, OP_C4X   ),
+  { "lopower", 0x10800001,0xffffffff, ""    , OP_LPWR  },  /* Z_CLASS */
+  A_CLASS_INSN(  "lsh",           0x09800000, OP_C3X   ),
+  T_CLASS_INSN(  "lsh",           0x04000000, OP_C3X   ),
+  Q_CLASS_INSN(  "lsh",   "sti",  0xdc000000, OP_C3X   ),
+  A_CLASS_INSN(  "lwl0",          0xb4000000, OP_C4X   ),
+  A_CLASS_INSN(  "lwl1",          0xb4800000, OP_C4X   ),
+  A_CLASS_INSN(  "lwl2",          0xb5000000, OP_C4X   ),
+  A_CLASS_INSN(  "lwl3",          0xb5800000, OP_C4X   ),
+  A_CLASS_INSN(  "lwr0",          0xb6000000, OP_C4X   ),
+  A_CLASS_INSN(  "lwr1",          0xb6800000, OP_C4X   ),
+  A_CLASS_INSN(  "lwr2",          0xb7000000, OP_C4X   ),
+  A_CLASS_INSN(  "lwr3",          0xb7800000, OP_C4X   ),
+  { "maxspeed",0x10800000,0xffffffff, ""    , OP_LPWR  },  /* Z_CLASS */
+  A_CLASS_INSN(  "mb0",           0xb8000000, OP_C4X   ),
+  A_CLASS_INSN(  "mb1",           0xb8800000, OP_C4X   ),
+  A_CLASS_INSN(  "mb2",           0xb9000000, OP_C4X   ),
+  A_CLASS_INSN(  "mb3",           0xb9800000, OP_C4X   ),
+  A_CLASS_INSN(  "mh0",           0xbc000000, OP_C4X   ),
+  A_CLASS_INSN(  "mh1",           0xbc800000, OP_C4X   ),
+  A_CLASS_INSN(  "mh2",           0xbd000000, OP_C4X   ),
+  A_CLASS_INSN(  "mh3",           0xbd800000, OP_C4X   ),
+  B_CLASS_INSN(  "mpyf",          0x0a000000, OP_C3X   ),
+  SC_CLASS_INSN( "mpyf",          0x04800000, OP_C3X   ),
+  M_CLASS_INSN(  "mpyf",  "addf", 0x80000000, OP_C3X   ),
+  QC_CLASS_INSN( "mpyf",  "stf",  0xde000000, OP_C3X   ),
+  M_CLASS_INSN(  "mpyf",  "subf", 0x84000000, OP_C3X   ),
+  A_CLASS_INSN(  "mpyi",          0x0a800000, OP_C3X   ),
+  TC_CLASS_INSN( "mpyi",          0x05000000, OP_C3X   ),
+  M_CLASS_INSN(  "mpyi",  "addi", 0x88000000, OP_C3X   ),
+  QC_CLASS_INSN( "mpyi",  "sti",  0xe0000000, OP_C3X   ),
+  M_CLASS_INSN(  "mpyi",  "subi", 0x8c000000, OP_C3X   ),
+  A_CLASS_INSN(  "mpyshi",        0x1d800000, OP_C4X   ),
+  TC_CLASS_INSN( "mpyshi",        0x28800000, OP_C4X   ),
+  A_CLASS_INSN(  "mpyuhi",        0x1e000000, OP_C4X   ),
+  TC_CLASS_INSN( "mpyuhi",        0x29000000, OP_C4X   ),
+  A_CLASS_INSN(  "negb",          0x0b000000, OP_C3X   ),
+  B_CLASS_INSN(  "negf",          0x0b800000, OP_C3X   ),
+  P_CLASS_INSN(  "negf",  "stf",  0xe2000000, OP_C3X   ),
+  A_CLASS_INSN(  "negi",          0x0c000000, OP_C3X   ),
+  P_CLASS_INSN(  "negi",  "sti",  0xe4000000, OP_C3X   ),
+  A2_CLASS_INSN( "nop",           0x0c800000, OP_C3X   ),
+  B_CLASS_INSN(  "norm",          0x0d000000, OP_C3X   ),
+  AU_CLASS_INSN( "not",           0x0d800000, OP_C3X   ),
+  P_CLASS_INSN(  "not",   "sti",  0xe6000000, OP_C3X   ),
+  AU_CLASS_INSN( "or",            0x10000000, OP_C3X   ),
+  TC_CLASS_INSN( "or",            0x05800000, OP_C3X   ),
+  QC_CLASS_INSN( "or",    "sti",  0xe8000000, OP_C3X   ),
+  R_CLASS_INSN(  "pop",           0x0e200000, OP_C3X   ),
+  RF_CLASS_INSN( "popf",          0x0ea00000, OP_C3X   ),
+  R_CLASS_INSN(  "push",          0x0f200000, OP_C3X   ),
+  RF_CLASS_INSN( "pushf",         0x0fa00000, OP_C3X   ),
+  BA_CLASS_INSN( "rcpf",          0x1d000000, OP_C4X   ),
+  { "retiB",  0x78000000, 0xffe00000, ""    , OP_C3X   },  /* Z_CLASS */
+  { "reti",   0x78000000, 0xffe00000, ""    , OP_C3X   },  /* Z_CLASS  - Alias for retiu */
+  { "retiBd", 0x78200000, 0xffe00000, ""    , OP_C4X   },  /* Z_CLASS */
+  { "retid",  0x78200000, 0xffe00000, ""    , OP_C4X   },  /* Z_CLASS - Alias for retiud */
+  { "retsB",  0x78800000, 0xffe00000, ""    , OP_C3X   },  /* Z_CLASS */
+  { "rets",   0x78800000, 0xffe00000, ""    , OP_C3X   },  /* Z_CLASS  - Alias for retsu */
+  B_CLASS_INSN(  "rnd",           0x11000000, OP_C3X   ),
+  R_CLASS_INSN(  "rol",           0x11e00001, OP_C3X   ),
+  R_CLASS_INSN(  "rolc",          0x12600001, OP_C3X   ),
+  R_CLASS_INSN(  "ror",           0x12e0ffff, OP_C3X   ),
+  R_CLASS_INSN(  "rorc",          0x1360ffff, OP_C3X   ),
+  { "rptb",   0x64000000, 0xff000000, "B"   , OP_C3X   },  /* I2_CLASS */
+  { "rptb",   0x79000000, 0xff000000, "Q"   , OP_C4X   },  /* I2_CLASS */
+  { "rptbd",  0x65000000, 0xff000000, "B"   , OP_C4X   },  /* I2_CLASS */ 
+  { "rptbd",  0x79800000, 0xff000000, "Q"   , OP_C4X   },  /* I2_CLASS */
+  A3_CLASS_INSN( "rpts",          0x139b0000, OP_C3X   ),
+  B_CLASS_INSN(  "rsqrf",         0x1c800000, OP_C4X   ),
+  { "sigi",   0x16000000, 0xffe00000, ""    , OP_C3X   },  /* Z_CLASS */
+  A6_CLASS_INSN( "sigi",          0x16000000, OP_C4X   ),
+  B7_CLASS_INSN( "stf",           0x14000000, OP_C3X   ),
+  LS_CLASS_INSN( "stf",           0xc0000000, OP_C3X   ),
+  B7_CLASS_INSN( "stfi",          0x14800000, OP_C3X   ),
+  A7_CLASS_INSN( "sti",           0x15000000, OP_C3X   ),
+  { "sti",    0x15000000, 0xffe00000, "T,@" , OP_C4X   },  /* Class A7 - Alias for stik */
+  { "sti",    0x15600000, 0xffe00000, "T,*" , OP_C4X   },  /* Class A7 */
+  LS_CLASS_INSN( "sti",           0xc2000000, OP_C3X   ),
+  A7_CLASS_INSN( "stii",          0x15800000, OP_C3X   ),
+  { "stik",   0x15000000, 0xffe00000, "T,@" , OP_C4X   },  /* Z_CLASS */
+  { "stik",   0x15600000, 0xffe00000, "T,*" , OP_C4X   },  /* Z_CLASS */
+  A_CLASS_INSN(  "subb",          0x16800000, OP_C3X   ),
+  T_CLASS_INSN(  "subb",          0x06000000, OP_C3X   ),
+  A_CLASS_INSN(  "subc",          0x17000000, OP_C3X   ),
+  B_CLASS_INSN(  "subf",          0x17800000, OP_C3X   ),
+  S_CLASS_INSN(  "subf",          0x06800000, OP_C3X   ),
+  Q_CLASS_INSN(  "subf",  "stf",  0xea000000, OP_C3X   ),
+  A_CLASS_INSN(  "subi",          0x18000000, OP_C3X   ),
+  T_CLASS_INSN(  "subi",          0x07000000, OP_C3X   ),
+  Q_CLASS_INSN(  "subi",  "sti",  0xec000000, OP_C3X   ),
+  A_CLASS_INSN(  "subrb",         0x18800000, OP_C3X   ),
+  B_CLASS_INSN(  "subrf",         0x19000000, OP_C3X   ),
+  A_CLASS_INSN(  "subri",         0x19800000, OP_C3X   ),
+  { "swi",    0x66000000, 0xffffffff, ""    , OP_C3X   },  /* Z_CLASS */
+  B_CLASS_INSN(  "toieee",        0x1b800000, OP_C4X   ),
+  P_CLASS_INSN(  "toieee","stf",  0xf0000000, OP_C4X   ),
+  { "trapB",  0x74000000, 0xffe00000, "V"   , OP_C3X   },  /* Z_CLASS */
+  { "trap",   0x74000000, 0xffe00000, "V"   , OP_C3X   },  /* Z_CLASS - Alias for trapu */
+  AU_CLASS_INSN( "tstb",          0x1a000000, OP_C3X   ),
+  T2C_CLASS_INSN("tstb",          0x07800000, OP_C3X   ),
+  AU_CLASS_INSN( "xor",           0x1a800000, OP_C3X   ),
+  TC_CLASS_INSN( "xor",           0x08000000, OP_C3X   ),
+  QC_CLASS_INSN( "xor",   "sti",  0xee000000, OP_C3X   ),
+
+  /* Dummy entry, not included in c3x_num_insts.  This
+     lets code examine entry i + 1 without checking
+     if we've run off the end of the table.  */
+  { "",      0x0, 0x00, "", 0 }
+};
+
+const unsigned int c4x_num_insts = (((sizeof c4x_insts) / (sizeof c4x_insts[0])) - 1);