2003-06-27 David Carlton <carlton@kealia.com>

	* Merge with mainline; tag is carlton_dictionary-20030627-merge.

15 files changed, 2280 insertions, 677 deletions

diff --git a/include/ChangeLog b/include/ChangeLog
index 8dfa46f77c9..f061efa770f 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,37 @@
+2003-06-25  Alan Modra  <amodra@bigpond.net.au>
+
+	* bfdlink.h: Correct spelling of "relocatable".
+
+2003-06-22  Zack Weinberg  <zack@codesourcery.com>
+
+	* safe-ctype.h (HC_UNKNOWN, HC_ASCII, HC_EBCDIC): Rename to
+	HOST_CHARSET_UNKNOWN, HOST_CHARSET_ASCII, HOST_CHARSET_EBCDIC
+	respectively.
+
+2003-06-21  Zack Weinberg  <zack@codesourcery.com>
+
+	* safe-ctype.h (HC_UNKNOWN, HC_ASCII, HC_EBCDIC, HOST_CHARSET):
+	New #defines.
+
+2003-06-17  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* ansidecl.h: Delete HAVE_LONG_DOUBLE GCC bootstrap support.
+
+2003-05-23  Jakub Jelinek  <jakub@redhat.com>
+
+	* bfdlink.h (struct bfd_link_info): Add execstack and noexecstack.
+	* elf/common.h (PT_GNU_STACK): Define.
+
+2003-06-03  H.J. Lu <hongjiu.lu@intel.com>
+
+	* bfdlink.h (LD_DEFINITION_IN_DISCARDED_SECTION): New.
+
+2003-05-30  Ulrich Drepper  <drepper@redhat.com>
+	    Jakub Jelinek  <jakub@redhat.com>
+
+	* bfdlink.h (struct bfd_link_info): Add pie and executable
+	bits.
+
 2003-05-21  Nick Clifton  <nickc@redhat.com>
 
 	* bfdlink.h (struct bfd_link_hash_table): Fix typo in comment.
diff --git a/include/ansidecl.h b/include/ansidecl.h
index f8f2d737bf0..d2c87768ce2 100644
--- a/include/ansidecl.h
+++ b/include/ansidecl.h
@@ -312,15 +312,4 @@ So instead we use the macro below and test it against specific values.  */
 #define __extension__
 #endif
 
-/* Bootstrap support:  Adjust certain macros defined by Autoconf,
-   which are only valid for the stage1 compiler.  If we detect
-   a modern version of GCC, we are probably in stage2 or beyond,
-   so unconditionally reset the values.  Note that const, inline,
-   etc. have been dealt with above.  */
-#if (GCC_VERSION >= 2007)
-# ifndef HAVE_LONG_DOUBLE
-#  define HAVE_LONG_DOUBLE 1
-# endif
-#endif /* GCC >= 2.7 */
-
 #endif	/* ansidecl.h	*/
diff --git a/include/bfdlink.h b/include/bfdlink.h
index 89d916ee83b..10746ee98e0 100644
--- a/include/bfdlink.h
+++ b/include/bfdlink.h
@@ -1,5 +1,5 @@
 /* bfdlink.h -- header file for BFD link routines
-   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2002
+   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2002, 2003
    Free Software Foundation, Inc.
    Written by Steve Chamberlain and Ian Lance Taylor, Cygnus Support.
 
@@ -204,7 +204,7 @@ struct bfd_sym_chain
 struct bfd_link_info
 {
   /* TRUE if BFD should generate a relocatable object file.  */
-  unsigned int relocateable: 1;
+  unsigned int relocatable: 1;
 
   /* TRUE if BFD should generate relocation information in the final
      executable.  */
@@ -291,6 +291,20 @@ struct bfd_link_info
   /* TRUE if relaxation is being finalized.  */
   unsigned int relax_finalizing: 1;
 
+  /* TRUE if generating a position independent executable.  */
+  unsigned int pie: 1;
+
+  /* TRUE if generating an executable, position independent or not.  */
+  unsigned int executable : 1;
+
+  /* TRUE if PT_GNU_STACK segment should be created with PF_R|PF_W|PF_X
+     flags.  */
+  unsigned int execstack: 1;
+
+  /* TRUE if PT_GNU_STACK segment should be created with PF_R|PF_W
+     flags.  */
+  unsigned int noexecstack: 1;
+
   /* Which symbols to strip.  */
   enum bfd_link_strip strip;
 
@@ -414,7 +428,7 @@ struct bfd_link_callbacks
   /* A function which is called to add a symbol to a set.  ENTRY is
      the link hash table entry for the set itself (e.g.,
      __CTOR_LIST__).  RELOC is the relocation to use for an entry in
-     the set when generating a relocateable file, and is also used to
+     the set when generating a relocatable file, and is also used to
      get the size of the entry when generating an executable file.
      ABFD, SEC and VALUE identify the value to add to the set.  */
   bfd_boolean (*add_to_set)
@@ -425,7 +439,7 @@ struct bfd_link_callbacks
      destructor is found.  This is only called by some object file
      formats.  CONSTRUCTOR is TRUE for a constructor, FALSE for a
      destructor.  This will use BFD_RELOC_CTOR when generating a
-     relocateable file.  NAME is the name of the symbol found.  ABFD,
+     relocatable file.  NAME is the name of the symbol found.  ABFD,
      SECTION and VALUE are the value of the symbol.  */
   bfd_boolean (*constructor)
     PARAMS ((struct bfd_link_info *, bfd_boolean constructor,
@@ -489,6 +503,9 @@ struct bfd_link_callbacks
      ld.  */
   bfd_boolean (*error_handler)
     PARAMS ((int id, const char * fmt, ...));
+
+/* Identifiers of linker error messages used by error_handler.  */
+#define LD_DEFINITION_IN_DISCARDED_SECTION	1
 };
 
 /* The linker builds link_order structures which tell the code how to
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index 59e05e318ad..eb4b7ccb55e 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,17 @@
+2003-06-13  Robert Millan <zeratul2@wanadoo.es>
+
+	* common.h (GNU_ABI_TAG_NETBSD): New tag.
+	(GNU_ABI_TAG_FREEBSD): New tag.
+
+2003-06-10  Richard Sandiford  <rsandifo@redhat.com>
+
+	* h8.h (E_H8_MACH_H8300SXN): New flag.
+
+2003-06-03  Nick Clifton  <nickc@redhat.com>
+
+	* v850.h (R_V850_32): Rename to R_V850_ABS32.
+        Add R_V850_REL32.
+
 2003-05-15  Roland McGrath  <roland@redhat.com>
 
 	* common.h (NT_AUXV, AT_*): New macros.
diff --git a/include/elf/common.h b/include/elf/common.h
index f342d573710..1a843393d85 100644
--- a/include/elf/common.h
+++ b/include/elf/common.h
@@ -288,6 +288,7 @@
 #define PT_HIPROC	0x7FFFFFFF	/* Processor-specific */
 
 #define PT_GNU_EH_FRAME	(PT_LOOS + 0x474e550)
+#define PT_GNU_STACK	(PT_LOOS + 0x474e551)
 
 /* Program segment permissions, in program header p_flags field.  */
 
@@ -396,6 +397,8 @@
 #define GNU_ABI_TAG_LINUX	0
 #define GNU_ABI_TAG_HURD	1
 #define GNU_ABI_TAG_SOLARIS	2
+#define GNU_ABI_TAG_FREEBSD	3
+#define GNU_ABI_TAG_NETBSD	4
 
 /* Values for NetBSD .note.netbsd.ident notes.  Note name is "NetBSD".  */
 
diff --git a/include/elf/h8.h b/include/elf/h8.h
index 79c0a34fb32..1aad7a4ed5b 100644
--- a/include/elf/h8.h
+++ b/include/elf/h8.h
@@ -95,5 +95,6 @@ END_RELOC_NUMBERS (R_H8_max)
 #define E_H8_MACH_H8300HN	0x00830000
 #define E_H8_MACH_H8300SN	0x00840000
 #define E_H8_MACH_H8300SX	0x00850000
+#define E_H8_MACH_H8300SXN	0x00860000
 
 #endif
diff --git a/include/elf/v850.h b/include/elf/v850.h
index a15c9ee0864..c949ab01f8c 100644
--- a/include/elf/v850.h
+++ b/include/elf/v850.h
@@ -53,7 +53,7 @@ START_RELOC_NUMBERS (v850_reloc_type)
      RELOC_NUMBER (R_V850_HI16_S, 3)
      RELOC_NUMBER (R_V850_HI16, 4)
      RELOC_NUMBER (R_V850_LO16, 5)
-     RELOC_NUMBER (R_V850_32, 6)
+     RELOC_NUMBER (R_V850_ABS32, 6)
      RELOC_NUMBER (R_V850_16, 7)
      RELOC_NUMBER (R_V850_8, 8)
      RELOC_NUMBER( R_V850_SDA_16_16_OFFSET, 9)		/* For ld.b, st.b, set1, clr1, not1, tst1, movea, movhi */
@@ -75,6 +75,7 @@ START_RELOC_NUMBERS (v850_reloc_type)
      RELOC_NUMBER (R_V850_LONGCALL, 25)
      RELOC_NUMBER (R_V850_LONGJUMP, 26)
      RELOC_NUMBER (R_V850_ALIGN, 27)
+     RELOC_NUMBER (R_V850_REL32, 28)
 END_RELOC_NUMBERS (R_V850_max)
 
 
diff --git a/include/gdb/ChangeLog b/include/gdb/ChangeLog
index 77a8551a460..79c817871ec 100644
--- a/include/gdb/ChangeLog
+++ b/include/gdb/ChangeLog
@@ -1,3 +1,7 @@
+2003-06-10  Corinna Vinschen  <vinschen@redhat.com>
+
+	* gdb/fileio.h: New file.
+
 2003-05-07  Andrew Cagney  <cagney@redhat.com>
 
 	* sim-d10v.h (sim_d10v_translate_addr): Add regcache parameter.
diff --git a/include/gdb/fileio.h b/include/gdb/fileio.h
new file mode 100644
index 00000000000..d84478103e2
--- /dev/null
+++ b/include/gdb/fileio.h
@@ -0,0 +1,146 @@
+/* Hosted File I/O interface definitions, for GDB, the GNU Debugger.
+
+   Copyright 2003 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or
+   modify it under the terms of the GNU General Public License as
+   published by the Free Software Foundation; either version 2 of the
+   License, or (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
+   02111-1307, USA.  */
+
+#ifndef GDB_FILEIO_H_
+#define GDB_FILEIO_H_
+
+/* The following flags are defined to be independent of the host
+   as well as the target side implementation of these constants.
+   All constants are defined with a leading FILEIO_ in the name
+   to allow the usage of these constants together with the
+   corresponding implementation dependent constants in one module. */
+
+/* open(2) flags */
+#define FILEIO_O_RDONLY           0x0
+#define FILEIO_O_WRONLY           0x1
+#define FILEIO_O_RDWR             0x2
+#define FILEIO_O_APPEND           0x8
+#define FILEIO_O_CREAT          0x200
+#define FILEIO_O_TRUNC          0x400
+#define FILEIO_O_EXCL           0x800
+#define FILEIO_O_SUPPORTED	(FILEIO_O_RDONLY | FILEIO_O_WRONLY| \
+				 FILEIO_O_RDWR   | FILEIO_O_APPEND| \
+				 FILEIO_O_CREAT  | FILEIO_O_TRUNC| \
+				 FILEIO_O_EXCL)
+
+/* mode_t bits */
+#define FILEIO_S_IFREG        0100000
+#define FILEIO_S_IFDIR         040000
+#define FILEIO_S_IFCHR         020000
+#define FILEIO_S_IRUSR           0400
+#define FILEIO_S_IWUSR           0200
+#define FILEIO_S_IXUSR           0100
+#define FILEIO_S_IRWXU           0700
+#define FILEIO_S_IRGRP            040
+#define FILEIO_S_IWGRP            020
+#define FILEIO_S_IXGRP            010
+#define FILEIO_S_IRWXG            070
+#define FILEIO_S_IROTH             04
+#define FILEIO_S_IWOTH             02
+#define FILEIO_S_IXOTH             01
+#define FILEIO_S_IRWXO             07
+#define FILEIO_S_SUPPORTED         (FILEIO_S_IFREG|FILEIO_S_IFDIR|  \
+				    FILEIO_S_IRWXU|FILEIO_S_IRWXG|  \
+                                    FILEIO_S_IRWXO)
+
+/* lseek(2) flags */
+#define FILEIO_SEEK_SET             0
+#define FILEIO_SEEK_CUR             1
+#define FILEIO_SEEK_END             2
+
+/* errno values */
+#define FILEIO_EPERM                1
+#define FILEIO_ENOENT               2
+#define FILEIO_EINTR                4
+#define FILEIO_EIO                  5
+#define FILEIO_EBADF                9
+#define FILEIO_EACCES              13
+#define FILEIO_EFAULT              14
+#define FILEIO_EBUSY               16
+#define FILEIO_EEXIST              17
+#define FILEIO_ENODEV              19
+#define FILEIO_ENOTDIR             20
+#define FILEIO_EISDIR              21
+#define FILEIO_EINVAL              22
+#define FILEIO_ENFILE              23
+#define FILEIO_EMFILE              24
+#define FILEIO_EFBIG               27
+#define FILEIO_ENOSPC              28
+#define FILEIO_ESPIPE              29
+#define FILEIO_EROFS               30
+#define FILEIO_ENOSYS		   88
+#define FILEIO_ENAMETOOLONG        91
+#define FILEIO_EUNKNOWN          9999
+
+/* limits */
+#define FILEIO_INT_MIN    -2147483648L
+#define FILEIO_INT_MAX     2147483647L
+#define FILEIO_UINT_MAX    4294967295UL
+#define FILEIO_LONG_MIN   -9223372036854775808LL
+#define FILEIO_LONG_MAX    9223372036854775807LL
+#define FILEIO_ULONG_MAX   18446744073709551615ULL
+
+/* Integral types as used in protocol. */
+#if 0
+typedef __int32_t fio_int_t;
+typedef __uint32_t fio_uint_t, fio_mode_t, fio_time_t;
+typedef __int64_t fio_long_t;
+typedef __uint64_t fio_ulong_t;
+#endif
+
+#define FIO_INT_LEN   4
+#define FIO_UINT_LEN  4
+#define FIO_MODE_LEN  4
+#define FIO_TIME_LEN  4
+#define FIO_LONG_LEN  8
+#define FIO_ULONG_LEN 8
+
+typedef char fio_int_t[FIO_INT_LEN];   
+typedef char fio_uint_t[FIO_UINT_LEN];
+typedef char fio_mode_t[FIO_MODE_LEN];
+typedef char fio_time_t[FIO_TIME_LEN];
+typedef char fio_long_t[FIO_LONG_LEN];
+typedef char fio_ulong_t[FIO_ULONG_LEN];
+
+/* Struct stat as used in protocol.  For complete independence
+   of host/target systems, it's defined as an array with offsets
+   to the members. */
+
+struct fio_stat {
+  fio_uint_t  fst_dev;
+  fio_uint_t  fst_ino;
+  fio_mode_t  fst_mode;
+  fio_uint_t  fst_nlink;
+  fio_uint_t  fst_uid;
+  fio_uint_t  fst_gid;
+  fio_uint_t  fst_rdev;
+  fio_ulong_t fst_size;
+  fio_ulong_t fst_blksize;
+  fio_ulong_t fst_blocks;
+  fio_time_t  fst_atime;
+  fio_time_t  fst_mtime;
+  fio_time_t  fst_ctime;
+};
+
+struct fio_timeval {
+  fio_time_t  ftv_sec;
+  fio_long_t  ftv_usec;
+};
+
+#endif /* GDB_FILEIO_H_ */
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 48004d0b674..e100c119316 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,11 +1,65 @@
+2003-06-25  Richard Sandiford  <rsandifo@redhat.com>
+
+	* h8300.h (IMM2_NS, IMM8_NS, IMM16_NS): Remove.
+	(IMM8U, IMM8U_NS): Define.
+	(h8_opcodes): Use IMM8U_NS for mov.[wl] #xx:8,@yy.
+
+2003-06-25  Richard Sandiford  <rsandifo@redhat.com>
+
+	* h8300.h (h8_opcodes): Fix the mov.l @(dd:32,ERs),ERd and
+	mov.l ERs,@(dd:32,ERd) entries.
+
+2003-06-23  H.J. Lu <hongjiu.lu@intel.com>
+
+	* i386.h (i386_optab): Support Intel Precott New Instructions.
+
+2003-06-10  Gary Hade <garyhade@us.ibm.com>
+
+	* ppc.h (PPC_OPERAND_DQ): Define.
+
+2003-06-10  Richard Sandiford  <rsandifo@redhat.com>
+
+	* h8300.h (IMM4_NS, IMM8_NS): New.
+	(h8_opcodes): Replace IMM4 with IMM4_NS in mov.b and mov.w entries.
+	Likewise IMM8 for mov.w and mov.l.  Likewise IMM16U for mov.l.
+
+2003-06-03  Michael Snyder  <msnyder@redhat.com>
+
+	* h8300.h (enum h8_model): Add AV_H8S to distinguish from H8H.
+	(ldc): Split ccr ops from exr ops (which are only available
+	on H8S or H8SX).
+	(stc): Ditto.
+	(andc, orc, xorc): Ditto.
+	(ldmac, stmac, clrmac, mac): Change access to AV_H8S.
+
+2003-06-03  Michael Snyder  <msnyder@redhat.com>
+	and Bernd Schmidt   <bernds@redhat.com>
+	and Alexandre Oliva <aoliva@redhat.com>
+	* h8300.h: Add support for h8300sx instruction set.
+
+2003-05-23  Jason Eckhardt  <jle@rice.edu>
+
+	* i860.h (expand_type): Add XP_ONLY.
+	(scyc.b): New XP instruction.
+	(ldio.l): Likewise.
+	(ldio.s): Likewise.
+	(ldio.b): Likewise.
+	(ldint.l): Likewise.
+	(ldint.s): Likewise.
+	(ldint.b): Likewise.
+	(stio.l): Likewise.
+	(stio.s): Likewise.
+	(stio.b): Likewise.
+	(pfld.q): Likewise.
+
 2003-05-20  Jason Eckhardt  <jle@rice.edu>
 
-	opcode/i860.h (flush): Set lower 3 bits properly and use 'L'
+	* i860.h (flush): Set lower 3 bits properly and use 'L'
 	for the immediate operand type instead of 'i'.
 
 2003-05-20  Jason Eckhardt  <jle@rice.edu>
 
-	opcode/i860.h (fzchks): Both S and R bits must be set.
+	* i860.h (fzchks): Both S and R bits must be set.
 	(pfzchks): Likewise.
 	(faddp): Likewise.
 	(pfaddp): Likewise.
@@ -125,7 +179,7 @@
 	fields.
 	(h8_opcodes). Modify initializer and initializer macros to no
 	longer initialize the removed fields.
-	
+
 2002-11-19  Svein E. Seldal  <Svein.Seldal@solidas.com>
 
 	* tic4x.h (c4x_insts): Fixed LDHI constraint
@@ -162,10 +216,10 @@
 	* cgen.h: Test __BFD_H_SEEN__ rather than BFD_VERSION_DATE.
 
 2002-09-30  Gavin Romig-Koch  <gavin@redhat.com>
-            Ken Raeburn  <raeburn@cygnus.com>
-            Aldy Hernandez  <aldyh@redhat.com>
-            Eric Christopher  <echristo@redhat.com>
-            Richard Sandiford  <rsandifo@redhat.com>
+	    Ken Raeburn  <raeburn@cygnus.com>
+	    Aldy Hernandez  <aldyh@redhat.com>
+	    Eric Christopher  <echristo@redhat.com>
+	    Richard Sandiford  <rsandifo@redhat.com>
 
 	* mips.h: Update comment for new opcodes.
 	(OP_MASK_VECBYTE, OP_SH_VECBYTE): New.
@@ -176,12 +230,12 @@
 	Don't match CPU_R4111 with INSN_4100.
 
 2002-08-19  Elena Zannoni <ezannoni@redhat.com>
- 
-        From matthew green  <mrg@redhat.com>
 
-        * ppc.h (PPC_OPCODE_SPE): New opcode flag for Powerpc e500
+	From matthew green  <mrg@redhat.com>
+
+	* ppc.h (PPC_OPCODE_SPE): New opcode flag for Powerpc e500
 	instructions.
-        (PPC_OPCODE_ISEL, PPC_OPCODE_BRLOCK, PPC_OPCODE_PMR,
+	(PPC_OPCODE_ISEL, PPC_OPCODE_BRLOCK, PPC_OPCODE_PMR,
 	PPC_OPCODE_CACHELCK, PPC_OPCODE_RFMCI): New opcode flags for the
 	e500x2 Integer select, branch locking, performance monitor,
 	cache locking and machine check APUs, respectively.
@@ -236,9 +290,9 @@
 
 2002-05-17  Andrey Volkov  <avolkov@sources.redhat.com>
 
-        * h8300.h: Corrected defs of all control regs 
+	* h8300.h: Corrected defs of all control regs
 	and eepmov instr.
-		      
+
 2002-04-11  Alan Modra  <amodra@bigpond.net.au>
 
 	* i386.h: Add intel mode cmpsd and movsd.
@@ -505,9 +559,9 @@ Mon Dec 31 16:45:41 2001  Jeffrey A Law  (law@cygnus.com)
 
 2001-02-02  Patrick Macdonald  <patrickm@redhat.com>
 
-        * cgen.h (CGEN_SYNTAX_CHAR_TYPE): Typedef as unsigned short.
-        (CGEN_MAX_SYNTAX_ELEMENTS): Rename from CGEN_MAX_SYNTAX_BYTES.
-        (CGEN_SYNTAX): Define using CGEN_MAX_SYNTAX_ELEMENTS.
+	* cgen.h (CGEN_SYNTAX_CHAR_TYPE): Typedef as unsigned short.
+	(CGEN_MAX_SYNTAX_ELEMENTS): Rename from CGEN_MAX_SYNTAX_BYTES.
+	(CGEN_SYNTAX): Define using CGEN_MAX_SYNTAX_ELEMENTS.
 
 2001-01-24  Karsten Keil  <kkeil@suse.de>
 
@@ -582,35 +636,35 @@ Mon Dec 31 16:45:41 2001  Jeffrey A Law  (law@cygnus.com)
 
 2000-12-01  Chris Demetriou  <cgd@sibyte.com>
 
-        mips.h (OP_MASK_SYSCALL, OP_SH_SYSCALL): Delete.
-        (OP_MASK_CODE20, OP_SH_CODE20): Define, with values of old
-        OP_*_SYSCALL definitions.
-        (OP_SH_CODE19, OP_MASK_CODE19): Define, for use as
-        19 bit wait codes.
-        (MIPS operand specifier comments): Remove 'm', add 'U' and
-        'J', and update the meaning of 'B' so that it's more general.
-
-        * mips.h (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4,
-        INSN_ISA5): Renumber, redefine to mean the ISA at which the
-        instruction was added.
-        (INSN_ISA32): New constant.
-        (INSN_4650, INSN_4010, INSN_4100, INSN_3900, INSN_GP32):
-        Renumber to avoid new and/or renumbered INSN_* constants.
-        (INSN_MIPS32): Delete.
-        (ISA_UNKNOWN): New constant to indicate unknown ISA.
-        (ISA_MIPS1, ISA_MIPS2, ISA_MIPS3, ISA_MIPS4, ISA_MIPS5,
-        ISA_MIPS32): New constants, defined to be the mask of INSN_*
-        constants available at that ISA level.
-        (CPU_UNKNOWN): New constant to indicate unknown CPU.
-        (CPU_4K, CPU_MIPS32_4K): Rename the former to the latter,
-        define it with a unique value.
-        (OPCODE_IS_MEMBER): Update for new ISA membership-related
-        constant meanings.
-
-        * mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New
-        definitions.
-
-        * mips.h (CPU_SB1): New constant.
+	mips.h (OP_MASK_SYSCALL, OP_SH_SYSCALL): Delete.
+	(OP_MASK_CODE20, OP_SH_CODE20): Define, with values of old
+	OP_*_SYSCALL definitions.
+	(OP_SH_CODE19, OP_MASK_CODE19): Define, for use as
+	19 bit wait codes.
+	(MIPS operand specifier comments): Remove 'm', add 'U' and
+	'J', and update the meaning of 'B' so that it's more general.
+
+	* mips.h (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4,
+	INSN_ISA5): Renumber, redefine to mean the ISA at which the
+	instruction was added.
+	(INSN_ISA32): New constant.
+	(INSN_4650, INSN_4010, INSN_4100, INSN_3900, INSN_GP32):
+	Renumber to avoid new and/or renumbered INSN_* constants.
+	(INSN_MIPS32): Delete.
+	(ISA_UNKNOWN): New constant to indicate unknown ISA.
+	(ISA_MIPS1, ISA_MIPS2, ISA_MIPS3, ISA_MIPS4, ISA_MIPS5,
+	ISA_MIPS32): New constants, defined to be the mask of INSN_*
+	constants available at that ISA level.
+	(CPU_UNKNOWN): New constant to indicate unknown CPU.
+	(CPU_4K, CPU_MIPS32_4K): Rename the former to the latter,
+	define it with a unique value.
+	(OPCODE_IS_MEMBER): Update for new ISA membership-related
+	constant meanings.
+
+	* mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New
+	definitions.
+
+	* mips.h (CPU_SB1): New constant.
 
 2000-10-20  Jakub Jelinek  <jakub@redhat.com>
 
@@ -791,14 +845,14 @@ Fri Apr 21 13:20:53 2000  Richard Henderson  <rth@cygnus.com>
 
 2000-03-02  J"orn Rennecke <amylaar@cygnus.co.uk>
 
-        * d30v.h:
-        (SHORT_B2r, SHORT_B3, SHORT_B3r, SHORT_B3b, SHORT_B3br): Updated.
-        (SHORT_D1r, SHORT_D2, SHORT_D2r, SHORT_D2Br, SHORT_U): Updated.
-        (SHORT_F, SHORT_AF, SHORT_T, SHORT_A5, SHORT_CMP, SHORT_CMPU): Updated.
-        (SHORT_A1, SHORT_AA, SHORT_RA, SHORT_MODINC, SHORT_MODDEC): Updated.
-        (SHORT_C1, SHORT_C2, SHORT_UF, SHORT_A2, SHORT_NONE, LONG): Updated.
-        (LONG_U, LONG_Ur, LONG_CMP, LONG_M, LONG_M2, LONG_2, LONG_2r): Updated.
-        (LONG_2b, LONG_2br, LONG_D, LONG_Dr, LONG_Dbr): Updated.
+	* d30v.h:
+	(SHORT_B2r, SHORT_B3, SHORT_B3r, SHORT_B3b, SHORT_B3br): Updated.
+	(SHORT_D1r, SHORT_D2, SHORT_D2r, SHORT_D2Br, SHORT_U): Updated.
+	(SHORT_F, SHORT_AF, SHORT_T, SHORT_A5, SHORT_CMP, SHORT_CMPU): Updated.
+	(SHORT_A1, SHORT_AA, SHORT_RA, SHORT_MODINC, SHORT_MODDEC): Updated.
+	(SHORT_C1, SHORT_C2, SHORT_UF, SHORT_A2, SHORT_NONE, LONG): Updated.
+	(LONG_U, LONG_Ur, LONG_CMP, LONG_M, LONG_M2, LONG_2, LONG_2r): Updated.
+	(LONG_2b, LONG_2br, LONG_D, LONG_Dr, LONG_Dbr): Updated.
 
 2000-02-25  Alan Modra  <alan@spri.levels.unisa.edu.au>
 
@@ -808,7 +862,7 @@ Fri Apr 21 13:20:53 2000  Richard Henderson  <rth@cygnus.com>
 2000-02-24  Nick Clifton  <nickc@cygnus.com>
 
 	* cgen.h (cgen_cpu_desc): Rename field 'flags' to
-        'signed_overflow_ok_p'.
+	'signed_overflow_ok_p'.
 	Delete prototypes for cgen_set_flags() and cgen_get_flags().
 
 2000-02-24  Andrew Haley  <aph@cygnus.com>
@@ -877,14 +931,14 @@ Wed Nov 24 20:28:58 1999  Jeffrey A Law  (law@cygnus.com)
 
 Sun Oct 10 01:46:56 1999  Jerry Quinn <jerry.quinn.adv91@alum.dartmouth.org>
 
-	* hppa.h (pa_opcodes):  Add load and store cache control to
+	* hppa.h (pa_opcodes): Add load and store cache control to
 	instructions.  Add ordered access load and store.
 
 	* hppa.h (pa_opcode): Add new entries for addb and addib.
 
 	* hppa.h (pa_opcodes): Fix cmpb and cmpib entries.
 
-	* hppa.h (pa_opcodes):  Add entries for cmpb and cmpib.
+	* hppa.h (pa_opcodes): Add entries for cmpb and cmpib.
 
 Thu Oct  7 00:12:25 MDT 1999	Diego Novillo <dnovillo@cygnus.com>
 
@@ -968,22 +1022,22 @@ Sat Aug 28 00:25:25 1999  Jerry Quinn <jquinn@nortelnetworks.com>
 	* hppa.h (pa_opcodes): Add extrd, extrw, depd, depdi, depw, depwi.
 	Add supporting args.
 
-	* hppa.h:  Document new completers and args.
-	* hppa.h (pa_opcodes):  Add 64 bit patterns and pa2.0 syntax for uxor,
+	* hppa.h: Document new completers and args.
+	* hppa.h (pa_opcodes): Add 64 bit patterns and pa2.0 syntax for uxor,
 	uaddcm, dcor, addi, add, sub, subi, shladd, rfi, and probe.  Add pa2.0
 	extensions for ssm, rsm, pdtlb, pitlb.  Add performance instructions
 	pmenb and pmdis.
 
-	* hppa.h (pa_opcodes):  Add pa2.0 instructions hadd, hshl,
+	* hppa.h (pa_opcodes): Add pa2.0 instructions hadd, hshl,
 	hshr, hsub, mixh, mixw, permh.
 
 	* hppa.h (pa_opcodes): Change completers in instructions to
 	use 'c' prefix.
 
-	* hppa.h (pa_opcodes):  Add popbts, new forms of bb, havg,
+	* hppa.h (pa_opcodes): Add popbts, new forms of bb, havg,
 	hshladd, hshradd, shrpd, and shrpw instructions.  Update arg comments.
 
-	* hppa.h (pa_opcodes):  Change fmpyfadd, fmpynfadd, fneg,
+	* hppa.h (pa_opcodes): Change fmpyfadd, fmpynfadd, fneg,
 	fnegabs to use 'I' instead of 'F'.
 
 1999-08-21  Alan Modra  <alan@spri.levels.unisa.edu.au>
@@ -1001,7 +1055,7 @@ Fri Aug  6 09:46:35 1999  Jerry Quinn <jquinn@nortelnetworks.com>
 	* hppa.h (pa_opcodes): Add 64 bit versions of or, xor, and,
 	and andcm.  Add 32 and 64 bit version of cmpclr, cmpiclr.
 
-	* hppa.h:  Document 64 bit condition completers.
+	* hppa.h: Document 64 bit condition completers.
 
 Thu Aug  5 16:56:07 1999  Jerry Quinn <jquinn@nortelnetworks.com>
 
@@ -1020,7 +1074,7 @@ Wed Jul 28 02:04:24 1999  Jerry Quinn <jquinn@nortelnetworks.com>
 
 	* hppa.h (pa_opcodes): Mark all PA2.0 opcodes with FLAG_STRICT.
 
-	* hppa.h (pa_opcodes):  Change xmpyu, fmpyfadd,
+	* hppa.h (pa_opcodes): Change xmpyu, fmpyfadd,
 	and fmpynfadd to use 'J' and 'K' instead of 'E' and 'X'.
 
 1999-07-13  Alan Modra  <alan@spri.levels.unisa.edu.au>
@@ -1177,22 +1231,22 @@ Sat Feb 13 14:13:44 1999  Richard Henderson  <rth@cygnus.com>
 
 Mon Feb  1 21:09:14 1999  Catherine Moore  <clm@cygnus.com>
 
-        * i386.h (d_Suf, x_Suf, sld_Suf, sldx_Suf, bwld_Suf):  Define.
-        (x_FP, d_FP, dls_FP, sldx_FP):  Define.
-        Change *Suf definitions to include x and d suffixes.
-        (movsx):  Use w_Suf and b_Suf.
-        (movzx):  Likewise.
-        (movs):  Use bwld_Suf.
-        (fld):  Change ordering.  Use sld_FP.
-        (fild):  Add Intel Syntax equivalent of fildq.
-        (fst):  Use sld_FP.
-        (fist):  Use sld_FP.
-        (fstp):  Use sld_FP.  Add x_FP version.
-        (fistp):  LLongMem version for Intel Syntax.
-        (fcom, fcomp):  Use sld_FP.
-        (fadd, fiadd, fsub):  Use sld_FP.
-        (fsubr):  Use sld_FP.
-        (fmul, fimul, fdvi, fidiv, fdivr):  Use sld_FP.
+	* i386.h (d_Suf, x_Suf, sld_Suf, sldx_Suf, bwld_Suf): Define.
+	(x_FP, d_FP, dls_FP, sldx_FP): Define.
+	Change *Suf definitions to include x and d suffixes.
+	(movsx): Use w_Suf and b_Suf.
+	(movzx): Likewise.
+	(movs): Use bwld_Suf.
+	(fld): Change ordering.  Use sld_FP.
+	(fild): Add Intel Syntax equivalent of fildq.
+	(fst): Use sld_FP.
+	(fist): Use sld_FP.
+	(fstp): Use sld_FP.  Add x_FP version.
+	(fistp): LLongMem version for Intel Syntax.
+	(fcom, fcomp): Use sld_FP.
+	(fadd, fiadd, fsub): Use sld_FP.
+	(fsubr): Use sld_FP.
+	(fmul, fimul, fdvi, fidiv, fdivr): Use sld_FP.
 
 1999-01-27  Doug Evans  <devans@casey.cygnus.com>
 
@@ -1762,7 +1816,7 @@ Fri Apr  4 14:02:32 1997  Ian Lance Taylor  <ian@cygnus.com>
 
 Tue Mar 25 22:57:26 1997  Stu Grossman  (grossman@critters.cygnus.com)
 
-	* v850.h (extract):  Make unsigned.
+	* v850.h (extract): Make unsigned.
 
 Mon Mar 24 14:38:15 1997  Ian Lance Taylor  <ian@cygnus.com>
 
@@ -1980,7 +2034,7 @@ Wed Oct  2 21:31:26 1996  Jeffrey A Law  (law@cygnus.com)
 
 Fri Sep 27 18:26:46 1996  Stu Grossman  (grossman@critters.cygnus.com)
 
-	* v850.h:  Add new flag to indicate this instruction uses a PC
+	* v850.h: Add new flag to indicate this instruction uses a PC
 	displacement.
 
 Fri Sep 13 14:58:13 1996  Jeffrey A Law  (law@cygnus.com)
@@ -2349,9 +2403,9 @@ Mon Jan 23 16:45:43 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
 
 	Sat Jan 21 17:50:38 1995  Pat Rankin  (rankin@eql.caltech.edu)
 
-	* vax.h (struct vot_wot, field `args'):  Make it pointer to const
+	* vax.h (struct vot_wot, field `args'): Make it pointer to const
 	char.
-	(struct vot, field `name'):  ditto.
+	(struct vot, field `name'): ditto.
 
 Thu Jan 19 14:47:53 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
 
@@ -2607,7 +2661,7 @@ Thu Aug  5 09:15:17 1993  Jim Kingdon  (kingdon@lioth.cygnus.com)
 
 Fri Jul 30 18:41:11 1993  John Gilmore  (gnu@cygnus.com)
 
-	* sparc.h (F_JSR, F_UNBR, F_CONDBR):  Add new flags to mark
+	* sparc.h (F_JSR, F_UNBR, F_CONDBR): Add new flags to mark
 	jump instructions, for use in disassemblers.
 
 Thu Jul 22 07:25:27 1993  Ian Lance Taylor  (ian@cygnus.com)
@@ -2726,29 +2780,29 @@ Fri Apr  9 13:26:16 1993  Jim Kingdon  (kingdon@cygnus.com)
 
 Thu Mar 18 13:45:31 1993  Per Bothner  (bothner@rtl.cygnus.com)
 
-	* i386.h:  486 extensions from John Hassey (hassey@dg-rtp.dg.com).
-	* mips.h:  Add casts, to suppress warnings about shifting too much.
-	* m68k.h:  Document the placement code '9'.
+	* i386.h: 486 extensions from John Hassey (hassey@dg-rtp.dg.com).
+	* mips.h: Add casts, to suppress warnings about shifting too much.
+	* m68k.h: Document the placement code '9'.
 
 Thu Feb 18 02:03:14 1993  John Gilmore  (gnu@cygnus.com)
 
-	* m68k.h (BREAK_UP_BIG_DECL, AND_OTHER_PART):  Add kludge which
+	* m68k.h (BREAK_UP_BIG_DECL, AND_OTHER_PART): Add kludge which
 	allows callers to break up the large initialized struct full of
 	opcodes into two half-sized ones.  This permits GCC to compile
 	this module, since it takes exponential space for initializers.
-	(numopcodes, endop):  Revise to use AND_OTHER_PART in size calcs.
+	(numopcodes, endop): Revise to use AND_OTHER_PART in size calcs.
 
 Thu Feb  4 02:06:56 1993  John Gilmore  (gnu@cygnus.com)
 
-	* a29k.h:  Remove RCS crud, update GPL to v2, update copyrights.
-	* convex.h:  Added, from GDB's convx-opcode.h.  Added CONST to all
+	* a29k.h: Remove RCS crud, update GPL to v2, update copyrights.
+	* convex.h: Added, from GDB's convx-opcode.h.  Added CONST to all
 	initialized structs in it.
 
 Thu Jan 28 21:32:22 1993  John Gilmore  (gnu@cygnus.com)
 
 	Delta 88 changes inspired by Carl Greco, <cgreco@Creighton.Edu>:
-	* m88k.h (PMEM):  Avoid previous definition from <sys/param.h>.
-	(AND):  Change to AND_ to avoid ansidecl.h `AND' conflict.
+	* m88k.h (PMEM): Avoid previous definition from <sys/param.h>.
+	(AND): Change to AND_ to avoid ansidecl.h `AND' conflict.
 
 Sat Jan 23 18:10:49 PST 1993  Ralph Campbell  (ralphc@pyramid.com)
 
@@ -2764,7 +2818,7 @@ Sun Jan  3 14:13:35 1993  Steve Chamberlain  (sac@thepub.cygnus.com)
 
 Mon Dec 21 21:29:08 1992  Stu Grossman  (grossman at cygnus.com)
 
-	* hppa.h:  Move handy aliases to the front.  Fix masks for extract
+	* hppa.h: Move handy aliases to the front.  Fix masks for extract
 	and deposit instructions.
 
 Sat Dec 12 16:09:48 1992  Ian Lance Taylor  (ian@cygnus.com)
@@ -2799,7 +2853,7 @@ Tue Sep 22 14:08:14 1992  Ken Raeburn  (raeburn@cambridge.cygnus.com)
 
 Tue Sep 22 00:38:41 1992  John Gilmore  (gnu@cygnus.com)
 
-	* mips.h (break):  Disassemble the argument.  Patch from
+	* mips.h (break): Disassemble the argument.  Patch from
 	jonathan@cs.stanford.edu (Jonathan Stone).
 
 Wed Sep  9 11:25:28 1992  Ian Lance Taylor  (ian@cygnus.com)
@@ -2836,10 +2890,10 @@ Wed Aug 19 11:22:24 1992  Ian Lance Taylor  (ian@cygnus.com)
 
 Fri Aug 14 14:20:38 1992  Per Bothner  (bothner@cygnus.com)
 
-	* m68k.h:  Merged in patches (mostly m68040-specific) from
+	* m68k.h: Merged in patches (mostly m68040-specific) from
 	Colin Smith <colin@wrs.com>.
 
-	* m68k.h:  Merged m68kmri.h and m68k.h (using the former as a
+	* m68k.h: Merged m68kmri.h and m68k.h (using the former as a
 	base).  Also cleaned up duplicates, re-ordered instructions for
 	the sake of dis-assembling (so aliases come after standard names).
 	* m68kmri.h: Now just defines some macros, and #includes m68k.h.
@@ -2857,24 +2911,24 @@ Mon Aug 10 23:22:33 1992  Ken Raeburn  (raeburn@cygnus.com)
 
 Sun Jun 28 13:29:03 1992  Fred Fish  (fnf@cygnus.com)
 
-	* h8300.h:  Finish filling in all the holes in the opcode table,
+	* h8300.h: Finish filling in all the holes in the opcode table,
 	so that the Lucid C compiler can digest this as well...
 
 Fri Jun 26 21:27:17 1992  John Gilmore  (gnu at cygnus.com)
 
-	* i386.h:  Add setc, setnc, addr16, data16, repz, repnz aliases.
+	* i386.h: Add setc, setnc, addr16, data16, repz, repnz aliases.
 	Fix opcodes on various sizes of fild/fist instructions
 	(16bit=no suffix, 32bit="l" suffix, 64bit="ll" suffix).
 	Use tabs to indent for comments.  Fixes suggested by Minh Tran-Le.
 
 Thu Jun 25 16:13:26 1992  Stu Grossman  (grossman at cygnus.com)
 
-	* h8300.h:  Fill in all the holes in the opcode table so that the
+	* h8300.h: Fill in all the holes in the opcode table so that the
 	losing HPUX C compiler can digest this...
 
 Thu Jun 11 12:15:25 1992  John Gilmore  (gnu at cygnus.com)
 
-	* mips.h:  Fix decoding of coprocessor instructions, somewhat.
+	* mips.h: Fix decoding of coprocessor instructions, somewhat.
 	(Fix by Eric Anderson, 3jean@maas-neotek.arc.nasa.gov.)
 
 Thu May 28 11:17:44 1992  Jim Wilson  (wilson@sphagnum.cygnus.com)
@@ -2884,35 +2938,35 @@ Thu May 28 11:17:44 1992  Jim Wilson  (wilson@sphagnum.cygnus.com)
 
 Tue May  5 14:23:27 1992  Per Bothner  (bothner@rtl.cygnus.com)
 
-	* mips.h:  Add some more opcode synonyms (from Frank Yellin,
+	* mips.h: Add some more opcode synonyms (from Frank Yellin,
 	fy@lucid.com).
 
 Thu Apr 16 18:25:26 1992  Per Bothner  (bothner@cygnus.com)
 
-	* rs6k.h:  New version from IBM (Metin).
+	* rs6k.h: New version from IBM (Metin).
 
 Thu Apr  9 00:31:19 1992  Per Bothner  (bothner@rtl.cygnus.com)
 
 	* rs6k.h: Fix incorrect extended opcode for instructions `fm'
-        and `fd'.  (From metin@ibmpa.awdpa.ibm.com (Metin G. Ozisik).)
+	and `fd'.  (From metin@ibmpa.awdpa.ibm.com (Metin G. Ozisik).)
 
 Tue Apr  7 13:38:47 1992  Stu Grossman  (grossman at cygnus.com)
 
-	* rs6k.h:  Move from ../../gdb/rs6k-opcode.h.
+	* rs6k.h: Move from ../../gdb/rs6k-opcode.h.
 
 Fri Apr  3 11:30:20 1992  Fred Fish  (fnf@cygnus.com)
 
-	* m68k.h (one, two):  Cast macro args to unsigned to suppress
+	* m68k.h (one, two): Cast macro args to unsigned to suppress
 	complaints from compiler and lint about integer overflow during
 	shift.
 
 Sun Mar 29 12:22:08 1992  John Gilmore  (gnu at cygnus.com)
 
-	* sparc.h (OP):  Avoid signed overflow when shifting to high order bit.
+	* sparc.h (OP): Avoid signed overflow when shifting to high order bit.
 
 Fri Mar  6 00:22:38 1992  John Gilmore  (gnu at cygnus.com)
 
-	* mips.h:  Make bitfield layout depend on the HOST compiler,
+	* mips.h: Make bitfield layout depend on the HOST compiler,
 	not on the TARGET system.
 
 Fri Feb 21 01:29:51 1992  K. Richard Pixley  (rich@cygnus.com)
@@ -2927,15 +2981,15 @@ Thu Jan 30 07:31:44 1992  Steve Chamberlain  (sac at rtl.cygnus.com)
 
 Thu Jan 30 01:07:24 1992  John Gilmore  (gnu at cygnus.com)
 
-	* sparc.h:  Remove "cypress" architecture.  Remove "fitox" and
+	* sparc.h: Remove "cypress" architecture.  Remove "fitox" and
 	similar instructions -- they've been renamed to "fitoq", etc.
 	REALLY fix tsubcctv.  Fix "fcmpeq" and "fcmpq" which had wrong
 	number of arguments.
-	* h8300.h:  Remove extra ; which produces compiler warning.
+	* h8300.h: Remove extra ; which produces compiler warning.
 
 Tue Jan 28 22:59:22 1992  Stu Grossman  (grossman at cygnus.com)
 
-	* sparc.h:  fix opcode for tsubcctv.
+	* sparc.h: fix opcode for tsubcctv.
 
 Tue Jan  7 17:19:39 1992  K. Richard Pixley  (rich at cygnus.com)
 
@@ -2943,7 +2997,7 @@ Tue Jan  7 17:19:39 1992  K. Richard Pixley  (rich at cygnus.com)
 
 Fri Dec 27 10:55:50 1991  Per Bothner  (bothner at cygnus.com)
 
-	* sparc.h (nop):  Made the 'lose' field be even tighter,
+	* sparc.h (nop): Made the 'lose' field be even tighter,
 	so only a standard 'nop' is disassembled as a nop.
 
 Sun Dec 22 12:18:18 1991  Michael Tiemann  (tiemann at cygnus.com)
@@ -2953,7 +3007,7 @@ Sun Dec 22 12:18:18 1991  Michael Tiemann  (tiemann at cygnus.com)
 
 Wed Dec 18 17:19:44 1991  Stu Grossman  (grossman at cygnus.com)
 
-	* m68k.h, sparc.h:  ANSIfy enums.
+	* m68k.h, sparc.h: ANSIfy enums.
 
 Tue Dec 10 00:22:20 1991  K. Richard Pixley  (rich at rtl.cygnus.com)
 
diff --git a/include/opcode/h8300.h b/include/opcode/h8300.h
index 02f415be846..bfac3f8c73e 100644
--- a/include/opcode/h8300.h
+++ b/include/opcode/h8300.h
@@ -26,119 +26,219 @@
 
 typedef int op_type;
 
-#define Hex0	0
-#define Hex1 	1
-#define Hex2 	2
-#define Hex3 	3
-#define Hex4 	4
-#define Hex5 	5
-#define Hex6 	6
-#define Hex7 	7
-#define Hex8 	8
-#define Hex9 	9
-#define HexA 	10
-#define HexB 	11
-#define HexC 	12
-#define HexD 	13
-#define HexE 	14
-#define HexF 	15
-
-#define L_8		0x01
-#define L_16		0x02
-#define L_32		0x04
-#define L_P             0x08
-#define L_24		0x10
-#define MEMRELAX 	0x20			/* Move insn which may relax.  */ 
-#define SRC             0x40
-#define DST             0x80
-
-#define REG		0x100
-#define EXR		0x200
-#define MACREG		0x800
-#define SRC_IN_DST	0x400
-#define IMM		0x1000
-#define DISP		0x2000
-#define IND		0x4000
-#define INC		0x8000
-#define DEC		0x10000
-#define L_3		0x20000
-#define KBIT 		0x40000
-#define DBIT            0x80000
-#define DISPREG         0x100000
-#define IGNORE 		0x200000
-#define E      		0x400000		/* FIXME: end of nibble sequence?  */
-#define L_2		0x800000
-#define B30  		0x1000000 		/* Bit 3 must be low.  */
-#define B31  		0x2000000		/* Bit 3 must be high.  */
-#define CCR		0x4000000
-#define ABS             0x8000000
-#define ABSJMP		0x10000000  
-#define ABS8MEM         0x20000000	
-#define PCREL           0x40000000
-#define MEMIND          0x80000000
-
-#define IMM3 		IMM | L_3
-#define IMM2 		IMM | L_2
-
-#define SIZE		(L_2 | L_3 | L_8 | L_16 | L_32 | L_P | L_24)
-#define MODE		(REG | IMM | DISP | IND | INC | DEC | CCR | ABS | MEMIND | EXR)
-
-#define RD8 		(DST | L_8  | REG)
-#define RD16 		(DST | L_16 | REG)
-#define RD32 		(DST | L_32 | REG)
-#define RS8 		(SRC | L_8  | REG)
-#define RS16 		(SRC | L_16 | REG)
-#define RS32		(SRC | L_32 | REG)
-
-#define RSP 		(SRC | L_P | REG)
-#define RDP 		(DST | L_P | REG)
-
-#define IMM8 		(IMM | SRC | L_8)
-#define IMM16 		(IMM | SRC | L_16)
-#define IMM32 		(IMM | SRC | L_32)
-
-#define ABS8SRC 	(SRC | ABS | L_8 | ABS8MEM)
-#define ABS8DST		(DST | ABS | L_8 | ABS8MEM)
-
-#define DISP8 		(PCREL | L_8)
-#define DISP16 		(PCREL | L_16)
-
-#define DISP8SRC	(DISP | L_8  | SRC)
-#define DISP16SRC	(DISP | L_16 | SRC)
-
-#define DISP8DST	(DISP | L_8  | DST)
-#define DISP16DST	(DISP | L_16 | DST)
-
-#define ABS16SRC 	(SRC | ABS | L_16)
-#define ABS16DST 	(DST | ABS | L_16)
-#define ABS24SRC 	(SRC | ABS | L_24)
-#define ABS24DST 	(DST | ABS | L_24)
-#define ABS32SRC 	(SRC | ABS | L_32)
-#define ABS32DST 	(DST | ABS | L_32)
-
-#define RDDEC 		(DST | DEC)
-#define RSINC 		(SRC | INC)
-#define RDINC		(DST | INC)
-
-#define RDIND 		(DST | IND)
-#define RSIND 		(SRC | IND)
-
-#define MS32            (SRC | L_32 | MACREG)
-#define MD32            (DST | L_32 | MACREG)
+enum h8_flags {
+  L_2  =	0x10,
+  L_3  =	0x20,
+  /* 3 bit constant, zero not accepted.  */
+  L_3NZ =	0x30,
+  L_4  =	0x40,
+  L_5  =	0x50,
+  L_8  =	0x60,
+  L_8U =	0x70,
+  L_16 =	0x80,
+  L_16U =	0x90,
+  L_24 =	0xA0,
+  L_32 =	0xB0,
+  L_P  =	0xC0,
+
+  /* Mask to isolate the L_x size bits.  */
+  SIZE =	0xF0,
+
+  REG =		0x0100,
+  ABS =		0x0200,
+  MEMIND =	0x0300,
+  IMM =		0x0400,
+  DISP =	0x0500,
+  IND =		0x0600,
+  POSTINC =	0x0700,
+  POSTDEC =	0x0800,
+  PREINC =	0x0900,
+  PREDEC =	0x0A00,
+  PCREL =	0x0B00,
+  KBIT =	0x0C00,
+  DBIT =	0x0D00,
+  CONST_2 =     0x0E00,
+  CONST_4 =     0x0F00,
+  CONST_8 =     0x1000,
+  CONST_16 =    0x1100,
+  INDEXB =      0x1200,
+  INDEXW =      0x1300,
+  INDEXL =      0x1400,
+  PCIDXB =      0x1500,
+  PCIDXW =      0x1600,
+  PCIDXL =      0x1700,
+  VECIND =      0x1800,
+  LOWREG =      0x1900,
+  DATA   =      0x2000,
+
+  /* Synonyms.  */
+  INC =		POSTINC,
+  DEC =		PREDEC,
+  /* Control Registers.  */
+  CCR =		0x4000,
+  EXR =		0x4100,
+  MACH = 	0x4200,
+  MACL = 	0x4300,
+  RESERV1 = 	0x4400,
+  RESERV2 = 	0x4500,
+  VBR = 	0x4600,
+  SBR = 	0x4700,
+  MACREG =	0x4800,
+  CCR_EXR = 	0x4900,
+  VBR_SBR = 	0x4A00,
+  CC_EX_VB_SB =	0x4B00,
+  RESERV3 =	0x4C00,
+  RESERV4 = 	0x4D00,
+  RESERV5 = 	0x4E00,
+  RESERV6 = 	0x4F00,
+
+  /* Mask to isolate the addressing mode bits (REG .. PREDEC).  */
+  MODE =	0x7F00,
+
+  CTRL = 	0x4000,
+
+  NO_SYMBOLS =  0x8000,
+  SRC =		0x10000,
+  DST =		0x20000,
+  OP3 =		0x40000,
+  MEMRELAX = 	0x80000,		/* Move insn which may relax.  */
+
+  DISPREG =	0x100000,
+  IGNORE =	0x200000,
+  ABSJMP =	0x400000,
+
+  B00 =         0x800000, 		/* Bit 0 must be low.   */
+  B01 =         0x1000000, 		/* Bit 0 must be high.  */
+  B10 = 	0x2000000, 		/* Bit 1 must be low.   */
+  B11 = 	0x4000000, 		/* Bit 1 must be high.  */
+  B20 = 	0x8000000, 		/* Bit 2 must be low.   */
+  B21 = 	0x10000000, 		/* Bit 2 must be high.  */
+  B30 =		0x20000000, 		/* Bit 3 must be low.   */
+  B31 =		0x40000000,		/* Bit 3 must be high.  */
+  E =  		0x80000000,		/* End of nibble sequence.  */
+
+  /* Immediates smaller than 8 bits are always unsigned.  */
+  IMM3 =	IMM | L_3,
+  IMM4 =	IMM | L_4,
+  IMM5 =	IMM | L_5,
+  IMM3NZ =	IMM | L_3NZ,
+  IMM2 =	IMM | L_2,
+
+  IMM8 =	IMM | SRC | L_8,
+  IMM8U =	IMM | SRC | L_8U,
+  IMM16 =	IMM | SRC | L_16,
+  IMM16U =	IMM | SRC | L_16U,
+  IMM32 =	IMM | SRC | L_32,
+
+  IMM3NZ_NS =   IMM3NZ | NO_SYMBOLS,
+  IMM4_NS =	IMM4 | NO_SYMBOLS,
+  IMM8U_NS =	IMM8U | NO_SYMBOLS,
+  IMM16U_NS =   IMM16U | NO_SYMBOLS,
+
+  RD8  =	DST | L_8  | REG,
+  RD16 =	DST | L_16 | REG,
+  RD32 =	DST | L_32 | REG,
+  R3_8  =       OP3 | L_8  | REG,
+  R3_16 =       OP3 | L_16 | REG,
+  R3_32 =       OP3 | L_32 | REG,
+  RS8  =	SRC | L_8  | REG,
+  RS16 =	SRC | L_16 | REG,
+  RS32 =	SRC | L_32 | REG,
+
+  RSP =		SRC | L_P | REG,
+  RDP =		DST | L_P | REG,
+
+  PCREL8 =	PCREL | L_8,
+  PCREL16 =	PCREL | L_16,
+
+  OP3PCREL8 =	OP3 | PCREL | L_8,
+  OP3PCREL16 =	OP3 | PCREL | L_16,
+
+  INDEXB16  =	INDEXB | L_16,
+  INDEXW16  =	INDEXW | L_16,
+  INDEXL16  =	INDEXL | L_16,
+  INDEXB16D =	INDEXB | L_16 | DST,
+  INDEXW16D =	INDEXW | L_16 | DST,
+  INDEXL16D =	INDEXL | L_16 | DST,
+
+  INDEXB32  =	INDEXB | L_32,
+  INDEXW32  =	INDEXW | L_32,
+  INDEXL32  =	INDEXL | L_32,
+  INDEXB32D =	INDEXB | L_32 | DST,
+  INDEXW32D =	INDEXW | L_32 | DST,
+  INDEXL32D =	INDEXL | L_32 | DST,
+
+  DISP2SRC =	DISP | L_2  | SRC,
+  DISP16SRC =	DISP | L_16 | SRC,
+  DISP32SRC =	DISP | L_32 | SRC,
+
+  DISP2DST =	DISP | L_2  | DST,
+  DISP16DST =	DISP | L_16 | DST,
+  DISP32DST =	DISP | L_32 | DST,
+
+  DSTDISPREG =  DST | DISPREG,
+  SRCDISPREG =  SRC | DISPREG,
+
+  ABS8SRC  = 	SRC | ABS | L_8,
+  ABS16SRC = 	SRC | ABS | L_16U,
+  ABS24SRC = 	SRC | ABS | L_24,
+  ABS32SRC = 	SRC | ABS | L_32,
+
+  ABS8DST  =	DST | ABS | L_8,
+  ABS16DST = 	DST | ABS | L_16U,
+  ABS24DST = 	DST | ABS | L_24,
+  ABS32DST = 	DST | ABS | L_32,
+
+  ABS8OP3  =	OP3 | ABS | L_8,
+  ABS16OP3 = 	OP3 | ABS | L_16U,
+  ABS24OP3 = 	OP3 | ABS | L_24,
+  ABS32OP3 = 	OP3 | ABS | L_32,
+
+  RDDEC =	DST | DEC,
+  RSINC =	SRC | INC,
+  RDINC =	DST | INC,
+
+  RSPOSTINC =	SRC | POSTINC,
+  RDPOSTINC =	DST | POSTINC,
+  RSPREINC =	SRC | PREINC,
+  RDPREINC =	DST | PREINC,
+  RSPOSTDEC =	SRC | POSTDEC,
+  RDPOSTDEC =	DST | POSTDEC,
+  RSPREDEC =	SRC | PREDEC,
+  RDPREDEC =	DST | PREDEC,
+
+  RSIND =	SRC | IND,
+  RDIND =	DST | IND,
+  R3_IND = 	OP3 | IND,
+
+#define MS32	(SRC | L_32 | MACREG)
+#define MD32	(DST | L_32 | MACREG)
 
 #if 1
-#define OR8 RS8		/* ??? OR as in One Register?  */
-#define OR16 RS16
-#define OR32 RS32
+  OR8  =	RS8,		/* ??? OR as in One Register.  */
+  OR16 =	RS16,
+  OR32 =	RS32,
 #else
-#define OR8 RD8
-#define OR16 RD16
-#define OR32 RD32
+  OR8  =	RD8,
+  OR16 =	RD16,
+  OR32 =	RD32
 #endif
+};
+
+enum ctrlreg {
+  C_CCR  = 0, 
+  C_EXR  = 1, 
+  C_MACH = 2, 
+  C_MACL = 3, 
+  C_VBR  = 6, 
+  C_SBR  = 7
+};
+
+enum {MAX_CODE_NIBBLES = 33};
 
 struct code 
 {
-  op_type nib[30];
+  op_type nib[MAX_CODE_NIBBLES];
 };
 
 struct arg 
@@ -146,10 +246,18 @@ struct arg
   op_type nib[3];
 };
 
+/* Availability of instructions on processor models.  */
+enum h8_model {
+  AV_H8,
+  AV_H8H,
+  AV_H8S,
+  AV_H8SX
+};
+
 struct h8_opcode 
 {
   int how;
-  int inbase;
+  enum h8_model available;
   int time;
   char *name;
   struct arg args;
@@ -158,454 +266,1629 @@ struct h8_opcode
 
 #ifdef DEFINE_TABLE
 
-#define BITOP(code, imm, name, op00, op01,op10,op11, op20,op21,op30)\
-{ code, 1, 2, name,	{{imm,RD8,E}},	{{op00, op01, imm, RD8, E, 0, 0, 0, 0}}},\
-{ code, 1, 6, name,	{{imm,RDIND,E}},{{op10, op11, B30|RDIND, 0, op00,op01, imm, 0, E}}},\
-{ code, 1, 6, name,	{{imm,ABS8DST,E}},{{op20, op21, ABS8DST, IGNORE, op00,op01, imm, 0,E}}}\
-,{ code, 0, 6, name,	{{imm,ABS16DST,E}},{{0x6,0xa,0x1,op30,ABS16DST,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}}},\
-{ code, 0, 6, name,	{{imm,ABS32DST,E}},{{0x6,0xa,0x3,op30,ABS32DST,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}}}
-
-
-#define EBITOP(code, imm, name, op00, op01,op10,op11, op20,op21,op30)\
-   BITOP(code,imm, name, op00+1, op01, op10,op11, op20,op21,op30),\
-   BITOP(code,RS8,  name, op00, op01, op10,op11, op20,op21,op30)
-
-#define WTWOP(code,name, op1, op2) \
-{ code, 1, 2, name, {{RS16, RD16, E}}, {{ op1, op2, RS16, RD16, E, 0, 0, 0, 0}}}
+#define DATA2   DATA, DATA
+#define DATA3   DATA, DATA, DATA
+#define DATA5   DATA, DATA, DATA, DATA, DATA
+#define DATA7   DATA, DATA, DATA, DATA, DATA, DATA, DATA
+
+#define IMM8LIST	IMM8,   DATA
+#define IMM16LIST	IMM16,  DATA3
+#define IMM16ULIST	IMM16U, DATA3
+#define IMM24LIST	IMM24,  DATA5
+#define IMM32LIST	IMM32,  DATA7
+
+#define DISP16LIST DISP | L_16, DATA3
+#define DISP24LIST DISP | L_24, DATA5
+#define DISP32LIST DISP | L_32, DATA7
+
+#define ABS8LIST   ABS  | L_8,   DATA
+#define ABS16LIST  ABS  | L_16U, DATA3
+#define ABS24LIST  ABS  | L_24,  DATA5
+#define ABS32LIST  ABS  | L_32,  DATA7
+
+#define DSTABS8LIST  DST | ABS | L_8,   DATA
+#define DSTABS16LIST DST | ABS | L_16U, DATA3
+#define DSTABS24LIST DST | ABS | L_24,  DATA5
+#define DSTABS32LIST DST | ABS | L_32,  DATA7
+
+#define OP3ABS8LIST  OP3 | ABS | L_8,  DATA
+#define OP3ABS16LIST OP3 | ABS | L_16, DATA3
+#define OP3ABS24LIST OP3 | ABS | L_24, DATA5
+#define OP3ABS32LIST OP3 | ABS | L_32, DATA7
+
+#define DSTDISP16LIST DST | DISP | L_16, DATA3
+#define DSTDISP24LIST DST | DISP | L_24, DATA5
+#define DSTDISP32LIST DST | DISP | L_32, DATA7
+
+#define A16LIST   L_16,  DATA3
+#define A24LIST   L_24,  DATA5
+#define A32LIST   L_32,  DATA7
+
+/* Extended Operand Prefixes: */
+
+#define PREFIX_010	0x0, 0x1, 0x0
+#define PREFIX_015	0x0, 0x1, 0x5
+#define PREFIX_017	0x0, 0x1, 0x7
+
+#define PREFIX_0100	0x0, 0x1, 0x0, 0x0
+#define PREFIX_010_D2	0x0, 0x1, 0x0, B30 | B21 | DISP2SRC
+#define PREFIX_0101	0x0, 0x1, 0x0, 0x1
+#define PREFIX_0102	0x0, 0x1, 0x0, 0x2
+#define PREFIX_0103	0x0, 0x1, 0x0, 0x3
+#define PREFIX_0104	0x0, 0x1, 0x0, 0x4
+#define PREFIX_0105	0x0, 0x1, 0x0, 0x5
+#define PREFIX_0106	0x0, 0x1, 0x0, 0x6
+#define PREFIX_0107	0x0, 0x1, 0x0, 0x7
+#define PREFIX_0108	0x0, 0x1, 0x0, 0x8
+#define PREFIX_0109	0x0, 0x1, 0x0, 0x9
+#define PREFIX_010A	0x0, 0x1, 0x0, 0xa
+#define PREFIX_010D	0x0, 0x1, 0x0, 0xd
+#define PREFIX_010E	0x0, 0x1, 0x0, 0xe
+
+#define PREFIX_0150	0x0, 0x1, 0x5, 0x0
+#define PREFIX_015_D2	0x0, 0x1, 0x5, B30 | B21 | DISP2SRC
+#define PREFIX_0151	0x0, 0x1, 0x5, 0x1
+#define PREFIX_0152	0x0, 0x1, 0x5, 0x2
+#define PREFIX_0153	0x0, 0x1, 0x5, 0x3
+#define PREFIX_0154	0x0, 0x1, 0x5, 0x4
+#define PREFIX_0155	0x0, 0x1, 0x5, 0x5
+#define PREFIX_0156	0x0, 0x1, 0x5, 0x6
+#define PREFIX_0157	0x0, 0x1, 0x5, 0x7
+#define PREFIX_0158	0x0, 0x1, 0x5, 0x8
+#define PREFIX_0159	0x0, 0x1, 0x5, 0x9
+#define PREFIX_015A	0x0, 0x1, 0x5, 0xa
+#define PREFIX_015D	0x0, 0x1, 0x5, 0xd
+#define PREFIX_015E	0x0, 0x1, 0x5, 0xe
+#define PREFIX_015F	0x0, 0x1, 0x5, 0xf
+
+#define PREFIX_0170	0x0, 0x1, 0x7, 0x0
+#define PREFIX_017_D2S	0x0, 0x1, 0x7, B30 | B21 | DISP2SRC
+#define PREFIX_017_D2D	0x0, 0x1, 0x7, B30 | B21 | DISP2DST
+#define PREFIX_0171	0x0, 0x1, 0x7, 0x1
+#define PREFIX_0172	0x0, 0x1, 0x7, 0x2
+#define PREFIX_0173	0x0, 0x1, 0x7, 0x3
+#define PREFIX_0174	0x0, 0x1, 0x7, 0x4
+#define PREFIX_0175	0x0, 0x1, 0x7, 0x5
+#define PREFIX_0176	0x0, 0x1, 0x7, 0x6
+#define PREFIX_0177	0x0, 0x1, 0x7, 0x7
+#define PREFIX_0178	0x0, 0x1, 0x7, 0x8
+#define PREFIX_0179	0x0, 0x1, 0x7, 0x9
+#define PREFIX_017A	0x0, 0x1, 0x7, 0xa
+#define PREFIX_017D	0x0, 0x1, 0x7, 0xd
+#define PREFIX_017E	0x0, 0x1, 0x7, 0xe
+#define PREFIX_017F	0x0, 0x1, 0x7, 0xf
+
+#define PREFIX_6A15	0x6, 0xa, 0x1, 0x5
+#define PREFIX_6A35	0x6, 0xa, 0x3, 0x5
+#define PREFIX_6B15	0x6, 0xb, 0x1, 0x5
+#define PREFIX_6B35	0x6, 0xb, 0x3, 0x5
+
+#define PREFIX_78R4	0x7, 0x8, B31 | DISPREG, 0x4
+#define PREFIX_78R5	0x7, 0x8, B31 | DISPREG, 0x5
+#define PREFIX_78R6	0x7, 0x8, B31 | DISPREG, 0x6
+#define PREFIX_78R7	0x7, 0x8, B31 | DISPREG, 0x7
+
+#define PREFIX_78R4W	0x7, 0x8, B30 | DISPREG, 0x4
+#define PREFIX_78R5W	0x7, 0x8, B30 | DISPREG, 0x5
+#define PREFIX_78R6W	0x7, 0x8, B30 | DISPREG, 0x6
+#define PREFIX_78R7W	0x7, 0x8, B30 | DISPREG, 0x7
+
+#define PREFIX_78R4WD	0x7, 0x8, B30 | DSTDISPREG, 0x4
+#define PREFIX_78R5WD	0x7, 0x8, B30 | DSTDISPREG, 0x5
+#define PREFIX_78R6WD	0x7, 0x8, B30 | DSTDISPREG, 0x6
+#define PREFIX_78R7WD	0x7, 0x8, B30 | DSTDISPREG, 0x7
+
+#define PREFIX_7974	0x7, 0x9, 0x7, 0x4
+#define PREFIX_7A74	0x7, 0xa, 0x7, 0x4
+#define PREFIX_7A7C	0x7, 0xa, 0x7, 0xc
+
+
+/* Source standard fragment: */
+#define FROM_IND	 0, RSIND
+#define FROM_POSTINC	 8, RSPOSTINC
+#define FROM_POSTDEC	10, RSPOSTDEC
+#define FROM_PREINC	 9, RSPREINC
+#define FROM_PREDEC	11, RSPREDEC
+#define FROM_DISP2	B30 | B20 | DISP2SRC, DISPREG 
+#define FROM_DISP16	12, B30 | DISPREG
+#define FROM_DISP32	12, B31 | DISPREG
+#define FROM_DISP16B	13, B30 | DISPREG
+#define FROM_DISP16W	14, B30 | DISPREG
+#define FROM_DISP16L	15, B30 | DISPREG
+#define FROM_DISP32B	13, B31 | DISPREG
+#define FROM_DISP32W	14, B31 | DISPREG
+#define FROM_DISP32L	15, B31 | DISPREG
+#define FROM_ABS16	 4, B30 | IGNORE
+#define FROM_ABS32	 4, B31 | IGNORE
+
+/* Destination standard fragment: */
+#define TO_IND		 0, RDIND
+#define TO_IND_MOV	 0, RDIND | B30
+#define TO_POSTINC	 8, RDPOSTINC
+#define TO_POSTINC_MOV	 8, RDPOSTINC | B30
+#define TO_POSTDEC	10, RDPOSTDEC
+#define TO_POSTDEC_MOV	10, RDPOSTDEC | B30
+#define TO_PREINC	 9, RDPREINC
+#define TO_PREINC_MOV	 9, RDPREINC  | B30
+#define TO_PREDEC	11, RDPREDEC
+#define TO_PREDEC_MOV	11, RDPREDEC  | B30
+#define TO_DISP2	B30 | B20 | DISP2DST, DSTDISPREG
+#define TO_DISP2_MOV	B30 | B20 | DISP2DST, DSTDISPREG | B30
+#define TO_DISP16	12, B30 | DSTDISPREG
+#define TO_DISP32	12, B31 | DSTDISPREG
+#define TO_DISP16B	13, B30 | DSTDISPREG
+#define TO_DISP16W	14, B30 | DSTDISPREG
+#define TO_DISP16L	15, B30 | DSTDISPREG
+#define TO_DISP32B	13, B31 | DSTDISPREG
+#define TO_DISP32W	14, B31 | DSTDISPREG
+#define TO_DISP32L	15, B31 | DSTDISPREG
+#define TO_ABS16	 4, B30 | IGNORE
+#define TO_ABS32	 4, B31 | IGNORE
+
+/* Source fragment for three-word instruction: */
+#define TFROM_IND	6,  9, B30 | RSIND, 12
+#define TFROM_DISP2	6,  9, B30 | DISPREG, 12
+#define TFROM_ABS16	6, 11, B30 | B20 | B10 | IGNORE, 12, ABS16LIST
+#define TFROM_ABS32	6, 11, B30 | B20 | B11 | IGNORE, 12, ABS32LIST
+#define TFROM_POSTINC	6, 13, B30 | RSPOSTINC, 12
+#define TFROM_PREINC	6, 13, B30 | RSPREINC, 12
+#define TFROM_POSTDEC	6, 13, B30 | RSPOSTDEC, 12
+#define TFROM_PREDEC	6, 13, B30 | RSPREDEC, 12
+#define TFROM_DISP16	6, 15, B30 | DISPREG, 12, DISP16LIST
+#define TFROM_DISP32	6, 11, 2, 12, DISP32LIST
+#define TFROM_DISP16B	6, 15, B30 | DISPREG, 12, DISP16LIST
+#define TFROM_DISP16W	6, 15, B30 | DISPREG, 12, DISP16LIST
+#define TFROM_DISP16L	6, 15, B30 | DISPREG, 12, DISP16LIST
+#define TFROM_DISP32B	6, 11, 2, 12, DISP32LIST
+#define TFROM_DISP32W	6, 11, 2, 12, DISP32LIST
+#define TFROM_DISP32L	6, 11, 2, 12, DISP32LIST
+#define TFROM_ABS16W	6, 11, 1, 12, ABS16LIST
+#define TFROM_ABS32W	6, 11, 3, 12, ABS32LIST
+
+/* Source fragment for three-word instruction: */
+#define TFROM_IND_B	6,  8, B30 | RSIND, 12
+#define TFROM_ABS16_B	6, 10, B30 | B20 | B10 | IGNORE, 12, ABS16LIST
+#define TFROM_ABS32_B	6, 10, B30 | B20 | B11 | IGNORE, 12, ABS32LIST
+
+#define TFROM_DISP2_B	6,  8, B30 | DISPREG, 12
+#define TFROM_POSTINC_B	6, 12, B30 | RSPOSTINC, 12
+#define TFROM_PREINC_B	6, 12, B30 | RSPREINC, 12
+#define TFROM_POSTDEC_B	6, 12, B30 | RSPOSTDEC, 12
+#define TFROM_PREDEC_B	6, 12, B30 | RSPREDEC, 12
+#define TFROM_DISP16_B	6, 14, B30 | DISPREG, 12, DISP16LIST
+#define TFROM_DISP32_B	6, 10, 2, 12, DISP32LIST
+#define TFROM_DISP16B_B	6, 14, B30 | DISPREG, 12, DISP16LIST
+#define TFROM_DISP16W_B	6, 14, B30 | DISPREG, 12, DISP16LIST
+#define TFROM_DISP16L_B	6, 14, B30 | DISPREG, 12, DISP16LIST
+#define TFROM_DISP32B_B	6, 10, 2, 12, DISP32LIST
+#define TFROM_DISP32W_B	6, 10, 2, 12, DISP32LIST
+#define TFROM_DISP32L_B	6, 10, 2, 12, DISP32LIST
+
+#define TFROM_ABS16W_B	6, 10, 1, 12, ABS16LIST
+#define TFROM_ABS32W_B	6, 10, 3, 12, ABS32LIST
+
+/* Extended Operand Class Expanders: */
+
+#define MOVFROM_STD(CODE, PREFIX, NAME, SRC, SRC_INFIX) \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND,     E}},  {{PREFIX, SRC_INFIX, TO_IND_MOV,     E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}},  {{PREFIX, SRC_INFIX, TO_POSTINC_MOV, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}},  {{PREFIX, SRC_INFIX, TO_POSTDEC_MOV, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}},  {{PREFIX, SRC_INFIX, TO_PREINC_MOV,  E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}},  {{PREFIX, SRC_INFIX, TO_PREDEC_MOV,  E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}},  {{PREFIX, SRC_INFIX, TO_DISP2_MOV,   E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}},  {{PREFIX, SRC_INFIX, TO_DISP16,  DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}},  {{PREFIX, SRC_INFIX, TO_DISP32,  DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}},  {{PREFIX, SRC_INFIX, TO_DISP16B, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}},  {{PREFIX, SRC_INFIX, TO_DISP16W, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}},  {{PREFIX, SRC_INFIX, TO_DISP16L, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}},  {{PREFIX, SRC_INFIX, TO_DISP32B, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}},  {{PREFIX, SRC_INFIX, TO_DISP32W, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}},  {{PREFIX, SRC_INFIX, TO_DISP32L, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST,  E}},  {{PREFIX, SRC_INFIX, TO_ABS16,   DSTABS16LIST,  E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST,  E}},  {{PREFIX, SRC_INFIX, TO_ABS32,   DSTABS32LIST,  E}}}
+
+#define MOVFROM_AD(CODE, PREFIX, NAME, SRC, SRC_INFIX, SRC_SUFFIX) \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND,     E}},  {{PREFIX, SRC_INFIX, TO_IND_MOV,     SRC_SUFFIX, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}},  {{PREFIX, SRC_INFIX, TO_POSTINC_MOV, SRC_SUFFIX, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}},  {{PREFIX, SRC_INFIX, TO_POSTDEC_MOV, SRC_SUFFIX, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}},  {{PREFIX, SRC_INFIX, TO_PREINC_MOV,  SRC_SUFFIX, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}},  {{PREFIX, SRC_INFIX, TO_PREDEC_MOV,  SRC_SUFFIX, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}},  {{PREFIX, SRC_INFIX, TO_DISP2_MOV,   SRC_SUFFIX, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}},  {{PREFIX, SRC_INFIX, TO_DISP16,  SRC_SUFFIX, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}},  {{PREFIX, SRC_INFIX, TO_DISP32,  SRC_SUFFIX, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}},  {{PREFIX, SRC_INFIX, TO_DISP16B, SRC_SUFFIX, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}},  {{PREFIX, SRC_INFIX, TO_DISP16W, SRC_SUFFIX, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}},  {{PREFIX, SRC_INFIX, TO_DISP16L, SRC_SUFFIX, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}},  {{PREFIX, SRC_INFIX, TO_DISP32B, SRC_SUFFIX, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}},  {{PREFIX, SRC_INFIX, TO_DISP32W, SRC_SUFFIX, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}},  {{PREFIX, SRC_INFIX, TO_DISP32L, SRC_SUFFIX, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST,  E}},  {{PREFIX, SRC_INFIX, TO_ABS16,   SRC_SUFFIX, DSTABS16LIST,  E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST,  E}},  {{PREFIX, SRC_INFIX, TO_ABS32,   SRC_SUFFIX, DSTABS32LIST,  E}}}
+
+#define MOVFROM_IMM8(CODE, PREFIX, NAME, SRC) \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND,     E}},  {{PREFIX,  0, RDIND,     IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}},  {{PREFIX,  8, RDPOSTINC, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}},  {{PREFIX, 10, RDPOSTDEC, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}},  {{PREFIX,  9, RDPREINC,  IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}},  {{PREFIX, 11, RDPREDEC,  IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}},  {{PREFIX, B30 | B20 | DISP2DST, DSTDISPREG, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}},  {{PREFIX, 12, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}},  {{PREFIX, 12, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}},  {{PREFIX, 13, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}},  {{PREFIX, 14, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}},  {{PREFIX, 15, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}},  {{PREFIX, 13, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}},  {{PREFIX, 14, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}},  {{PREFIX, 15, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST,  E}},  {{PREFIX,  4, B30 | IGNORE,     IMM8LIST, DSTABS16LIST,  E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST,  E}},  {{PREFIX,  4, B31 | IGNORE,     IMM8LIST, DSTABS32LIST,  E}}}
+
+#define MOVFROM_IMM(CODE, PREFIX, NAME, SRC, LIST) \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND,     E}},  {{PREFIX, LIST,  0, RDIND,     DATA2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}},  {{PREFIX, LIST,  8, RDPOSTINC, DATA2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}},  {{PREFIX, LIST, 10, RDPOSTDEC, DATA2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}},  {{PREFIX, LIST,  9, RDPREINC,  DATA2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}},  {{PREFIX, LIST, 11, RDPREDEC,  DATA2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}},  {{PREFIX, LIST, B30 | B20 | DISP2DST, DSTDISPREG, DATA2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}},  {{PREFIX, LIST, 12, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}},  {{PREFIX, LIST, 12, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}},  {{PREFIX, LIST, 13, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}},  {{PREFIX, LIST, 14, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}},  {{PREFIX, LIST, 15, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}},  {{PREFIX, LIST, 13, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}},  {{PREFIX, LIST, 14, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}},  {{PREFIX, LIST, 15, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST,  E}},  {{PREFIX, LIST,  4, B30 | IGNORE,     DATA2, DSTABS16LIST,  E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST,  E}},  {{PREFIX, LIST,  4, B31 | IGNORE,     DATA2, DSTABS32LIST,  E}}}
+
+#define MOVFROM_REG_BW(CODE, NAME, SRC, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \
+  {CODE, AV_H8,   4, NAME, {{SRC, RDIND,     E}}, {{                              6, OP1, B31 | RDIND,      SRC,                E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, 3,                    6, OP3, B31 | RDPOSTINC,  SRC,                E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, 1,                    6, OP3, B31 | RDPOSTDEC,  SRC,                E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}}, {{PREFIX, 2,                    6, OP3, B31 | RDPREINC,   SRC,                E}}}, \
+  {CODE, AV_H8,   6, NAME, {{SRC, RDPREDEC,  E}}, {{                              6, OP3, B31 | RDPREDEC,   SRC,                E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}}, {{PREFIX, B30 | B20 | DISP2DST, 6, OP1, B31 | DSTDISPREG, SRC,                E}}}, \
+  {CODE, AV_H8,   6, NAME, {{SRC, DISP16DST, E}}, {{                              6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8,   6, NAME, {{SRC, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 0,    6, OP2, 10,               SRC, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, 1,                    6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, 2,                    6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, 3,                    6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 1,    6, OP2, 10,               SRC, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 2,    6, OP2, 10,               SRC, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 3,    6, OP2, 10,               SRC, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8,   4, NAME, {{SRC, ABS16DST,  E}}, {{                              6, OP2, 8,                SRC, RELAX16  | DSTABS16LIST, E}}}, \
+  {CODE, AV_H8,   6, NAME, {{SRC, ABS32DST,  E}}, {{                              6, OP2, 10,               SRC, MEMRELAX | DSTABS32LIST, E}}}
+
+#define MOVTO_REG_BW(CODE, NAME, DST, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \
+  {CODE, AV_H8,   4, NAME, {{RSIND,     DST, E}}, {{                              6, OP1, B30 | RSIND,     DST,             E}}}, \
+  {CODE, AV_H8,   6, NAME, {{RSPOSTINC, DST, E}}, {{                              6, OP3, B30 | RSPOSTINC, DST,             E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, DST, E}}, {{PREFIX, 2,                    6, OP3, B30 | RSPOSTDEC, DST,             E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPREINC,  DST, E}}, {{PREFIX, 1,                    6, OP3, B30 | RSPREINC,  DST,             E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPREDEC,  DST, E}}, {{PREFIX, 3,                    6, OP3, B30 | RSPREDEC,  DST,             E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{DISP2SRC,  DST, E}}, {{PREFIX, B30 | B20 | DISP2SRC, 6, OP1, B30 | DISPREG,   DST,             E}}}, \
+  {CODE, AV_H8,   6, NAME, {{DISP16SRC, DST, E}}, {{                              6, OP4, B30 | DISPREG,   DST, DISP16LIST, E}}}, \
+  {CODE, AV_H8,   6, NAME, {{DISP32SRC, DST, E}}, {{7, 8, B30 | DISPREG, 0,       6, OP2, 2,               DST, DISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXB16,  DST, E}}, {{PREFIX, 1,                    6, OP4, B30 | DISPREG,   DST, DISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXW16,  DST, E}}, {{PREFIX, 2,                    6, OP4, B30 | DISPREG,   DST, DISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXL16,  DST, E}}, {{PREFIX, 3,                    6, OP4, B30 | DISPREG,   DST, DISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXB32,  DST, E}}, {{7, 8, B30 | DISPREG, 1,       6, OP2, 2,               DST, DISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXW32,  DST, E}}, {{7, 8, B30 | DISPREG, 2,       6, OP2, 2,               DST, DISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXL32,  DST, E}}, {{7, 8, B30 | DISPREG, 3,       6, OP2, 2,               DST, DISP32LIST, E}}}, \
+  {CODE, AV_H8,   4, NAME, {{ABS16SRC,  DST, E}}, {{                              6, OP2, 0,               DST, RELAX16  | ABS16LIST, E}}}, \
+  {CODE, AV_H8,   6, NAME, {{ABS32SRC,  DST, E}}, {{                              6, OP2, 2,               DST, MEMRELAX | ABS32LIST, E}}}
+
+/*
+ * Expansion macros for two-word (plus data) instructions.
+ */
+
+/* Expansion from one source to "standard" destinations.  */
+#define EXPAND2_STD_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, NIB1, NIB2) \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}}, {{PREFIX, TO_PREINC,  NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}}, {{PREFIX, TO_PREDEC,  NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}}, {{PREFIX, TO_DISP2,   NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16,  NIB1, NIB2, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32,  NIB1, NIB2, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, NIB1, NIB2, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, TO_DISP16W, NIB1, NIB2, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, TO_DISP16L, NIB1, NIB2, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, TO_DISP32B, NIB1, NIB2, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, TO_DISP32W, NIB1, NIB2, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, TO_DISP32L, NIB1, NIB2, DSTDISP32LIST, E}}}
+
+/* Expansion from one destination to "standard" sources.  */
+#define EXPAND2_STD_DST(CODE, WEIGHT, NAME, DST, PREFIX, NIB1, NIB2) \
+  {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, DST, E}}, {{PREFIX, FROM_POSTINC, NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, DST, E}}, {{PREFIX, FROM_POSTDEC, NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPREINC,  DST, E}}, {{PREFIX, FROM_PREINC,  NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPREDEC,  DST, E}}, {{PREFIX, FROM_PREDEC,  NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{DISP2SRC,  DST, E}}, {{PREFIX, FROM_DISP2,   NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, DST, E}}, {{PREFIX, FROM_DISP16,  NIB1, NIB2, DISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, DST, E}}, {{PREFIX, FROM_DISP32,  NIB1, NIB2, DISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXB16,  DST, E}}, {{PREFIX, FROM_DISP16B, NIB1, NIB2, DISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXW16,  DST, E}}, {{PREFIX, FROM_DISP16W, NIB1, NIB2, DISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXL16,  DST, E}}, {{PREFIX, FROM_DISP16L, NIB1, NIB2, DISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXB32,  DST, E}}, {{PREFIX, FROM_DISP32B, NIB1, NIB2, DISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXW32,  DST, E}}, {{PREFIX, FROM_DISP32W, NIB1, NIB2, DISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXL32,  DST, E}}, {{PREFIX, FROM_DISP32L, NIB1, NIB2, DISP32LIST, E}}}
+
+/* Expansion from immediate source to "standard" destinations.  */
+#define EXPAND2_STD_IMM(CODE, WEIGHT, NAME, SRC, PREFIX, OPCODE, IGN, IMMLIST) \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, OPCODE, IGN, IMMLIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, OPCODE, IGN, IMMLIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}}, {{PREFIX, TO_PREINC,  OPCODE, IGN, IMMLIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}}, {{PREFIX, TO_PREDEC,  OPCODE, IGN, IMMLIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}}, {{PREFIX, TO_DISP2,   OPCODE, IGN, IMMLIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16,  OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32,  OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, TO_DISP16W, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, TO_DISP16L, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, TO_DISP32B, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, TO_DISP32W, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, TO_DISP32L, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}
+
+/* Expansion from abs/disp source to "standard" destinations.  */
+#define EXPAND2_STD_ABSDISP(CODE, WEIGHT, NAME, SRC, PREFIX, DSTLIST, NIB1, NIB2) \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, DSTLIST, TO_POSTINC, NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, DSTLIST, TO_POSTDEC, NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}}, {{PREFIX, DSTLIST, TO_PREINC,  NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}}, {{PREFIX, DSTLIST, TO_PREDEC,  NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}}, {{PREFIX, DSTLIST, TO_DISP2,   NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, DSTLIST, TO_DISP16,  NIB1, NIB2, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, DSTLIST, TO_DISP32,  NIB1, NIB2, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, DSTLIST, TO_DISP16B, NIB1, NIB2, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, DSTLIST, TO_DISP16W, NIB1, NIB2, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, DSTLIST, TO_DISP16L, NIB1, NIB2, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, DSTLIST, TO_DISP32B, NIB1, NIB2, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, DSTLIST, TO_DISP32W, NIB1, NIB2, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, DSTLIST, TO_DISP32L, NIB1, NIB2, DSTDISP32LIST, E}}}
+
+/* Expansion from ind source to "standard" destinations.  */
+#define EXPAND2_STD_IND(CODE, WEIGHT, NAME, OPCODE, BIT) \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPOSTINC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_POSTINC, OPCODE, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPOSTDEC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_POSTDEC, OPCODE, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPREINC,  E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_PREINC,  OPCODE, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPREDEC,  E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_PREDEC,  OPCODE, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, DISP2DST,  E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP2,   OPCODE, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, DISP16DST, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16,  OPCODE, IGNORE, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, DISP32DST, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32,  OPCODE, IGNORE, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXB16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16B, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXW16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16W, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXL16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16L, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXB32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32B, OPCODE, IGNORE, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXW32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32W, OPCODE, IGNORE, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXL32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32L, OPCODE, IGNORE, DSTDISP32LIST, E}}}
+
+/*
+ * Expansion macros for three word (plus data) instructions.
+ */
+
+#define EXPAND3_STD_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, INFIX, OPCODE)  \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, INFIX,  8, RDPOSTINC, OPCODE, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, INFIX, 10, RDPOSTDEC, OPCODE, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}}, {{PREFIX, INFIX,  9, RDPREINC,  OPCODE, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}}, {{PREFIX, INFIX, 11, RDPREDEC,  OPCODE, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}}, {{PREFIX, INFIX, B30 | B20 | DISP2DST, DSTDISPREG, OPCODE, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, INFIX, 12, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, INFIX, 12, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, INFIX, 13, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, INFIX, 14, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, INFIX, 15, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, INFIX, 13, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, INFIX, 14, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, INFIX, 15, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}
+
+#define EXPAND3_L_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, INFIX, OPCODE)  \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND,     E}}, {{PREFIX, INFIX,  0, RDIND,     OPCODE, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, INFIX,  8, RDPOSTINC, OPCODE, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, INFIX, 10, RDPOSTDEC, OPCODE, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}}, {{PREFIX, INFIX,  9, RDPREINC,  OPCODE, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}}, {{PREFIX, INFIX, 11, RDPREDEC,  OPCODE, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}}, {{PREFIX, INFIX, B30 | B20 | DISP2DST, DSTDISPREG, OPCODE, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, INFIX, 12, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, INFIX, 12, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, INFIX, 13, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, INFIX, 14, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, INFIX, 15, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, INFIX, 13, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, INFIX, 14, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, INFIX, 15, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST,  E}}, {{PREFIX, INFIX,  4, B30 | IGNORE,     OPCODE, B30 | IGNORE, DSTABS16LIST,  E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST,  E}}, {{PREFIX, INFIX,  4, B31 | IGNORE,     OPCODE, B30 | IGNORE, DSTABS32LIST,  E}}}
+
+
+#define EXPAND_STD_MATRIX_L(CODE, NAME, OPCODE) \
+  EXPAND3_L_SRC (CODE, 6, NAME, RSIND,     PREFIX_0104,   TFROM_IND,     OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, RSPOSTINC, PREFIX_0104,   TFROM_POSTINC, OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, RSPOSTDEC, PREFIX_0106,   TFROM_POSTDEC, OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, RSPREINC,  PREFIX_0105,   TFROM_PREINC,  OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, RSPREDEC,  PREFIX_0107,   TFROM_PREDEC,  OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, DISP2SRC,  PREFIX_010_D2, TFROM_DISP2,   OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, DISP16SRC, PREFIX_0104,   TFROM_DISP16,  OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, DISP32SRC, PREFIX_78R4,   TFROM_DISP32,  OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, INDEXB16,  PREFIX_0105,   TFROM_DISP16B, OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, INDEXW16,  PREFIX_0106,   TFROM_DISP16W, OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, INDEXL16,  PREFIX_0107,   TFROM_DISP16L, OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, INDEXB32,  PREFIX_78R5,   TFROM_DISP32B, OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, INDEXW32,  PREFIX_78R6,   TFROM_DISP32W, OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, INDEXL32,  PREFIX_78R7,   TFROM_DISP32L, OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, ABS16SRC,  PREFIX_0104,   TFROM_ABS16,   OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, ABS32SRC,  PREFIX_0104,   TFROM_ABS32,   OPCODE)
+
+
+#define EXPAND_STD_MATRIX_W(CODE, NAME, OPCODE) \
+  EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTINC, PREFIX_0154,   TFROM_POSTINC, OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTDEC, PREFIX_0156,   TFROM_POSTDEC, OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, RSPREINC,  PREFIX_0155,   TFROM_PREINC,  OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, RSPREDEC,  PREFIX_0157,   TFROM_PREDEC,  OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, DISP2SRC,  PREFIX_015_D2, TFROM_DISP2,   OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, DISP16SRC, PREFIX_0154,   TFROM_DISP16,  OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, DISP32SRC, PREFIX_78R4W,  TFROM_DISP32,  OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, INDEXB16,  PREFIX_0155,   TFROM_DISP16B, OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, INDEXW16,  PREFIX_0156,   TFROM_DISP16W, OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, INDEXL16,  PREFIX_0157,   TFROM_DISP16L, OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, INDEXB32,  PREFIX_78R5W,  TFROM_DISP32B, OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, INDEXW32,  PREFIX_78R6W,  TFROM_DISP32W, OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, INDEXL32,  PREFIX_78R7W,  TFROM_DISP32L, OPCODE)
+
+#define EXPAND_STD_MATRIX_B(CODE, NAME, OPCODE) \
+  EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTINC, PREFIX_0174,    TFROM_POSTINC_B, OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTDEC, PREFIX_0176,    TFROM_POSTDEC_B, OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, RSPREINC,  PREFIX_0175,    TFROM_PREINC_B,  OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, RSPREDEC,  PREFIX_0177,    TFROM_PREDEC_B,  OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, DISP2SRC,  PREFIX_017_D2S, TFROM_DISP2_B,   OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, DISP16SRC, PREFIX_0174,    TFROM_DISP16_B,  OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, DISP32SRC, PREFIX_78R4W,   TFROM_DISP32_B,  OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, INDEXB16,  PREFIX_0175,    TFROM_DISP16B_B, OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, INDEXW16,  PREFIX_0176,    TFROM_DISP16W_B, OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, INDEXL16,  PREFIX_0177,    TFROM_DISP16L_B, OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, INDEXB32,  PREFIX_78R5W,   TFROM_DISP32B_B, OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, INDEXW32,  PREFIX_78R6W,   TFROM_DISP32W_B, OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, INDEXL32,  PREFIX_78R7W,   TFROM_DISP32L_B, OPCODE)
+
+
+/*
+ * Use the expansion macros to fill out the opcode table.
+ */
+
+#define EXPAND_FROM_REG8(CODE, NAME, OP1, OP2, OP3) \
+  {CODE, AV_H8SX, 0, NAME, {{RS8, RDIND,     E}}, {{0x7, 0xd, B30 | RDIND, IGNORE,             OP1, OP2, RS8, IGNORE, E}}}, \
+  EXPAND2_STD_SRC (CODE, 2, NAME, RS8, PREFIX_0179, OP3, RS8), \
+  {CODE, AV_H8SX, 0, NAME, {{RS8, ABS8DST,   E}}, {{0x7, 0xf, DSTABS8LIST,                     OP1, OP2, RS8, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RS8, ABS16DST,  E}}, {{0x6, 0xa, 0x1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, RS8, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RS8, ABS32DST,  E}}, {{0x6, 0xa, 0x3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, RS8, IGNORE, E}}}
+
+#define EXPAND_TO_REG8(CODE, NAME, OP1, OP2, OP3) \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, RD8,     E}}, {{0x7, 0xc, B30 | RSIND, IGNORE,          OP1, OP2, IGNORE, RD8, E}}}, \
+  EXPAND2_STD_DST (CODE, 2, NAME, RD8, PREFIX_017A, OP3, RD8), \
+  {CODE, AV_H8SX, 0, NAME, {{ABS8SRC,  RD8,  E}}, {{0x7, 0xe, ABS8LIST,                     OP1, OP2, IGNORE, RD8, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD8,  E}}, {{0x6, 0xa, 0x1, B30 | IGNORE, ABS16LIST, OP1, OP2, IGNORE, RD8, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD8,  E}}, {{0x6, 0xa, 0x3, B30 | IGNORE, ABS32LIST, OP1, OP2, IGNORE, RD8, E}}}
+
+#define EXPAND_FROM_IND8(CODE, NAME, OPCODE) \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, RDIND,    E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_IND,   OPCODE, IGNORE, E}}}, \
+  EXPAND2_STD_IND (CODE, 2, NAME, OPCODE, B30), \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS16DST, E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS32DST, E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}}
+
+#define EXPAND_FROM_ABS16_B(CODE, NAME, OPCODE) \
+  {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RDIND,    E}}, {{PREFIX_6A15, ABS16LIST, TO_IND,   OPCODE, IGNORE, E}}}, \
+  EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS16SRC, PREFIX_6A15, ABS16LIST, OPCODE, IGNORE), \
+  {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS16DST, E}}, {{PREFIX_6A15, ABS16LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS32DST, E}}, {{PREFIX_6A15, ABS16LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}}
+
+#define EXPAND_FROM_ABS32_B(CODE, NAME, OPCODE) \
+  {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RDIND,    E}}, {{PREFIX_6A35, ABS32LIST, TO_IND,   OPCODE, IGNORE, E}}}, \
+  EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS32SRC, PREFIX_6A35, ABS32LIST, OPCODE, IGNORE), \
+  {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS16DST, E}}, {{PREFIX_6A35, ABS32LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS32DST, E}}, {{PREFIX_6A35, ABS32LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}}
+
+#define EXPAND_FROM_IMM16_W(CODE, NAME, OPCODE) \
+  {CODE, AV_H8SX, 0, NAME, {{IMM16, RDIND,    E}}, {{PREFIX_015E, TO_IND, OPCODE, IGNORE, IMM16LIST, E}}}, \
+  EXPAND2_STD_IMM (CODE, 2, NAME, IMM16, PREFIX_015E, OPCODE, IGNORE, IMM16LIST), \
+  {CODE, AV_H8SX, 0, NAME, {{IMM16, ABS16DST, E}}, {{PREFIX_015E, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, IMM16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM16, ABS32DST, E}}, {{PREFIX_015E, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, IMM16LIST, E}}}
+
+#define EXPAND_FROM_REG16(CODE, NAME, OP1, OP2, OP3) \
+  {CODE, AV_H8,   2, NAME, {{RS16, RDIND,    E}}, {{0x7, 0xd, B31 | RDIND, IGNORE,             OP1, OP2, RS16, IGNORE, E}}}, \
+  EXPAND2_STD_SRC (CODE, 2, NAME, RS16, PREFIX_0159, OP3, RS16), \
+  {CODE, AV_H8SX, 0, NAME, {{RS16, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, RS16, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RS16, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, RS16, IGNORE, E}}}
+
+#define EXPAND_TO_REG16(CODE, NAME, OP1, OP2, OP3) \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, RD16,    E}}, {{0x7, 0xc, B31 | RSIND, IGNORE,          OP1, OP2, IGNORE, RD16, E}}}, \
+  EXPAND2_STD_DST (CODE, 2, NAME, RD16, PREFIX_015A, OP3, RD16), \
+  {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD16, E}}, {{0x6, 0xb, 0x1, B30 | IGNORE, ABS16LIST, OP1, OP2, IGNORE, RD16, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD16, E}}, {{0x6, 0xb, 0x3, B30 | IGNORE, ABS32LIST, OP1, OP2, IGNORE, RD16, E}}}
+
+#define EXPAND_FROM_IND16(CODE, NAME, OPCODE) \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, RDIND,    E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_IND, OPCODE, IGNORE, E}}}, \
+  EXPAND2_STD_IND (CODE, 2, NAME, OPCODE, B31), \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS16DST, E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS32DST, E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}}
+
+#define EXPAND_FROM_ABS16_W(CODE, NAME, OPCODE) \
+  {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RDIND,    E}}, {{PREFIX_6B15, ABS16LIST, TO_IND,   OPCODE, IGNORE, E}}}, \
+  EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS16SRC, PREFIX_6B15, ABS16LIST, OPCODE, IGNORE), \
+  {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS16DST, E}}, {{PREFIX_6B15, ABS16LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS32DST, E}}, {{PREFIX_6B15, ABS16LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}}
+
+#define EXPAND_FROM_ABS32_W(CODE, NAME, OPCODE) \
+  {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RDIND,    E}}, {{PREFIX_6B35, ABS32LIST, TO_IND,   OPCODE, IGNORE, E}}}, \
+  EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS32SRC, PREFIX_6B35, ABS32LIST, OPCODE, IGNORE), \
+  {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS16DST, E}}, {{PREFIX_6B35, ABS32LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS32DST, E}}, {{PREFIX_6B35, ABS32LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}}
+
+#define EXPAND_FROM_IMM16_L(CODE, NAME, OPCODE) \
+  {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, RDIND,    E}}, {{PREFIX_010E, TO_IND, OPCODE, B30 | IGNORE, IMM16ULIST, E}}}, \
+  EXPAND2_STD_IMM (CODE, 2, NAME, IMM16U_NS, PREFIX_010E, OPCODE, B30 | IGNORE, IMM16ULIST), \
+  {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, ABS16DST, E}}, {{PREFIX_010E, TO_ABS16, OPCODE, B30 | IGNORE, DSTABS16LIST, IMM16ULIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, ABS32DST, E}}, {{PREFIX_010E, TO_ABS32, OPCODE, B30 | IGNORE, DSTABS32LIST, IMM16ULIST, E}}}
+
+#define EXPAND_FROM_IMM32_L(CODE, NAME, OPCODE) \
+  {CODE, AV_H8SX, 0, NAME, {{IMM32, RDIND,    E}}, {{PREFIX_010E, TO_IND, OPCODE, B31 | IGNORE, IMM32LIST, E}}}, \
+  EXPAND2_STD_IMM (CODE, 2, NAME, IMM32, PREFIX_010E, OPCODE, B31 | IGNORE, IMM32LIST), \
+  {CODE, AV_H8SX, 0, NAME, {{IMM32, ABS16DST, E}}, {{PREFIX_010E, TO_ABS16, OPCODE, B31 | IGNORE, DSTABS16LIST, IMM32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM32, ABS32DST, E}}, {{PREFIX_010E, TO_ABS32, OPCODE, B31 | IGNORE, DSTABS32LIST, IMM32LIST, E}}}
+
+#define EXPAND_FROM_REG32(CODE, NAME, OPCODE) \
+  {CODE, AV_H8SX, 0, NAME, {{RS32, RDIND,    E}}, {{PREFIX_0109, TO_IND,   OPCODE, B30 | RS32, E}}}, \
+  EXPAND2_STD_SRC (CODE, 2, NAME, RS32, PREFIX_0109, OPCODE, B30 | RS32), \
+  {CODE, AV_H8SX, 0, NAME, {{RS32, ABS16DST, E}}, {{PREFIX_0109, TO_ABS16, OPCODE, B30 | RS32, DSTABS16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RS32, ABS32DST, E}}, {{PREFIX_0109, TO_ABS32, OPCODE, B30 | RS32, DSTABS32LIST, E}}}
+
+#define EXPAND_TO_REG32(CODE, NAME, OPCODE) \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, RD32,    E}}, {{PREFIX_010A, FROM_IND,   OPCODE, B30 | RD32, E}}}, \
+  EXPAND2_STD_DST (CODE, 2, NAME, RD32, PREFIX_010A, OPCODE, B30 | RD32), \
+  {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD32, E}}, {{PREFIX_010A, FROM_ABS16, OPCODE, B30 | RD32, ABS16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD32, E}}, {{PREFIX_010A, FROM_ABS32, OPCODE, B30 | RD32, ABS32LIST, E}}}
+
+
+#define EXPAND_TWOOP_B(CODE, NAME, OP1, OP2, OP3, OP4, BIT) \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, RDIND,     E}}, {{0x7, 0xd,                 B30 | RDIND,            IGNORE,                      OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPOSTINC, E}}, {{PREFIX_0174,    0x6, 0xc, B30 | RDPOSTINC,  B31 | B20 | IGNORE,                OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPOSTDEC, E}}, {{PREFIX_0176,    0x6, 0xc, B30 | RDPOSTDEC,  B31 | B20 | IGNORE,                OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPREINC,  E}}, {{PREFIX_0175,    0x6, 0xc, B30 | RDPREINC,   B31 | B20 | IGNORE,                OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPREDEC,  E}}, {{PREFIX_0177,    0x6, 0xc, B30 | RDPREDEC,   B31 | B20 | IGNORE,                OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, DISP2DST,  E}}, {{PREFIX_017_D2D, 0x6, 0x8, B30 | DSTDISPREG, B31 | B20 | IGNORE,                OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, DISP16DST, E}}, {{PREFIX_0174,    0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, DISP32DST, E}}, {{PREFIX_78R4WD,  0x6, 0xa, 2,                B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXB16D, E}}, {{PREFIX_0175,    0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXW16D, E}}, {{PREFIX_0176,    0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXL16D, E}}, {{PREFIX_0177,    0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXB32D, E}}, {{PREFIX_78R5WD,  0x6, 0xa, 2,                B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXW32D, E}}, {{PREFIX_78R6WD,  0x6, 0xa, 2,                B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXL32D, E}}, {{PREFIX_78R7WD,  0x6, 0xa, 2,                B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, ABS8DST,   E}}, {{0x7, 0xf,                                                       DSTABS8LIST,   OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, ABS16DST,  E}}, {{0x6, 0xa, 0x1,                              B31 | B20 | IGNORE, DSTABS16LIST,  OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, ABS32DST,  E}}, {{0x6, 0xa, 0x3,                              B31 | B20 | IGNORE, DSTABS32LIST,  OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8,   2, NAME, {{RS8,  RD8,       E}}, {{OP2, OP3, RS8, RD8, E}}}, \
+  EXPAND_FROM_REG8      (CODE, NAME, OP2, OP3, OP4), \
+  EXPAND_TO_REG8        (CODE, NAME, OP2, OP3, OP4), \
+  EXPAND_FROM_IND8      (CODE, NAME, OP4), \
+  EXPAND_STD_MATRIX_B   (CODE, NAME, OP4), \
+  EXPAND_FROM_ABS16_B   (CODE, NAME, OP4), \
+  EXPAND_FROM_ABS32_B   (CODE, NAME, OP4)
+
+#define EXPAND_TWOOP_W(CODE, NAME, OP1, OP2, OP3) \
+  {CODE, AV_H8H,  6, NAME, {{IMM16, RD16, E}}, {{0x7, 0x9, OP3, RD16, IMM16LIST, E}}}, \
+  EXPAND_FROM_IMM16_W   (CODE, NAME, OP3), \
+  EXPAND_FROM_REG16     (CODE, NAME, OP1, OP2, OP3), \
+  EXPAND_TO_REG16       (CODE, NAME, OP1, OP2, OP3), \
+  EXPAND_FROM_IND16     (CODE, NAME, OP3), \
+  EXPAND_STD_MATRIX_W   (CODE, NAME, OP3), \
+  EXPAND_FROM_ABS16_W   (CODE, NAME, OP3), \
+  EXPAND_FROM_ABS32_W   (CODE, NAME, OP3)
+
+#define EXPAND_TWOOP_L(CODE, NAME, OP1)  \
+  {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, RD32, E}}, {{0x7, 0xa, OP1, B31 | RD32, IMM16ULIST, E}}}, \
+  {CODE, AV_H8H,  6, NAME, {{IMM32,     RD32, E}}, {{0x7, 0xa, OP1, B30 | RD32, IMM32LIST,  E}}}, \
+  EXPAND_FROM_IMM16_L   (CODE, NAME, OP1), \
+  EXPAND_FROM_IMM32_L   (CODE, NAME, OP1), \
+  EXPAND_FROM_REG32     (CODE, NAME, OP1), \
+  EXPAND_TO_REG32       (CODE, NAME, OP1), \
+  EXPAND_STD_MATRIX_L   (CODE, NAME, OP1)
+
+
+/*
+ * Old expanders: 
+ */
+
+#define BITOP(code, imm, name, op00, op01, op10,  op11, op20, op21, op30, op4) \
+  {code, AV_H8,  2, name, {{imm, RD8,      E}}, {{op00, op01, imm,  RD8,   E}}}, \
+  {code, AV_H8,  6, name, {{imm, RDIND,    E}}, {{op10, op11, B30 | RDIND, 0,  op00, op01, imm, 0, E}}}, \
+  {code, AV_H8,  6, name, {{imm, ABS8DST,  E}}, {{op20, op21, DSTABS8LIST,     op00, op01, imm, 0, E}}}, \
+  {code, AV_H8H, 6, name, {{imm, ABS16DST, E}}, {{0x6,  0xa,  0x1,  op30, DST | ABS16LIST, op00, op01, imm, op4, E}}}, \
+  {code, AV_H8H, 6, name, {{imm, ABS32DST, E}}, {{0x6,  0xa,  0x3,  op30, DST | ABS32LIST, op00, op01, imm, op4, E}}}
+
+#define BITOP_B(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \
+  {code, AV_H8SX, 0, name, {{imm, RDIND,    E}}, {{op10, op11, B30 | RDIND, 0,  op00, op01, imm, op4, E}}}, \
+  {code, AV_H8SX, 0, name, {{imm, ABS8DST,  E}}, {{op20, op21, DSTABS8LIST,     op00, op01, imm, op4, E}}}, \
+  {code, AV_H8SX, 0, name, {{imm, ABS16DST, E}}, {{0x6,  0xa,  0x1,  op30, DST | ABS16LIST, op00, op01, imm, op4, E}}}, \
+  {code, AV_H8SX, 0, name, {{imm, ABS32DST, E}}, {{0x6,  0xa,  0x3,  op30, DST | ABS32LIST, op00, op01, imm, op4, E}}}
+
+#define EBITOP(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \
+  BITOP(code, imm, name, op00+1, op01, op10, op11, op20, op21, op30, op4), \
+  BITOP(code, RS8, name, op00,   op01, op10, op11, op20, op21, op30, op4)
+
+#define EBITOP_B(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \
+  BITOP_B(code, imm, name, op00+1, op01, op10, op11, op20, op21, op30, op4), \
+  BITOP_B(code, RS8, name, op00,   op01, op10, op11, op20, op21, op30, op4)
+
+#define WTWOP(code, name, op1, op2) \
+  {code, AV_H8, 2, name, {{RS16, RD16, E}}, {{op1, op2, RS16, RD16, E}}}
 
 #define BRANCH(code, name, op) \
-{ code, 1, 4,name,{{DISP8,E,0}}, {{ 0x4, op, DISP8, IGNORE, E, 0, 0, 0, 0}}}, \
-{ code, 0, 6,name,{{DISP16,E,0}}, {{ 0x5, 0x8, op, 0x0, DISP16, IGNORE, IGNORE, IGNORE, E,0}}} 
-
-#define SOP(code, x,name) \
-{code, 1, x,  name 
-
-#define NEW_SOP(code, in,x,name) \
-{code, in, x,  name 
-#define EOP  }
-
-#define TWOOP(code, name, op1, op2,op3) \
-{ code,1, 2,name, {{IMM8, RD8, E}},	{{ op1, RD8, IMM8, IGNORE, E, 0, 0, 0, 0}}},\
-{ code, 1, 2,name, {{RS8, RD8, E}},	{{ op2, op3, RS8, RD8, E, 0, 0, 0, 0}}} 
-
-#define UNOP(code,name, op1, op2) \
-{ code, 1, 2, name, {{OR8, E, 0}}, {{ op1, op2, 0, OR8, E, 0, 0, 0, 0}}}
-
-#define UNOP3(code, name, op1, op2, op3) \
-{ O(code,SB), 1, 2, name, {{OR8,  E, 0}}, {{op1, op2, op3+0, OR8,  E, 0, 0, 0, 0}}}, \
-{ O(code,SW), 0, 2, name, {{OR16, E, 0}}, {{op1, op2, op3+1, OR16, E, 0, 0, 0, 0}}}, \
-{ O(code,SL), 0, 2, name, {{OR32, E, 0}}, {{op1, op2, op3+3, OR32|B30, E, 0, 0, 0, 0}}} \
-,{ O(code,SB), 1, 2, name, {{IMM, OR8 | SRC_IN_DST,  E}}, {{op1, op2, op3+4, OR8 | SRC_IN_DST,  E, 0, 0, 0, 0}}}, \
-{ O(code,SW), 0, 2, name, {{IMM, OR16 | SRC_IN_DST, E}}, {{op1, op2, op3+5, OR16 | SRC_IN_DST, E, 0, 0, 0, 0}}}, \
-{ O(code,SL), 0, 2, name, {{IMM, OR32 | SRC_IN_DST, E}}, {{op1, op2, op3+7, OR32 | SRC_IN_DST|B30 , E, 0, 0, 0, 0}}}
-
-
-#define IMM32LIST IMM32,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
-#define IMM24LIST IMM24,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
-#define IMM16LIST IMM16,IGNORE,IGNORE,IGNORE
-#define A16LIST L_16,IGNORE,IGNORE,IGNORE
-#define DISP24LIST DISP|L_24,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
-#define DISP32LIST DISP|L_32,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
-#define ABS24LIST ABS|L_24,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
-#define ABS32LIST ABS|L_32,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
-#define A24LIST L_24,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
-#define A32LIST L_32,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
-#define PREFIX32 0x0,0x1,0x0,0x0
-#define PREFIXLDC 0x0,0x1,0x4,0x0
-
-
-#define O(op, size) (op * 4 + size)
-
-#define O_RECOMPILE 0
-#define O_ADD  1
-#define O_ADDX 2
-#define O_AND  3
-#define O_BAND 4
-#define O_BRA  5
-#define O_BRN  6
-#define O_BHI  7
-#define O_BLS  8
-#define O_BCC  9
-#define O_BCS  10
-#define O_BNE  11  
-#define O_BVC  12
-#define O_BVS  13
-#define O_BPL  14
-#define O_BMI  15
-#define O_BGE  16
-#define O_BLT  17
-#define O_BGT  18
-#define O_BLE  19
-#define O_ANDC 20
-#define O_BEQ 21
-#define O_BCLR 22
-#define O_BIAND 23
-#define O_BILD 24
-#define O_BIOR 25
-#define O_BIXOR 26
-#define O_BIST 27
-#define O_BLD 28
-#define O_BNOT 29
-#define O_BSET 30
-#define O_BSR 31
-#define O_BXOR 32
-#define O_CMP 33
-#define O_DAA 34
-#define O_DAS 35
-#define O_DEC 36
-#define O_DIVU 37
-#define O_DIVS 38
-#define O_INC 39
-#define O_LDC 40
-#define O_MOV_TO_MEM 41
-#define O_OR 42
-#define O_ROTL 43
-#define O_ROTR 44
-#define O_ROTXL 45
-#define O_ROTXR 46
-#define O_BPT 47
-#define O_SHAL 48
-#define O_SHAR 49
-#define O_SHLL 50
-#define O_SHLR 51
-#define O_SUB  52
-#define O_SUBS 53
-#define O_TRAPA 54
-#define O_XOR 55
-#define O_XORC 56
-#define O_BOR 57
-#define O_BST 58
-#define O_BTST 59
-#define O_EEPMOV 60
-#define O_EXTS 61
-#define O_EXTU 62
-#define O_JMP 63
-#define O_JSR 64
-#define O_MULU 65
-#define O_MULS 66
-#define O_NOP 67
-#define O_NOT 68
-#define O_ORC 69
-#define O_RTE 70
-#define O_STC 71
-#define O_SUBX 72
-#define O_NEG 73
-#define O_RTS 74
-#define O_SLEEP 75
-#define O_ILL 76
-#define O_ADDS 77
-#define O_SYSCALL 78
-#define O_MOV_TO_REG 79
-#define O_TAS 80
-#define O_CLRMAC 82
-#define O_LDMAC 83
-#define O_MAC 84
-#define O_LDM 85
-#define O_STM 86
-#define O_STMAC 87
-#define O_LAST 88
-/* Change made for System Call processing.  */
-#define O_SYS_CREAT 100
-#define O_SYS_OPEN 101
-#define O_SYS_READ 102
-#define O_SYS_WRITE 103
-#define O_SYS_LSEEK 104
-#define O_SYS_CLOSE 105
-#define O_SYS_STAT 106
-#define O_SYS_FSTAT 107
+  {code, AV_H8H, 6, name, {{PCREL16, E}}, {{0x5, 0x8, op, 0x0, PCREL16, DATA3 | B00, E}}}, \
+  {code, AV_H8,  4, name, {{PCREL8,  E}}, {{0x4, op,           PCREL8,  DATA  | B00, E}}}
+
+
+#define UNOP(code, name, op1, op2) \
+  {code, AV_H8, 2, name, {{OR8, E}}, {{op1, op2, 0, OR8, E}}}
+
+#define EXPAND_UNOP_STD_B(CODE, NAME, PREFIX, OP1, OP2, OP3) \
+  {CODE, AV_H8,   2, NAME, {{OR8,       E}}, {{                                                                  OP1, OP2, OP3, OR8,    E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND,     E}}, {{           7, 13, B30 | RSIND,             IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 12, B30 | RSPOSTINC,   B31 | IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 12, B30 | RSPOSTDEC,   B31 | IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPREINC,  E}}, {{PREFIX, 5, 6, 12, B30 | RSPREINC,    B31 | IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPREDEC,  E}}, {{PREFIX, 7, 6, 12, B30 | RSPREDEC,    B31 | IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{DISP2SRC,  E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6,  8, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 14, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B30 | DISPREG, 4,    6, 10, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXB16,  E}}, {{PREFIX, 5, 6, 14, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXW16,  E}}, {{PREFIX, 6, 6, 14, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXL16,  E}}, {{PREFIX, 7, 6, 14, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXB32,  E}}, {{7, 8, B30 | DISPREG, 5,    6, 10, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXW32,  E}}, {{7, 8, B30 | DISPREG, 6,    6, 10, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXL32,  E}}, {{7, 8, B30 | DISPREG, 7,    6, 10, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS8SRC,   E}}, {{                           7, 15,                   ABS8LIST,     OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS16SRC,  E}}, {{                           6, 10, 1, B31 | IGNORE,  ABS16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS32SRC,  E}}, {{                           6, 10, 3, B31 | IGNORE,  ABS32LIST,    OP1, OP2, OP3, IGNORE, E}}}
+
+#define EXPAND_UNOP_STD_W(CODE, NAME, PREFIX, OP1, OP2, OP3) \
+  {CODE, AV_H8H,  2, NAME, {{OR16,      E}}, {{                                                                  OP1, OP2, OP3, OR16,   E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND,     E}}, {{           7, 13, B31 | RSIND,             IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RSPOSTINC,   B31 | IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RSPOSTDEC,   B31 | IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPREINC,  E}}, {{PREFIX, 5, 6, 13, B30 | RSPREINC,    B31 | IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPREDEC,  E}}, {{PREFIX, 7, 6, 13, B30 | RSPREDEC,    B31 | IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{DISP2SRC,  E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6,  9, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 15, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B30 | DISPREG, 4,    6, 11, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXB16,  E}}, {{PREFIX, 5, 6, 15, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXW16,  E}}, {{PREFIX, 6, 6, 15, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXL16,  E}}, {{PREFIX, 7, 6, 15, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXB32,  E}}, {{7, 8, B30 | DISPREG, 5,    6, 11, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXW32,  E}}, {{7, 8, B30 | DISPREG, 6,    6, 11, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXL32,  E}}, {{7, 8, B30 | DISPREG, 7,    6, 11, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS16SRC,  E}}, {{                           6, 11, 1, B31 | IGNORE,  ABS16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS32SRC,  E}}, {{                           6, 11, 3, B31 | IGNORE,  ABS32LIST,    OP1, OP2, OP3, IGNORE, E}}}
+
+#define EXPAND_UNOP_STD_L(CODE, NAME, PREFIX, OP1, OP2, OP3) \
+  {CODE, AV_H8H,  2, NAME, {{OR32,      E}}, {{                                                                  OP1, OP2, OP3, B30 | OR32,   E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND,     E}}, {{PREFIX, 4, 6,  9, B30 | RSIND,       B31 | IGNORE,                OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RSPOSTINC,   B31 | IGNORE,                OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RSPOSTDEC,   B31 | IGNORE,                OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPREINC,  E}}, {{PREFIX, 5, 6, 13, B30 | RSPREINC,    B31 | IGNORE,                OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPREDEC,  E}}, {{PREFIX, 7, 6, 13, B30 | RSPREDEC,    B31 | IGNORE,                OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{DISP2SRC,  E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6,  9, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 15, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B31 | DISPREG, 4,    6, 11, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXB16,  E}}, {{PREFIX, 5, 6, 15, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXW16,  E}}, {{PREFIX, 6, 6, 15, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXL16,  E}}, {{PREFIX, 7, 6, 15, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXB32,  E}}, {{7, 8, B31 | DISPREG, 5,    6, 11, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXW32,  E}}, {{7, 8, B31 | DISPREG, 6,    6, 11, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXL32,  E}}, {{7, 8, B31 | DISPREG, 7,    6, 11, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS16SRC,  E}}, {{PREFIX, 4,                 6, 11, 0, B31 | IGNORE,  ABS16LIST,    OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS32SRC,  E}}, {{PREFIX, 4,                 6, 11, 2, B31 | IGNORE,  ABS32LIST,    OP1, OP2, OP3, B30 | IGNORE, E}}}
+
+#define EXPAND_UNOP_EXTENDED_B(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3) \
+  {CODE, AV_H8,   2, NAME, {{CONST, RD8,       E}}, {{                                                                     OP1, OP2, OP3, RD8,    E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDIND,     E}}, {{           7, 13, B30 | RDIND,             IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 12, B30 | RDPOSTINC,   B31 | IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 12, B30 | RDPOSTDEC,   B31 | IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC,  E}}, {{PREFIX, 5, 6, 12, B30 | RDPREINC,    B31 | IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC,  E}}, {{PREFIX, 7, 6, 12, B30 | RDPREDEC,    B31 | IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST,  E}}, {{PREFIX, B30 | B21 | DISP2DST, 6,  8, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 14, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 4, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 14, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 14, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 14, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 5, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 6, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 7, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, ABS8DST,   E}}, {{                           7, 15,                  DSTABS8LIST,      OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST,  E}}, {{                           6, 10, 1, B31 | IGNORE, DSTABS16LIST,     OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST,  E}}, {{                           6, 10, 3, B31 | IGNORE, DSTABS32LIST,     OP1, OP2, OP3, IGNORE, E}}}
+
+#define EXPAND_UNOP_EXTENDED_W(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3) \
+  {CODE, AV_H8,   2, NAME, {{CONST, RD16,      E}}, {{                                                                     OP1, OP2, OP3, RD16,   E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDIND,     E}}, {{           7, 13, B31 | RDIND,             IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RDPOSTINC,   B31 | IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RDPOSTDEC,   B31 | IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC,  E}}, {{PREFIX, 5, 6, 13, B30 | RDPREINC,    B31 | IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC,  E}}, {{PREFIX, 7, 6, 13, B30 | RDPREDEC,    B31 | IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST,  E}}, {{PREFIX, B30 | B21 | DISP2DST, 6,  9, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 15, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 4, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 15, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 15, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 15, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 5, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 6, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 7, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST,  E}}, {{                           6, 11, 1, B31 | IGNORE, DSTABS16LIST,     OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST,  E}}, {{                           6, 11, 3, B31 | IGNORE, DSTABS32LIST,     OP1, OP2, OP3, IGNORE, E}}}
+
+#define EXPAND_UNOP_EXTENDED_L(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3, BIT) \
+  {CODE, AV_H8,   2, NAME, {{CONST, RD32,      E}}, {{                                                                     OP1, OP2, OP3, BIT | RD32,   E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDIND,     E}}, {{PREFIX, 4, 6,  9, B30 | RDIND,       B31 | IGNORE,                   OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RDPOSTINC,   B31 | IGNORE,                   OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RDPOSTDEC,   B31 | IGNORE,                   OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC,  E}}, {{PREFIX, 5, 6, 13, B30 | RDPREINC,    B31 | IGNORE,                   OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC,  E}}, {{PREFIX, 7, 6, 13, B30 | RDPREDEC,    B31 | IGNORE,                   OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST,  E}}, {{PREFIX, B30 | B21 | DISP2DST, 6,  9, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 15, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B31 | DSTDISPREG, 4, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 15, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 15, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 15, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B31 | DSTDISPREG, 5, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B31 | DSTDISPREG, 6, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B31 | DSTDISPREG, 7, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST,  E}}, {{PREFIX, 4,                 6, 11, 0, B31 | IGNORE, DSTABS16LIST,     OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST,  E}}, {{PREFIX, 4,                 6, 11, 2, B31 | IGNORE, DSTABS32LIST,     OP1, OP2, OP3, BIT | IGNORE, E}}}
+
+#define PREFIXLDC 0x0, 0x1, 0x4, B30 | CCR_EXR | DST
+#define PREFIXSTC 0x0, 0x1, 0x4, B30 | CCR_EXR | SRC
+
+#define O(op, size)  (op*4+size)
+#define OP_SIZE(HOW) (HOW % 4)
+#define OP_KIND(HOW) (HOW / 4)
+
+enum h8_asm_codes {
+  O_RECOMPILE =	 0,
+  O_ADD,
+  O_ADDX,
+  O_AND,
+  O_BAND,
+  O_BRA,
+  O_BRAB,
+  O_BRAW,
+  O_BRAL,
+  O_BRAS,
+  O_BRABC,
+  O_BRABS,
+  O_BSRBC,
+  O_BSRBS,
+  O_BRN,
+  O_BHI,
+  O_BLS,
+  O_BCC,
+  O_BCS,
+  O_BNE,
+  O_BVC,
+  O_BVS,
+  O_BPL,
+  O_BMI,
+  O_BGE,
+  O_BLT,
+  O_BGT,
+  O_BLE,
+  O_ANDC,
+  O_BEQ,
+  O_BCLR,
+  O_BCLREQ,
+  O_BCLRNE,
+  O_BSETEQ,
+  O_BSETNE,
+  O_BFLD,
+  O_BFST,
+  O_BIAND,
+  O_BILD,
+  O_BIOR,
+  O_BIXOR,
+  O_BIST,
+  O_BISTZ,
+  O_BLD,
+  O_BNOT,
+  O_BOR,
+  O_BSET,
+  O_BSR,
+  O_BXOR,
+  O_CMP,
+  O_DAA,
+  O_DAS,
+  O_DEC,
+  O_DIVU,
+  O_DIVS,
+  O_DIVXU,
+  O_DIVXS,
+  O_INC,
+  O_LDC,
+  O_MOV,
+  O_MOVAB,
+  O_MOVAW,
+  O_MOVAL,
+  O_MOVMD,
+  O_MOVSD,
+  O_OR,
+  O_ROTL,
+  O_ROTR,
+  O_ROTXL,
+  O_ROTXR,
+  O_BPT,
+  O_SHAL,
+  O_SHAR,
+  O_SHLL,
+  O_SHLR,
+  O_SUB,
+  O_SUBS,
+  O_TRAPA,
+  O_XOR,
+  O_XORC,
+  O_BST,
+  O_BSTZ,
+  O_BTST,
+  O_EEPMOV,
+  O_EXTS,
+  O_EXTU,
+  O_JMP,
+  O_JSR,
+  O_MULU,
+  O_MULUU,
+  O_MULS,
+  O_MULSU,
+  O_MULXU,
+  O_MULXS,
+  O_NOP,
+  O_NOT,
+  O_ORC,
+  O_RTE,
+  O_RTEL,
+  O_STC,
+  O_SUBX,
+  O_NEG,
+  O_RTS,
+  O_RTSL,
+  O_SLEEP,
+  O_ILL,
+  O_ADDS,
+  O_SYSCALL,
+  O_TAS,
+  O_CLRMAC,
+  O_LDMAC,
+  O_MAC,
+  O_LDM,
+  O_STM,
+  O_STMAC,
+  O_LAST,
+  /* Change made for System Call processing.  */
+  O_SYS_CREAT,
+  O_SYS_OPEN,
+  O_SYS_READ,
+  O_SYS_WRITE,
+  O_SYS_LSEEK,
+  O_SYS_CLOSE,
+  O_SYS_STAT,
+  O_SYS_FSTAT,
 /* Space reserved for future file I/O system calls.  */
-#define O_SYS_CMDLINE 120
-/* End of System Call specific Changes.  */
-#define SB 0
-#define SW 1
-#define SL 2
-#define SN 3
+ O_SYS_CMDLINE
+  /* End of System Call specific Changes.  */
+};
+
+enum h8_size {
+  SB =	 0,
+  SW =	 1,
+  SL =	 2,
+  SN =	 3
+};
+
 
 /* FIXME: Lots of insns have "E, 0, 0, 0, 0" in the nibble code sequences.
    Methinks the zeroes aren't necessary.  Once confirmed, nuke 'em.  */
 
-const struct h8_opcode h8_opcodes[] = 
+struct h8_opcode h8_opcodes[] = 
 {
-  TWOOP(O(O_ADD,SB),"add.b", 0x8, 0x0,0x8),
-  
-  NEW_SOP(O(O_ADD,SW),1,2,"add.w"),{{RS16,RD16,E}},{{0x0,0x9,RS16,RD16,E}} EOP,
-  NEW_SOP(O(O_ADD,SW),0,4,"add.w"),{{IMM16,RD16,E}},{{0x7,0x9,0x1,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP,
-  NEW_SOP(O(O_ADD,SL),0,2,"add.l"),{{RS32,RD32,E }}, {{0x0,0xA,B31|RS32,B30|RD32,E}} EOP,
-  NEW_SOP(O(O_ADD,SL),0,6,"add.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x1,B30|RD32,IMM32LIST,E}} EOP,
-  NEW_SOP(O(O_ADDS,SL),1,2,"adds"), {{KBIT,RDP,E}},   {{0x0,0xB,KBIT,RDP,E,0,0,0,0}} EOP,
-
-  TWOOP(O(O_ADDX,SB),"addx",0x9,0x0,0xE),
-  TWOOP(O(O_AND,SB), "and.b",0xE,0x1,0x6),
-
-  NEW_SOP(O(O_AND,SW),0,2,"and.w"),{{RS16,RD16,E }},{{0x6,0x6,RS16,RD16,E}} EOP,
-  NEW_SOP(O(O_AND,SW),0,4,"and.w"),{{IMM16,RD16,E }},{{0x7,0x9,0x6,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP,
+  {O (O_ADD, SB), AV_H8,   2, "add.b", {{IMM8,      RD8,      E}}, {{0x8, RD8, IMM8LIST, E}}}, 
+  EXPAND_TWOOP_B (O (O_ADD, SB), "add.b", 0x8, 0x0, 0x8, 0x1, 0), 
+
+  {O (O_ADD, SW), AV_H8,   6, "add.w", {{RS16,      RD16,     E}}, {{0x0, 0x9, RS16,         RD16,   E}}}, 
+  {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, RD16,     E}}, {{0x0, 0xa, B30 | IMM3NZ, RD16,   E}}}, 
+  {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, RDIND,    E}}, {{0x7, 0xd,      B31 | RDIND,  IGNORE,       0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}}, 
+  {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}}, 
+  {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}}, 
+  EXPAND_TWOOP_W (O (O_ADD, SW), "add.w", 0x0, 0x9, 0x1), 
+
+  {O (O_ADD, SL), AV_H8H,  6, "add.l", {{RS32,      RD32,     E}}, {{0x0, 0xa, B31 | RS32,   B30 | RD32, E}}}, 
+  {O (O_ADD, SL), AV_H8SX, 0, "add.l", {{IMM3NZ_NS, RD32,     E}}, {{0x0, 0xa, B31 | IMM3NZ, B31 | RD32, E}}}, 
+  EXPAND_TWOOP_L (O (O_ADD, SL), "add.l", 0x1), 
+
+  {O (O_ADDS, SL), AV_H8,  2, "adds",  {{KBIT,  RDP,  E}}, {{0x0, 0xB,KBIT, RDP, E}}},
+
+  {O (O_ADDX, SB), AV_H8,   2, "addx",   {{IMM8,      RD8,       E}}, {{0x9, RD8, IMM8LIST, E}}},
+  {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{IMM8,      RDIND,     E}}, {{0x7, 0xd, B30 | RDIND, IGNORE,                        0x9, IGNORE, IMM8LIST, E}}},
+  {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{IMM8,      RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0x9, IGNORE, IMM8LIST, E}}},
+  {O (O_ADDX, SB), AV_H8,   2, "addx",   {{RS8,       RD8,       E}}, {{0x0, 0xe, RS8,  RD8,    E}}},
+  {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RS8,       RDIND,     E}}, {{0x7, 0xd, B30 | RDIND, IGNORE,                              0x0, 0xe, RS8, IGNORE, E}}},
+  {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RS8,       RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31       | IGNORE, 0x0, 0xe, RS8, IGNORE, E}}},
+  {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSIND,     RD8,       E}}, {{0x7, 0xc, B30 | RSIND, IGNORE,                              0x0, 0xe, IGNORE, RD8, E}}},
+  {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSPOSTDEC, RD8,       E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, B30 | B20 | IGNORE, 0x0, 0xe, IGNORE, RD8, E}}},
+  {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSIND,     RDIND,     E}}, {{PREFIX_0174, 0x6, 0x8, B30 | RSIND,     0xd, 0x0, RDIND,     0x1, IGNORE, E}}},
+  {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}},
+
+  {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16,     RD16,      E}}, {{PREFIX_0151,                         0x7, 0x9, 0x1, RD16,   IMM16LIST, E}}}, 
+  {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16,     RDIND,     E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x7, 0x9, 0x1, IGNORE, IMM16LIST, E}}}, 
+  {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16,     RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0x9, 0x1, IGNORE, IMM16LIST, E}}}, 
+  {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16,      RD16,      E}}, {{PREFIX_0151, 0x0, 0x9, RS16,  RD16,    E}}},
+  {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16,      RDIND,     E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x0, 0x9, RS16, IGNORE, E}}},
+  {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16,      RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x0, 0x9, RS16, IGNORE, E}}},
+  {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSIND,     RD16,      E}}, {{0x7, 0xc, B31 | RSIND, B01 | IGNORE, 0x0, 0x9, IGNORE, RD16, E}}},
+  {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSPOSTDEC, RD16,      E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x0, 0x9, IGNORE, RD16, E}}},
+  {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSIND,     RDIND,     E}}, {{PREFIX_0154, 0x6, 0x9, B30 | RSIND,     0xd, 0x0, RDIND,     0x1, IGNORE, E}}},
+  {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}},
+
+  {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32,     RD32,      E}}, {{PREFIX_0101, 0x7, 0xa, 0x1,  RD32, IMM32LIST, E}}},
+  {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32,     RDIND,     E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND,     B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x1, IGNORE, IMM32LIST, E}}},
+  {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32,     RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x1, IGNORE, IMM32LIST, E}}},
+  {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32,      RD32,      E}}, {{PREFIX_0101, 0x0, 0xa, B31 | RS32,  B30 | RD32,    E}}},
+  {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32,      RDIND,     E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND,     B31 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | RS32, B30 | IGNORE, E}}},
+  {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32,      RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | RS32, B30 | IGNORE, E}}},
+  {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSIND,     RD32,      E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND,     B30 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | IGNORE, B30 | RD32, E}}},
+  {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSPOSTDEC, RD32,      E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | IGNORE, B30 | RD32, E}}},
+  {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSIND,     RDIND,     E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND,     0xd, 0x0, RDIND,     0x1, IGNORE, E}}},
+  {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}},
+
+  {O (O_AND, SB), AV_H8,   2, "and.b", {{IMM8, RD8,  E}}, {{0xe, RD8, IMM8LIST, E}}}, 
+  EXPAND_TWOOP_B (O (O_AND, SB), "and.b", 0xe, 0x1, 0x6, 0x6, 0), 
+
+  {O (O_AND, SW), AV_H8,   2, "and.w", {{RS16, RD16, E}}, {{0x6, 0x6, RS16, RD16,   E}}}, 
+  EXPAND_TWOOP_W (O (O_AND, SW), "and.w", 0x6, 0x6, 0x6), 
+
+  {O (O_AND, SL), AV_H8H,  2, "and.l", {{RS32,  RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x6, B30 | RS32, B30 | RD32, E}}},
+  EXPAND_TWOOP_L (O (O_AND, SL), "and.l", 0x6), 
+
+  {O (O_ANDC, SB), AV_H8,  2, "andc", {{IMM8,  CCR | DST, E}}, {{0x0, 0x6, IMM8LIST, E}}},
+  {O (O_ANDC, SB), AV_H8S, 2, "andc", {{IMM8,  EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x6, IMM8LIST, E}}},
+
+  BRANCH (O (O_BRA, SB), "bra", 0x0),
+
+  {O (O_BRAB, SB), AV_H8SX, 0, "bra", {{LOWREG | L_8,  E}}, {{0x5, 0x9, LOWREG | L_8  | B30, 0x5, E}}},
+  {O (O_BRAW, SW), AV_H8SX, 0, "bra", {{LOWREG | L_16, E}}, {{0x5, 0x9, LOWREG | L_16 | B30, 0x6, E}}},
+  {O (O_BRAL, SL), AV_H8SX, 0, "bra", {{RS32, E}}, {{0x5, 0x9, RS32 | B30, 0x7, E}}},
+
+  {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, RDIND,    OP3PCREL8}},  {{0x7, 0xC, B30 | RDIND, 0x0,            0x4, B30 | IMM3,      OP3PCREL8,  DATA,  E}}},
+  {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS8DST,  OP3PCREL8}},  {{0x7, 0xE, DSTABS8LIST,                 0x4, B30 | IMM3,      OP3PCREL8,  DATA,  E}}},
+  {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS16DST, OP3PCREL8}},  {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST,      0x4, B30 | IMM3,      OP3PCREL8,  DATA,  E}}},
+  {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS32DST, OP3PCREL8}},  {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST,      0x4, B30 | IMM3,      OP3PCREL8,  DATA,  E}}},
+  {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, RDIND,    OP3PCREL8}},  {{0x7, 0xC, B30 | RDIND, 0x0,            0x4, B31 | IMM3,      OP3PCREL8,  DATA,  E}}},
+  {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS8DST,  OP3PCREL8}},  {{0x7, 0xE, DSTABS8LIST,                 0x4, B31 | IMM3,      OP3PCREL8,  DATA,  E}}},
+  {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS16DST, OP3PCREL8}},  {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST,      0x4, B31 | IMM3,      OP3PCREL8,  DATA,  E}}},
+  {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS32DST, OP3PCREL8}},  {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST,      0x4, B31 | IMM3,      OP3PCREL8,  DATA,  E}}},
+  {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, RDIND,    OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0,       0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS8DST,  OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST,            0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, RDIND,    OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0,       0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS8DST,  OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST,            0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
   
-  NEW_SOP(O(O_AND,SL),0,6,"and.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x6,B30|RD32,IMM32LIST,E}} EOP,
-  NEW_SOP(O(O_AND,SL),0,2,"and.l") ,{{RS32,RD32,E }},{{0x0,0x1,0xF,0x0,0x6,0x6,B30|RS32,B30|RD32,E}} EOP,
-
-  NEW_SOP(O(O_ANDC,SB),1,2,"andc"), {{IMM8,CCR|DST,E}},{{ 0x0,0x6,IMM8,IGNORE,E,0,0,0,0}} EOP,
-  NEW_SOP(O(O_ANDC,SB),1,2,"andc"), {{IMM8,EXR|DST,E}},{{ 0x0,0x1,0x4,0x1,0x0,0x6,IMM8,IGNORE,E,0,0,0,0}} EOP,
-
-  BITOP(O(O_BAND,SB), IMM3|B30,"band",0x7,0x6,0x7,0xC,0x7,0xE,0x0),
-  BRANCH(O(O_BRA,SB),"bra",0x0),
-  BRANCH(O(O_BRA,SB),"bt",0x0),
-  BRANCH(O(O_BRN,SB),"brn",0x1),
-  BRANCH(O(O_BRN,SB),"bf",0x1),
-  BRANCH(O(O_BHI,SB),"bhi",0x2),
-  BRANCH(O(O_BLS,SB),"bls",0x3),
-  BRANCH(O(O_BCC,SB),"bcc",0x4),
-  BRANCH(O(O_BCC,SB),"bhs",0x4),
-  BRANCH(O(O_BCS,SB),"bcs",0x5),
-  BRANCH(O(O_BCS,SB),"blo",0x5),
-  BRANCH(O(O_BNE,SB),"bne",0x6),
-  BRANCH(O(O_BEQ,SB),"beq",0x7),
-  BRANCH(O(O_BVC,SB),"bvc",0x8),
-  BRANCH(O(O_BVS,SB),"bvs",0x9),
-  BRANCH(O(O_BPL,SB),"bpl",0xA),
-  BRANCH(O(O_BMI,SB),"bmi",0xB),
-  BRANCH(O(O_BGE,SB),"bge",0xC),
-  BRANCH(O(O_BLT,SB),"blt",0xD),
-  BRANCH(O(O_BGT,SB),"bgt",0xE),
-  BRANCH(O(O_BLE,SB),"ble",0xF),
-
-  EBITOP(O(O_BCLR,SB),IMM3|B30,"bclr", 0x6,0x2,0x7,0xD,0x7,0xF,0x8),
-  BITOP(O(O_BIAND,SB),IMM3|B31,"biand",0x7,0x6,0x7,0xC,0x7,0xE,0x0),
-  BITOP(O(O_BILD,SB), IMM3|B31,"bild", 0x7,0x7,0x7,0xC,0x7,0xE,0x0),
-  BITOP(O(O_BIOR,SB), IMM3|B31,"bior", 0x7,0x4,0x7,0xC,0x7,0xE,0x0),
-  BITOP(O(O_BIST,SB), IMM3|B31,"bist", 0x6,0x7,0x7,0xD,0x7,0xF,0x8),
-  BITOP(O(O_BIXOR,SB),IMM3|B31,"bixor",0x7,0x5,0x7,0xC,0x7,0xE,0x0),
-  BITOP(O(O_BLD,SB),  IMM3|B30,"bld",  0x7,0x7,0x7,0xC,0x7,0xE,0x0),
-  EBITOP(O(O_BNOT,SB),IMM3|B30,"bnot", 0x6,0x1,0x7,0xD,0x7,0xF,0x8),
-  BITOP(O(O_BOR,SB),  IMM3|B30,"bor",  0x7,0x4,0x7,0xC,0x7,0xE,0x0),
-  EBITOP(O(O_BSET,SB),IMM3|B30,"bset", 0x6,0x0,0x7,0xD,0x7,0xF,0x8),
-
-  SOP(O(O_BSR,SB),6,"bsr"),{{DISP8,E,0}},{{ 0x5,0x5,DISP8,IGNORE,E,0,0,0,0}} EOP,
-  SOP(O(O_BSR,SB),6,"bsr"),{{DISP16,E,0}},{{ 0x5,0xC,0x0,0x0,DISP16,IGNORE,IGNORE,IGNORE,E,0,0,0,0}} EOP,
-  BITOP(O(O_BST,SB), IMM3|B30,"bst",0x6,0x7,0x7,0xD,0x7,0xF,0x8),
-  EBITOP(O(O_BTST,SB), IMM3|B30,"btst",0x6,0x3,0x7,0xC,0x7,0xE,0x0),
-  BITOP(O(O_BXOR,SB), IMM3|B30,"bxor",0x7,0x5,0x7,0xC,0x7,0xE,0x0),
-
-  TWOOP(O(O_CMP,SB), "cmp.b",0xA,0x1,0xC),
-  WTWOP(O(O_CMP,SW), "cmp.w",0x1,0xD),
-
-  NEW_SOP(O(O_CMP,SW),1,2,"cmp.w"),{{RS16,RD16,E }},{{0x1,0xD,RS16,RD16,E}} EOP,
-  NEW_SOP(O(O_CMP,SW),0,4,"cmp.w"),{{IMM16,RD16,E }},{{0x7,0x9,0x2,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP,
-
-  NEW_SOP(O(O_CMP,SL),0,6,"cmp.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x2,B30|RD32,IMM32LIST,E}} EOP,
-  NEW_SOP(O(O_CMP,SL),0,2,"cmp.l") ,{{RS32,RD32,E }},{{0x1,0xF,B31|RS32,B30|RD32,E}} EOP,
-
-  UNOP(O(O_DAA,SB), "daa",0x0,0xF),
-  UNOP(O(O_DAS,SB), "das",0x1,0xF),
-  UNOP(O(O_DEC,SB), "dec.b",0x1,0xA),
-
-  NEW_SOP(O(O_DEC, SW),0,2,"dec.w") ,{{DBIT,RD16,E }},{{0x1,0xB,0x5|DBIT,RD16,E}} EOP,
-  NEW_SOP(O(O_DEC, SL),0,2,"dec.l") ,{{DBIT,RD32,E }},{{0x1,0xB,0x7|DBIT,RD32|B30,E}} EOP,
-
-  NEW_SOP(O(O_DIVU,SB),1,13,"divxu.b"), {{RS8,RD16,E}}, {{0x5,0x1,RS8,RD16,E,0,0,0,0}}EOP,
-  NEW_SOP(O(O_DIVU,SW),0,21,"divxu.w"),{{RS16,RD32,E}},{{0x5,0x3,RS16,B30|RD32,E}}EOP,
-    
-  NEW_SOP(O(O_DIVS,SB),0,13,"divxs.b") ,{{RS8,RD16,E }},{{0x0,0x1,0xD,0x0,0x5,0x1,RS8,RD16,E}} EOP,
-  NEW_SOP(O(O_DIVS,SW),0,21,"divxs.w") ,{{RS16,RD32,E }},{{0x0,0x1,0xD,0x0,0x5,0x3,RS16,B30|RD32,E}} EOP,
-
-  NEW_SOP(O(O_EEPMOV,SB),1,4,"eepmov.b"),{{E,0,0}},{{0x7,0xB,0x5,0xC,0x5,0x9,0x8,0xF,E}}EOP,
-  NEW_SOP(O(O_EEPMOV,SW),0,4,"eepmov.w"),{{E,0,0}},{{0x7,0xB,0xD,0x4,0x5,0x9,0x8,0xF,E}} EOP,
-    
-  NEW_SOP(O(O_EXTS,SW),0,2,"exts.w"),{{OR16,E,0}},{{0x1,0x7,0xD,OR16,E   }}EOP,
-  NEW_SOP(O(O_EXTS,SL),0,2,"exts.l"),{{OR32,E,0}},{{0x1,0x7,0xF,OR32|B30,E   }}EOP,
-
-  NEW_SOP(O(O_EXTU,SW),0,2,"extu.w"),{{OR16,E,0}},{{0x1,0x7,0x5,OR16,E   }}EOP,
-  NEW_SOP(O(O_EXTU,SL),0,2,"extu.l"),{{OR32,E,0}},{{0x1,0x7,0x7,OR32|B30,E   }}EOP,
-    
-  UNOP(O(O_INC,SB), "inc",0x0,0xA),
-
-  NEW_SOP(O(O_INC,SW),0,2,"inc.w") ,{{DBIT,RD16,E }},{{0x0,0xB,0x5|DBIT,RD16,E}} EOP,
-  NEW_SOP(O(O_INC,SL),0,2,"inc.l") ,{{DBIT,RD32,E }},{{0x0,0xB,0x7|DBIT,RD32|B30,E}} EOP,
-
-  SOP(O(O_JMP,SB),4,"jmp"),{{RSIND,E,0}},{{0x5,0x9,B30|RSIND,0x0,E,0,0,0,0}}EOP,
-  SOP(O(O_JMP,SB),6,"jmp"),{{SRC|ABSJMP,E,0}},{{0x5,0xA,SRC|ABSJMP,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,E}}EOP,
-  SOP(O(O_JMP,SB),8,"jmp"),{{SRC|MEMIND,E,0}},{{0x5,0xB,SRC|MEMIND,IGNORE,E,0,0,0,0}}EOP,
-
-  SOP(O(O_JSR,SB),6,"jsr"),{{SRC|RSIND,E,0}}, {{0x5,0xD,B30|RSIND,0x0,E,0,0,0,0}}EOP,
-  SOP(O(O_JSR,SB),8,"jsr"),{{SRC|ABSJMP,E,0}},{{0x5,0xE,SRC|ABSJMP,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,E}}EOP,
-  SOP(O(O_JSR,SB),8,"jsr"),{{SRC|MEMIND,E,0}},{{0x5,0xF,SRC|MEMIND,IGNORE,E,0,0,0,0}}EOP,
-
-  NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{IMM8,CCR|DST,E}},         {{ 0x0,0x7,IMM8,IGNORE,E,0,0,0,0}}EOP,
-  NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{OR8,CCR|DST,E}},          {{ 0x0,0x3,0x0,OR8,E,0,0,0,0}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS16SRC,CCR|DST,E}},     {{PREFIXLDC,0x6,0xB,0x0,0x0,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS32SRC,CCR|DST,E}},     {{PREFIXLDC,0x6,0xB,0x2,0x0,SRC|ABS32LIST,E}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_16,CCR|DST,E}},{{PREFIXLDC,0x6,0xF,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_32,CCR|DST,E}},{{PREFIXLDC,0x7,0x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSINC,CCR|DST,E}},        {{PREFIXLDC,0x6,0xD,B30|RSINC,0x0,E}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSIND,CCR|DST,E}},        {{PREFIXLDC,0x6,0x9,B30|RSIND,0x0,E}} EOP,
-
-  NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{IMM8,EXR|DST,E}},         {{ 0x0,0x1,0x4,0x1,0x0,0x7,IMM8,IGNORE,E,0,0,0,0}}EOP,
-  NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{OR8,EXR|DST,E}},          {{ 0x0,0x3,0x1,OR8,E,0,0,0,0}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS16SRC,EXR|DST,E}},     {{ 0x0,0x1,0x4,0x1,0x6,0xb,0x0,0x0,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS32SRC,EXR|DST,E}},     {{ 0x0,0x1,0x4,0x1,0x6,0xb,0x2,0x0,SRC|ABS32LIST,E}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_16,EXR|DST,E}},{{ 0x0,0x1,0x4,0x1,0x6,0xf,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_32,EXR|DST,E}},{{ 0x0,0x1,0x4,0x1,0x7,0x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSINC,EXR|DST,E}},        {{ 0x0,0x1,0x4,0x1,0x6,0xd,B30|RSINC,0x0,E}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSIND,EXR|DST,E}},        {{ 0x0,0x1,0x4,0x1,0x6,0x9,B30|RSIND,0x0,E}} EOP,
-
-  SOP(O(O_MOV_TO_REG,SB),4,"mov.b"),{{ABS|SRC|L_16|MEMRELAX,RD8,E}},  {{ 0x6,0xA,0x0,RD8,SRC|ABS|MEMRELAX|A16LIST,E}}EOP,
-  SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{{ABS|SRC|L_32|MEMRELAX,RD8,E }}, {{ 0x6,0xA,0x2,RD8,SRC|ABS|MEMRELAX|A32LIST,E }}EOP,
-  SOP(O(O_MOV_TO_MEM,SB),4,"mov.b"),{{RS8,ABS|L_16|MEMRELAX|DST,E}},     {{ 0x6,0xA,0x8,RS8,DST|ABS|MEMRELAX|A16LIST,E}}EOP,
-  SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{{RS8,ABS|DST|L_32|MEMRELAX,E }},    {{ 0x6,0xA,0xA,RS8,DST|ABS|MEMRELAX|A32LIST,E }}EOP,
-    
-  SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{{DISP|L_32|SRC,RD8,E}},  {{ 0x7,0x8,B30|DISPREG,0x0,0x6,0xA,0x2,RD8,SRC|DISP32LIST,E}}EOP,
-  SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{{RS8,DISP|L_32|DST,E}},  {{ 0x7,0x8,B30|DISPREG,0x0,0x6,0xA,0xA,RS8,DST|DISP32LIST,E}}EOP,
-
-
-
-  SOP(O(O_MOV_TO_REG,SB),2,"mov.b"),{{RS8,RD8,E}},	    {{ 0x0,0xC,RS8,RD8,E,0,0,0,0}}EOP,
-  SOP(O(O_MOV_TO_REG,SB),2,"mov.b"),{{IMM8,RD8,E}},           {{ 0xF,RD8,IMM8,IGNORE,E,0,0,0,0}}EOP,
-  SOP(O(O_MOV_TO_REG,SB),4,"mov.b"),{{RSIND,RD8,E}},          {{ 0x6,0x8,B30|RSIND,RD8,E,0,0,0,0}}EOP,
-  SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{{DISP16SRC,RD8,E}},      {{ 0x6,0xE,B30|DISPREG,RD8,DISP16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
-  SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{{RSINC,RD8,E}},          {{ 0x6,0xC,B30|RSINC,RD8,E,0,0,0,0}}EOP,
-
-  SOP(O(O_MOV_TO_REG,SB),4,"mov.b"),{{ABS8SRC,RD8,E}},        {{ 0x2,RD8,ABS8SRC,IGNORE,E,0,0,0,0}}EOP,
-  SOP(O(O_MOV_TO_MEM,SB),4,"mov.b"),{{RS8,RDIND,E}},          {{ 0x6,0x8,RDIND|B31,RS8,E,0,0,0,0}}EOP,
-  SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{{RS8,DISP16DST,E}},      {{ 0x6,0xE,DISPREG|B31,RS8,DISP16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
-  SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{{RS8,RDDEC|B31,E}},      {{ 0x6,0xC,RDDEC|B31,RS8,E,0,0,0,0}}EOP,
-
-  SOP(O(O_MOV_TO_MEM,SB),4,"mov.b"),{{RS8,ABS8DST,E}},        {{ 0x3,RS8,ABS8DST,IGNORE,E,0,0,0,0}}EOP,
-
-  SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,RDIND,E}},        {{ 0x6,0x9,RDIND|B31,RS16,E,0,0,0,0}}EOP,
-  SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{{DISP|L_32|SRC,RD16,E}},{{ 0x7,0x8,B30|DISPREG,0x0,0x6,0xB,0x2,RD16,SRC|DISP32LIST,E}}EOP,
-  SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,DISP|L_32|DST,E}},{{ 0x7,0x8,B30|DISPREG,0x0,0x6,0xB,0xA,RS16,DST|DISP32LIST,E}}EOP,
-  SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{{ABS|L_32|MEMRELAX|SRC,RD16,E }},{{ 0x6,0xB,0x2,RD16,SRC|MEMRELAX|ABS32LIST,E }}EOP,
-  SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,ABS|L_32|MEMRELAX|DST,E }},{{ 0x6,0xB,0xA,RS16,DST|MEMRELAX|ABS32LIST,E }}EOP,
-  SOP(O(O_MOV_TO_REG,SW),2,"mov.w"),{{RS16,RD16,E}},         {{ 0x0,0xD,RS16, RD16,E,0,0,0,0}}EOP,
-  SOP(O(O_MOV_TO_REG,SW),4,"mov.w"),{{IMM16,RD16,E}},        {{ 0x7,0x9,0x0,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}}EOP,
-  SOP(O(O_MOV_TO_REG,SW),4,"mov.w"),{{RSIND,RD16,E}},        {{ 0x6,0x9,B30|RSIND,RD16,E,0,0,0,0}}EOP,
-  SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{{DISP16SRC,RD16,E}},    {{ 0x6,0xF,B30|DISPREG,RD16,DISP16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
-  SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{{RSINC,RD16,E}},        {{ 0x6,0xD,B30|RSINC,RD16,E,0,0,0,0}}EOP,
-  SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{{ABS16SRC,RD16,E}},     {{ 0x6,0xB,0x0,RD16,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
-
-  SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,DISP16DST,E}},    {{ 0x6,0xF,DISPREG|B31,RS16,DISP16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
-  SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,RDDEC,E}},        {{ 0x6,0xD,RDDEC|B31,RS16,E,0,0,0,0}}EOP,
-  SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,ABS16DST,E}},     {{ 0x6,0xB,0x8,RS16,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
-
-  SOP(O(O_MOV_TO_REG,SL),4,"mov.l"),{{IMM32,RD32,E}},        {{ 0x7,0xA,0x0,B30|RD32,IMM32LIST,E}}EOP,
-  SOP(O(O_MOV_TO_REG,SL),2,"mov.l"),{{RS32,RD32,E}},         {{ 0x0,0xF,B31|RS32,B30|RD32,E,0,0,0,0}}EOP,
-
-  SOP(O(O_MOV_TO_REG,SL),4,"mov.l"),{{RSIND,RD32,E}},        {{ PREFIX32,0x6,0x9,RSIND|B30,B30|RD32,E,0,0,0,0 }}EOP,
-  SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{{DISP16SRC,RD32,E}},    {{ PREFIX32,0x6,0xF,DISPREG|B30,B30|RD32,DISP16SRC,IGNORE,IGNORE,IGNORE,E }}EOP,
-  SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{{DISP|L_32|SRC,RD32,E}},{{ PREFIX32,0x7,0x8,B30|DISPREG,0x0,0x6,0xB,0x2,B30|RD32,SRC|DISP32LIST,E }}EOP,
-  SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{{RSINC,RD32,E}},        {{ PREFIX32,0x6,0xD,B30|RSINC,B30|RD32,E,0,0,0,0 }}EOP,
-  SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{{ABS16SRC,RD32,E}},     {{ PREFIX32,0x6,0xB,0x0,B30|RD32,ABS16SRC,IGNORE,IGNORE,IGNORE,E }}EOP,
-  SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{{ABS32SRC|MEMRELAX,RD32,E }},    {{ PREFIX32,0x6,0xB,0x2,B30|RD32,SRC|MEMRELAX|ABS32LIST,E }}EOP,
-  SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,RDIND,E}},        {{ PREFIX32,0x6,0x9,RDIND|B31,B30|RS32,E,0,0,0,0 }}EOP,
-  SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,DISP16DST,E}},    {{ PREFIX32,0x6,0xF,DISPREG|B31,B30|RS32,DISP16DST,IGNORE,IGNORE,IGNORE,E }}EOP,
-  SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,DISP|L_32|DST,E}},{{ PREFIX32,0x7,0x8,B31|DISPREG,0x0,0x6,0xB,0xA,B30|RS32,DST|DISP32LIST,E }}EOP,
-  SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,RDDEC,E}},        {{ PREFIX32,0x6,0xD,RDDEC|B31,B30|RS32,E,0,0,0,0 }}EOP,
-  SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,ABS16DST,E}},     {{ PREFIX32,0x6,0xB,0x8,B30|RS32,ABS16DST,IGNORE,IGNORE,IGNORE,E }}EOP,
-  SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,ABS32DST|MEMRELAX,E }},    {{ PREFIX32,0x6,0xB,0xA,B30|RS32,DST|MEMRELAX|ABS32LIST,E }}EOP,
-
-  SOP(O(O_MOV_TO_REG,SB),10,"movfpe"),{{ABS16SRC,RD8,E}},{{ 0x6,0xA,0x4,RD8,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
-  SOP(O(O_MOV_TO_MEM,SB),10,"movtpe"),{{RS8,ABS16DST,E}},{{ 0x6,0xA,0xC,RS8,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
-
-  NEW_SOP(O(O_MULU,SB),1,14,"mulxu.b"),{{RS8,RD16,E}}, {{ 0x5,0x0,RS8,RD16,E,0,0,0,0}}EOP,
-  NEW_SOP(O(O_MULU,SW),0,14,"mulxu.w"),{{RS16,RD32,E}},{{ 0x5,0x2,RS16,B30|RD32,E,0,0,0,0}}EOP,
-
-  NEW_SOP(O(O_MULS,SB),0,20,"mulxs.b"),{{RS8,RD16,E}}, {{ 0x0,0x1,0xc,0x0,0x5,0x0,RS8,RD16,E}}EOP,
-  NEW_SOP(O(O_MULS,SW),0,20,"mulxs.w"),{{RS16,RD32,E}},{{ 0x0,0x1,0xc,0x0,0x5,0x2,RS16,B30|RD32,E}}EOP,
-  
-  /* ??? This can use UNOP3.  */
-  NEW_SOP(O(O_NEG,SB),1,2,"neg.b"),{{ OR8,E, 0}},{{ 0x1,0x7,0x8,OR8,E,0,0,0,0}}EOP,
-  NEW_SOP(O(O_NEG,SW),0,2,"neg.w"),{{ OR16,E,0}},{{ 0x1,0x7,0x9,OR16,E}}EOP,
-  NEW_SOP(O(O_NEG,SL),0,2,"neg.l"),{{ OR32,E,0}},{{ 0x1,0x7,0xB,B30|OR32,E}}EOP,
-    
-  NEW_SOP(O(O_NOP,SN),1,2,"nop"),{{E,0,0}},{{ 0x0,0x0,0x0,0x0,E,0,0,0,0}}EOP,
-
-  /* ??? This can use UNOP3.  */
-  NEW_SOP(O(O_NOT,SB),1,2,"not.b"),{{ OR8,E, 0}},{{ 0x1,0x7,0x0,OR8,E,0,0,0,0}}EOP,
-  NEW_SOP(O(O_NOT,SW),0,2,"not.w"),{{ OR16,E,0}},{{ 0x1,0x7,0x1,OR16,E}}EOP,
-  NEW_SOP(O(O_NOT,SL),0,2,"not.l"),{{ OR32,E,0}},{{ 0x1,0x7,0x3,B30|OR32,E}}EOP,
-
-  TWOOP(O(O_OR, SB),"or.b",0xC,0x1,0x4),
-  NEW_SOP(O(O_OR,SW),0,4,"or.w"),{{IMM16,RD16,E }},{{0x7,0x9,0x4,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP,
-  NEW_SOP(O(O_OR,SW),0,2,"or.w"),{{RS16,RD16,E }},{{0x6,0x4,RS16,RD16,E}} EOP,
-
-  NEW_SOP(O(O_OR,SL),0,6,"or.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x4,B30|RD32,IMM32LIST,E}} EOP,
-  NEW_SOP(O(O_OR,SL),0,2,"or.l"),{{RS32,RD32,E }},{{0x0,0x1,0xF,0x0,0x6,0x4,B30|RS32,B30|RD32,E}} EOP,
-
-  NEW_SOP(O(O_ORC,SB),1,2,"orc"),{{IMM8,CCR|DST,E}},{{ 0x0,0x4,IMM8,IGNORE,E,0,0,0,0}}EOP,
-  NEW_SOP(O(O_ORC,SB),1,2,"orc"),{{IMM8,EXR|DST,E}},{{ 0x0,0x1,0x4,0x1,0x0,0x4,IMM8,IGNORE,E,0,0,0,0}}EOP,
-
-  NEW_SOP(O(O_MOV_TO_REG,SW),1,6,"pop.w"),{{OR16,E,0}},{{ 0x6,0xD,0x7,OR16,E,0,0,0,0}}EOP,
-  NEW_SOP(O(O_MOV_TO_REG,SL),0,6,"pop.l"),{{OR32,E,0}},{{ PREFIX32,0x6,0xD,0x7,OR32|B30,E,0,0,0,0}}EOP,
-  NEW_SOP(O(O_MOV_TO_MEM,SW),1,6,"push.w"),{{OR16,E,0}},{{ 0x6,0xD,0xF,OR16,E,0,0,0,0}}EOP,
-  NEW_SOP(O(O_MOV_TO_MEM,SL),0,6,"push.l"),{{OR32,E,0}},{{ PREFIX32,0x6,0xD,0xF,OR32|B30,E,0,0,0,0}}EOP,
-
-  UNOP3(O_ROTL,  "rotl", 0x1,0x2,0x8),
-  UNOP3(O_ROTR,  "rotr", 0x1,0x3,0x8),
-  UNOP3(O_ROTXL, "rotxl",0x1,0x2,0x0),
-  UNOP3(O_ROTXR, "rotxr",0x1,0x3,0x0),
-
-  SOP(O(O_BPT,SN),  10,"bpt"),{{E,0,0}},{{ 0x7,0xA,0xF,0xF,E,0,0,0,0}}EOP,
-  SOP(O(O_RTE,SN),  10,"rte"),{{E,0,0}},{{ 0x5,0x6,0x7,0x0,E,0,0,0,0}}EOP,
-  SOP(O(O_RTS,SN),   8,"rts"),{{E,0,0}},{{ 0x5,0x4,0x7,0x0,E,0,0,0,0}}EOP,
-
-  UNOP3(O_SHAL,  "shal",0x1,0x0,0x8),
-  UNOP3(O_SHAR,  "shar",0x1,0x1,0x8),
-  UNOP3(O_SHLL,  "shll",0x1,0x0,0x0),
-  UNOP3(O_SHLR,  "shlr",0x1,0x1,0x0),
-
-  SOP(O(O_SLEEP,SN),2,"sleep"),{{E,0,0}},{{ 0x0,0x1,0x8,0x0,E,0,0,0,0}} EOP,
-
-  NEW_SOP(O(O_STC,SB), 1,2,"stc"),{{CCR|SRC,RD8,E}},{{ 0x0,0x2,0x0,RD8,E,0,0,0,0}} EOP,
-
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,RDIND,E}},        {{PREFIXLDC,0x6,0x9,B31|RDIND,0x0,E}} EOP,
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,DISP|DST|L_16,E}},{{PREFIXLDC,0x6,0xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,DISP|DST|L_32,E}},{{PREFIXLDC,0x7,0x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}}EOP,
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,RDDEC,E}},        {{PREFIXLDC,0x6,0xD,B31|RDDEC,0x0,E}}EOP,
-
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,ABS16DST,E}},     {{PREFIXLDC,0x6,0xB,0x8,0x0,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,ABS32DST,E}},     {{PREFIXLDC,0x6,0xB,0xA,0x0,DST|ABS32LIST,E}}EOP,
-
-  NEW_SOP(O(O_STC,SB), 1,2,"stc"),{{EXR|SRC,RD8,E}},{{ 0x0,0x2,0x1,RD8,E,0,0,0,0}} EOP,
-
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,RDIND,E}},        {{0x0,0x1,0x4,0x1,0x6,0x9,B31|RDIND,0x0,E}} EOP,
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,DISP|DST|L_16,E}},{{0x0,0x1,0x4,0x1,0x6,0xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,DISP|DST|L_32,E}},{{0x0,0x1,0x4,0x1,0x7,0x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}}EOP,
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,RDDEC,E}},        {{0x0,0x1,0x4,0x1,0x6,0xD,B31|RDDEC,0x0,E}}EOP,
-
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,ABS16DST,E}},     {{0x0,0x1,0x4,0x1,0x6,0xB,0x8,0x0,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,ABS32DST,E}},     {{0x0,0x1,0x4,0x1,0x6,0xB,0xA,0x0,DST|ABS32LIST,E}}EOP,
-
-  SOP(O(O_SUB,SB),2,"sub.b"),{{RS8,RD8,E}},{{ 0x1,0x8,RS8,RD8,E,0,0,0,0}}EOP,
-
-  NEW_SOP(O(O_SUB,SW),1,2,"sub.w"),{{RS16,RD16,E }},  {{0x1,0x9,RS16,RD16,E}} EOP,
-  NEW_SOP(O(O_SUB,SW),0,4,"sub.w"),{{IMM16,RD16,E }}, {{0x7,0x9,0x3,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP,
-  NEW_SOP(O(O_SUB,SL),0,2,"sub.l") ,{{RS32,RD32,E }}, {{0x1,0xA,B31|RS32,B30|RD32,E}} EOP,
-  NEW_SOP(O(O_SUB,SL),0,6,"sub.l"), {{IMM32,RD32,E }},{{0x7,0xA,0x3,B30|RD32,IMM32LIST,E}} EOP,
-
-  SOP(O(O_SUBS,SL),2,"subs"),{{KBIT,RDP,E}},{{ 0x1,0xB,KBIT,RDP,E,0,0,0,0}}EOP,
-  TWOOP(O(O_SUBX,SB),"subx",0xB,0x1,0xE),
-
-  NEW_SOP(O(O_TRAPA,SB),0,2,"trapa"),{{ IMM2,E}},  {{0x5,0x7,IMM2,IGNORE,E  }}EOP,
-  NEW_SOP(O(O_TAS,SB),0,2,"tas"),{{RSIND,E}},  {{0x0,0x1,0xe,0x0,0x7,0xb,B30|RSIND,0xc,E  }}EOP,
-
-  TWOOP(O(O_XOR, SB),"xor",0xD,0x1,0x5),
-
-  NEW_SOP(O(O_XOR,SW),0,4,"xor.w"),{{IMM16,RD16,E }},{{0x7,0x9,0x5,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP,
-  NEW_SOP(O(O_XOR,SW),0,2,"xor.w"),{{RS16,RD16,E }},{{0x6,0x5,RS16,RD16,E}} EOP,
-
-  NEW_SOP(O(O_XOR,SL),0,6,"xor.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x5,B30|RD32,IMM32LIST,E}} EOP,
-  NEW_SOP(O(O_XOR,SL),0,2,"xor.l") ,{{RS32,RD32,E }},{{0x0,0x1,0xF,0x0,0x6,0x5,B30|RS32,B30|RD32,E}} EOP,
-
-  SOP(O(O_XORC,SB),2,"xorc"),{{IMM8,CCR|DST,E}},{{ 0x0,0x5,IMM8,IGNORE,E,0,0,0,0}}EOP,
-  SOP(O(O_XORC,SB),2,"xorc"),{{IMM8,EXR|DST,E}},{{ 0x0,0x1,0x4,0x1,0x0,0x5,IMM8,IGNORE,E,0,0,0,0}}EOP,
-
-  NEW_SOP(O(O_CLRMAC,SN),1,2,"clrmac"),{{E, 0, 0}},{{0x0,0x1,0xa,0x0,E}} EOP,
-  NEW_SOP(O(O_MAC,SL),1,2,"mac"),{{RSINC,RDINC,E}},{{0x0,0x1,0x6,0x0,0x6,0xd,B30|RSINC,B30|RDINC,E}} EOP,
-  NEW_SOP(O(O_LDMAC,SL),1,2,"ldmac"),{{RS32,MD32,E}},{{0x0,0x3,MD32,RS32,E}} EOP,
-  NEW_SOP(O(O_STMAC,SL),1,2,"stmac"),{{MS32,RD32,E}},{{0x0,0x2,MS32,RD32,E}} EOP,  
-  NEW_SOP(O(O_LDM,SL),0,6,"ldm.l"),{{RSINC, RS32, E}},{{ 0x0,0x1,IGNORE,0x0,0x6,0xD,0x7,IGNORE,E}}EOP,
-  NEW_SOP(O(O_STM,SL),0,6,"stm.l"),{{RS32, RDDEC, E}},{{0x0,0x1,IGNORE,0x0,0x6,0xD,0xF,IGNORE,E}}EOP,
-  {0, 0, 0, NULL, {{0,0,0}}, {{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}}}
+  {O (O_BRAS,  SB), AV_H8SX, 0, "bra/s",  {{PCREL8, E}}, {{0x4, 0x0, PCREL8, DATA | B01, E}}},
+
+  {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, RDIND,    OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0,       0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS8DST,  OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST,            0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, RDIND,    OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0,       0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS8DST,  OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST,            0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+
+  BRANCH (O (O_BRA, SB), "bt",  0x0),
+  BRANCH (O (O_BRN, SB), "brn", 0x1),
+  BRANCH (O (O_BRN, SB), "bf",  0x1),
+  BRANCH (O (O_BHI, SB), "bhi", 0x2),
+  BRANCH (O (O_BLS, SB), "bls", 0x3),
+  BRANCH (O (O_BCC, SB), "bcc", 0x4),
+  BRANCH (O (O_BCC, SB), "bhs", 0x4),
+  BRANCH (O (O_BCS, SB), "bcs", 0x5),
+  BRANCH (O (O_BCS, SB), "blo", 0x5),
+  BRANCH (O (O_BNE, SB), "bne", 0x6),
+  BRANCH (O (O_BEQ, SB), "beq", 0x7),
+  BRANCH (O (O_BVC, SB), "bvc", 0x8),
+  BRANCH (O (O_BVS, SB), "bvs", 0x9),
+  BRANCH (O (O_BPL, SB), "bpl", 0xA),
+  BRANCH (O (O_BMI, SB), "bmi", 0xB),
+  BRANCH (O (O_BGE, SB), "bge", 0xC),
+  BRANCH (O (O_BLT, SB), "blt", 0xD),
+  BRANCH (O (O_BGT, SB), "bgt", 0xE),
+  BRANCH (O (O_BLE, SB), "ble", 0xF),
+
+  EBITOP (O (O_BCLR,  SB), IMM3 | B30, "bclr",  0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0),
+  BITOP  (O (O_BAND,  SB), IMM3 | B30, "band",  0x7, 0x6, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
+  BITOP  (O (O_BIAND, SB), IMM3 | B31, "biand", 0x7, 0x6, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
+  BITOP  (O (O_BILD,  SB), IMM3 | B31, "bild",  0x7, 0x7, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
+  BITOP  (O (O_BIOR,  SB), IMM3 | B31, "bior",  0x7, 0x4, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
+  BITOP  (O (O_BIST,  SB), IMM3 | B31, "bist",  0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0),
+  BITOP  (O (O_BIXOR, SB), IMM3 | B31, "bixor", 0x7, 0x5, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
+  BITOP  (O (O_BLD,   SB), IMM3 | B30, "bld",   0x7, 0x7, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
+  EBITOP (O (O_BNOT,  SB), IMM3 | B30, "bnot",  0x6, 0x1, 0x7, 0xD, 0x7, 0xF, 0x8, 0),
+  BITOP  (O (O_BOR,   SB), IMM3 | B30, "bor",   0x7, 0x4, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
+  EBITOP (O (O_BSET,  SB), IMM3 | B30, "bset",  0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0),
+  BITOP  (O (O_BST,   SB), IMM3 | B30, "bst",   0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0),
+  EBITOP (O (O_BTST,  SB), IMM3 | B30, "btst",  0x6, 0x3, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
+  BITOP  (O (O_BXOR,  SB), IMM3 | B30, "bxor",  0x7, 0x5, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
+
+  EBITOP_B (O (O_BCLREQ,  SB), IMM3 | B30, "bclr/eq",  0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7),
+  EBITOP_B (O (O_BCLRNE,  SB), IMM3 | B30, "bclr/ne",  0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0x6),
+  EBITOP_B (O (O_BSETEQ,  SB), IMM3 | B30, "bset/eq",  0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7),
+  EBITOP_B (O (O_BSETNE,  SB), IMM3 | B30, "bset/ne",  0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0x6),
+  BITOP_B  (O (O_BISTZ,   SB), IMM3 | B31, "bistz",    0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7),
+  BITOP_B  (O (O_BSTZ,    SB), IMM3 | B30, "bstz",     0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7),
+
+  {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, RDIND,    R3_8}},  {{0x7, 0xC,           B30 | RDIND, 0x0, 0xF, R3_8, IMM8LIST, E}}},
+  {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS8DST,  R3_8}},  {{0x7, 0xE,           DSTABS8LIST,      0xF, R3_8, IMM8LIST, E}}},
+  {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS16DST, R3_8}},  {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST,     0xF, R3_8, IMM8LIST, E}}},
+  {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS32DST, R3_8}},  {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST,     0xF, R3_8, IMM8LIST, E}}},
+
+  /* Because the assembler treats SRC, DST and OP3 as ordinals, 
+     I must designate the second argument, an immediate value, as DST.
+     May God have mercy on my soul.  */
+  {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, R3_IND}},   {{0x7, 0xD,           B30 | R3_IND, 0x0, 0xF, RS8, DST | IMM8LIST, E}}},
+  {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS8OP3}},  {{0x7, 0xF,           OP3ABS8LIST,       0xF, RS8, DST | IMM8LIST, E}}},
+  {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS16OP3}}, {{0x6, 0xA, 0x1, 0x8, OP3ABS16LIST,      0xF, RS8, DST | IMM8LIST, E}}},
+  {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS32OP3}}, {{0x6, 0xA, 0x3, 0x8, OP3ABS32LIST,      0xF, RS8, DST | IMM8LIST, E}}},
+
+  {O (O_BSR, SB), AV_H8,   6, "bsr", {{PCREL8,  E}}, {{0x5, 0x5,           PCREL8,  DATA,  E}}},
+  {O (O_BSR, SB), AV_H8,   6, "bsr", {{PCREL16, E}}, {{0x5, 0xC, 0x0, 0x0, PCREL16, DATA3, E}}},
+  {O (O_BSR, SB), AV_H8SX, 0, "bsr", {{LOWREG | L_8,    E}}, {{0x5, 0xd, B30 | LOWREG | L_8,  0x5, E}}},
+  {O (O_BSR, SW), AV_H8SX, 0, "bsr", {{LOWREG | L_16,   E}}, {{0x5, 0xd, B30 | LOWREG | L_16, 0x6, E}}},
+  {O (O_BSR, SL), AV_H8SX, 0, "bsr", {{OR32,   E}}, {{0x5, 0xd, B30 | OR32, 0x7, E}}},
+
+  {O (O_CMP, SB), AV_H8,   2, "cmp.b", {{IMM8, RD8, E}}, {{0xa, RD8, IMM8LIST, E}}}, 
+  EXPAND_TWOOP_B (O (O_CMP, SB), "cmp.b", 0xa, 0x1, 0xc, 0x2, B00), 
+
+  {O (O_CMP, SW), AV_H8,   2, "cmp.w", {{RS16,      RD16,     E}}, {{0x1, 0xd, RS16,         RD16,   E}}}, 
+  {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, RD16,     E}}, {{0x1, 0xf, B30 | IMM3NZ, RD16,   E}}}, 
+  {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, RDIND,    E}}, {{0x7, 0xd,      B31 | RDIND,  IGNORE,       0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}}, 
+  {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}}, 
+  {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}}, 
+  EXPAND_TWOOP_W (O (O_CMP, SW), "cmp.w", 0x1, 0xd, 0x2), 
+
+  {O (O_CMP, SL), AV_H8H,  6, "cmp.l", {{RS32,      RD32,     E}}, {{0x1, 0xf, B31 | RS32,   B30 | RD32, E}}}, 
+  {O (O_CMP, SL), AV_H8SX, 0, "cmp.l", {{IMM3NZ_NS, RD32,     E}}, {{0x1, 0xf, B31 | IMM3NZ, B31 | RD32, E}}}, 
+  EXPAND_TWOOP_L (O (O_CMP, SL), "cmp.l", 0x2), 
+
+  UNOP (O (O_DAA, SB), "daa",   0x0, 0xF),
+  UNOP (O (O_DAS, SB), "das",   0x1, 0xF),
+  UNOP (O (O_DEC, SB), "dec.b", 0x1, 0xA),
+
+  {O (O_DEC, SW), AV_H8H, 2, "dec.w", {{DBIT, RD16, E}}, {{0x1, 0xB, 0x5 | DBIT, RD16,       E}}},
+  {O (O_DEC, SL), AV_H8H, 2, "dec.l", {{DBIT, RD32, E}}, {{0x1, 0xB, 0x7 | DBIT, RD32 | B30, E}}},
+
+  {O (O_DIVS, SW), AV_H8SX, 0, "divs.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xd, 0x6, 0x5, 0x1, IMM4, RD16, E}}},
+  {O (O_DIVS, SW), AV_H8SX, 0, "divs.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xd, 0x2, 0x5, 0x1, RS16, RD16, E}}},
+  {O (O_DIVS, SL), AV_H8SX, 0, "divs.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xd, 0x6, 0x5, 0x3, IMM4,       B30 | RD32, E}}},
+  {O (O_DIVS, SL), AV_H8SX, 0, "divs.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xd, 0x2, 0x5, 0x3, B30 | RS32, B30 | RD32, E}}},
+
+  {O (O_DIVU, SW), AV_H8SX, 0, "divu.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xd, 0xe, 0x5, 0x1, IMM4, RD16, E}}},
+  {O (O_DIVU, SW), AV_H8SX, 0, "divu.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xd, 0xa, 0x5, 0x1, RS16, RD16, E}}},
+  {O (O_DIVU, SL), AV_H8SX, 0, "divu.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xd, 0xe, 0x5, 0x3, IMM4,       B30 | RD32, E}}},
+  {O (O_DIVU, SL), AV_H8SX, 0, "divu.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xd, 0xa, 0x5, 0x3, B30 | RS32, B30 | RD32, E}}},
+
+  {O (O_DIVXS, SB), AV_H8SX, 0,  "divxs.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xD, 0x4, 0x5, 0x1, IMM4, RD16, E}}},
+  {O (O_DIVXS, SB), AV_H8H,  13, "divxs.b", {{RS8,  RD16, E}}, {{0x0, 0x1, 0xD, 0x0, 0x5, 0x1, RS8,  RD16, E}}},
+  {O (O_DIVXS, SW), AV_H8SX, 0,  "divxs.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xD, 0x4, 0x5, 0x3, IMM4, B30 | RD32, E}}},
+  {O (O_DIVXS, SW), AV_H8H,  21, "divxs.w", {{RS16, RD32, E}}, {{0x0, 0x1, 0xD, 0x0, 0x5, 0x3, RS16, B30 | RD32, E}}},
+
+  {O (O_DIVXU, SB), AV_H8SX, 0,  "divxu.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xD, 0xC, 0x5, 0x1, IMM4, RD16, E}}},
+  {O (O_DIVXU, SB), AV_H8,   13, "divxu.b", {{RS8,  RD16, E}}, {{0x5, 0x1,                     RS8,  RD16, E}}},
+  {O (O_DIVXU, SW), AV_H8SX, 0,  "divxu.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xD, 0xC, 0x5, 0x3, IMM4, B30 | RD32, E}}},
+  {O (O_DIVXU, SW), AV_H8H,  21, "divxu.w", {{RS16, RD32, E}}, {{0x5, 0x3,                     RS16, B30 | RD32, E}}},
+
+  {O (O_EEPMOV, SB), AV_H8,  4, "eepmov.b", {{E}}, {{0x7, 0xB, 0x5, 0xC, 0x5, 0x9, 0x8, 0xF, E}}},
+  {O (O_EEPMOV, SW), AV_H8H, 4, "eepmov.w", {{E}}, {{0x7, 0xB, 0xD, 0x4, 0x5, 0x9, 0x8, 0xF, E}}},
+
+  EXPAND_UNOP_STD_W      (O (O_EXTS, SW), "exts.w",          PREFIX_015, 0x1, 0x7, 0xd),
+  EXPAND_UNOP_STD_L      (O (O_EXTS, SL), "exts.l",          PREFIX_010, 0x1, 0x7, 0xf),
+  EXPAND_UNOP_EXTENDED_L (O (O_EXTS, SL), "exts.l", CONST_2, PREFIX_010, 0x1, 0x7, 0xe, 0),
+  EXPAND_UNOP_STD_W      (O (O_EXTU, SW), "extu.w",          PREFIX_015, 0x1, 0x7, 0x5),
+  EXPAND_UNOP_STD_L      (O (O_EXTU, SL), "extu.l",          PREFIX_010, 0x1, 0x7, 0x7),
+  EXPAND_UNOP_EXTENDED_L (O (O_EXTU, SL), "extu.l", CONST_2, PREFIX_010, 0x1, 0x7, 0x6, 0),
+
+  UNOP (O (O_INC, SB), "inc", 0x0, 0xA),
+
+  {O (O_INC, SW), AV_H8H,  2, "inc.w", {{DBIT, RD16, E}},    {{0x0, 0xB, 0x5 | DBIT, RD16,       E}}},
+  {O (O_INC, SL), AV_H8H,  2, "inc.l", {{DBIT, RD32, E}},    {{0x0, 0xB, 0x7 | DBIT, RD32 | B30, E}}},
+
+  {O (O_JMP, SN), AV_H8,   4, "jmp", {{RSIND, E}},         {{0x5, 0x9, B30 | RSIND, 0x0, E}}},
+  {O (O_JMP, SN), AV_H8,   6, "jmp", {{ABSJMP | L_24, E}}, {{0x5, 0xA, SRC | ABSJMP | L_24, DATA5, E}}},
+
+  {O (O_JMP, SN), AV_H8SX, 0, "jmp", {{ABSJMP | L_32, E}}, {{0x5, 0x9, 0x0, 0x8, ABSJMP | L_32, DATA7, E}}},
+
+  {O (O_JMP, SN), AV_H8,   8, "jmp", {{MEMIND, E}}, {{0x5, 0xB, SRC | MEMIND, DATA, E}}},
+  {O (O_JMP, SN), AV_H8SX, 0, "jmp", {{VECIND, E}}, {{0x5, 0x9, B31 | SRC | VECIND, DATA, E}}},
+
+  {O (O_JSR, SN), AV_H8,   6, "jsr", {{RSIND, E}},         {{0x5, 0xD, B30 | RSIND, 0x0, E}}},
+  {O (O_JSR, SN), AV_H8,   8, "jsr", {{ABSJMP | L_24, E}}, {{0x5, 0xE, SRC | ABSJMP | L_24, DATA5, E}}},
+
+  {O (O_JSR, SN), AV_H8SX, 0, "jsr", {{ABSJMP | L_32, E}}, {{0x5, 0xD, 0x0, 0x8, ABSJMP | L_32, DATA7, E}}},
+
+  {O (O_JSR, SN), AV_H8,   8, "jsr", {{MEMIND, E}}, {{0x5, 0xF, SRC | MEMIND, DATA, E}}},
+  {O (O_JSR, SN), AV_H8,   8, "jsr", {{VECIND, E}}, {{0x5, 0xD, SRC | VECIND, DATA, E}}},
+
+  {O (O_LDC, SB), AV_H8,   2, "ldc", {{IMM8,       CCR     | DST, E}}, {{                           0x0, 0x7, IMM8LIST, E}}},
+  {O (O_LDC, SB), AV_H8S,  2, "ldc", {{IMM8,       EXR     | DST, E}}, {{0x0, 0x1, 0x4,  EXR | DST, 0x0, 0x7, IMM8LIST, E}}},
+  {O (O_LDC, SB), AV_H8,   2, "ldc", {{RS8,        CCR     | DST, E}}, {{0x0, 0x3, B30 | CCR | DST, RS8, E}}},
+  {O (O_LDC, SB), AV_H8S,  2, "ldc", {{RS8,        EXR     | DST, E}}, {{0x0, 0x3, B30 | EXR | DST, RS8, E}}},
+  {O (O_LDC, SW), AV_H8H,  2, "ldc", {{RSIND,      CCR     | DST, E}}, {{PREFIXLDC, 0x6, 0x9, B30 | RSIND,     IGNORE, E}}},
+  {O (O_LDC, SW), AV_H8S,  2, "ldc", {{RSIND,      EXR     | DST, E}}, {{PREFIXLDC, 0x6, 0x9, B30 | RSIND,     IGNORE, E}}},
+  {O (O_LDC, SW), AV_H8H,  2, "ldc", {{RSPOSTINC,  CCR     | DST, E}}, {{PREFIXLDC, 0x6, 0xD, B30 | RSPOSTINC, IGNORE, E}}},
+  {O (O_LDC, SW), AV_H8S,  2, "ldc", {{RSPOSTINC,  EXR     | DST, E}}, {{PREFIXLDC, 0x6, 0xD, B30 | RSPOSTINC, IGNORE, E}}},
+  {O (O_LDC, SW), AV_H8H,  2, "ldc", {{DISP16SRC,  CCR     | DST, E}}, {{PREFIXLDC, 0x6, 0xF, B30 | DISPREG,                     IGNORE, SRC | DISP16LIST, E}}},
+  {O (O_LDC, SW), AV_H8S,  2, "ldc", {{DISP16SRC,  EXR     | DST, E}}, {{PREFIXLDC, 0x6, 0xF, B30 | DISPREG,                     IGNORE, SRC | DISP16LIST, E}}},
+  {O (O_LDC, SW), AV_H8H,  2, "ldc", {{DISP32SRC,  CCR     | DST, E}}, {{PREFIXLDC, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xB, 0x2, IGNORE, SRC | DISP32LIST, E}}},
+  {O (O_LDC, SW), AV_H8S,  2, "ldc", {{DISP32SRC,  EXR     | DST, E}}, {{PREFIXLDC, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xB, 0x2, IGNORE, SRC | DISP32LIST, E}}},
+  {O (O_LDC, SW), AV_H8H,  2, "ldc", {{ABS16SRC,   CCR     | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, IGNORE, SRC | ABS16LIST, E}}},
+  {O (O_LDC, SW), AV_H8S,  2, "ldc", {{ABS16SRC,   EXR     | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, IGNORE, SRC | ABS16LIST, E}}},
+  {O (O_LDC, SW), AV_H8H,  2, "ldc", {{ABS32SRC,   CCR     | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | ABS32LIST, E}}},
+  {O (O_LDC, SW), AV_H8S,  2, "ldc", {{ABS32SRC,   EXR     | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | ABS32LIST, E}}},
+  {O (O_LDC, SL), AV_H8SX, 0, "ldc", {{RS32, B30 | VBR_SBR | DST, E}}, {{0x0, 0x3, B30 | VBR_SBR | DST, RS32, E}}},
+
+
+  {O (O_MOV, SB), AV_H8,   2, "mov.b", {{IMM8, RD8,      E}}, {{0xF, RD8,            IMM8LIST,     E}}},
+  {O (O_MOV, SB), AV_H8SX, 0, "mov.b", {{IMM4_NS, ABS16DST, E}}, {{0x6, 0xa, 0xd, IMM4, DSTABS16LIST, E}}},
+  {O (O_MOV, SB), AV_H8SX, 0, "mov.b", {{IMM4_NS, ABS32DST, E}}, {{0x6, 0xa, 0xf, IMM4, DSTABS32LIST, E}}},
+  MOVFROM_IMM8 (O (O_MOV, SB), PREFIX_017D, "mov.b", IMM8),
+
+  {O (O_MOV, SB), AV_H8,   2,    "mov.b", {{RS8, RD8,     E}}, {{0x0, 0xC, RS8, RD8,    E}}},
+  MOVFROM_REG_BW (O (O_MOV, SB), "mov.b", RS8, PREFIX_017, 8, 10, 12, 14, MEMRELAX),
+  {O (O_MOV, SB), AV_H8,   4,    "mov.b", {{RS8, ABS8DST, E}}, {{0x3, RS8, DSTABS8LIST, E}}},
+  MOVTO_REG_BW (O (O_MOV, SB),   "mov.b", RD8, PREFIX_017, 8, 10, 12, 14, MEMRELAX),
+  {O (O_MOV, SB), AV_H8,   4,    "mov.b", {{ABS8SRC, RD8, E}}, {{0x2, RD8, ABS8LIST,    E}}},
+
+  MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSIND,     FROM_IND), 
+  MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPOSTINC, FROM_POSTINC), 
+  MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPOSTDEC, FROM_POSTDEC), 
+  MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPREINC,  FROM_PREINC), 
+  MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPREDEC,  FROM_PREDEC), 
+  MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP2SRC,  FROM_DISP2), 
+  MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP16SRC, FROM_DISP16,  DISP16LIST), 
+  MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP32SRC, FROM_DISP32,  DISP32LIST), 
+  MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXB16,  FROM_DISP16B, DISP16LIST), 
+  MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXW16,  FROM_DISP16W, DISP16LIST), 
+  MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXL16,  FROM_DISP16L, DISP16LIST), 
+  MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXB32,  FROM_DISP32B, DISP32LIST), 
+  MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXW32,  FROM_DISP32W, DISP32LIST), 
+  MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXL32,  FROM_DISP32L, DISP32LIST), 
+  MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", ABS16SRC,  FROM_ABS16,   ABS16LIST), 
+  MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", ABS32SRC,  FROM_ABS32,   ABS32LIST), 
+
+  {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM3NZ_NS, RD16, E}}, {{0x0, 0xf, B30 | IMM3NZ, RD16,   E}}},
+  {O (O_MOV, SW), AV_H8,   4, "mov.w", {{IMM16,     RD16, E}}, {{0x7, 0x9, 0x0, RD16, IMM16LIST, E}}},
+  {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM4_NS,  ABS16DST, E}}, {{0x6, 0xb, 0xd, IMM4, DSTABS16LIST, E}}},
+  {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM4_NS,  ABS32DST, E}}, {{0x6, 0xb, 0xf, IMM4, DSTABS32LIST, E}}},
+
+  MOVFROM_IMM8 (O (O_MOV, SW), PREFIX_015D,   "mov.w", IMM8U_NS),
+  MOVFROM_IMM  (O (O_MOV, SW), PREFIX_7974,   "mov.w", IMM16, IMM16LIST),
+
+  {O (O_MOV, SW), AV_H8,   2, "mov.w", {{RS16, RD16,      E}}, {{0x0, 0xD, RS16, RD16, E}}},
+  MOVFROM_REG_BW (O (O_MOV, SW), "mov.w", RS16, PREFIX_015, 9, 11, 13, 15, 0),
+  MOVTO_REG_BW   (O (O_MOV, SW), "mov.w", RD16, PREFIX_015, 9, 11, 13, 15, 0),
+
+  MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSIND,     FROM_IND), 
+  MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPOSTINC, FROM_POSTINC), 
+  MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPOSTDEC, FROM_POSTDEC), 
+  MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPREINC,  FROM_PREINC), 
+  MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPREDEC,  FROM_PREDEC), 
+  MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP2SRC,  FROM_DISP2), 
+  MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP16SRC, FROM_DISP16,  DISP16LIST), 
+  MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP32SRC, FROM_DISP32,  DISP32LIST), 
+  MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXB16,  FROM_DISP16B, DISP16LIST), 
+  MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXW16,  FROM_DISP16W, DISP16LIST), 
+  MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXL16,  FROM_DISP16L, DISP16LIST), 
+  MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXB32,  FROM_DISP32B, DISP32LIST), 
+  MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXW32,  FROM_DISP32W, DISP32LIST), 
+  MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXL32,  FROM_DISP32L, DISP32LIST), 
+  MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", ABS16SRC,  FROM_ABS16,   ABS16LIST), 
+  MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", ABS32SRC,  FROM_ABS32,   ABS32LIST), 
+
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{IMM3NZ_NS, RD32, E}}, {{0x0, 0xf, B31 | IMM3NZ, B31 | RD32, E}}},
+
+  MOVFROM_IMM8 (O (O_MOV, SL), PREFIX_010D, "mov.l", IMM8U_NS),
+  MOVFROM_IMM  (O (O_MOV, SL), PREFIX_7A7C, "mov.l", IMM16U_NS, IMM16ULIST),
+
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{IMM16U_NS, RD32, E}}, {{0x7, 0xa, 0x0, B31 | RD32, IMM16ULIST, E}}},
+  {O (O_MOV, SL), AV_H8H,  4, "mov.l", {{IMM32,     RD32, E}}, {{0x7, 0xa, 0x0, B30 | RD32, IMM32LIST,  E}}},
+
+  MOVFROM_IMM (O (O_MOV, SL), PREFIX_7A74, "mov.l", IMM32, IMM32LIST),
+
+  {O (O_MOV, SL), AV_H8H,  2, "mov.l", {{RS32, RD32,      E}}, {{0x0, 0xf, B31 | RS32, B30 | RD32, E}}},
+
+  {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{RS32, RDIND,     E}}, {{PREFIX_0100,                       0x6, 0x9, B31 | RDIND, B30 | RS32, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPOSTINC, E}}, {{PREFIX_0103,                       0x6, 0xd, B31 | RDPOSTINC,   RS32, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPOSTDEC, E}}, {{PREFIX_0101,                       0x6, 0xd, B31 | RDPOSTDEC,   RS32, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPREINC,  E}}, {{PREFIX_0102,                       0x6, 0xd, B31 | RDPREINC,    RS32, E}}}, 
+  {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{RS32, RDPREDEC,  E}}, {{PREFIX_0100,                       0x6, 0xd, B31 | RDPREDEC,    RS32, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, DISP2DST,  E}}, {{PREFIX_010,  B30 | B20 | DISP2DST, 0x6, 0x9, B31 | DSTDISPREG,  RS32, E}}}, 
+  {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{RS32, DISP16DST, E}}, {{PREFIX_0100,                       0x6, 0xf, B31 | DSTDISPREG,  RS32, DSTDISP16LIST, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{RS32, DISP32DST, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x0,   0x6, 0xb, 0xa,               RS32, DSTDISP32LIST, E}}},
+  {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{RS32, DISP32DST, E}}, {{PREFIX_0100,                       0x7, 0x8, B31 | DSTDISPREG, 0x0,   0x6, 0xb, 0xa,               RS32, DSTDISP32LIST, E}}},
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXB16D, E}}, {{PREFIX_0101,                       0x6, 0xf, B31 | DSTDISPREG,  RS32, DSTDISP16LIST, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXW16D, E}}, {{PREFIX_0102,                       0x6, 0xf, B31 | DSTDISPREG,  RS32, DSTDISP16LIST, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXL16D, E}}, {{PREFIX_0103,                       0x6, 0xf, B31 | DSTDISPREG,  RS32, DSTDISP16LIST, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXB32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x1,   0x6, 0xb, 0xa,               RS32, DSTDISP32LIST, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXW32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x2,   0x6, 0xb, 0xa,               RS32, DSTDISP32LIST, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXL32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x3,   0x6, 0xb, 0xa,               RS32, DSTDISP32LIST, E}}}, 
+  {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{RS32, ABS16DST,  E}}, {{PREFIX_0100,                       0x6, 0xb, 0x8,            RS32, DSTABS16LIST,            E}}},
+  {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{RS32, ABS32DST,  E}}, {{PREFIX_0100,                       0x6, 0xb, 0xa,            RS32, MEMRELAX | DSTABS32LIST, E}}},
+
+  {O (O_MOV, SL), AV_H8H,  4, "mov.l", {{RSIND,     RD32, E}}, {{PREFIX_0100,                       0x6, 0x9, B30 | RSIND,     RD32, E}}}, 
+  {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{RSPOSTINC, RD32, E}}, {{PREFIX_0100,                       0x6, 0xd, B30 | RSPOSTINC, RD32, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPOSTDEC, RD32, E}}, {{PREFIX_0102,                       0x6, 0xd, B30 | RSPOSTDEC, RD32, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPREINC,  RD32, E}}, {{PREFIX_0101,                       0x6, 0xd, B30 | RSPREINC,  RD32, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPREDEC,  RD32, E}}, {{PREFIX_0103,                       0x6, 0xd, B30 | RSPREDEC,  RD32, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{DISP2SRC,  RD32, E}}, {{PREFIX_010,  B30 | B20 | DISP2SRC, 0x6, 0x9, B30 | DISPREG,   RD32, E}}}, 
+  {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{DISP16SRC, RD32, E}}, {{PREFIX_0100,                       0x6, 0xf, B30 | DISPREG,   RD32, SRC | DISP16LIST, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{DISP32SRC, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x0,      0x6, 0xb, 0x2,             RD32, SRC | DISP32LIST, E}}},
+  {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{DISP32SRC, RD32, E}}, {{PREFIX_0100,                       0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xb, 0x2,             RD32, SRC | DISP32LIST, E}}},
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXB16,  RD32, E}}, {{PREFIX_0101,                       0x6, 0xf, B30 | DISPREG,   RD32, SRC | DISP16LIST, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXW16,  RD32, E}}, {{PREFIX_0102,                       0x6, 0xf, B30 | DISPREG,   RD32, SRC | DISP16LIST, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXL16,  RD32, E}}, {{PREFIX_0103,                       0x6, 0xf, B30 | DISPREG,   RD32, SRC | DISP16LIST, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXB32,  RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x1,      0x6, 0xb, 0x2,             RD32, SRC | DISP32LIST, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXW32,  RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x2,      0x6, 0xb, 0x2,             RD32, SRC | DISP32LIST, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXL32,  RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x3,      0x6, 0xb, 0x2,             RD32, SRC | DISP32LIST, E}}}, 
+  {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{ABS16SRC,  RD32, E}}, {{PREFIX_0100,                       0x6, 0xb, 0x0,             RD32, SRC | ABS16LIST,  E}}}, 
+  {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{ABS32SRC,  RD32, E}}, {{PREFIX_0100,                       0x6, 0xb, 0x2,             RD32, SRC | MEMRELAX | ABS32LIST, E}}}, 
+
+  MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSIND,     FROM_IND), 
+  MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPOSTINC, FROM_POSTINC), 
+  MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPOSTDEC, FROM_POSTDEC), 
+  MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPREINC,  FROM_PREINC), 
+  MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPREDEC,  FROM_PREDEC), 
+  MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP2SRC,  FROM_DISP2), 
+  MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP16SRC, FROM_DISP16,  DISP16LIST), 
+  MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP32SRC, FROM_DISP32,  DISP32LIST), 
+  MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXB16,  FROM_DISP16B, DISP16LIST), 
+  MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXW16,  FROM_DISP16W, DISP16LIST), 
+  MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXL16,  FROM_DISP16L, DISP16LIST), 
+  MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXB32,  FROM_DISP32B, DISP32LIST), 
+  MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXW32,  FROM_DISP32W, DISP32LIST), 
+  MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXL32,  FROM_DISP32L, DISP32LIST), 
+  MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", ABS16SRC,  FROM_ABS16,   ABS16LIST), 
+  MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", ABS32SRC,  FROM_ABS32,   ABS32LIST), 
+
+#define DO_MOVA1(TYPE, OP0, OP1) \
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, DISP16LIST, E}}}, \
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, DISP16LIST, E}}}, \
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, DISP16LIST, E}}}, \
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, DISP16LIST, E}}}, \
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, DISP16LIST, E}}}, \
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, DISP16LIST, E}}}, \
+\
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, DISP32LIST, E}}}, \
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, DISP32LIST, E}}}, \
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, DISP32LIST, E}}}, \
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, DISP32LIST, E}}}, \
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, DISP32LIST, E}}}, \
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, DISP32LIST, E}}}
+
+#define DO_MOVA2(TYPE, OP0, OP1, OP2) \
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, OP2, DISP16LIST, E}}}, \
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, OP2, DISP16LIST, E}}}, \
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, OP2, DISP16LIST, E}}}, \
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, OP2, DISP16LIST, E}}}, \
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, OP2, DISP16LIST, E}}}, \
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, OP2, DISP16LIST, E}}}, \
+\
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, OP2, DISP32LIST, E}}}, \
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, OP2, DISP32LIST, E}}}, \
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, OP2, DISP32LIST, E}}}, \
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, OP2, DISP32LIST, E}}}, \
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, OP2, DISP32LIST, E}}}, \
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, OP2, DISP32LIST, E}}}
+
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, E}}, {{0x7, 0xA, 0x8, B31 | DISPREG, DISP16LIST, E}}},
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, E}}, {{0x7, 0xA, 0x9, B31 | DISPREG, DISP16LIST, E}}},
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xA, B31 | DISPREG, DISP16LIST, E}}},
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xB, B31 | DISPREG, DISP16LIST, E}}},
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xC, B31 | DISPREG, DISP16LIST, E}}},
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xD, B31 | DISPREG, DISP16LIST, E}}},
+
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, E}}, {{0x7, 0xA, 0x8, B30 | DISPREG, DISP32LIST, E}}},
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, E}}, {{0x7, 0xA, 0x9, B30 | DISPREG, DISP32LIST, E}}},
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xA, B30 | DISPREG, DISP32LIST, E}}},
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xB, B30 | DISPREG, DISP32LIST, E}}},
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xC, B30 | DISPREG, DISP32LIST, E}}},
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xD, B30 | DISPREG, DISP32LIST, E}}},
+
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, RD8,  R3_32}}, {{0x7, 0x8, RD8,  0x8, 0x7, 0xA, 0x8, B31 | R3_32, DISP16LIST, E}}},
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B31 | R3_32, DISP16LIST, E}}},
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, RD8,  R3_32}}, {{0x7, 0x8, RD8,  0x8, 0x7, 0xA, 0xA, B31 | R3_32, DISP16LIST, E}}},
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B31 | R3_32, DISP16LIST, E}}},
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, RD8,  R3_32}}, {{0x7, 0x8, RD8,  0x8, 0x7, 0xA, 0xC, B31 | R3_32, DISP16LIST, E}}},
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B31 | R3_32, DISP16LIST, E}}},
+
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, RD8,  R3_32}}, {{0x7, 0x8, RD8,  0x8, 0x7, 0xA, 0x8, B30 | R3_32, DISP32LIST, E}}},
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B30 | R3_32, DISP32LIST, E}}},
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, RD8,  R3_32}}, {{0x7, 0x8, RD8,  0x8, 0x7, 0xA, 0xA, B30 | R3_32, DISP32LIST, E}}},
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B30 | R3_32, DISP32LIST, E}}},
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, RD8,  R3_32}}, {{0x7, 0x8, RD8,  0x8, 0x7, 0xA, 0xC, B30 | R3_32, DISP32LIST, E}}},
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B30 | R3_32, DISP32LIST, E}}},
+
+  DO_MOVA1 (RDIND,     0x0, B30 | RDIND),
+  DO_MOVA1 (RDPOSTINC, 0x8, B30 | RDPOSTINC),
+  DO_MOVA1 (RDPOSTDEC, 0xA, B30 | RDPOSTDEC),
+  DO_MOVA1 (RDPREINC,  0x9, B30 | RDPREINC),
+  DO_MOVA1 (RDPREDEC,  0xB, B30 | RDPREDEC),
+  DO_MOVA1 (DISP2DST, B30 | B20 | DISP2DST,  B30 | DSTDISPREG),
+  DO_MOVA2 (DISP16DST, 0xC,      B30 | DSTDISPREG, DSTDISP16LIST),
+  DO_MOVA2 (DISP32DST, 0xC,      B31 | DSTDISPREG, DSTDISP32LIST),
+  DO_MOVA2 (INDEXB16 | DST, 0xD, B30 | DSTDISPREG, DSTDISP16LIST),
+  DO_MOVA2 (INDEXW16 | DST, 0xE, B30 | DSTDISPREG, DSTDISP16LIST),
+  DO_MOVA2 (INDEXL16 | DST, 0xF, B30 | DSTDISPREG, DSTDISP16LIST),
+  DO_MOVA2 (INDEXB32 | DST, 0xD, B31 | DSTDISPREG, DSTDISP32LIST),
+  DO_MOVA2 (INDEXW32 | DST, 0xE, B31 | DSTDISPREG, DSTDISP32LIST),
+  DO_MOVA2 (INDEXL32 | DST, 0xF, B31 | DSTDISPREG, DSTDISP32LIST),
+  DO_MOVA2 (ABS16DST | DST, 0x4, 0x0,              DSTABS16LIST),
+  DO_MOVA2 (ABS32DST | DST, 0x4, 0x8,              DSTABS32LIST),
+
+  {O (O_MOV, SB), AV_H8, 10, "movfpe", {{ABS16SRC, RD8, E}}, {{0x6, 0xA, 0x4, RD8, ABS16SRC, DATA3, E}}},
+  {O (O_MOV, SB), AV_H8, 10, "movtpe", {{RS8, ABS16DST, E}}, {{0x6, 0xA, 0xC, RS8, ABS16DST, DATA3, E}}},
+
+  {O (O_MOVMD, SB), AV_H8SX, 0, "movmd.b", {{E}},         {{0x7, 0xb, 0x9, 0x4, E}}},
+  {O (O_MOVMD, SW), AV_H8SX, 0, "movmd.w", {{E}},         {{0x7, 0xb, 0xa, 0x4, E}}},
+  {O (O_MOVMD, SL), AV_H8SX, 0, "movmd.l", {{E}},         {{0x7, 0xb, 0xb, 0x4, E}}},
+  {O (O_MOVSD, SB), AV_H8SX, 0, "movsd.b", {{PCREL16, E}}, {{0x7, 0xb, 0x8, 0x4, PCREL16, DATA3, E}}},
+
+  {O (O_MULS, SW), AV_H8SX, 0, "muls.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0x6, 0x5, 0x0, IMM4, RD16, E}}},
+  {O (O_MULS, SW), AV_H8SX, 0, "muls.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xc, 0x2, 0x5, 0x0, RS16, RD16, E}}},
+  {O (O_MULS, SL), AV_H8SX, 0, "muls.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x6, 0x5, 0x2, IMM4,       B30 | RD32, E}}},
+  {O (O_MULS, SL), AV_H8SX, 0, "muls.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0x2, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}},
+
+  {O (O_MULU, SW), AV_H8SX, 0, "mulu.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0xe, 0x5, 0x0, IMM4, RD16, E}}},
+  {O (O_MULU, SW), AV_H8SX, 0, "mulu.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xc, 0xa, 0x5, 0x0, RS16, RD16, E}}},
+  {O (O_MULU, SL), AV_H8SX, 0, "mulu.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xe, 0x5, 0x2, IMM4,       B30 | RD32, E}}},
+  {O (O_MULU, SL), AV_H8SX, 0, "mulu.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0xa, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}},
+
+  {O (O_MULSU, SL), AV_H8SX, 0, "muls/u.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x7, 0x5, 0x2, IMM4,       B30 | RD32, E}}},
+  {O (O_MULSU, SL), AV_H8SX, 0, "muls/u.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0x3, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}},
+  {O (O_MULUU, SL), AV_H8SX, 0, "mulu/u.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xf, 0x5, 0x2, IMM4,       B30 | RD32, E}}},
+  {O (O_MULUU, SL), AV_H8SX, 0, "mulu/u.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0xb, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}},
+
+  {O (O_MULXS, SB), AV_H8SX, 0,  "mulxs.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0x4, 0x5, 0x0, IMM4, RD16,       E}}},
+  {O (O_MULXS, SB), AV_H8H,  20, "mulxs.b", {{RS8,  RD16, E}}, {{0x0, 0x1, 0xc, 0x0, 0x5, 0x0, RS8,  RD16,       E}}},
+  {O (O_MULXS, SW), AV_H8SX, 0,  "mulxs.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x4, 0x5, 0x2, IMM4, B30 | RD32, E}}},
+  {O (O_MULXS, SW), AV_H8H,  20, "mulxs.w", {{RS16, RD32, E}}, {{0x0, 0x1, 0xc, 0x0, 0x5, 0x2, RS16, B30 | RD32, E}}},
+
+  {O (O_MULXU, SB), AV_H8SX, 0,  "mulxu.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0xc, 0x5, 0x0, IMM4, RD16, E}}},
+  {O (O_MULXU, SB), AV_H8,   14, "mulxu.b", {{RS8,  RD16, E}}, {{0x5, 0x0,                     RS8,  RD16, E}}},
+  {O (O_MULXU, SW), AV_H8SX, 0,  "mulxu.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xc, 0x5, 0x2, IMM4, B30 | RD32, E}}},
+  {O (O_MULXU, SW), AV_H8H,  14, "mulxu.w", {{RS16, RD32, E}}, {{0x5, 0x2,                     RS16, B30 | RD32, E}}},
+
+  EXPAND_UNOP_STD_B (O (O_NEG,  SB), "neg.b", PREFIX_017, 0x1, 0x7, 0x8),
+  EXPAND_UNOP_STD_W (O (O_NEG,  SW), "neg.w", PREFIX_015, 0x1, 0x7, 0x9),
+  EXPAND_UNOP_STD_L (O (O_NEG,  SL), "neg.l", PREFIX_010, 0x1, 0x7, 0xb),
+
+  {O (O_NOP, SN), AV_H8,  2, "nop",   {{E}},  {{0x0, 0x0, 0x0, 0x0, E}}},
+
+  EXPAND_UNOP_STD_B (O (O_NOT,  SB), "not.b", PREFIX_017, 0x1, 0x7, 0x0),
+  EXPAND_UNOP_STD_W (O (O_NOT,  SW), "not.w", PREFIX_015, 0x1, 0x7, 0x1),
+  EXPAND_UNOP_STD_L (O (O_NOT,  SL), "not.l", PREFIX_010, 0x1, 0x7, 0x3),
+
+  {O (O_OR,  SB), AV_H8,  2, "or.b",  {{IMM8, RD8,  E}}, {{0xc, RD8, IMM8LIST, E}}}, 
+  EXPAND_TWOOP_B (O (O_OR, SB), "or.b", 0xc, 0x1, 0x4, 0x4, 0), 
+
+  {O (O_OR,  SW), AV_H8,  2, "or.w",  {{RS16, RD16, E}}, {{0x6, 0x4, RS16, RD16, E}}}, 
+  EXPAND_TWOOP_W (O (O_OR, SW), "or.w", 0x6, 0x4, 0x4), 
+
+  {O (O_OR,  SL), AV_H8H, 2, "or.l",  {{RS32, RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x4, B30 | RS32, B30 | RD32, E}}},
+  EXPAND_TWOOP_L (O (O_OR, SL), "or.l", 0x4), 
+
+  {O (O_ORC, SB), AV_H8,  2, "orc", {{IMM8, CCR | DST, E}}, {{0x0, 0x4, IMM8LIST, E}}},
+  {O (O_ORC, SB), AV_H8S, 2, "orc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x4, IMM8LIST, E}}},
+
+  {O (O_MOV, SW), AV_H8,  6, "pop.w",  {{OR16, E}}, {{0x6, 0xD, 0x7, OR16, E}}},
+  {O (O_MOV, SL), AV_H8H, 6, "pop.l",  {{OR32, E}}, {{PREFIX_0100, 0x6, 0xD, 0x7, OR32 | B30, E}}},
+  {O (O_MOV, SW), AV_H8,  6, "push.w", {{OR16, E}}, {{0x6, 0xD, 0xF, OR16, E}}},
+  {O (O_MOV, SL), AV_H8H, 6, "push.l", {{OR32, E}}, {{PREFIX_0100, 0x6, 0xD, 0xF, OR32 | B30, E}}},
+
+  EXPAND_UNOP_STD_B      (O (O_ROTL,  SB), "rotl.b",           PREFIX_017, 0x1, 0x2, 0x8),
+  EXPAND_UNOP_EXTENDED_B (O (O_ROTL,  SB), "rotl.b",  CONST_2, PREFIX_017, 0x1, 0x2, 0xc),
+  EXPAND_UNOP_STD_W      (O (O_ROTL,  SW), "rotl.w",           PREFIX_015, 0x1, 0x2, 0x9),
+  EXPAND_UNOP_EXTENDED_W (O (O_ROTL,  SW), "rotl.w",  CONST_2, PREFIX_015, 0x1, 0x2, 0xd),
+  EXPAND_UNOP_STD_L      (O (O_ROTL,  SL), "rotl.l",           PREFIX_010, 0x1, 0x2, 0xb),
+  EXPAND_UNOP_EXTENDED_L (O (O_ROTL,  SL), "rotl.l",  CONST_2, PREFIX_010, 0x1, 0x2, 0xf, B30),
+  EXPAND_UNOP_STD_B      (O (O_ROTR,  SB), "rotr.b",           PREFIX_017, 0x1, 0x3, 0x8),
+  EXPAND_UNOP_EXTENDED_B (O (O_ROTR,  SB), "rotr.b",  CONST_2, PREFIX_017, 0x1, 0x3, 0xc),
+  EXPAND_UNOP_STD_W      (O (O_ROTR,  SW), "rotr.w",           PREFIX_015, 0x1, 0x3, 0x9),
+  EXPAND_UNOP_EXTENDED_W (O (O_ROTR,  SW), "rotr.w",  CONST_2, PREFIX_015, 0x1, 0x3, 0xd),
+  EXPAND_UNOP_STD_L      (O (O_ROTR,  SL), "rotr.l",           PREFIX_010, 0x1, 0x3, 0xb),
+  EXPAND_UNOP_EXTENDED_L (O (O_ROTR,  SL), "rotr.l",  CONST_2, PREFIX_010, 0x1, 0x3, 0xf, B30),
+  EXPAND_UNOP_STD_B      (O (O_ROTXL, SB), "rotxl.b",          PREFIX_017, 0x1, 0x2, 0x0),
+  EXPAND_UNOP_EXTENDED_B (O (O_ROTXL, SB), "rotxl.b", CONST_2, PREFIX_017, 0x1, 0x2, 0x4),
+  EXPAND_UNOP_STD_W      (O (O_ROTXL, SW), "rotxl.w",          PREFIX_015, 0x1, 0x2, 0x1),
+  EXPAND_UNOP_EXTENDED_W (O (O_ROTXL, SW), "rotxl.w", CONST_2, PREFIX_015, 0x1, 0x2, 0x5),
+  EXPAND_UNOP_STD_L      (O (O_ROTXL, SL), "rotxl.l",          PREFIX_010, 0x1, 0x2, 0x3),
+  EXPAND_UNOP_EXTENDED_L (O (O_ROTXL, SL), "rotxl.l", CONST_2, PREFIX_010, 0x1, 0x2, 0x7, B30),
+  EXPAND_UNOP_STD_B      (O (O_ROTXR, SB), "rotxr.b",          PREFIX_017, 0x1, 0x3, 0x0),
+  EXPAND_UNOP_EXTENDED_B (O (O_ROTXR, SB), "rotxr.b", CONST_2, PREFIX_017, 0x1, 0x3, 0x4),
+  EXPAND_UNOP_STD_W      (O (O_ROTXR, SW), "rotxr.w",          PREFIX_015, 0x1, 0x3, 0x1),
+  EXPAND_UNOP_EXTENDED_W (O (O_ROTXR, SW), "rotxr.w", CONST_2, PREFIX_015, 0x1, 0x3, 0x5),
+  EXPAND_UNOP_STD_L      (O (O_ROTXR, SL), "rotxr.l",          PREFIX_010, 0x1, 0x3, 0x3),
+  EXPAND_UNOP_EXTENDED_L (O (O_ROTXR, SL), "rotxr.l", CONST_2, PREFIX_010, 0x1, 0x3, 0x7, B30),
+
+
+  {O (O_BPT,  SN), AV_H8,  10, "bpt",   {{E}}, {{0x7, 0xA, 0xF, 0xF, E}}},
+  {O (O_RTE,  SN), AV_H8,  10, "rte",   {{E}}, {{0x5, 0x6, 0x7, 0x0, E}}},
+  {O (O_RTS,  SN), AV_H8,   8, "rts",   {{E}}, {{0x5, 0x4, 0x7, 0x0, E}}},
+  {O (O_RTEL, SN), AV_H8SX, 0, "rte/l", {{RS32, RD32, E}}, {{0x5, 0x6, RS32 | B30, RD32 | B30, E}}},
+  {O (O_RTSL, SN), AV_H8SX, 0, "rts/l", {{RS32, RD32, E}}, {{0x5, 0x4, RS32 | B30, RD32 | B30, E}}},
+
+  EXPAND_UNOP_STD_B      (O (O_SHAL, SB), "shal.b",          PREFIX_017, 0x1, 0x0, 0x8),
+  EXPAND_UNOP_EXTENDED_B (O (O_SHAL, SB), "shal.b", CONST_2, PREFIX_017, 0x1, 0x0, 0xc),
+  EXPAND_UNOP_STD_W      (O (O_SHAL, SW), "shal.w",          PREFIX_015, 0x1, 0x0, 0x9),
+  EXPAND_UNOP_EXTENDED_W (O (O_SHAL, SW), "shal.w", CONST_2, PREFIX_015, 0x1, 0x0, 0xd),
+  EXPAND_UNOP_STD_L      (O (O_SHAL, SL), "shal.l",          PREFIX_010, 0x1, 0x0, 0xb),
+  EXPAND_UNOP_EXTENDED_L (O (O_SHAL, SL), "shal.l", CONST_2, PREFIX_010, 0x1, 0x0, 0xf, B30),
+  EXPAND_UNOP_STD_B      (O (O_SHAR, SB), "shar.b",          PREFIX_017, 0x1, 0x1, 0x8),
+  EXPAND_UNOP_EXTENDED_B (O (O_SHAR, SB), "shar.b", CONST_2, PREFIX_017, 0x1, 0x1, 0xc),
+  EXPAND_UNOP_STD_W      (O (O_SHAR, SW), "shar.w",          PREFIX_015, 0x1, 0x1, 0x9),
+  EXPAND_UNOP_EXTENDED_W (O (O_SHAR, SW), "shar.w", CONST_2, PREFIX_015, 0x1, 0x1, 0xd),
+  EXPAND_UNOP_STD_L      (O (O_SHAR, SL), "shar.l",          PREFIX_010, 0x1, 0x1, 0xb),
+  EXPAND_UNOP_EXTENDED_L (O (O_SHAR, SL), "shar.l", CONST_2, PREFIX_010, 0x1, 0x1, 0xf, B30),
+
+  EXPAND_UNOP_STD_B      (O (O_SHLL, SB), "shll.b",          PREFIX_017, 0x1, 0x0, 0x0),
+
+  {O (O_SHLL, SB), AV_H8SX, 0, "shll.b", {{RS8,  RD8,  E}}, {{0x7, 0x8, RS8,        0x8,  0x1, 0x0, 0x0, RD8,  E}}},
+
+  EXPAND_UNOP_EXTENDED_B (O (O_SHLL, SB), "shll.b", CONST_2, PREFIX_017, 0x1, 0x0, 0x4),
+  EXPAND_UNOP_EXTENDED_B (O (O_SHLL, SB), "shll.b", CONST_4, PREFIX_017, 0x1, 0x0, 0xa),
+  {O (O_SHLL, SB), AV_H8SX, 0, "shll.b", {{IMM5, RD8,  E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x0, RD8,  E}}},
+
+  EXPAND_UNOP_STD_W      (O (O_SHLL, SW), "shll.w",          PREFIX_015, 0x1, 0x0, 0x1),
+
+  {O (O_SHLL, SW), AV_H8SX, 0, "shll.w", {{RS8,  RD16, E}}, {{0x7, 0x8, RS8,        0x8,  0x1, 0x0, 0x1, RD16, E}}},
+
+  EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_2, PREFIX_015, 0x1, 0x0, 0x5),
+  EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_4, PREFIX_015, 0x1, 0x0, 0x2),
+  EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_8, PREFIX_015, 0x1, 0x0, 0x6),
+  {O (O_SHLL, SW), AV_H8SX, 0, "shll.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x1, RD16, E}}},
+
+  EXPAND_UNOP_STD_L      (O (O_SHLL, SL), "shll.l",           PREFIX_010, 0x1, 0x0, 0x3),
+
+  {O (O_SHLL, SL), AV_H8SX, 0, "shll.l", {{RS8,  RD32, E}}, {{0x7, 0x8, RS8,        0x8,  0x1, 0x0, 0x3, B30 | RD32, E}}},
+
+  EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_2,  PREFIX_010, 0x1, 0x0, 0x7, B30),
+  EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_4,  PREFIX_010, 0x1, 0x0, 0x3, B31),
+  EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_8,  PREFIX_010, 0x1, 0x0, 0x7, B31),
+  EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_16, PREFIX_010, 0x1, 0x0, 0xf, B31),
+  {O (O_SHLL, SL), AV_H8SX, 0, "shll.l", {{IMM5, RD32, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x3, B30 | RD32, E}}},
+
+  EXPAND_UNOP_STD_B      (O (O_SHLR, SB), "shlr.b",          PREFIX_017, 0x1, 0x1, 0x0),
+
+  {O (O_SHLR, SB), AV_H8SX, 0, "shlr.b", {{RS8,  RD8,  E}}, {{0x7, 0x8, RS8,        0x8,  0x1, 0x1, 0x0, RD8,  E}}},
+
+  EXPAND_UNOP_EXTENDED_B (O (O_SHLR, SB), "shlr.b", CONST_2, PREFIX_017, 0x1, 0x1, 0x4),
+  EXPAND_UNOP_EXTENDED_B (O (O_SHLR, SB), "shlr.b", CONST_4, PREFIX_017, 0x1, 0x1, 0xa),
+  {O (O_SHLR, SB), AV_H8SX, 0, "shlr.b", {{IMM5, RD8,  E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x0, RD8,  E}}},
+
+  EXPAND_UNOP_STD_W      (O (O_SHLR, SW), "shlr.w",          PREFIX_015, 0x1, 0x1, 0x1),
+
+  {O (O_SHLR, SW), AV_H8SX, 0, "shlr.w", {{RS8,  RD16, E}}, {{0x7, 0x8, RS8,        0x8,  0x1, 0x1, 0x1, RD16, E}}},
+
+  EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_2, PREFIX_015, 0x1, 0x1, 0x5),
+  EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_4, PREFIX_015, 0x1, 0x1, 0x2),
+  EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_8, PREFIX_015, 0x1, 0x1, 0x6),
+  {O (O_SHLR, SW), AV_H8SX, 0, "shlr.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x1, RD16, E}}},
+
+  EXPAND_UNOP_STD_L      (O (O_SHLR, SL), "shlr.l",           PREFIX_010, 0x1, 0x1, 0x3),
+
+  {O (O_SHLR, SL), AV_H8SX, 0, "shlr.l", {{RS8,  RD32, E}}, {{0x7, 0x8, RS8,        0x8,  0x1, 0x1, 0x3, B30 | RD32, E}}},
+
+  EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_2,  PREFIX_010, 0x1, 0x1, 0x7, B30),
+  EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_4,  PREFIX_010, 0x1, 0x1, 0x3, B31),
+  EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_8,  PREFIX_010, 0x1, 0x1, 0x7, B31),
+  EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_16, PREFIX_010, 0x1, 0x1, 0xf, B31),
+  {O (O_SHLR, SL), AV_H8SX, 0, "shlr.l", {{IMM5, RD32, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x3, B30 | RD32, E}}},
+
+  {O (O_SLEEP, SN), AV_H8, 2, "sleep", {{E}}, {{0x0, 0x1, 0x8, 0x0, E}}},
+
+  {O (O_STC, SB), AV_H8,   2, "stc", {{CCR | SRC, RD8,            E}}, {{0x0, 0x2, B30 | CCR | SRC,           RD8,    E}}},
+  {O (O_STC, SB), AV_H8S,  2, "stc", {{EXR | SRC, RD8,            E}}, {{0x0, 0x2, B30 | EXR | SRC,           RD8,    E}}},
+  {O (O_STC, SW), AV_H8H,  2, "stc", {{CCR | SRC, RDIND,          E}}, {{PREFIXSTC, 0x6, 0x9, B31 | RDIND,    IGNORE, E}}},
+  {O (O_STC, SW), AV_H8S,  2, "stc", {{EXR | SRC, RDIND,          E}}, {{PREFIXSTC, 0x6, 0x9, B31 | RDIND,    IGNORE, E}}},
+  {O (O_STC, SW), AV_H8H,  2, "stc", {{CCR | SRC, RDPREDEC,       E}}, {{PREFIXSTC, 0x6, 0xD, B31 | RDPREDEC, IGNORE, E}}},
+  {O (O_STC, SW), AV_H8S,  2, "stc", {{EXR | SRC, RDPREDEC,       E}}, {{PREFIXSTC, 0x6, 0xD, B31 | RDPREDEC, IGNORE, E}}},
+  {O (O_STC, SW), AV_H8H,  2, "stc", {{CCR | SRC, DISP16DST,      E}}, {{PREFIXSTC, 0x6, 0xF, B31 | DSTDISPREG,                   IGNORE, DSTDISP16LIST, E}}},
+  {O (O_STC, SW), AV_H8S,  2, "stc", {{EXR | SRC, DISP16DST,      E}}, {{PREFIXSTC, 0x6, 0xF, B31 | DSTDISPREG,                   IGNORE, DSTDISP16LIST, E}}},
+  {O (O_STC, SW), AV_H8H,  2, "stc", {{CCR | SRC, DISP32DST,      E}}, {{PREFIXSTC, 0x7, 0x8, B30 | DSTDISPREG, 0, 0x6, 0xB, 0xA, IGNORE, DSTDISP32LIST, E}}},
+  {O (O_STC, SW), AV_H8S,  2, "stc", {{EXR | SRC, DISP32DST,      E}}, {{PREFIXSTC, 0x7, 0x8, B30 | DSTDISPREG, 0, 0x6, 0xB, 0xA, IGNORE, DSTDISP32LIST, E}}},
+  {O (O_STC, SW), AV_H8H,  2, "stc", {{CCR | SRC, ABS16DST,       E}}, {{PREFIXSTC, 0x6, 0xB, 0x8, IGNORE, DST | ABS16LIST, E}}},
+  {O (O_STC, SW), AV_H8S,  2, "stc", {{EXR | SRC, ABS16DST,       E}}, {{PREFIXSTC, 0x6, 0xB, 0x8, IGNORE, DST | ABS16LIST, E}}},
+  {O (O_STC, SW), AV_H8H,  2, "stc", {{CCR | SRC, ABS32DST,       E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | ABS32LIST, E}}},
+  {O (O_STC, SW), AV_H8S,  2, "stc", {{EXR | SRC, ABS32DST,       E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | ABS32LIST, E}}},
+  {O (O_STC, SL), AV_H8SX, 0, "stc", {{B30 | VBR_SBR | SRC, RD32, E}}, {{0x0, 0x2, B30 | VBR_SBR | SRC, RD32, E}}},
+
+
+  EXPAND_TWOOP_B (O (O_SUB, SB), "sub.b", 0xa, 0x1, 0x8, 0x3, B01), 
+
+  {O (O_SUB, SW), AV_H8,   2, "sub.w", {{RS16,      RD16,     E}}, {{0x1, 0x9, RS16,         RD16,   E}}}, 
+  {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, RD16,     E}}, {{0x1, 0xa, B30 | IMM3NZ, RD16,   E}}}, 
+  {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, RDIND,    E}}, {{0x7, 0xd,      B31 | RDIND,  IGNORE,       0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}}, 
+  {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}}, 
+  {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}}, 
+  EXPAND_TWOOP_W (O (O_SUB, SW), "sub.w", 0x1, 0x9, 0x3), 
+
+  {O (O_SUB, SL), AV_H8H,  6, "sub.l", {{RS32,      RD32,     E}}, {{0x1, 0xa, B31 | RS32,   B30 | RD32, E}}}, 
+  {O (O_SUB, SL), AV_H8SX, 0, "sub.l", {{IMM3NZ_NS, RD32,     E}}, {{0x1, 0xa, B31 | IMM3NZ, B31 | RD32, E}}}, 
+  EXPAND_TWOOP_L (O (O_SUB, SL), "sub.l", 0x3), 
+
+  {O (O_SUBS, SL), AV_H8, 2, "subs", {{KBIT, RDP, E}}, {{0x1, 0xB,KBIT, RDP, E}}},
+
+  {O (O_SUBX, SB), AV_H8,   2, "subx",   {{IMM8,      RD8,       E}}, {{0xb, RD8, IMM8LIST, E}}},
+  {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{IMM8,      RDIND,     E}}, {{0x7, 0xd, B30 | RDIND, IGNORE,                        0xb, IGNORE, IMM8LIST, E}}},
+  {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{IMM8,      RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0xb, IGNORE, IMM8LIST, E}}},
+  {O (O_SUBX, SB), AV_H8,   2, "subx",   {{RS8,       RD8,       E}}, {{0x1, 0xe, RS8,  RD8,    E}}},
+  {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RS8,       RDIND,     E}}, {{0x7, 0xd, B30 | RDIND, IGNORE,                              0x1, 0xe, RS8, IGNORE, E}}},
+  {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RS8,       RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31       | IGNORE, 0x1, 0xe, RS8, IGNORE, E}}},
+  {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSIND,     RD8,       E}}, {{0x7, 0xc, B30 | RSIND, IGNORE,                              0x1, 0xe, IGNORE, RD8, E}}},
+  {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSPOSTDEC, RD8,       E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, B30 | B20 | IGNORE, 0x1, 0xe, IGNORE, RD8, E}}},
+  {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSIND,     RDIND,     E}}, {{PREFIX_0174, 0x6, 0x8, B30 | RSIND,     0xd, 0x0, RDIND,     0x3, IGNORE, E}}},
+  {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}},
+
+  {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16,     RD16,      E}}, {{PREFIX_0151,                         0x7, 0x9, 0x3, RD16,   IMM16LIST, E}}}, 
+  {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16,     RDIND,     E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x7, 0x9, 0x3, IGNORE, IMM16LIST, E}}}, 
+  {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16,     RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0x9, 0x3, IGNORE, IMM16LIST, E}}}, 
+  {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16,      RD16,      E}}, {{PREFIX_0151, 0x1, 0x9, RS16,  RD16,    E}}},
+  {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16,      RDIND,     E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x1, 0x9, RS16, IGNORE, E}}},
+  {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16,      RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x1, 0x9, RS16, IGNORE, E}}}, 
+  {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSIND,     RD16,      E}}, {{0x7, 0xc, B31 | RSIND, B01 | IGNORE, 0x1, 0x9, IGNORE, RD16, E}}},
+  {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSPOSTDEC, RD16,      E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x1, 0x9, IGNORE, RD16, E}}},
+  {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSIND,     RDIND,     E}}, {{PREFIX_0154, 0x6, 0x9, B30 | RSIND,     0xd, 0x0, RDIND,     0x3, IGNORE, E}}},
+  {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}},
+
+  {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32,     RD32,      E}}, {{PREFIX_0101, 0x7, 0xa, 0x3,  RD32, IMM32LIST, E}}},
+  {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32,     RDIND,     E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND,     B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x3, IGNORE, IMM32LIST, E}}},
+  {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32,     RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x3, IGNORE, IMM32LIST, E}}},
+  {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32,      RD32,      E}}, {{PREFIX_0101, 0x1, 0xa, B31 | RS32,  B30 | RD32,    E}}},
+  {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32,      RDIND,     E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND,     B31 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | RS32, B30 | IGNORE, E}}},
+  {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32,      RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | RS32, B30 | IGNORE, E}}},
+  {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSIND,     RD32,      E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND,     B30 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | IGNORE, B30 | RD32, E}}},
+  {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSPOSTDEC, RD32,      E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | IGNORE, B30 | RD32, E}}},
+  {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSIND,     RDIND,     E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND,     0xd, 0x0, RDIND,     0x3, IGNORE, E}}},
+  {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}},
+
+  {O (O_TRAPA, SB), AV_H8H, 2, "trapa", {{IMM2,  E}}, {{0x5, 0x7, IMM2, IGNORE, E}}},
+  {O (O_TAS,   SB), AV_H8H, 2, "tas",   {{RSIND, E}}, {{0x0, 0x1, 0xe, 0x0, 0x7, 0xb, B30 | RSIND, 0xc, E}}},
+
+  {O (O_XOR,   SB), AV_H8,  2, "xor.b", {{IMM8, RD8,  E}}, {{0xd, RD8, IMM8LIST, E}}}, 
+  EXPAND_TWOOP_B (O (O_XOR, SB), "xor.b", 0xd, 0x1, 0x5, 0x5, 0), 
+
+  {O (O_XOR,   SW), AV_H8,  2, "xor.w", {{RS16, RD16, E}}, {{0x6, 0x5, RS16, RD16, E}}}, 
+  EXPAND_TWOOP_W (O (O_XOR, SW), "xor.w", 0x6, 0x5, 0x5), 
+
+  {O (O_XOR,   SL), AV_H8H, 2, "xor.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x5, B30 | RS32, B30 | RD32, E}}},
+  EXPAND_TWOOP_L (O (O_XOR, SL), "xor.l", 0x5), 
+
+  {O (O_XORC, SB), AV_H8,  2, "xorc", {{IMM8, CCR | DST, E}}, {{0x0, 0x5, IMM8LIST, E}}},
+  {O (O_XORC, SB), AV_H8S, 2, "xorc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x5, IMM8LIST, E}}},
+
+  {O (O_CLRMAC, SN), AV_H8S, 2, "clrmac", {{E}}, {{0x0, 0x1, 0xa, 0x0, E}}},
+  {O (O_MAC,    SW), AV_H8S, 2, "mac",    {{RSPOSTINC, RDPOSTINC, E}}, {{0x0, 0x1, 0x6, 0x0, 0x6, 0xd, B30 | RSPOSTINC, B30 | RDPOSTINC, E}}},
+  {O (O_LDMAC,  SL), AV_H8S, 2, "ldmac",  {{RS32, MD32, E}}, {{0x0, 0x3, MD32, RS32, E}}},
+  {O (O_STMAC,  SL), AV_H8S, 2, "stmac",  {{MS32, RD32, E}}, {{0x0, 0x2, MS32, RD32, E}}},
+  {O (O_LDM,    SL), AV_H8H, 6, "ldm.l",  {{RSPOSTINC, RD32, E}}, {{0x0, 0x1, DATA, 0x0, 0x6, 0xD, 0x7, B30 | RD32, E}}},
+  {O (O_STM,    SL), AV_H8H, 6, "stm.l",  {{RS32, RDPREDEC,  E}}, {{0x0, 0x1, DATA, 0x0, 0x6, 0xD, 0xF, B30 | RS32, E}}},
+  {0, 0, 0, NULL, {{0, 0, 0}}, {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}}
 };
 #else
 extern const struct h8_opcode h8_opcodes[];
 #endif
+
diff --git a/include/opcode/i386.h b/include/opcode/i386.h
index 71c204c81f5..cb3a99a4e6f 100644
--- a/include/opcode/i386.h
+++ b/include/opcode/i386.h
@@ -1302,6 +1302,30 @@ static const template i386_optab[] = {
 {"punpckhqdq",2, 0x660f6d,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
 {"punpcklqdq",2, 0x660f6c,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
 
+/* Prescott New Instructions.  */
+
+{"addsubpd",  2, 0x660fd0,  X, CpuPNI, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"addsubps",  2, 0xf20fd0,  X, CpuPNI, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"fisttp",    1, 0xdf,      1, CpuPNI, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
+/* Intel Syntax */
+{"fisttpd",   1, 0xdd,      1, CpuPNI, FP|Modrm,	{ LLongMem, 0, 0} },
+{"fisttpq",   1, 0xdd,      1, CpuPNI, FP|Modrm,	{ LLongMem, 0, 0} },
+{"fisttpll",  1, 0xdd,      1, CpuPNI, FP|Modrm,	{ LLongMem, 0, 0} },
+{"haddpd",    2, 0x660f7c,  X, CpuPNI, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"haddps",    2, 0xf20f7c,  X, CpuPNI, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"hsubpd",    2, 0x660f7d,  X, CpuPNI, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"hsubps",    2, 0xf20f7d,  X, CpuPNI, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"lddqu",     2, 0xf20ff0,  X, CpuPNI, FP|Modrm,	{ LLongMem, RegXMM, 0 } },
+{"monitor",   0, 0x0f01, 0xc8, CpuPNI, FP|ImmExt,	{ 0, 0, 0} },
+/* Need to ensure only "monitor %eax,%ecx,%edx" is accepted. */
+{"monitor",   3, 0x0f01, 0xc8, CpuPNI, FP|ImmExt,	{ Reg32, Reg32, Reg32} },
+{"movddup",   2, 0xf20f12,  X, CpuPNI, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"movshdup",  2, 0xf30f16,  X, CpuPNI, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"movsldup",  2, 0xf30f12,  X, CpuPNI, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"mwait",     0, 0x0f01, 0xc9, CpuPNI, FP|ImmExt,	{ 0, 0, 0} },
+/* Need to ensure only "mwait %eax,%ecx" is accepted.  */
+{"mwait",     2, 0x0f01, 0xc9, CpuPNI, FP|ImmExt,	{ Reg32, Reg32, 0} },
+
 /* AMD 3DNow! instructions.  */
 
 {"prefetch", 1, 0x0f0d,	   0, Cpu3dnow, FP|Modrm,		{ ByteMem, 0, 0 } },
diff --git a/include/opcode/i860.h b/include/opcode/i860.h
index 6fdcdba6ecc..6e2a683a499 100644
--- a/include/opcode/i860.h
+++ b/include/opcode/i860.h
@@ -40,7 +40,7 @@ struct i860_opcode
 
 enum expand_type
 {
-    E_MOV = 1, E_ADDR, E_U32, E_AND, E_S32, E_DELAY
+    E_MOV = 1, E_ADDR, E_U32, E_AND, E_S32, E_DELAY, XP_ONLY
 };
 
 
@@ -135,6 +135,10 @@ static const struct i860_opcode i860_opcodes[] =
 { "pfld.d",	0x64000000, 0x98000007, "L(2),g", E_ADDR },	/* pfld.d #const(isrc2),fdest */
 { "pfld.d",	0x60000001, 0x9c000006, "1(2)++,g", 0 },	/* pfld.d isrc1(isrc2)++,fdest */
 { "pfld.d",	0x64000001, 0x98000006, "L(2)++,g", E_ADDR },	/* pfld.d #const(isrc2)++,fdest */
+{ "pfld.q",	0x60000004, 0x9c000003, "1(2),g", XP_ONLY },	/* pfld.q isrc1(isrc2),fdest */
+{ "pfld.q",	0x64000004, 0x98000003, "L(2),g", XP_ONLY },	/* pfld.q #const(isrc2),fdest */
+{ "pfld.q",	0x60000005, 0x9c000002, "1(2)++,g", XP_ONLY },	/* pfld.q isrc1(isrc2)++,fdest */
+{ "pfld.q",	0x64000005, 0x98000002, "L(2)++,g", XP_ONLY },	/* pfld.q #const(isrc2)++,fdest */
 
 { "fst.l",	0x28000002, 0xd4000001, "g,1(2)", 0 },	/* fst.l fdest,isrc1(isrc2) */
 { "fst.l",	0x2c000002, 0xd0000001, "g,K(2)", E_ADDR },	/* fst.l fdest,#const(isrc2) */
@@ -204,6 +208,16 @@ static const struct i860_opcode i860_opcodes[] =
 { "calli",	0x4c000002, 0xb000001d, "1", E_DELAY },	/* calli isrc1ni */
 { "intovr",	0x4c000004, 0xb000001b, "", 0 },	/* intovr trap on integer overflow */
 { "unlock",	0x4c000007, 0xb0000018, "", 0 },	/* unlock clear BL in dirbase */
+{ "ldio.l",	0x4c000408, 0xb00003f7, "2,d", XP_ONLY },	/* ldio.l isrc2,idest */
+{ "ldio.s",	0x4c000208, 0xb00005f7, "2,d", XP_ONLY },	/* ldio.s isrc2,idest */
+{ "ldio.b",	0x4c000008, 0xb00007f7, "2,d", XP_ONLY },	/* ldio.b isrc2,idest */
+{ "stio.l",	0x4c000409, 0xb00003f6, "1,2", XP_ONLY },	/* stio.l isrc1ni,isrc2 */
+{ "stio.s",	0x4c000209, 0xb00005f6, "1,2", XP_ONLY },	/* stio.s isrc1ni,isrc2 */
+{ "stio.b",	0x4c000009, 0xb00007f6, "1,2", XP_ONLY },	/* stio.b isrc1ni,isrc2 */
+{ "ldint.l",	0x4c00040a, 0xb00003f5, "2,d", XP_ONLY },	/* ldint.l isrc2,idest */
+{ "ldint.s",	0x4c00020a, 0xb00005f5, "2,d", XP_ONLY },	/* ldint.s isrc2,idest */
+{ "ldint.b",	0x4c00000a, 0xb00007f5, "2,d", XP_ONLY },	/* ldint.b isrc2,idest */
+{ "scyc.b",	0x4c00000b, 0xb00007f4, "2", XP_ONLY },		/* scyc.b isrc2 */
 
 /* CTRL-Format Instructions */
 { "br",		0x68000000, 0x94000000, "l", E_DELAY },	/* br lbroff */
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index ffd313acd52..c4adf712b75 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -1,5 +1,5 @@
 /* ppc.h -- Header file for PowerPC opcode table
-   Copyright 1994, 1995, 1999, 2000, 2001, 2002
+   Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003
    Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support
 
@@ -273,6 +273,9 @@ extern const struct powerpc_operand powerpc_operands[];
 
 /* This operand is for the DS field in a DS form instruction.  */
 #define PPC_OPERAND_DS (020000)
+
+/* This operand is for the DQ field in a DQ form instruction.  */
+#define PPC_OPERAND_DQ (040000)
 
 /* The POWER and PowerPC assemblers use a few macros.  We keep them
    with the operands table for simplicity.  The macro table is an
diff --git a/include/safe-ctype.h b/include/safe-ctype.h
index b2ad8490bd0..69a3f74cc6f 100644
--- a/include/safe-ctype.h
+++ b/include/safe-ctype.h
@@ -37,7 +37,24 @@ Boston, MA 02111-1307, USA.  */
 
 #ifdef isalpha
  #error "safe-ctype.h and ctype.h may not be used simultaneously"
+#endif
+
+/* Determine host character set.  */
+#define HOST_CHARSET_UNKNOWN 0
+#define HOST_CHARSET_ASCII   1
+#define HOST_CHARSET_EBCDIC  2
+
+#if  '\n' == 0x0A && ' ' == 0x20 && '0' == 0x30 \
+   && 'A' == 0x41 && 'a' == 0x61 && '!' == 0x21
+#  define HOST_CHARSET HOST_CHARSET_ASCII
 #else
+# if '\n' == 0x15 && ' ' == 0x40 && '0' == 0xF0 \
+   && 'A' == 0xC1 && 'a' == 0x81 && '!' == 0x5A
+#  define HOST_CHARSET HOST_CHARSET_EBCDIC
+# else
+#  define HOST_CHARSET HOST_CHARSET_UNKNOWN
+# endif
+#endif
 
 /* Categories.  */
 
@@ -99,5 +116,4 @@ extern const unsigned char  _sch_tolower[256];
 #define TOUPPER(c) _sch_toupper[(c) & 0xff]
 #define TOLOWER(c) _sch_tolower[(c) & 0xff]
 
-#endif /* no ctype.h */
 #endif /* SAFE_CTYPE_H */