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authorRichard Earnshaw <richard.earnshaw@arm.com>2002-01-15 15:41:23 +0000
committerRichard Earnshaw <richard.earnshaw@arm.com>2002-01-15 15:41:23 +0000
commit758e315cb92f4ccd5add35d7cbaee0e88e300cc2 (patch)
tree0da010790ff49fc7235ae028a09831f2c2027889 /opcodes/arm-dis.c
parent58a506cb89b60b4984764a5341f9279a78922560 (diff)
downloadgdb-758e315cb92f4ccd5add35d7cbaee0e88e300cc2.tar.gz
* arm-opc.h (arm_opcodes): Add patterns for VFP instructions.
* arm-dis.c (print_insn_arm): Support new disassembly qualifiers for VFP bitfields.
Diffstat (limited to 'opcodes/arm-dis.c')
-rw-r--r--opcodes/arm-dis.c80
1 files changed, 79 insertions, 1 deletions
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 104b933bbc2..b2807c5325a 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -630,7 +630,85 @@ print_insn_arm (pc, info, given)
abort ();
}
break;
-
+
+ case 'y':
+ case 'z':
+ {
+ int single = *c == 'y';
+ int regno;
+
+ switch (bitstart)
+ {
+ case 4: /* Sm pair */
+ func (stream, "{");
+ /* Fall through. */
+ case 0: /* Sm, Dm */
+ regno = given & 0x0000000f;
+ if (single)
+ {
+ regno <<= 1;
+ regno += (given >> 5) & 1;
+ }
+ break;
+
+ case 1: /* Sd, Dd */
+ regno = (given >> 12) & 0x0000000f;
+ if (single)
+ {
+ regno <<= 1;
+ regno += (given >> 22) & 1;
+ }
+ break;
+
+ case 2: /* Sn, Dn */
+ regno = (given >> 16) & 0x0000000f;
+ if (single)
+ {
+ regno <<= 1;
+ regno += (given >> 7) & 1;
+ }
+ break;
+
+ case 3: /* List */
+ func (stream, "{");
+ regno = (given >> 12) & 0x0000000f;
+ if (single)
+ {
+ regno <<= 1;
+ regno += (given >> 22) & 1;
+ }
+ break;
+
+
+ default:
+ abort ();
+ }
+
+ func (stream, "%c%d", single ? 's' : 'd', regno);
+
+ if (bitstart == 3)
+ {
+ int count = given & 0xff;
+
+ if (single == 0)
+ count >>= 1;
+
+ if (--count)
+ {
+ func (stream, "-%c%d",
+ single ? 's' : 'd',
+ regno + count);
+ }
+
+ func (stream, "}");
+ }
+ else if (bitstart == 4)
+ func (stream, ", %c%d}", single ? 's' : 'd',
+ regno + 1);
+
+ break;
+ }
+
case '`':
c++;
if ((given & (1 << bitstart)) == 0)