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| author | Jim Wilson <wilson@tuliptree.org> | 2002-12-05 02:08:02 +0000 |
|---|---|---|
| committer | Jim Wilson <wilson@tuliptree.org> | 2002-12-05 02:08:02 +0000 |
| commit | 08a9754291c505ebb23407bb89ce34f0d53e9c6f (patch) | |
| tree | 02c3594a32c820dc5415cc01da08041639580fe2 /opcodes/ia64-opc-i.c | |
| parent | 2ceb8bb65e2ab9d7cb3b6e5ebc44743065c0f2d5 (diff) | |
| download | gdb-08a9754291c505ebb23407bb89ce34f0d53e9c6f.tar.gz | |
Patch to update IA-64 port to SDM 2.1.
bfd/ChangeLog
* cpu-ia64-opc.c: Add operand constant "ar.csd".
gas/ChangeLog
* config/tc-ia64.c (pseudo_func): Add "@pause" constant for "hint"
instruction.
(emit_one_bundle): Handle "hint" instruction.
(operand_match): Match IA64_OPND_AR_CSD.
gas/testsuite/ChangeLog
* gas/ia64/opc-b.d: Update for instructions added by SDM2.1.
* gas/ia64/opc-b.s: Ditto.
* gas/ia64/opc-f.d: Ditto.
* gas/ia64/opc-f.s: Ditto.
* gas/ia64/opc-i.d: Ditto.
* gas/ia64/opc-i.s: Ditto.
* gas/ia64/opc-m.d: Ditto.
* gas/ia64/opc-m.s: Ditto.
* gas/ia64/opc-x.d: Ditto.
* gas/ia64/opc-x.s: Ditto.
include/opcode/ChangeLog
* ia64.h: Fix copyright message.
(IA64_OPND_AR_CSD): New operand kind.
opcodes/ChangeLog
* ia64-opc-d.c (ia64_opcodes_d): Add "hint" instruction.
* ia64-opc-b.c: Add "hint.b" instruction.
* ia64-opc-f.c: Add "hint.f" instruction.
* ia64-opc-i.c: Add "hint.i" instruction.
* ia64-opc-m.c: Add "hint.m", "fc.i", "ld16", "st16", and
"cmp8xchg16" instructions.
* ia64-opc-x.c: Add "hint.x" instruction.
* ia64-opc.h (AR_CSD): New macro.
* ia64-ic.tbl: Update according to SDM2.1.
* ia64-raw.tbl: Ditto.
* ia64-waw.tbl: Ditto.
* ia64-gen.c (in_iclass): Handle "hint" like "nop".
(lookup_regindex): Recognize AR[FCR], AR[EFLAG], AR[CSD],
AR[SSD], AR[CFLG], AR[FSR], AR[FIR], and AR[FDR].
* ia64-asmtab.c: Regenerate.
Diffstat (limited to 'opcodes/ia64-opc-i.c')
| -rw-r--r-- | opcodes/ia64-opc-i.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/opcodes/ia64-opc-i.c b/opcodes/ia64-opc-i.c index 8de169611ef..86440f7b57f 100644 --- a/opcodes/ia64-opc-i.c +++ b/opcodes/ia64-opc-i.c @@ -86,6 +86,8 @@ #define OpX3(a,b) (bOp (a) | bX3 (b)), (mOp | mX3) #define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \ (mOp | mX3 | mX6) +#define OpX3X6Yb(a,b,c,d) (bOp (a) | bX3 (b) | bX6(c) | bYb(d)), \ + (mOp | mX3 | mX6 | mYb) #define OpX3XbIhWh(a,b,c,d,e) \ (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e)), \ (mOp | mX3 | mXb | mIh | mWh) @@ -102,7 +104,8 @@ struct ia64_opcode ia64_opcodes_i[] = /* I-type instruction encodings (sorted according to major opcode). */ {"break.i", I0, OpX3X6 (0, 0, 0x00), {IMMU21}, X_IN_MLX, 0, NULL}, - {"nop.i", I0, OpX3X6 (0, 0, 0x01), {IMMU21}, X_IN_MLX, 0, NULL}, + {"nop.i", I0, OpX3X6Yb (0, 0, 0x01, 0), {IMMU21}, X_IN_MLX, 0, NULL}, + {"hint.i", I0, OpX3X6Yb (0, 0, 0x01, 1), {IMMU21}, X_IN_MLX, 0, NULL}, {"chk.s.i", I0, OpX3 (0, 1), {R2, TGT25b}, EMPTY}, {"mov", I, OpX3XbIhWhTag13 (0, 7, 0, 0, 1, 0), {B1, R2}, PSEUDO, 0, NULL}, |